Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T22,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T22,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T22,T49,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T49,T50
1	0	Covered	T14,T28,T29
1	1	Covered	T22,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T49,T50
0	1	Covered	T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T49,T50
0	1	Covered	T22,T49,T50
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T49,T50
1	-	Covered	T22,T49,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T49,T50
0	1	Covered	T22,T49,T50
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T49,T50
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T49,T50
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T49,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T221,T204,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T49,T50
DetectSt	-	-	-	-	1	-	-	Covered	T80
DetectSt	-	-	-	-	0	1	-	Covered	T22,T49,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T49,T50
StableSt	-	-	-	-	-	-	0	Covered	T22,T49,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	129	0	0
CntIncr_A	6912820	31666	0	0
CntNoWrap_A	6912820	6250522	0	0
DetectStDropOut_A	6912820	1	0	0
DetectedOut_A	6912820	5261	0	0
DetectedPulseOut_A	6912820	60	0	0
DisabledIdleSt_A	6912820	6184212	0	0
DisabledNoDetection_A	6912820	6186408	0	0
EnterDebounceSt_A	6912820	68	0	0
EnterDetectSt_A	6912820	61	0	0
EnterStableSt_A	6912820	60	0	0
PulseIsPulse_A	6912820	60	0	0
StayInStableSt	6912820	5177	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	129	0	0
T22	4822	4	0	0
T23	5841	0	0	0
T49	0	2	0	0
T50	0	8	0	0
T66	0	6	0	0
T67	0	2	0	0
T80	0	6	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	4	0	0
T167	0	2	0	0
T192	0	2	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	31666	0	0
T22	4822	68	0	0
T23	5841	0	0	0
T49	0	14	0	0
T50	0	201	0	0
T66	0	291	0	0
T67	0	33	0	0
T80	0	154	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	180	0	0
T167	0	53	0	0
T192	0	28	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	176	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250522	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1	0	0
T80	1789	1	0	0
T81	341286	0	0	0
T137	1047	0	0	0
T196	428	0	0	0
T197	522	0	0	0
T232	1202	0	0	0
T233	14558	0	0	0
T234	502	0	0	0
T235	522	0	0	0
T236	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5261	0	0
T22	4822	91	0	0
T23	5841	0	0	0
T49	0	148	0	0
T50	0	218	0	0
T66	0	93	0	0
T67	0	42	0	0
T80	0	86	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	223	0	0
T167	0	312	0	0
T192	0	41	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	319	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	60	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T49	0	1	0	0
T50	0	4	0	0
T66	0	3	0	0
T67	0	1	0	0
T80	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T167	0	1	0	0
T192	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6184212	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6186408	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	68	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T49	0	1	0	0
T50	0	4	0	0
T66	0	3	0	0
T67	0	1	0	0
T80	0	3	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T167	0	1	0	0
T192	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	61	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T49	0	1	0	0
T50	0	4	0	0
T66	0	3	0	0
T67	0	1	0	0
T80	0	3	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T167	0	1	0	0
T192	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	60	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T49	0	1	0	0
T50	0	4	0	0
T66	0	3	0	0
T67	0	1	0	0
T80	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T167	0	1	0	0
T192	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	60	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T49	0	1	0	0
T50	0	4	0	0
T66	0	3	0	0
T67	0	1	0	0
T80	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	2	0	0
T167	0	1	0	0
T192	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5177	0	0
T22	4822	88	0	0
T23	5841	0	0	0
T49	0	147	0	0
T50	0	213	0	0
T66	0	89	0	0
T67	0	41	0	0
T80	0	84	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	220	0	0
T167	0	310	0	0
T192	0	39	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	316	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	34	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T49	0	1	0	0
T50	0	3	0	0
T66	0	2	0	0
T67	0	1	0	0
T80	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T165	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T203	0	1	0	0
T221	0	1	0	0
T232	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T49,T45,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T49,T45,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T49,T45,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T49,T45
1	0	Covered	T14,T28,T29
1	1	Covered	T49,T45,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T49,T45,T46
0	1	Covered	T165
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T45,T46
0	1	Covered	T46,T181,T80
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T49,T45,T46
1	-	Covered	T46,T181,T80

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T49,T45,T46
0	1	Covered	T49,T45,T46
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T45,T46
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T49,T45,T46
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T49,T45,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T143
DebounceSt	-	0	0	-	-	-	-	Covered	T49,T45,T46
DetectSt	-	-	-	-	1	-	-	Covered	T165
DetectSt	-	-	-	-	0	1	-	Covered	T49,T45,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T181,T80
StableSt	-	-	-	-	-	-	0	Covered	T49,T45,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	97	0	0
CntIncr_A	6912820	41537	0	0
CntNoWrap_A	6912820	6250554	0	0
DetectStDropOut_A	6912820	1	0	0
DetectedOut_A	6912820	3121	0	0
DetectedPulseOut_A	6912820	47	0	0
DisabledIdleSt_A	6912820	6052019	0	0
DisabledNoDetection_A	6912820	6054208	0	0
EnterDebounceSt_A	6912820	49	0	0
EnterDetectSt_A	6912820	48	0	0
EnterStableSt_A	6912820	47	0	0
PulseIsPulse_A	6912820	47	0	0
StayInStableSt	6912820	3052	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6912820	6387	0	0
gen_low_level_sva.LowLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	97	0	0
T40	21099	0	0	0
T45	881	2	0	0
T46	0	4	0	0
T49	3627	2	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	2	0	0
T80	0	6	0	0
T92	720	0	0	0
T95	724	0	0	0
T143	0	1	0	0
T144	0	2	0	0
T165	0	2	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T181	0	2	0	0
T232	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	41537	0	0
T40	21099	0	0	0
T45	881	94	0	0
T46	0	72	0	0
T49	3627	14	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	33	0	0
T80	0	154	0	0
T92	720	0	0	0
T95	724	0	0	0
T143	0	38789	0	0
T144	0	31	0	0
T165	0	90	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T181	0	65	0	0
T232	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250554	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1	0	0
T165	10761	1	0	0
T179	402	0	0	0
T238	13849	0	0	0
T239	2069	0	0	0
T240	425	0	0	0
T241	525	0	0	0
T242	508	0	0	0
T243	646	0	0	0
T244	11556	0	0	0
T245	43652	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	3121	0	0
T40	21099	0	0	0
T45	881	41	0	0
T46	0	29	0	0
T49	3627	51	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	102	0	0
T78	0	14	0	0
T80	0	171	0	0
T92	720	0	0	0
T95	724	0	0	0
T144	0	43	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T181	0	138	0	0
T203	0	43	0	0
T232	0	207	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	47	0	0
T40	21099	0	0	0
T45	881	1	0	0
T46	0	2	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	1	0	0
T78	0	1	0	0
T80	0	3	0	0
T92	720	0	0	0
T95	724	0	0	0
T144	0	1	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T181	0	1	0	0
T203	0	1	0	0
T232	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6052019	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6054208	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	49	0	0
T40	21099	0	0	0
T45	881	1	0	0
T46	0	2	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	1	0	0
T80	0	3	0	0
T92	720	0	0	0
T95	724	0	0	0
T143	0	1	0	0
T144	0	1	0	0
T165	0	1	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T181	0	1	0	0
T232	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	48	0	0
T40	21099	0	0	0
T45	881	1	0	0
T46	0	2	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	1	0	0
T80	0	3	0	0
T92	720	0	0	0
T95	724	0	0	0
T144	0	1	0	0
T165	0	1	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T181	0	1	0	0
T203	0	1	0	0
T232	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	47	0	0
T40	21099	0	0	0
T45	881	1	0	0
T46	0	2	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	1	0	0
T78	0	1	0	0
T80	0	3	0	0
T92	720	0	0	0
T95	724	0	0	0
T144	0	1	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T181	0	1	0	0
T203	0	1	0	0
T232	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	47	0	0
T40	21099	0	0	0
T45	881	1	0	0
T46	0	2	0	0
T49	3627	1	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	1	0	0
T78	0	1	0	0
T80	0	3	0	0
T92	720	0	0	0
T95	724	0	0	0
T144	0	1	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T181	0	1	0	0
T203	0	1	0	0
T232	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	3052	0	0
T40	21099	0	0	0
T45	881	39	0	0
T46	0	27	0	0
T49	3627	49	0	0
T52	7733	0	0	0
T62	866	0	0	0
T67	0	100	0	0
T78	0	13	0	0
T80	0	166	0	0
T92	720	0	0	0
T95	724	0	0	0
T144	0	41	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T181	0	137	0	0
T203	0	41	0	0
T232	0	206	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6387	0	0
T14	3575	3	0	0
T15	72309	0	0	0
T16	25996	37	0	0
T17	1089	0	0	0
T18	6700	31	0	0
T20	0	9	0	0
T28	424	2	0	0
T29	427	1	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	3	0	0
T55	0	2	0	0
T56	0	5	0	0
T57	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	23	0	0
T46	756	2	0	0
T54	24414	0	0	0
T80	0	1	0	0
T119	0	1	0	0
T168	0	1	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T180	0	1	0	0
T181	972	1	0	0
T190	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T211	489	0	0	0
T232	0	1	0	0
T246	544	0	0	0
T247	524	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T21,T45,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T21,T45,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T21,T45,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T45,T46
1	0	Covered	T14,T28,T29
1	1	Covered	T21,T45,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T45,T46
0	1	Covered	T66,T248
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T45,T46
0	1	Covered	T45,T46,T47
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T45,T46
1	-	Covered	T45,T46,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T45,T46
0	1	Covered	T21,T45,T46
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T45,T46
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T45,T46
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T45,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T81,T190
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T45,T46
DetectSt	-	-	-	-	1	-	-	Covered	T66,T248
DetectSt	-	-	-	-	0	1	-	Covered	T21,T45,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T46,T47
StableSt	-	-	-	-	-	-	0	Covered	T21,T45,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	119	0	0
CntIncr_A	6912820	112637	0	0
CntNoWrap_A	6912820	6250532	0	0
DetectStDropOut_A	6912820	2	0	0
DetectedOut_A	6912820	25597	0	0
DetectedPulseOut_A	6912820	53	0	0
DisabledIdleSt_A	6912820	5807963	0	0
DisabledNoDetection_A	6912820	5810161	0	0
EnterDebounceSt_A	6912820	64	0	0
EnterDetectSt_A	6912820	55	0	0
EnterStableSt_A	6912820	53	0	0
PulseIsPulse_A	6912820	53	0	0
StayInStableSt	6912820	25523	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	119	0	0
T21	571	2	0	0
T45	881	3	0	0
T46	756	2	0	0
T47	0	2	0	0
T50	0	4	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	6	0	0
T67	0	4	0	0
T80	0	2	0	0
T95	724	0	0	0
T171	505	0	0	0
T181	0	4	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	112637	0	0
T21	571	46	0	0
T45	881	188	0	0
T46	756	36	0	0
T47	0	50	0	0
T50	0	114	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	291	0	0
T67	0	66	0	0
T80	0	46	0	0
T95	724	0	0	0
T171	505	0	0	0
T181	0	130	0	0
T182	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250532	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	2	0	0
T66	36908	1	0	0
T110	4917	0	0	0
T248	0	1	0	0
T249	423	0	0	0
T250	14966	0	0	0
T251	504	0	0	0
T252	2196	0	0	0
T253	432	0	0	0
T254	522	0	0	0
T255	402	0	0	0
T256	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	25597	0	0
T21	571	116	0	0
T45	881	27	0	0
T46	756	41	0	0
T47	0	123	0	0
T50	0	184	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	249	0	0
T67	0	179	0	0
T80	0	49	0	0
T95	724	0	0	0
T171	505	0	0	0
T181	0	32	0	0
T182	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	53	0	0
T21	571	1	0	0
T45	881	1	0	0
T46	756	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T80	0	1	0	0
T95	724	0	0	0
T171	505	0	0	0
T181	0	2	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5807963	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5810161	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	64	0	0
T21	571	1	0	0
T45	881	2	0	0
T46	756	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	3	0	0
T67	0	2	0	0
T80	0	1	0	0
T95	724	0	0	0
T171	505	0	0	0
T181	0	2	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	55	0	0
T21	571	1	0	0
T45	881	1	0	0
T46	756	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	3	0	0
T67	0	2	0	0
T80	0	1	0	0
T95	724	0	0	0
T171	505	0	0	0
T181	0	2	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	53	0	0
T21	571	1	0	0
T45	881	1	0	0
T46	756	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T80	0	1	0	0
T95	724	0	0	0
T171	505	0	0	0
T181	0	2	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	53	0	0
T21	571	1	0	0
T45	881	1	0	0
T46	756	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T80	0	1	0	0
T95	724	0	0	0
T171	505	0	0	0
T181	0	2	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	25523	0	0
T21	571	114	0	0
T45	881	26	0	0
T46	756	40	0	0
T47	0	122	0	0
T50	0	182	0	0
T57	426	0	0	0
T58	685	0	0	0
T59	422	0	0	0
T60	425	0	0	0
T61	1041	0	0	0
T66	0	246	0	0
T67	0	176	0	0
T80	0	47	0	0
T95	724	0	0	0
T171	505	0	0	0
T181	0	30	0	0
T182	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	30	0	0
T45	881	1	0	0
T46	756	1	0	0
T47	867	1	0	0
T50	0	2	0	0
T54	24414	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T95	724	0	0	0
T166	0	1	0	0
T167	0	1	0	0
T171	505	0	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T181	0	2	0	0
T232	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T46,T48,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T46,T48,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T46,T48,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T46,T48
1	0	Covered	T14,T28,T29
1	1	Covered	T46,T48,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T46,T48,T47
0	1	Covered	T237
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T46,T48,T47
0	1	Covered	T181,T232,T143
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T46,T48,T47
1	-	Covered	T181,T232,T143

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T46,T48,T47
0	1	Covered	T46,T48,T47
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T46,T48,T47
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T46,T48,T47
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T46,T48,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T257
DebounceSt	-	0	0	-	-	-	-	Covered	T46,T48,T47
DetectSt	-	-	-	-	1	-	-	Covered	T237
DetectSt	-	-	-	-	0	1	-	Covered	T46,T48,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T181,T232,T143
StableSt	-	-	-	-	-	-	0	Covered	T46,T48,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	86	0	0
CntIncr_A	6912820	161566	0	0
CntNoWrap_A	6912820	6250565	0	0
DetectStDropOut_A	6912820	1	0	0
DetectedOut_A	6912820	258002	0	0
DetectedPulseOut_A	6912820	41	0	0
DisabledIdleSt_A	6912820	5616869	0	0
DisabledNoDetection_A	6912820	5619065	0	0
EnterDebounceSt_A	6912820	44	0	0
EnterDetectSt_A	6912820	42	0	0
EnterStableSt_A	6912820	41	0	0
PulseIsPulse_A	6912820	41	0	0
StayInStableSt	6912820	257942	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6912820	6430	0	0
gen_low_level_sva.LowLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	86	0	0
T46	756	2	0	0
T47	867	2	0	0
T48	615	2	0	0
T54	24414	0	0	0
T64	2095	0	0	0
T80	0	1	0	0
T81	0	2	0	0
T143	0	4	0	0
T167	0	2	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T181	0	4	0	0
T207	409	0	0	0
T232	0	4	0	0
T258	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	161566	0	0
T46	756	36	0	0
T47	867	50	0	0
T48	615	28	0	0
T54	24414	0	0	0
T64	2095	0	0	0
T80	0	62	0	0
T81	0	63180	0	0
T143	0	77578	0	0
T167	0	53	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T181	0	130	0	0
T207	409	0	0	0
T232	0	176	0	0
T258	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250565	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1	0	0
T237	1084	1	0	0
T259	791	0	0	0
T260	22526	0	0	0
T261	430	0	0	0
T262	9143	0	0	0
T263	444	0	0	0
T264	15492	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	258002	0	0
T46	756	226	0	0
T47	867	127	0	0
T48	615	40	0	0
T54	24414	0	0	0
T64	2095	0	0	0
T81	0	254695	0	0
T143	0	80	0	0
T167	0	116	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T181	0	268	0	0
T203	0	418	0	0
T207	409	0	0	0
T232	0	258	0	0
T258	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	41	0	0
T46	756	1	0	0
T47	867	1	0	0
T48	615	1	0	0
T54	24414	0	0	0
T64	2095	0	0	0
T81	0	1	0	0
T143	0	2	0	0
T167	0	1	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T181	0	2	0	0
T203	0	1	0	0
T207	409	0	0	0
T232	0	2	0	0
T258	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5616869	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5619065	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	44	0	0
T46	756	1	0	0
T47	867	1	0	0
T48	615	1	0	0
T54	24414	0	0	0
T64	2095	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T143	0	2	0	0
T167	0	1	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T181	0	2	0	0
T207	409	0	0	0
T232	0	2	0	0
T258	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	42	0	0
T46	756	1	0	0
T47	867	1	0	0
T48	615	1	0	0
T54	24414	0	0	0
T64	2095	0	0	0
T81	0	1	0	0
T143	0	2	0	0
T167	0	1	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T181	0	2	0	0
T203	0	1	0	0
T207	409	0	0	0
T232	0	2	0	0
T258	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	41	0	0
T46	756	1	0	0
T47	867	1	0	0
T48	615	1	0	0
T54	24414	0	0	0
T64	2095	0	0	0
T81	0	1	0	0
T143	0	2	0	0
T167	0	1	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T181	0	2	0	0
T203	0	1	0	0
T207	409	0	0	0
T232	0	2	0	0
T258	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	41	0	0
T46	756	1	0	0
T47	867	1	0	0
T48	615	1	0	0
T54	24414	0	0	0
T64	2095	0	0	0
T81	0	1	0	0
T143	0	2	0	0
T167	0	1	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T181	0	2	0	0
T203	0	1	0	0
T207	409	0	0	0
T232	0	2	0	0
T258	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	257942	0	0
T46	756	224	0	0
T47	867	125	0	0
T48	615	38	0	0
T54	24414	0	0	0
T64	2095	0	0	0
T81	0	254693	0	0
T143	0	77	0	0
T167	0	114	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T181	0	265	0	0
T203	0	416	0	0
T207	409	0	0	0
T232	0	255	0	0
T258	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6430	0	0
T14	3575	3	0	0
T15	72309	0	0	0
T16	25996	27	0	0
T17	1089	0	0	0
T18	6700	29	0	0
T20	0	14	0	0
T28	424	2	0	0
T29	427	2	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	1	0	0
T55	0	3	0	0
T56	0	5	0	0
T57	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	20	0	0
T66	36908	0	0	0
T119	0	2	0	0
T143	0	1	0	0
T173	0	2	0	0
T181	972	1	0	0
T182	567	0	0	0
T211	489	0	0	0
T213	0	2	0	0
T220	0	1	0	0
T231	0	2	0	0
T232	0	1	0	0
T246	544	0	0	0
T247	524	0	0	0
T249	423	0	0	0
T250	14966	0	0	0
T251	504	0	0	0
T265	0	1	0	0
T266	0	1	0	0
T267	494	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T28,T29,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T28,T29
1	0	Covered	T28,T29,T15
1	1	Covered	T28,T29,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T22,T47,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T22,T47,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T22,T47,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T22,T47
1	0	Covered	T28,T29,T15
1	1	Covered	T22,T47,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T47,T50
0	1	Covered	T80,T268
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T47,T50
0	1	Covered	T22,T47,T50
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T47,T50
1	-	Covered	T22,T47,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T47,T50
0	1	Covered	T22,T47,T50
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T47,T50
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T47,T50
IdleSt	0	-	-	-	-	-	-	Covered	T28,T29,T15
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T47,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T144,T174,T266
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T47,T50
DetectSt	-	-	-	-	1	-	-	Covered	T80,T268
DetectSt	-	-	-	-	0	1	-	Covered	T22,T47,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T47,T50
StableSt	-	-	-	-	-	-	0	Covered	T22,T47,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	130	0	0
CntIncr_A	6912820	302960	0	0
CntNoWrap_A	6912820	6250521	0	0
DetectStDropOut_A	6912820	2	0	0
DetectedOut_A	6912820	245083	0	0
DetectedPulseOut_A	6912820	60	0	0
DisabledIdleSt_A	6912820	5376052	0	0
DisabledNoDetection_A	6912820	5378245	0	0
EnterDebounceSt_A	6912820	68	0	0
EnterDetectSt_A	6912820	62	0	0
EnterStableSt_A	6912820	60	0	0
PulseIsPulse_A	6912820	60	0	0
StayInStableSt	6912820	244998	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	130	0	0
T22	4822	4	0	0
T23	5841	0	0	0
T47	0	4	0	0
T50	0	6	0	0
T80	0	2	0	0
T81	0	4	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T166	0	2	0	0
T167	0	4	0	0
T181	0	2	0	0
T192	0	6	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	302960	0	0
T22	4822	68	0	0
T23	5841	0	0	0
T47	0	100	0	0
T50	0	144	0	0
T80	0	46	0	0
T81	0	126360	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T166	0	49	0	0
T167	0	106	0	0
T181	0	65	0	0
T192	0	128	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	176	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250521	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	2	0	0
T80	1789	1	0	0
T81	341286	0	0	0
T137	1047	0	0	0
T196	428	0	0	0
T197	522	0	0	0
T232	1202	0	0	0
T233	14558	0	0	0
T234	502	0	0	0
T235	522	0	0	0
T236	403	0	0	0
T268	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	245083	0	0
T22	4822	114	0	0
T23	5841	0	0	0
T47	0	274	0	0
T50	0	283	0	0
T81	0	88112	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T166	0	182	0	0
T167	0	163	0	0
T181	0	325	0	0
T192	0	161	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T221	0	43	0	0
T232	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	60	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T47	0	2	0	0
T50	0	3	0	0
T81	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T166	0	1	0	0
T167	0	2	0	0
T181	0	1	0	0
T192	0	3	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T221	0	1	0	0
T232	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5376052	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5378245	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	68	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T47	0	2	0	0
T50	0	3	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T166	0	1	0	0
T167	0	2	0	0
T181	0	1	0	0
T192	0	3	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	62	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T47	0	2	0	0
T50	0	3	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T166	0	1	0	0
T167	0	2	0	0
T181	0	1	0	0
T192	0	3	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T232	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	60	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T47	0	2	0	0
T50	0	3	0	0
T81	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T166	0	1	0	0
T167	0	2	0	0
T181	0	1	0	0
T192	0	3	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T221	0	1	0	0
T232	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	60	0	0
T22	4822	2	0	0
T23	5841	0	0	0
T47	0	2	0	0
T50	0	3	0	0
T81	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T166	0	1	0	0
T167	0	2	0	0
T181	0	1	0	0
T192	0	3	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T221	0	1	0	0
T232	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	244998	0	0
T22	4822	111	0	0
T23	5841	0	0	0
T47	0	271	0	0
T50	0	279	0	0
T81	0	88110	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T166	0	181	0	0
T167	0	160	0	0
T181	0	323	0	0
T192	0	156	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T221	0	42	0	0
T232	0	45	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	33	0	0
T22	4822	1	0	0
T23	5841	0	0	0
T47	0	1	0	0
T50	0	2	0	0
T81	0	2	0	0
T82	713	0	0	0
T94	1531	0	0	0
T101	404	0	0	0
T102	405	0	0	0
T103	8402	0	0	0
T166	0	1	0	0
T167	0	1	0	0
T192	0	1	0	0
T193	740	0	0	0
T194	422	0	0	0
T195	585	0	0	0
T212	0	2	0	0
T221	0	1	0	0
T232	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T28,T29,T15
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T15
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T45,T46,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T45,T46,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T45,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T48
1	0	Covered	T14,T28,T29
1	1	Covered	T45,T46,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T47
0	1	Covered	T81,T237
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T47
0	1	Covered	T45,T47,T66
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T46,T47
1	-	Covered	T45,T47,T66

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T46,T47
0	1	Covered	T45,T46,T47
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T46,T47
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T46,T47
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T269
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T46,T47
DetectSt	-	-	-	-	1	-	-	Covered	T81,T237
DetectSt	-	-	-	-	0	1	-	Covered	T45,T46,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T47,T66
StableSt	-	-	-	-	-	-	0	Covered	T45,T46,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	81	0	0
CntIncr_A	6912820	251579	0	0
CntNoWrap_A	6912820	6250570	0	0
DetectStDropOut_A	6912820	2	0	0
DetectedOut_A	6912820	3085	0	0
DetectedPulseOut_A	6912820	38	0	0
DisabledIdleSt_A	6912820	5422688	0	0
DisabledNoDetection_A	6912820	5424874	0	0
EnterDebounceSt_A	6912820	41	0	0
EnterDetectSt_A	6912820	40	0	0
EnterStableSt_A	6912820	38	0	0
PulseIsPulse_A	6912820	38	0	0
StayInStableSt	6912820	3028	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6912820	7124	0	0
gen_low_level_sva.LowLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	81	0	0
T45	881	4	0	0
T46	756	2	0	0
T47	867	2	0	0
T54	24414	0	0	0
T66	0	4	0	0
T67	0	2	0	0
T80	0	2	0	0
T81	0	4	0	0
T95	724	0	0	0
T165	0	2	0	0
T166	0	2	0	0
T171	505	0	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	251579	0	0
T45	881	188	0	0
T46	756	36	0	0
T47	867	50	0	0
T54	24414	0	0	0
T66	0	194	0	0
T67	0	33	0	0
T80	0	62	0	0
T81	0	126360	0	0
T95	724	0	0	0
T165	0	90	0	0
T166	0	49	0	0
T171	505	0	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T182	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6250570	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	2	0	0
T81	341286	1	0	0
T196	428	0	0	0
T197	522	0	0	0
T237	1084	1	0	0
T259	791	0	0	0
T260	22526	0	0	0
T261	430	0	0	0
T262	9143	0	0	0
T263	444	0	0	0
T264	15492	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	3085	0	0
T45	881	84	0	0
T46	756	81	0	0
T47	867	32	0	0
T54	24414	0	0	0
T66	0	245	0	0
T67	0	99	0	0
T80	0	77	0	0
T81	0	42	0	0
T95	724	0	0	0
T165	0	53	0	0
T166	0	43	0	0
T171	505	0	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T182	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	38	0	0
T45	881	2	0	0
T46	756	1	0	0
T47	867	1	0	0
T54	24414	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T95	724	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T171	505	0	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5422688	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5424874	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	41	0	0
T45	881	2	0	0
T46	756	1	0	0
T47	867	1	0	0
T54	24414	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0
T95	724	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T171	505	0	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	40	0	0
T45	881	2	0	0
T46	756	1	0	0
T47	867	1	0	0
T54	24414	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0
T95	724	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T171	505	0	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	38	0	0
T45	881	2	0	0
T46	756	1	0	0
T47	867	1	0	0
T54	24414	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T95	724	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T171	505	0	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	38	0	0
T45	881	2	0	0
T46	756	1	0	0
T47	867	1	0	0
T54	24414	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T95	724	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T171	505	0	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	3028	0	0
T45	881	81	0	0
T46	756	79	0	0
T47	867	31	0	0
T54	24414	0	0	0
T66	0	242	0	0
T67	0	98	0	0
T80	0	75	0	0
T81	0	40	0	0
T95	724	0	0	0
T165	0	51	0	0
T166	0	41	0	0
T171	505	0	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T178	425	0	0	0
T182	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	7124	0	0
T15	72309	1	0	0
T16	25996	25	0	0
T17	1089	5	0	0
T18	6700	25	0	0
T19	96134	0	0	0
T20	0	21	0	0
T28	424	3	0	0
T29	427	2	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	3	0	0
T55	0	3	0	0
T56	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	17	0	0
T45	881	1	0	0
T47	867	1	0	0
T65	1640	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T76	5942	0	0	0
T95	724	0	0	0
T100	698	0	0	0
T108	4670	0	0	0
T117	0	1	0	0
T168	0	1	0	0
T171	505	0	0	0
T172	0	1	0	0
T180	0	1	0	0
T192	0	1	0	0
T208	507	0	0	0
T209	506	0	0	0
T213	0	1	0	0