Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T23
1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T23
1	0	Covered	T16,T18,T23
1	1	Covered	T16,T18,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T23
0	1	Covered	T23,T52,T104
1	0	Covered	T23,T52,T43

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T41
0	1	Covered	T16,T18,T41
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T41
1	-	Covered	T16,T18,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T18,T23
0	1	Covered	T16,T18,T23
0	0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T23
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T23
IdleSt	0	-	-	-	-	-	-	Covered	T16,T18,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T270,T78,T271
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T23
DetectSt	-	-	-	-	1	-	-	Covered	T23,T52,T43
DetectSt	-	-	-	-	0	1	-	Covered	T16,T18,T41
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T23
StableSt	-	-	-	-	-	-	1	Covered	T16,T18,T41
StableSt	-	-	-	-	-	-	0	Covered	T16,T18,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	3339	0	0
CntIncr_A	6912820	120297	0	0
CntNoWrap_A	6912820	6247312	0	0
DetectStDropOut_A	6912820	439	0	0
DetectedOut_A	6912820	69779	0	0
DetectedPulseOut_A	6912820	985	0	0
DisabledIdleSt_A	6912820	5789917	0	0
DisabledNoDetection_A	6912820	5791984	0	0
EnterDebounceSt_A	6912820	1680	0	0
EnterDetectSt_A	6912820	1661	0	0
EnterStableSt_A	6912820	985	0	0
PulseIsPulse_A	6912820	985	0	0
StayInStableSt	6912820	68709	0	0
gen_high_event_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	881	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	3339	0	0
T16	25996	14	0	0
T17	1089	0	0	0
T18	6700	48	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	34	0	0
T32	416	0	0	0
T41	0	22	0	0
T43	0	8	0	0
T52	0	46	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	54	0	0
T105	0	52	0	0
T106	0	38	0	0
T159	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	120297	0	0
T16	25996	462	0	0
T17	1089	0	0	0
T18	6700	1320	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	842	0	0
T32	416	0	0	0
T41	0	561	0	0
T43	0	572	0	0
T52	0	1695	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	1756	0	0
T105	0	1783	0	0
T106	0	1026	0	0
T159	0	2604	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6247312	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25521	0	0
T17	1089	688	0	0
T18	6700	6251	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	439	0	0
T23	5841	10	0	0
T40	21099	0	0	0
T45	881	0	0	0
T49	3627	0	0	0
T52	7733	6	0	0
T62	866	0	0	0
T92	720	0	0	0
T103	8402	0	0	0
T104	0	22	0	0
T105	0	11	0	0
T106	0	19	0	0
T107	0	5	0	0
T108	0	11	0	0
T109	0	2	0	0
T110	0	5	0	0
T111	0	20	0	0
T169	454	0	0	0
T170	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	69779	0	0
T16	25996	623	0	0
T17	1089	0	0	0
T18	6700	93	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T41	0	2816	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	927	0	0
T159	0	1786	0	0
T216	0	78	0	0
T218	0	2457	0	0
T272	0	1982	0	0
T273	0	704	0	0
T274	0	34	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	985	0	0
T16	25996	7	0	0
T17	1089	0	0	0
T18	6700	24	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T41	0	11	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	27	0	0
T159	0	12	0	0
T216	0	1	0	0
T218	0	30	0	0
T272	0	23	0	0
T273	0	17	0	0
T274	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5789917	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	20290	0	0
T17	1089	688	0	0
T18	6700	3213	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5791984	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	20297	0	0
T17	1089	689	0	0
T18	6700	3213	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1680	0	0
T16	25996	7	0	0
T17	1089	0	0	0
T18	6700	24	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	17	0	0
T32	416	0	0	0
T41	0	11	0	0
T43	0	4	0	0
T52	0	23	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	27	0	0
T105	0	26	0	0
T106	0	19	0	0
T159	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1661	0	0
T16	25996	7	0	0
T17	1089	0	0	0
T18	6700	24	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	17	0	0
T32	416	0	0	0
T41	0	11	0	0
T43	0	4	0	0
T52	0	23	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	27	0	0
T105	0	26	0	0
T106	0	19	0	0
T159	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	985	0	0
T16	25996	7	0	0
T17	1089	0	0	0
T18	6700	24	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T41	0	11	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	27	0	0
T159	0	12	0	0
T216	0	1	0	0
T218	0	30	0	0
T272	0	23	0	0
T273	0	17	0	0
T274	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	985	0	0
T16	25996	7	0	0
T17	1089	0	0	0
T18	6700	24	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T41	0	11	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	27	0	0
T159	0	12	0	0
T216	0	1	0	0
T218	0	30	0	0
T272	0	23	0	0
T273	0	17	0	0
T274	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	68709	0	0
T16	25996	615	0	0
T17	1089	0	0	0
T18	6700	69	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T41	0	2799	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	900	0	0
T159	0	1772	0	0
T216	0	76	0	0
T218	0	2426	0	0
T272	0	1959	0	0
T273	0	687	0	0
T274	0	33	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	881	0	0
T16	25996	6	0	0
T17	1089	0	0	0
T18	6700	24	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T41	0	5	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	27	0	0
T159	0	10	0	0
T218	0	29	0	0
T272	0	23	0	0
T273	0	17	0	0
T274	0	1	0	0
T275	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T16,T18
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T18
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T16,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T14,T16,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T14,T16,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T18
1	0	Covered	T14,T16,T18
1	1	Covered	T14,T16,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T20
0	1	Covered	T76,T67,T112
1	0	Covered	T78,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T20
0	1	Covered	T14,T16,T20
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T16,T20
1	-	Covered	T14,T16,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T16,T20
0	1	Covered	T14,T16,T20
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T20
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T16,T20
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T16,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T20,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T16,T20
DetectSt	-	-	-	-	1	-	-	Covered	T76,T67,T112
DetectSt	-	-	-	-	0	1	-	Covered	T14,T16,T20
DetectSt	-	-	-	-	0	0	-	Covered	T14,T16,T20
StableSt	-	-	-	-	-	-	1	Covered	T14,T16,T20
StableSt	-	-	-	-	-	-	0	Covered	T14,T16,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	964	0	0
CntIncr_A	6912820	53082	0	0
CntNoWrap_A	6912820	6249687	0	0
DetectStDropOut_A	6912820	80	0	0
DetectedOut_A	6912820	12627	0	0
DetectedPulseOut_A	6912820	348	0	0
DisabledIdleSt_A	6912820	5868331	0	0
DisabledNoDetection_A	6912820	5869880	0	0
EnterDebounceSt_A	6912820	532	0	0
EnterDetectSt_A	6912820	432	0	0
EnterStableSt_A	6912820	348	0	0
PulseIsPulse_A	6912820	348	0	0
StayInStableSt	6912820	12245	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	312	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	964	0	0
T14	3575	5	0	0
T15	72309	0	0	0
T16	25996	4	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T20	0	8	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T40	0	23	0	0
T41	0	12	0	0
T42	0	6	0	0
T51	0	1	0	0
T54	0	7	0	0
T94	0	1	0	0
T98	0	21	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	53082	0	0
T14	3575	70	0	0
T15	72309	0	0	0
T16	25996	102	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T20	0	444	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T40	0	1463	0	0
T41	0	486	0	0
T42	0	525	0	0
T51	0	20	0	0
T54	0	289	0	0
T94	0	20	0	0
T98	0	1597	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6249687	0	0
T14	3575	662	0	0
T15	72309	71908	0	0
T16	25996	25531	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	80	0	0
T67	29422	3	0	0
T76	5942	1	0	0
T109	5372	0	0	0
T112	8436	9	0	0
T113	0	6	0	0
T114	0	3	0	0
T115	0	7	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	5	0	0
T119	0	1	0	0
T121	177592	0	0	0
T122	427	0	0	0
T123	403	0	0	0
T124	492	0	0	0
T125	522	0	0	0
T126	6466	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	12627	0	0
T14	3575	8	0	0
T15	72309	0	0	0
T16	25996	168	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T20	0	113	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T40	0	266	0	0
T41	0	428	0	0
T42	0	25	0	0
T44	0	344	0	0
T50	0	57	0	0
T54	0	174	0	0
T98	0	214	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	348	0	0
T14	3575	2	0	0
T15	72309	0	0	0
T16	25996	2	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T20	0	3	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T40	0	10	0	0
T41	0	6	0	0
T42	0	3	0	0
T44	0	7	0	0
T50	0	8	0	0
T54	0	3	0	0
T98	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5868331	0	0
T14	3575	484	0	0
T15	72309	71908	0	0
T16	25996	24913	0	0
T17	1089	688	0	0
T18	6700	6206	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5869880	0	0
T14	3575	489	0	0
T15	72309	71909	0	0
T16	25996	24921	0	0
T17	1089	689	0	0
T18	6700	6207	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	532	0	0
T14	3575	3	0	0
T15	72309	0	0	0
T16	25996	2	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T20	0	5	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T40	0	13	0	0
T41	0	6	0	0
T42	0	3	0	0
T51	0	1	0	0
T54	0	4	0	0
T94	0	1	0	0
T98	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	432	0	0
T14	3575	2	0	0
T15	72309	0	0	0
T16	25996	2	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T20	0	3	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T40	0	10	0	0
T41	0	6	0	0
T42	0	3	0	0
T44	0	7	0	0
T54	0	3	0	0
T76	0	1	0	0
T98	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	348	0	0
T14	3575	2	0	0
T15	72309	0	0	0
T16	25996	2	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T20	0	3	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T40	0	10	0	0
T41	0	6	0	0
T42	0	3	0	0
T44	0	7	0	0
T50	0	8	0	0
T54	0	3	0	0
T98	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	348	0	0
T14	3575	2	0	0
T15	72309	0	0	0
T16	25996	2	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T20	0	3	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T40	0	10	0	0
T41	0	6	0	0
T42	0	3	0	0
T44	0	7	0	0
T50	0	8	0	0
T54	0	3	0	0
T98	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	12245	0	0
T14	3575	6	0	0
T15	72309	0	0	0
T16	25996	166	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T20	0	110	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T40	0	256	0	0
T41	0	422	0	0
T42	0	22	0	0
T44	0	337	0	0
T50	0	49	0	0
T54	0	171	0	0
T98	0	204	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	312	0	0
T14	3575	2	0	0
T15	72309	0	0	0
T16	25996	2	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T20	0	3	0	0
T28	424	0	0	0
T29	427	0	0	0
T30	8402	0	0	0
T31	622	0	0	0
T32	416	0	0	0
T40	0	10	0	0
T41	0	6	0	0
T42	0	3	0	0
T44	0	7	0	0
T50	0	8	0	0
T54	0	3	0	0
T98	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T23
1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T23
1	0	Covered	T16,T18,T23
1	1	Covered	T16,T18,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T23
0	1	Covered	T16,T23,T104
1	0	Covered	T16,T18,T23

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T52,T41,T43
0	1	Covered	T52,T41,T43
1	0	Covered	T83,T276

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T52,T41,T43
1	-	Covered	T52,T41,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T18,T23
0	1	Covered	T16,T18,T23
0	0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T23
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T23
IdleSt	0	-	-	-	-	-	-	Covered	T16,T18,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T270,T78,T271
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T23
DetectSt	-	-	-	-	1	-	-	Covered	T16,T18,T23
DetectSt	-	-	-	-	0	1	-	Covered	T52,T41,T43
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T23
StableSt	-	-	-	-	-	-	1	Covered	T52,T41,T43
StableSt	-	-	-	-	-	-	0	Covered	T52,T41,T43
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	3092	0	0
CntIncr_A	6912820	109128	0	0
CntNoWrap_A	6912820	6247559	0	0
DetectStDropOut_A	6912820	441	0	0
DetectedOut_A	6912820	68225	0	0
DetectedPulseOut_A	6912820	931	0	0
DisabledIdleSt_A	6912820	5793969	0	0
DisabledNoDetection_A	6912820	5796044	0	0
EnterDebounceSt_A	6912820	1554	0	0
EnterDetectSt_A	6912820	1541	0	0
EnterStableSt_A	6912820	931	0	0
PulseIsPulse_A	6912820	931	0	0
StayInStableSt	6912820	67217	0	0
gen_high_event_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	838	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	3092	0	0
T16	25996	12	0	0
T17	1089	0	0	0
T18	6700	34	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	50	0	0
T32	416	0	0	0
T41	0	24	0	0
T43	0	58	0	0
T52	0	12	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	16	0	0
T105	0	48	0	0
T106	0	2	0	0
T159	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	109128	0	0
T16	25996	546	0	0
T17	1089	0	0	0
T18	6700	961	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	1225	0	0
T32	416	0	0	0
T41	0	564	0	0
T43	0	2175	0	0
T52	0	408	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	517	0	0
T105	0	1416	0	0
T106	0	53	0	0
T159	0	4906	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6247559	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25523	0	0
T17	1089	688	0	0
T18	6700	6265	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	441	0	0
T16	25996	3	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	23	0	0
T32	416	0	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	12	0	0
T104	0	4	0	0
T106	0	1	0	0
T108	0	14	0	0
T109	0	7	0	0
T110	0	22	0	0
T111	0	11	0	0
T277	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	68225	0	0
T41	32730	1825	0	0
T43	10812	2980	0	0
T45	881	0	0	0
T52	7733	44	0	0
T68	492	0	0	0
T95	724	0	0	0
T104	7497	0	0	0
T105	0	2148	0	0
T107	0	626	0	0
T159	0	4363	0	0
T171	505	0	0	0
T218	0	909	0	0
T272	0	820	0	0
T273	0	40	0	0
T274	0	3243	0	0
T278	8424	0	0	0
T279	790	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	931	0	0
T41	32730	12	0	0
T43	10812	29	0	0
T45	881	0	0	0
T52	7733	6	0	0
T68	492	0	0	0
T95	724	0	0	0
T104	7497	0	0	0
T105	0	24	0	0
T107	0	13	0	0
T159	0	22	0	0
T171	505	0	0	0
T218	0	11	0	0
T272	0	15	0	0
T273	0	15	0	0
T274	0	31	0	0
T278	8424	0	0	0
T279	790	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5793969	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	20745	0	0
T17	1089	688	0	0
T18	6700	3297	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5796044	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	20753	0	0
T17	1089	689	0	0
T18	6700	3297	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1554	0	0
T16	25996	6	0	0
T17	1089	0	0	0
T18	6700	17	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	25	0	0
T32	416	0	0	0
T41	0	12	0	0
T43	0	29	0	0
T52	0	6	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	8	0	0
T105	0	24	0	0
T106	0	1	0	0
T159	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1541	0	0
T16	25996	6	0	0
T17	1089	0	0	0
T18	6700	17	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	25	0	0
T32	416	0	0	0
T41	0	12	0	0
T43	0	29	0	0
T52	0	6	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	8	0	0
T105	0	24	0	0
T106	0	1	0	0
T159	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	931	0	0
T41	32730	12	0	0
T43	10812	29	0	0
T45	881	0	0	0
T52	7733	6	0	0
T68	492	0	0	0
T95	724	0	0	0
T104	7497	0	0	0
T105	0	24	0	0
T107	0	13	0	0
T159	0	22	0	0
T171	505	0	0	0
T218	0	11	0	0
T272	0	15	0	0
T273	0	15	0	0
T274	0	31	0	0
T278	8424	0	0	0
T279	790	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	931	0	0
T41	32730	12	0	0
T43	10812	29	0	0
T45	881	0	0	0
T52	7733	6	0	0
T68	492	0	0	0
T95	724	0	0	0
T104	7497	0	0	0
T105	0	24	0	0
T107	0	13	0	0
T159	0	22	0	0
T171	505	0	0	0
T218	0	11	0	0
T272	0	15	0	0
T273	0	15	0	0
T274	0	31	0	0
T278	8424	0	0	0
T279	790	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	67217	0	0
T41	32730	1807	0	0
T43	10812	2951	0	0
T45	881	0	0	0
T52	7733	38	0	0
T68	492	0	0	0
T95	724	0	0	0
T104	7497	0	0	0
T105	0	2121	0	0
T107	0	608	0	0
T159	0	4336	0	0
T171	505	0	0	0
T218	0	898	0	0
T272	0	805	0	0
T273	0	25	0	0
T274	0	3211	0	0
T278	8424	0	0	0
T279	790	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	838	0	0
T41	32730	6	0	0
T43	10812	29	0	0
T45	881	0	0	0
T52	7733	6	0	0
T68	492	0	0	0
T95	724	0	0	0
T104	7497	0	0	0
T105	0	21	0	0
T107	0	8	0	0
T159	0	17	0	0
T171	505	0	0	0
T218	0	11	0	0
T272	0	15	0	0
T273	0	15	0	0
T274	0	30	0	0
T278	8424	0	0	0
T279	790	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T20
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T40,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T40,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T40,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T40,T52
1	0	Covered	T14,T16,T18
1	1	Covered	T40,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Covered	T50,T77,T66
1	0	Covered	T78,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Covered	T40,T41,T42
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T41,T42
1	-	Covered	T40,T41,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T41,T42
0	1	Covered	T40,T41,T42
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T42
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T42,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T50,T77,T66
DetectSt	-	-	-	-	0	1	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	0	0	-	Covered	T40,T41,T42
StableSt	-	-	-	-	-	-	1	Covered	T40,T41,T42
StableSt	-	-	-	-	-	-	0	Covered	T40,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	892	0	0
CntIncr_A	6912820	52961	0	0
CntNoWrap_A	6912820	6249759	0	0
DetectStDropOut_A	6912820	92	0	0
DetectedOut_A	6912820	13153	0	0
DetectedPulseOut_A	6912820	320	0	0
DisabledIdleSt_A	6912820	5859381	0	0
DisabledNoDetection_A	6912820	5860996	0	0
EnterDebounceSt_A	6912820	476	0	0
EnterDetectSt_A	6912820	418	0	0
EnterStableSt_A	6912820	320	0	0
PulseIsPulse_A	6912820	320	0	0
StayInStableSt	6912820	12803	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	288	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	892	0	0
T40	21099	15	0	0
T41	32730	8	0	0
T42	0	18	0	0
T44	0	18	0	0
T45	881	0	0	0
T50	0	12	0	0
T52	7733	0	0	0
T54	0	19	0	0
T68	492	0	0	0
T95	724	0	0	0
T98	0	19	0	0
T105	0	6	0	0
T107	0	10	0	0
T159	0	8	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T278	8424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	52961	0	0
T40	21099	1069	0	0
T41	32730	272	0	0
T42	0	1420	0	0
T44	0	2356	0	0
T45	881	0	0	0
T50	0	777	0	0
T52	7733	0	0	0
T54	0	1033	0	0
T68	492	0	0	0
T95	724	0	0	0
T98	0	1257	0	0
T105	0	213	0	0
T107	0	170	0	0
T159	0	944	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T278	8424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6249759	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	92	0	0
T50	47826	2	0	0
T66	0	13	0	0
T77	0	11	0	0
T114	0	7	0	0
T119	0	2	0	0
T214	491	0	0	0
T215	496	0	0	0
T216	504	0	0	0
T217	406	0	0	0
T218	11491	0	0	0
T219	491	0	0	0
T264	0	6	0	0
T280	0	4	0	0
T281	0	2	0	0
T282	0	7	0	0
T283	0	1	0	0
T284	404	0	0	0
T285	521	0	0	0
T286	481	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	13153	0	0
T40	21099	70	0	0
T41	32730	336	0	0
T42	0	191	0	0
T44	0	373	0	0
T45	881	0	0	0
T50	0	19	0	0
T52	7733	0	0	0
T54	0	237	0	0
T68	492	0	0	0
T95	724	0	0	0
T98	0	384	0	0
T105	0	205	0	0
T107	0	155	0	0
T159	0	297	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T278	8424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	320	0	0
T40	21099	7	0	0
T41	32730	4	0	0
T42	0	8	0	0
T44	0	8	0	0
T45	881	0	0	0
T50	0	4	0	0
T52	7733	0	0	0
T54	0	9	0	0
T68	492	0	0	0
T95	724	0	0	0
T98	0	9	0	0
T105	0	3	0	0
T107	0	5	0	0
T159	0	4	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T278	8424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5859381	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25535	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5860996	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	476	0	0
T40	21099	8	0	0
T41	32730	4	0	0
T42	0	10	0	0
T44	0	10	0	0
T45	881	0	0	0
T50	0	6	0	0
T52	7733	0	0	0
T54	0	10	0	0
T68	492	0	0	0
T95	724	0	0	0
T98	0	10	0	0
T105	0	3	0	0
T107	0	5	0	0
T159	0	4	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T278	8424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	418	0	0
T40	21099	7	0	0
T41	32730	4	0	0
T42	0	8	0	0
T44	0	8	0	0
T45	881	0	0	0
T50	0	6	0	0
T52	7733	0	0	0
T54	0	9	0	0
T68	492	0	0	0
T95	724	0	0	0
T98	0	9	0	0
T105	0	3	0	0
T107	0	5	0	0
T159	0	4	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T278	8424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	320	0	0
T40	21099	7	0	0
T41	32730	4	0	0
T42	0	8	0	0
T44	0	8	0	0
T45	881	0	0	0
T50	0	4	0	0
T52	7733	0	0	0
T54	0	9	0	0
T68	492	0	0	0
T95	724	0	0	0
T98	0	9	0	0
T105	0	3	0	0
T107	0	5	0	0
T159	0	4	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T278	8424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	320	0	0
T40	21099	7	0	0
T41	32730	4	0	0
T42	0	8	0	0
T44	0	8	0	0
T45	881	0	0	0
T50	0	4	0	0
T52	7733	0	0	0
T54	0	9	0	0
T68	492	0	0	0
T95	724	0	0	0
T98	0	9	0	0
T105	0	3	0	0
T107	0	5	0	0
T159	0	4	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T278	8424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	12803	0	0
T40	21099	63	0	0
T41	32730	332	0	0
T42	0	183	0	0
T44	0	365	0	0
T45	881	0	0	0
T50	0	15	0	0
T52	7733	0	0	0
T54	0	228	0	0
T68	492	0	0	0
T95	724	0	0	0
T98	0	375	0	0
T105	0	199	0	0
T107	0	150	0	0
T159	0	293	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T278	8424	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	288	0	0
T40	21099	7	0	0
T41	32730	4	0	0
T42	0	8	0	0
T44	0	8	0	0
T45	881	0	0	0
T50	0	4	0	0
T52	7733	0	0	0
T54	0	9	0	0
T68	492	0	0	0
T95	724	0	0	0
T98	0	9	0	0
T107	0	5	0	0
T159	0	4	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T218	0	1	0	0
T278	8424	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T23
1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T23
1	0	Covered	T16,T18,T23
1	1	Covered	T16,T18,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T23
0	1	Covered	T23,T41,T106
1	0	Covered	T18,T23,T41

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T52,T43
0	1	Covered	T16,T52,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T52,T43
1	-	Covered	T16,T52,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T18,T23
0	1	Covered	T16,T18,T23
0	0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T23
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T23
IdleSt	0	-	-	-	-	-	-	Covered	T16,T18,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T270,T78,T271
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T23
DetectSt	-	-	-	-	1	-	-	Covered	T18,T23,T41
DetectSt	-	-	-	-	0	1	-	Covered	T16,T52,T43
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T23
StableSt	-	-	-	-	-	-	1	Covered	T16,T52,T43
StableSt	-	-	-	-	-	-	0	Covered	T16,T52,T43
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	2985	0	0
CntIncr_A	6912820	105959	0	0
CntNoWrap_A	6912820	6247666	0	0
DetectStDropOut_A	6912820	465	0	0
DetectedOut_A	6912820	52655	0	0
DetectedPulseOut_A	6912820	739	0	0
DisabledIdleSt_A	6912820	5805216	0	0
DisabledNoDetection_A	6912820	5807322	0	0
EnterDebounceSt_A	6912820	1499	0	0
EnterDetectSt_A	6912820	1487	0	0
EnterStableSt_A	6912820	739	0	0
PulseIsPulse_A	6912820	739	0	0
StayInStableSt	6912820	51868	0	0
gen_high_event_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	691	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	2985	0	0
T16	25996	20	0	0
T17	1089	0	0	0
T18	6700	8	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	32	0	0
T32	416	0	0	0
T41	0	56	0	0
T43	0	56	0	0
T52	0	16	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	18	0	0
T105	0	28	0	0
T106	0	26	0	0
T159	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	105959	0	0
T16	25996	490	0	0
T17	1089	0	0	0
T18	6700	226	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	782	0	0
T32	416	0	0	0
T41	0	2507	0	0
T43	0	2772	0	0
T52	0	312	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	504	0	0
T105	0	960	0	0
T106	0	694	0	0
T159	0	3495	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6247666	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25515	0	0
T17	1089	688	0	0
T18	6700	6291	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	465	0	0
T23	5841	13	0	0
T40	21099	0	0	0
T41	0	16	0	0
T45	881	0	0	0
T49	3627	0	0	0
T52	7733	0	0	0
T62	866	0	0	0
T92	720	0	0	0
T103	8402	0	0	0
T106	0	13	0	0
T108	0	6	0	0
T109	0	24	0	0
T110	0	10	0	0
T111	0	5	0	0
T126	0	16	0	0
T169	454	0	0	0
T170	502	0	0	0
T277	0	11	0	0
T287	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	52655	0	0
T16	25996	1848	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T43	0	2227	0	0
T52	0	292	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	609	0	0
T104	0	1702	0	0
T218	0	134	0	0
T272	0	775	0	0
T273	0	749	0	0
T274	0	146	0	0
T275	0	874	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	739	0	0
T16	25996	10	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T43	0	28	0	0
T52	0	8	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	15	0	0
T104	0	9	0	0
T218	0	7	0	0
T272	0	22	0	0
T273	0	25	0	0
T274	0	4	0	0
T275	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5805216	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	19319	0	0
T17	1089	688	0	0
T18	6700	3297	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5807322	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	19323	0	0
T17	1089	689	0	0
T18	6700	3297	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1499	0	0
T16	25996	10	0	0
T17	1089	0	0	0
T18	6700	4	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	16	0	0
T32	416	0	0	0
T41	0	28	0	0
T43	0	28	0	0
T52	0	8	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	9	0	0
T105	0	14	0	0
T106	0	13	0	0
T159	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1487	0	0
T16	25996	10	0	0
T17	1089	0	0	0
T18	6700	4	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	16	0	0
T32	416	0	0	0
T41	0	28	0	0
T43	0	28	0	0
T52	0	8	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	9	0	0
T105	0	14	0	0
T106	0	13	0	0
T159	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	739	0	0
T16	25996	10	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T43	0	28	0	0
T52	0	8	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	15	0	0
T104	0	9	0	0
T218	0	7	0	0
T272	0	22	0	0
T273	0	25	0	0
T274	0	4	0	0
T275	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	739	0	0
T16	25996	10	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T43	0	28	0	0
T52	0	8	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	15	0	0
T104	0	9	0	0
T218	0	7	0	0
T272	0	22	0	0
T273	0	25	0	0
T274	0	4	0	0
T275	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	51868	0	0
T16	25996	1834	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T43	0	2199	0	0
T52	0	284	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	594	0	0
T104	0	1693	0	0
T218	0	127	0	0
T272	0	753	0	0
T273	0	722	0	0
T274	0	142	0	0
T275	0	851	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	691	0	0
T16	25996	6	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T43	0	28	0	0
T52	0	8	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T76	0	15	0	0
T104	0	9	0	0
T218	0	7	0	0
T272	0	22	0	0
T273	0	23	0	0
T274	0	4	0	0
T275	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T20
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T40,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T16,T40,T43

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T40,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T20,T40
1	0	Covered	T14,T16,T18
1	1	Covered	T16,T40,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T40,T43
0	1	Covered	T50,T77,T66
1	0	Covered	T78,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T40,T43
0	1	Covered	T16,T40,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T40,T43
1	-	Covered	T16,T40,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T40,T43
0	1	Covered	T16,T40,T43
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T40,T43
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T40,T43
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T40,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T42,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T40,T43
DetectSt	-	-	-	-	1	-	-	Covered	T50,T77,T66
DetectSt	-	-	-	-	0	1	-	Covered	T16,T40,T43
DetectSt	-	-	-	-	0	0	-	Covered	T16,T40,T43
StableSt	-	-	-	-	-	-	1	Covered	T16,T40,T43
StableSt	-	-	-	-	-	-	0	Covered	T16,T40,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	773	0	0
CntIncr_A	6912820	48902	0	0
CntNoWrap_A	6912820	6249878	0	0
DetectStDropOut_A	6912820	56	0	0
DetectedOut_A	6912820	10081	0	0
DetectedPulseOut_A	6912820	299	0	0
DisabledIdleSt_A	6912820	5888490	0	0
DisabledNoDetection_A	6912820	5890162	0	0
EnterDebounceSt_A	6912820	414	0	0
EnterDetectSt_A	6912820	360	0	0
EnterStableSt_A	6912820	299	0	0
PulseIsPulse_A	6912820	299	0	0
StayInStableSt	6912820	9764	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	279	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	773	0	0
T16	25996	3	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T40	0	8	0	0
T42	0	10	0	0
T43	0	6	0	0
T44	0	13	0	0
T50	0	20	0	0
T54	0	2	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T66	0	4	0	0
T77	0	12	0	0
T273	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	48902	0	0
T16	25996	118	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T40	0	520	0	0
T42	0	744	0	0
T43	0	216	0	0
T44	0	1466	0	0
T50	0	1299	0	0
T54	0	78	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T66	0	166	0	0
T77	0	1125	0	0
T273	0	178	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6249878	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25532	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	56	0	0
T50	47826	6	0	0
T66	0	2	0	0
T77	0	6	0	0
T214	491	0	0	0
T215	496	0	0	0
T216	504	0	0	0
T217	406	0	0	0
T218	11491	0	0	0
T219	491	0	0	0
T284	404	0	0	0
T285	521	0	0	0
T286	481	0	0	0
T288	0	5	0	0
T289	0	4	0	0
T290	0	1	0	0
T291	0	2	0	0
T292	0	2	0	0
T293	0	4	0	0
T294	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	10081	0	0
T16	25996	51	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T40	0	92	0	0
T42	0	130	0	0
T43	0	51	0	0
T44	0	497	0	0
T50	0	28	0	0
T54	0	55	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T67	0	5	0	0
T250	0	129	0	0
T273	0	119	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	299	0	0
T16	25996	1	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T40	0	4	0	0
T42	0	4	0	0
T43	0	3	0	0
T44	0	6	0	0
T50	0	3	0	0
T54	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T67	0	1	0	0
T250	0	4	0	0
T273	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5888490	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	23691	0	0
T17	1089	688	0	0
T18	6700	6299	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5890162	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	23696	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	414	0	0
T16	25996	2	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T40	0	4	0	0
T42	0	6	0	0
T43	0	3	0	0
T44	0	7	0	0
T50	0	11	0	0
T54	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T66	0	2	0	0
T77	0	6	0	0
T273	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	360	0	0
T16	25996	1	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T40	0	4	0	0
T42	0	4	0	0
T43	0	3	0	0
T44	0	6	0	0
T50	0	9	0	0
T54	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T66	0	2	0	0
T77	0	6	0	0
T273	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	299	0	0
T16	25996	1	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T40	0	4	0	0
T42	0	4	0	0
T43	0	3	0	0
T44	0	6	0	0
T50	0	3	0	0
T54	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T67	0	1	0	0
T250	0	4	0	0
T273	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	299	0	0
T16	25996	1	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T40	0	4	0	0
T42	0	4	0	0
T43	0	3	0	0
T44	0	6	0	0
T50	0	3	0	0
T54	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T67	0	1	0	0
T250	0	4	0	0
T273	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	9764	0	0
T16	25996	50	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T40	0	88	0	0
T42	0	126	0	0
T43	0	48	0	0
T44	0	491	0	0
T50	0	25	0	0
T54	0	54	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T67	0	4	0	0
T250	0	125	0	0
T273	0	117	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	279	0	0
T16	25996	1	0	0
T17	1089	0	0	0
T18	6700	0	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T32	416	0	0	0
T40	0	4	0	0
T42	0	4	0	0
T43	0	3	0	0
T44	0	6	0	0
T50	0	3	0	0
T54	0	1	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T67	0	1	0	0
T250	0	4	0	0
T273	0	2	0	0