Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T23
1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T23
1	0	Covered	T16,T18,T52
1	1	Covered	T16,T18,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T23
0	1	Covered	T104,T106,T108
1	0	Covered	T104,T105,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T23
0	1	Covered	T16,T18,T23
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T23
1	-	Covered	T16,T18,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T18,T23
0	1	Covered	T16,T18,T23
0	0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T23
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T23
IdleSt	0	-	-	-	-	-	-	Covered	T16,T18,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T270,T78,T271
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T23
DetectSt	-	-	-	-	1	-	-	Covered	T104,T105,T106
DetectSt	-	-	-	-	0	1	-	Covered	T16,T18,T23
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T23
StableSt	-	-	-	-	-	-	1	Covered	T16,T18,T23
StableSt	-	-	-	-	-	-	0	Covered	T16,T18,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	3283	0	0
CntIncr_A	6912820	117411	0	0
CntNoWrap_A	6912820	6247368	0	0
DetectStDropOut_A	6912820	481	0	0
DetectedOut_A	6912820	69958	0	0
DetectedPulseOut_A	6912820	897	0	0
DisabledIdleSt_A	6912820	5793027	0	0
DisabledNoDetection_A	6912820	5795094	0	0
EnterDebounceSt_A	6912820	1649	0	0
EnterDetectSt_A	6912820	1636	0	0
EnterStableSt_A	6912820	897	0	0
PulseIsPulse_A	6912820	897	0	0
StayInStableSt	6912820	68976	0	0
gen_high_event_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	799	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	3283	0	0
T16	25996	52	0	0
T17	1089	0	0	0
T18	6700	50	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	14	0	0
T32	416	0	0	0
T41	0	34	0	0
T43	0	56	0	0
T52	0	60	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	18	0	0
T105	0	48	0	0
T106	0	44	0	0
T159	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	117411	0	0
T16	25996	1534	0	0
T17	1089	0	0	0
T18	6700	1150	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	336	0	0
T32	416	0	0	0
T41	0	867	0	0
T43	0	2072	0	0
T52	0	1620	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	583	0	0
T105	0	1652	0	0
T106	0	1191	0	0
T159	0	4950	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6247368	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25483	0	0
T17	1089	688	0	0
T18	6700	6249	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	481	0	0
T42	27046	0	0	0
T46	756	0	0	0
T54	24414	0	0	0
T76	0	12	0	0
T104	7497	6	0	0
T105	14024	0	0	0
T106	0	22	0	0
T108	0	18	0	0
T109	0	2	0	0
T110	0	26	0	0
T111	0	9	0	0
T126	0	5	0	0
T175	407	0	0	0
T176	502	0	0	0
T177	644	0	0	0
T244	0	14	0	0
T277	0	5	0	0
T295	526	0	0	0
T296	431	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	69958	0	0
T16	25996	3455	0	0
T17	1089	0	0	0
T18	6700	1484	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	779	0	0
T32	416	0	0	0
T41	0	3712	0	0
T43	0	2927	0	0
T52	0	1999	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T107	0	704	0	0
T159	0	1497	0	0
T272	0	594	0	0
T273	0	1603	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	897	0	0
T16	25996	26	0	0
T17	1089	0	0	0
T18	6700	25	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	7	0	0
T32	416	0	0	0
T41	0	17	0	0
T43	0	28	0	0
T52	0	30	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T107	0	14	0	0
T159	0	22	0	0
T272	0	14	0	0
T273	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5793027	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	18129	0	0
T17	1089	688	0	0
T18	6700	2053	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5795094	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	18129	0	0
T17	1089	689	0	0
T18	6700	2053	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1649	0	0
T16	25996	26	0	0
T17	1089	0	0	0
T18	6700	25	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	7	0	0
T32	416	0	0	0
T41	0	17	0	0
T43	0	28	0	0
T52	0	30	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	9	0	0
T105	0	24	0	0
T106	0	22	0	0
T159	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	1636	0	0
T16	25996	26	0	0
T17	1089	0	0	0
T18	6700	25	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	7	0	0
T32	416	0	0	0
T41	0	17	0	0
T43	0	28	0	0
T52	0	30	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T104	0	9	0	0
T105	0	24	0	0
T106	0	22	0	0
T159	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	897	0	0
T16	25996	26	0	0
T17	1089	0	0	0
T18	6700	25	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	7	0	0
T32	416	0	0	0
T41	0	17	0	0
T43	0	28	0	0
T52	0	30	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T107	0	14	0	0
T159	0	22	0	0
T272	0	14	0	0
T273	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	897	0	0
T16	25996	26	0	0
T17	1089	0	0	0
T18	6700	25	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	7	0	0
T32	416	0	0	0
T41	0	17	0	0
T43	0	28	0	0
T52	0	30	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T107	0	14	0	0
T159	0	22	0	0
T272	0	14	0	0
T273	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	68976	0	0
T16	25996	3421	0	0
T17	1089	0	0	0
T18	6700	1459	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	772	0	0
T32	416	0	0	0
T41	0	3685	0	0
T43	0	2899	0	0
T52	0	1969	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T107	0	690	0	0
T159	0	1472	0	0
T272	0	580	0	0
T273	0	1586	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	799	0	0
T16	25996	18	0	0
T17	1089	0	0	0
T18	6700	25	0	0
T19	96134	0	0	0
T20	14380	0	0	0
T21	571	0	0	0
T23	0	7	0	0
T32	416	0	0	0
T41	0	7	0	0
T43	0	28	0	0
T52	0	30	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T107	0	14	0	0
T159	0	19	0	0
T272	0	14	0	0
T273	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T20
1	Covered	T14,T28,T29

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T14,T28,T29
1	1	Covered	T14,T28,T29

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T14,T28,T29	VC_COV_UNR
1	Covered	T16,T18,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T14,T28,T29
1	Covered	T16,T18,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T14,T16,T18
1	1	Covered	T16,T18,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T40,T273,T50
1	0	Covered	T78,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T16,T18,T20
1	0	Covered	T43,T78,T297

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T20
1	-	Covered	T16,T18,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5
DetectSt	168	Covered	T5
IdleSt	163	Covered	T5
StableSt	191	Covered	T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5
DebounceSt->IdleSt	163	Covered	T5
DetectSt->IdleSt	186	Covered	T5
DetectSt->StableSt	191	Covered	T5
IdleSt->DebounceSt	148	Covered	T5
StableSt->IdleSt	206	Covered	T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T18,T20
0	1	Covered	T16,T18,T20
0	0	Excluded	T14,T28,T29	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T20
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T20
IdleSt	0	-	-	-	-	-	-	Covered	T14,T28,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T54,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T20
DetectSt	-	-	-	-	1	-	-	Covered	T40,T273,T50
DetectSt	-	-	-	-	0	1	-	Covered	T16,T18,T20
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T20
StableSt	-	-	-	-	-	-	1	Covered	T16,T18,T20
StableSt	-	-	-	-	-	-	0	Covered	T16,T18,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T28,T29
0	Covered	T14,T28,T29

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6912820	821	0	0
CntIncr_A	6912820	47288	0	0
CntNoWrap_A	6912820	6249830	0	0
DetectStDropOut_A	6912820	69	0	0
DetectedOut_A	6912820	13367	0	0
DetectedPulseOut_A	6912820	311	0	0
DisabledIdleSt_A	6912820	5875941	0	0
DisabledNoDetection_A	6912820	5877575	0	0
EnterDebounceSt_A	6912820	436	0	0
EnterDetectSt_A	6912820	386	0	0
EnterStableSt_A	6912820	311	0	0
PulseIsPulse_A	6912820	311	0	0
StayInStableSt	6912820	13022	0	0
gen_high_level_sva.HighLevelEvent_A	6912820	6252897	0	0
gen_not_sticky_sva.StableStDropOut_A	6912820	273	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	821	0	0
T16	25996	14	0	0
T17	1089	0	0	0
T18	6700	2	0	0
T19	96134	0	0	0
T20	14380	4	0	0
T21	571	0	0	0
T23	0	9	0	0
T32	416	0	0	0
T40	0	4	0	0
T41	0	8	0	0
T42	0	10	0	0
T43	0	14	0	0
T52	0	12	0	0
T54	0	13	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	47288	0	0
T16	25996	497	0	0
T17	1089	0	0	0
T18	6700	42	0	0
T19	96134	0	0	0
T20	14380	218	0	0
T21	571	0	0	0
T23	0	210	0	0
T32	416	0	0	0
T40	0	306	0	0
T41	0	336	0	0
T42	0	795	0	0
T43	0	462	0	0
T52	0	402	0	0
T54	0	828	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6249830	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	25521	0	0
T17	1089	688	0	0
T18	6700	6297	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	69	0	0
T40	21099	2	0	0
T45	881	0	0	0
T48	615	0	0	0
T50	0	12	0	0
T52	7733	0	0	0
T64	2095	0	0	0
T95	724	0	0	0
T113	0	7	0	0
T119	0	3	0	0
T169	454	0	0	0
T170	502	0	0	0
T171	505	0	0	0
T238	0	3	0	0
T273	12536	5	0	0
T289	0	2	0	0
T298	0	3	0	0
T299	0	1	0	0
T300	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	13367	0	0
T16	25996	445	0	0
T17	1089	0	0	0
T18	6700	70	0	0
T19	96134	0	0	0
T20	14380	65	0	0
T21	571	0	0	0
T23	0	96	0	0
T32	416	0	0	0
T41	0	271	0	0
T42	0	120	0	0
T43	0	251	0	0
T52	0	521	0	0
T54	0	21	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T159	0	247	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	311	0	0
T16	25996	7	0	0
T17	1089	0	0	0
T18	6700	1	0	0
T19	96134	0	0	0
T20	14380	2	0	0
T21	571	0	0	0
T23	0	4	0	0
T32	416	0	0	0
T41	0	4	0	0
T42	0	5	0	0
T43	0	7	0	0
T52	0	6	0	0
T54	0	5	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T159	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5875941	0	0
T14	3575	667	0	0
T15	72309	71908	0	0
T16	25996	22088	0	0
T17	1089	688	0	0
T18	6700	4815	0	0
T28	424	23	0	0
T29	427	26	0	0
T30	8402	1	0	0
T31	622	221	0	0
T32	416	15	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	5877575	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	22089	0	0
T17	1089	689	0	0
T18	6700	4816	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	436	0	0
T16	25996	7	0	0
T17	1089	0	0	0
T18	6700	1	0	0
T19	96134	0	0	0
T20	14380	2	0	0
T21	571	0	0	0
T23	0	5	0	0
T32	416	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	5	0	0
T43	0	7	0	0
T52	0	6	0	0
T54	0	8	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	386	0	0
T16	25996	7	0	0
T17	1089	0	0	0
T18	6700	1	0	0
T19	96134	0	0	0
T20	14380	2	0	0
T21	571	0	0	0
T23	0	4	0	0
T32	416	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	5	0	0
T43	0	7	0	0
T52	0	6	0	0
T54	0	5	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	311	0	0
T16	25996	7	0	0
T17	1089	0	0	0
T18	6700	1	0	0
T19	96134	0	0	0
T20	14380	2	0	0
T21	571	0	0	0
T23	0	4	0	0
T32	416	0	0	0
T41	0	4	0	0
T42	0	5	0	0
T43	0	7	0	0
T52	0	6	0	0
T54	0	5	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T159	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	311	0	0
T16	25996	7	0	0
T17	1089	0	0	0
T18	6700	1	0	0
T19	96134	0	0	0
T20	14380	2	0	0
T21	571	0	0	0
T23	0	4	0	0
T32	416	0	0	0
T41	0	4	0	0
T42	0	5	0	0
T43	0	7	0	0
T52	0	6	0	0
T54	0	5	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T159	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	13022	0	0
T16	25996	438	0	0
T17	1089	0	0	0
T18	6700	69	0	0
T19	96134	0	0	0
T20	14380	63	0	0
T21	571	0	0	0
T23	0	92	0	0
T32	416	0	0	0
T41	0	267	0	0
T42	0	115	0	0
T43	0	244	0	0
T52	0	515	0	0
T54	0	16	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T159	0	244	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	6252897	0	0
T14	3575	675	0	0
T15	72309	71909	0	0
T16	25996	25544	0	0
T17	1089	689	0	0
T18	6700	6300	0	0
T28	424	24	0	0
T29	427	27	0	0
T30	8402	2	0	0
T31	622	222	0	0
T32	416	16	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6912820	273	0	0
T16	25996	7	0	0
T17	1089	0	0	0
T18	6700	1	0	0
T19	96134	0	0	0
T20	14380	2	0	0
T21	571	0	0	0
T23	0	4	0	0
T32	416	0	0	0
T41	0	4	0	0
T42	0	5	0	0
T43	0	6	0	0
T52	0	6	0	0
T54	0	5	0	0
T55	422	0	0	0
T56	501	0	0	0
T57	426	0	0	0
T159	0	3	0	0