ASSERT | PROPERTIES | SEQUENCES | |
Total | 1058 | 0 | 10 |
Category 0 | 1058 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 1058 | 0 | 10 |
Severity 0 | 1058 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 1058 | 100.00 |
Uncovered | 4 | 0.38 |
Success | 1054 | 99.62 |
Failure | 0 | 0.00 |
Incomplete | 4 | 0.38 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 8210187 | 663 | 0 | 912 | |
tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 8210187 | 330 | 0 | 912 | |
tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 8210187 | 62 | 0 | 912 | |
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 8210187 | 725 | 0 | 912 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1304240946 | 1370948 | 1370948 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1304240946 | 1657 | 1657 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1304240946 | 3574 | 3574 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1304240946 | 2610 | 2610 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1304240946 | 3102 | 3102 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1304240946 | 2095 | 2095 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1304240946 | 345 | 345 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1304240946 | 3555 | 3555 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1304240946 | 8918 | 8918 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1304240946 | 89576 | 89576 | 848 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1304240946 | 1370948 | 1370948 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1304240946 | 1657 | 1657 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1304240946 | 3574 | 3574 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1304240946 | 2610 | 2610 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1304240946 | 3102 | 3102 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1304240946 | 2095 | 2095 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1304240946 | 345 | 345 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1304240946 | 3555 | 3555 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1304240946 | 8918 | 8918 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1304240946 | 89576 | 89576 | 848 |