ASSERT | PROPERTIES | SEQUENCES | |
Total | 1058 | 0 | 10 |
Category 0 | 1058 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 1058 | 0 | 10 |
Severity 0 | 1058 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 1058 | 100.00 |
Uncovered | 3 | 0.28 |
Success | 1055 | 99.72 |
Failure | 0 | 0.00 |
Incomplete | 4 | 0.38 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 8587828 | 719 | 0 | 916 | |
tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 8587828 | 311 | 0 | 916 | |
tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 8587828 | 63 | 0 | 916 | |
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 8587828 | 795 | 0 | 916 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1397800002 | 1272416 | 1272416 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1397800002 | 4060 | 4060 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1397800002 | 10072 | 10072 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1397800002 | 7563 | 7563 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1397800002 | 9565 | 9565 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1397800002 | 5863 | 5863 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1397800002 | 5420 | 5420 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1397800002 | 8203 | 8203 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1397800002 | 14653 | 14653 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1397800002 | 98546 | 98546 | 854 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1397800002 | 1272416 | 1272416 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1397800002 | 4060 | 4060 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1397800002 | 10072 | 10072 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1397800002 | 7563 | 7563 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1397800002 | 9565 | 9565 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1397800002 | 5863 | 5863 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1397800002 | 5420 | 5420 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1397800002 | 8203 | 8203 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1397800002 | 14653 | 14653 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1397800002 | 98546 | 98546 | 854 |