Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_ec_rst_ctl_cdc

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	88.73			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1775488	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1954	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1775488	0	0
T1	138503	19617	0	0
T2	313506	2315	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	864	0	0
T8	0	15420	0	0
T9	0	5701	0	0
T10	0	4583	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1746	0	0
T41	0	1941	0	0
T57	0	1270	0	0
T58	0	1910	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1954	0	0
T1	138503	15	0	0
T2	313506	3	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	2	0	0
T8	0	18	0	0
T9	0	4	0	0
T10	0	5	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T3,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T3,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	888727	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	897	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	888727	0	0
T3	226608	4789	0	0
T6	730055	1612	0	0
T7	162836	1066	0	0
T13	0	1434	0	0
T17	0	477	0	0
T19	0	480	0	0
T22	0	2728	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T30	211512	0	0	0
T56	0	2879	0	0
T59	0	1912	0	0
T60	0	1466	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	897	0	0
T3	226608	3	0	0
T6	730055	4	0	0
T7	162836	1	0	0
T13	0	1	0	0
T17	0	1	0	0
T19	0	1	0	0
T22	0	3	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T30	211512	0	0	0
T56	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T3,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T3,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	932496	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	931	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	932496	0	0
T3	226608	4783	0	0
T6	730055	1604	0	0
T7	162836	1060	0	0
T13	0	1426	0	0
T17	0	466	0	0
T19	0	478	0	0
T22	0	2715	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T30	211512	0	0	0
T56	0	2875	0	0
T59	0	1904	0	0
T60	0	1464	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	931	0	0
T3	226608	3	0	0
T6	730055	4	0	0
T7	162836	1	0	0
T13	0	1	0	0
T17	0	1	0	0
T19	0	1	0	0
T22	0	3	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T30	211512	0	0	0
T56	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T3,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T3,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	922438	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	912	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	922438	0	0
T3	226608	4777	0	0
T6	730055	1596	0	0
T7	162836	1053	0	0
T13	0	1423	0	0
T17	0	452	0	0
T19	0	476	0	0
T22	0	2689	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T30	211512	0	0	0
T56	0	2871	0	0
T59	0	1901	0	0
T60	0	1462	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	912	0	0
T3	226608	3	0	0
T6	730055	4	0	0
T7	162836	1	0	0
T13	0	1	0	0
T17	0	1	0	0
T19	0	1	0	0
T22	0	3	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T30	211512	0	0	0
T56	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T3,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T7
1	-	Covered	T3,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T3,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	959472	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	962	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	959472	0	0
T3	226608	3353	0	0
T6	730055	1617	0	0
T7	162836	2498	0	0
T13	0	2875	0	0
T22	0	1740	0	0
T23	0	544	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T30	211512	0	0	0
T31	0	3264	0	0
T32	0	3979	0	0
T33	0	4823	0	0
T34	0	1959	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	962	0	0
T3	226608	2	0	0
T6	730055	4	0	0
T7	162836	2	0	0
T13	0	2	0	0
T22	0	2	0	0
T23	0	2	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T30	211512	0	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	6	0	0
T34	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T3,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T36,T37,T38
1	-	Covered	T3,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T3,T6,T7

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T3,T6,T7
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	588422	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	612	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	588422	0	0
T3	226608	1914	0	0
T6	730055	863	0	0
T7	162836	1054	0	0
T13	0	1421	0	0
T22	0	970	0	0
T23	0	228	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T30	211512	0	0	0
T31	0	1835	0	0
T32	0	1972	0	0
T33	0	2514	0	0
T34	0	975	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	612	0	0
T3	226608	1	0	0
T6	730055	2	0	0
T7	162836	1	0	0
T13	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T30	211512	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T15
1	-	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1104108	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1220	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1104108	0	0
T1	138503	17135	0	0
T2	313506	1481	0	0
T3	226608	1916	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	867	0	0
T7	0	1054	0	0
T8	0	10996	0	0
T10	0	5883	0	0
T12	0	10202	0	0
T13	0	5561	0	0
T14	0	450	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1220	0	0
T1	138503	12	0	0
T2	313506	1	0	0
T3	226608	1	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	2	0	0
T7	0	1	0	0
T8	0	13	0	0
T10	0	6	0	0
T12	0	6	0	0
T13	0	2	0	0
T14	0	1	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T25,T27

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T25,T27
1	1	Covered	T2,T25,T27

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T25,T27

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T25,T27
1	1	Covered	T2,T25,T27

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T25,T27
0	0	1	Covered	T2,T25,T27
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T25,T27
0	0	1	Covered	T2,T25,T27
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	2600775	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	2946	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	2600775	0	0
T2	313506	15983	0	0
T3	226608	0	0	0
T6	730055	0	0	0
T7	162836	0	0	0
T9	0	29843	0	0
T13	0	32508	0	0
T15	0	16325	0	0
T17	0	8385	0	0
T24	171952	0	0	0
T25	74471	10653	0	0
T26	95003	0	0	0
T27	246961	35503	0	0
T28	236877	32008	0	0
T29	58441	0	0	0
T61	0	8768	0	0
T62	0	17274	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	2946	0	0
T2	313506	20	0	0
T3	226608	0	0	0
T6	730055	0	0	0
T7	162836	0	0	0
T9	0	20	0	0
T13	0	20	0	0
T15	0	20	0	0
T17	0	20	0	0
T24	171952	0	0	0
T25	74471	20	0	0
T26	95003	0	0	0
T27	246961	20	0	0
T28	236877	20	0	0
T29	58441	0	0	0
T61	0	20	0	0
T62	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T6,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T6,T25
1	1	Covered	T2,T6,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T6,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T25
1	1	Covered	T2,T6,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T6,T25
0	0	1	Covered	T2,T6,T25
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T6,T25
0	0	1	Covered	T2,T6,T25
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	5232922	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	6644	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	5232922	0	0
T2	313506	81885	0	0
T3	226608	0	0	0
T6	730055	8427	0	0
T7	162836	0	0	0
T9	0	1182	0	0
T24	171952	0	0	0
T25	74471	595	0	0
T26	95003	0	0	0
T27	246961	1995	0	0
T28	236877	1935	0	0
T29	58441	7781	0	0
T61	0	478	0	0
T63	0	31138	0	0
T64	0	7893	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6644	0	0
T2	313506	101	0	0
T3	226608	0	0	0
T6	730055	20	0	0
T7	162836	0	0	0
T9	0	1	0	0
T24	171952	0	0	0
T25	74471	1	0	0
T26	95003	0	0	0
T27	246961	1	0	0
T28	236877	1	0	0
T29	58441	20	0	0
T61	0	1	0	0
T63	0	20	0	0
T64	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	6418568	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	7904	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6418568	0	0
T1	138503	21017	0	0
T2	313506	85102	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	9501	0	0
T8	0	15784	0	0
T24	171952	0	0	0
T25	74471	597	0	0
T26	95003	0	0	0
T27	246961	1997	0	0
T28	0	1937	0	0
T29	0	8054	0	0
T61	0	480	0	0
T63	0	31572	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	7904	0	0
T1	138503	15	0	0
T2	313506	105	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	22	0	0
T8	0	18	0	0
T24	171952	0	0	0
T25	74471	1	0	0
T26	95003	0	0	0
T27	246961	1	0	0
T28	0	1	0	0
T29	0	20	0	0
T61	0	1	0	0
T63	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T6,T29

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T6,T29
1	1	Covered	T2,T6,T29

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T6,T29

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T29
1	1	Covered	T2,T6,T29

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T6,T29
0	0	1	Covered	T2,T6,T29
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T6,T29
0	0	1	Covered	T2,T6,T29
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	5216509	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	6558	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	5216509	0	0
T2	313506	81148	0	0
T3	226608	0	0	0
T6	730055	8467	0	0
T7	162836	0	0	0
T13	0	32389	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	7920	0	0
T53	0	34465	0	0
T63	0	31365	0	0
T64	0	8081	0	0
T65	0	8539	0	0
T66	0	33310	0	0
T67	0	33013	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6558	0	0
T2	313506	100	0	0
T3	226608	0	0	0
T6	730055	20	0	0
T7	162836	0	0	0
T13	0	20	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	20	0	0
T53	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T6,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T6,T9
1	1	Covered	T2,T6,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T6,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T9
1	1	Covered	T2,T6,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T6,T9
0	0	1	Covered	T2,T6,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T6,T9
0	0	1	Covered	T2,T6,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	938824	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	958	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	938824	0	0
T2	313506	704	0	0
T3	226608	0	0	0
T6	730055	500	0	0
T7	162836	0	0	0
T9	0	1208	0	0
T11	0	1917	0	0
T13	0	3330	0	0
T15	0	1451	0	0
T17	0	939	0	0
T18	0	159	0	0
T19	0	477	0	0
T21	0	390	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	958	0	0
T2	313506	1	0	0
T3	226608	0	0	0
T6	730055	1	0	0
T7	162836	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	0	2	0	0
T15	0	2	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1710749	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1905	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1710749	0	0
T1	138503	19487	0	0
T2	313506	2311	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	498	0	0
T8	0	15384	0	0
T9	0	7272	0	0
T10	0	4542	0	0
T11	0	1915	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1743	0	0
T41	0	1939	0	0
T42	0	288	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1905	0	0
T1	138503	15	0	0
T2	313506	3	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	1	0	0
T8	0	18	0	0
T9	0	5	0	0
T10	0	5	0	0
T11	0	1	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T24,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T24,T26
1	1	Covered	T2,T24,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T24,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T24,T26
1	1	Covered	T2,T24,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T24,T26
0	0	1	Covered	T2,T24,T26
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T24,T26
0	0	1	Covered	T2,T24,T26
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1108662	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1186	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1108662	0	0
T2	313506	1330	0	0
T3	226608	0	0	0
T6	730055	0	0	0
T7	162836	0	0	0
T13	0	4778	0	0
T17	0	1785	0	0
T22	0	3482	0	0
T24	171952	4283	0	0
T25	74471	0	0	0
T26	95003	2368	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T47	0	8218	0	0
T48	0	1623	0	0
T50	0	5324	0	0
T51	0	4840	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1186	0	0
T2	313506	1	0	0
T3	226608	0	0	0
T6	730055	0	0	0
T7	162836	0	0	0
T13	0	3	0	0
T17	0	4	0	0
T22	0	4	0	0
T24	171952	5	0	0
T25	74471	0	0	0
T26	95003	5	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T47	0	5	0	0
T48	0	4	0	0
T50	0	6	0	0
T51	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T2,T24,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T24,T26,T47
1	1	Covered	T2,T24,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T24,T26,T47

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T24,T26
1	1	Covered	T24,T26,T47

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T24,T26
0	0	1	Covered	T24,T26,T47
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T2,T24,T26
0	0	1	Covered	T24,T26,T47
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	996624	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1039	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	996624	0	0
T2	313506	624	0	0
T3	226608	0	0	0
T6	730055	0	0	0
T7	162836	0	0	0
T13	0	4756	0	0
T17	0	1279	0	0
T22	0	2707	0	0
T24	171952	2355	0	0
T25	74471	0	0	0
T26	95003	1364	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T47	0	4805	0	0
T48	0	1242	0	0
T50	0	2514	0	0
T51	0	3052	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1039	0	0
T7	162836	0	0	0
T8	992305	0	0	0
T13	0	3	0	0
T17	0	3	0	0
T22	0	3	0	0
T24	171952	3	0	0
T25	74471	0	0	0
T26	95003	3	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T30	211512	0	0	0
T47	0	3	0	0
T48	0	3	0	0
T50	0	3	0	0
T51	0	3	0	0
T55	0	3	0	0
T56	201405	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	6299603	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	6717	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6299603	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	27789	0	0
T16	0	45982	0	0
T40	626416	129622	0	0
T41	240844	86051	0	0
T42	0	18727	0	0
T46	0	115820	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	42511	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	22751	0	0
T69	0	32092	0	0
T70	0	14975	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6717	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	70	0	0
T16	0	51	0	0
T40	626416	78	0	0
T41	240844	51	0	0
T42	0	51	0	0
T46	0	70	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	51	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	51	0	0
T69	0	79	0	0
T70	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	6168501	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	6695	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6168501	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	23586	0	0
T16	0	58500	0	0
T40	626416	135198	0	0
T41	240844	85841	0	0
T42	0	18517	0	0
T46	0	136506	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	41489	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	21679	0	0
T69	0	34457	0	0
T70	0	14765	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6695	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	62	0	0
T16	0	66	0	0
T40	626416	82	0	0
T41	240844	51	0	0
T42	0	51	0	0
T46	0	82	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	51	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	51	0	0
T69	0	88	0	0
T70	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	6263748	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	6856	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6263748	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	32131	0	0
T16	0	58230	0	0
T40	626416	107866	0	0
T41	240844	85631	0	0
T42	0	18307	0	0
T46	0	126861	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	40490	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	20583	0	0
T69	0	30165	0	0
T70	0	14555	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6856	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	86	0	0
T16	0	66	0	0
T40	626416	66	0	0
T41	240844	51	0	0
T42	0	51	0	0
T46	0	77	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	51	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	51	0	0
T69	0	81	0	0
T70	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	5996939	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	6535	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	5996939	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	29136	0	0
T16	0	53938	0	0
T40	626416	85159	0	0
T41	240844	85421	0	0
T42	0	18097	0	0
T46	0	96902	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	39555	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	19623	0	0
T69	0	22418	0	0
T70	0	14345	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6535	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	80	0	0
T16	0	61	0	0
T40	626416	52	0	0
T41	240844	51	0	0
T42	0	51	0	0
T46	0	60	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	51	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	51	0	0
T69	0	62	0	0
T70	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1144793	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1114	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1144793	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	818	0	0
T16	0	763	0	0
T40	626416	1869	0	0
T41	240844	1979	0	0
T42	0	328	0	0
T46	0	3814	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	701	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	519	0	0
T69	0	1838	0	0
T70	0	238	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1114	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	2	0	0
T16	0	1	0	0
T40	626416	1	0	0
T41	240844	1	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	1	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	1	0	0
T69	0	5	0	0
T70	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1162410	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1145	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1162410	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	706	0	0
T16	0	753	0	0
T40	626416	1840	0	0
T41	240844	1969	0	0
T42	0	318	0	0
T46	0	3744	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	636	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	475	0	0
T69	0	1602	0	0
T70	0	228	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1145	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	2	0	0
T16	0	1	0	0
T40	626416	1	0	0
T41	240844	1	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	1	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	1	0	0
T69	0	5	0	0
T70	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1102948	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1116	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1102948	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	818	0	0
T16	0	743	0	0
T40	626416	1808	0	0
T41	240844	1959	0	0
T42	0	308	0	0
T46	0	3659	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	578	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	423	0	0
T69	0	1513	0	0
T70	0	218	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1116	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	2	0	0
T16	0	1	0	0
T40	626416	1	0	0
T41	240844	1	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	1	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	1	0	0
T69	0	5	0	0
T70	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T40,T41,T42
0	0	1	Covered	T40,T41,T42
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1122163	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1121	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1122163	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	694	0	0
T16	0	733	0	0
T40	626416	1771	0	0
T41	240844	1949	0	0
T42	0	298	0	0
T46	0	3591	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	526	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	515	0	0
T69	0	1674	0	0
T70	0	208	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1121	0	0
T9	470883	0	0	0
T10	458037	0	0	0
T14	0	2	0	0
T16	0	1	0	0
T40	626416	1	0	0
T41	240844	1	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	357684	0	0	0
T48	86592	0	0	0
T49	0	1	0	0
T52	50602	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T65	63012	0	0	0
T68	0	1	0	0
T69	0	5	0	0
T70	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	7014798	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	7516	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	7014798	0	0
T1	138503	21252	0	0
T2	313506	1643	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15852	0	0
T9	0	6013	0	0
T10	0	5017	0	0
T12	0	1954	0	0
T13	0	10025	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	130175	0	0
T41	0	86147	0	0
T42	0	18823	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	7516	0	0
T1	138503	15	0	0
T2	313506	2	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	4	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	6	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	78	0	0
T41	0	51	0	0
T42	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	6742727	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	7332	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6742727	0	0
T1	138503	21110	0	0
T2	313506	703	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15816	0	0
T9	0	2806	0	0
T10	0	4979	0	0
T12	0	1942	0	0
T13	0	7151	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	135760	0	0
T41	0	85937	0	0
T42	0	18613	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	7332	0	0
T1	138503	15	0	0
T2	313506	1	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	2	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	4	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	82	0	0
T41	0	51	0	0
T42	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	6831597	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	7509	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6831597	0	0
T1	138503	20972	0	0
T2	313506	701	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15780	0	0
T9	0	2784	0	0
T10	0	4949	0	0
T12	0	1935	0	0
T13	0	7139	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	108320	0	0
T41	0	85727	0	0
T42	0	18403	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	7509	0	0
T1	138503	15	0	0
T2	313506	1	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	2	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	4	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	66	0	0
T41	0	51	0	0
T42	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	6548053	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	7202	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	6548053	0	0
T1	138503	20809	0	0
T2	313506	699	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15744	0	0
T9	0	2757	0	0
T10	0	4913	0	0
T12	0	1931	0	0
T13	0	7119	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	85508	0	0
T41	0	85517	0	0
T42	0	18193	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	7202	0	0
T1	138503	15	0	0
T2	313506	1	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	2	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	4	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	52	0	0
T41	0	51	0	0
T42	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1765711	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1873	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1765711	0	0
T1	138503	20696	0	0
T2	313506	1633	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15708	0	0
T9	0	5891	0	0
T10	0	4873	0	0
T12	0	1925	0	0
T13	0	9933	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1856	0	0
T41	0	1975	0	0
T42	0	324	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1873	0	0
T1	138503	15	0	0
T2	313506	2	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	4	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	6	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1657392	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1763	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1657392	0	0
T1	138503	20529	0	0
T2	313506	695	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15672	0	0
T9	0	2728	0	0
T10	0	4834	0	0
T12	0	1920	0	0
T13	0	7062	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1831	0	0
T41	0	1965	0	0
T42	0	314	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1763	0	0
T1	138503	15	0	0
T2	313506	1	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	2	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	4	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1639644	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1766	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1639644	0	0
T1	138503	20389	0	0
T2	313506	693	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15636	0	0
T9	0	2702	0	0
T10	0	4800	0	0
T12	0	1915	0	0
T13	0	7032	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1795	0	0
T41	0	1955	0	0
T42	0	304	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1766	0	0
T1	138503	15	0	0
T2	313506	1	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	2	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	4	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1630160	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1764	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1630160	0	0
T1	138503	20259	0	0
T2	313506	691	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15600	0	0
T9	0	2683	0	0
T10	0	4766	0	0
T12	0	1912	0	0
T13	0	7005	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1756	0	0
T41	0	1945	0	0
T42	0	294	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1764	0	0
T1	138503	15	0	0
T2	313506	1	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	2	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	4	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1725155	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1868	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1725155	0	0
T1	138503	20152	0	0
T2	313506	1623	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15564	0	0
T9	0	5804	0	0
T10	0	4735	0	0
T12	0	1901	0	0
T13	0	9801	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1849	0	0
T41	0	1973	0	0
T42	0	322	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1868	0	0
T1	138503	15	0	0
T2	313506	2	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	4	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	6	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1669867	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1793	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1669867	0	0
T1	138503	20050	0	0
T2	313506	687	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15528	0	0
T9	0	2639	0	0
T10	0	4708	0	0
T12	0	1891	0	0
T13	0	6948	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1820	0	0
T41	0	1963	0	0
T42	0	312	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1793	0	0
T1	138503	15	0	0
T2	313506	1	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	2	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	4	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1613434	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1744	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1613434	0	0
T1	138503	19900	0	0
T2	313506	685	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15492	0	0
T9	0	2613	0	0
T10	0	4668	0	0
T12	0	1889	0	0
T13	0	6921	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1787	0	0
T41	0	1953	0	0
T42	0	302	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1744	0	0
T1	138503	15	0	0
T2	313506	1	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	2	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	4	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1619672	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1760	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1619672	0	0
T1	138503	19750	0	0
T2	313506	683	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	15456	0	0
T9	0	2599	0	0
T10	0	4624	0	0
T12	0	1878	0	0
T13	0	6907	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1751	0	0
T41	0	1943	0	0
T42	0	292	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1760	0	0
T1	138503	15	0	0
T2	313506	1	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	18	0	0
T9	0	2	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	0	4	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1305000248	1045535	0	0
DstReqKnown_A	7280107	6401034	0	0
SrcAckBusyChk_A	1305000248	1194	0	0
SrcBusyKnown_A	1305000248	1303072987	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1045535	0	0
T1	138503	16998	0	0
T2	313506	1639	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	10971	0	0
T10	0	5820	0	0
T12	0	10155	0	0
T13	0	5235	0	0
T14	0	455	0	0
T15	0	724	0	0
T16	0	759	0	0
T20	0	16914	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7280107	6401034	0	0
T1	35063	34582	0	0
T2	13507	6282	0	0
T3	1601	1201	0	0
T4	425	25	0	0
T5	427	27	0	0
T6	41075	36965	0	0
T24	716	316	0	0
T25	496	96	0	0
T26	759	359	0	0
T27	493	93	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1194	0	0
T1	138503	12	0	0
T2	313506	2	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T8	0	13	0	0
T10	0	6	0	0
T12	0	6	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T20	0	10	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1303072987	0	0
T1	138503	138182	0	0
T2	313506	312336	0	0
T3	226608	226532	0	0
T4	53189	53115	0	0
T5	51284	51195	0	0
T6	730055	727214	0	0
T24	171952	171887	0	0
T25	74471	74374	0	0
T26	95003	94943	0	0
T27	246961	246903	0	0