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Module Instance : tb.dut.u_reg.u_key_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.76 100.00 88.73 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.61 100.00 94.44 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

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Module Instances:
tb.dut.u_reg.u_key_intr_status_cdc
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT2,T6,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT2,T6,T9
11CoveredT2,T6,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T4,T5
01CoveredT2,T6,T9
10CoveredT2,T6,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T6,T9
11CoveredT2,T6,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T4,T5
10Not Covered
11CoveredT2,T6,T9

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T5
0 1 - Covered T2,T6,T9
0 0 1 Covered T2,T6,T9
0 0 0 Covered T1,T4,T5


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T4,T5
0 1 - Covered T2,T6,T9
0 0 1 Covered T2,T6,T9
0 0 0 Covered T1,T4,T5


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1305000248 652384 0 0
DstReqKnown_A 7280107 6401034 0 0
SrcAckBusyChk_A 1305000248 746 0 0
SrcBusyKnown_A 1305000248 1303072987 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1305000248 652384 0 0
T2 313506 2569 0 0
T3 226608 0 0 0
T6 730055 1232 0 0
T7 162836 0 0 0
T9 0 2760 0 0
T11 0 3829 0 0
T13 0 5214 0 0
T15 0 1411 0 0
T17 0 875 0 0
T18 0 136 0 0
T19 0 830 0 0
T21 0 734 0 0
T24 171952 0 0 0
T25 74471 0 0 0
T26 95003 0 0 0
T27 246961 0 0 0
T28 236877 0 0 0
T29 58441 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7280107 6401034 0 0
T1 35063 34582 0 0
T2 13507 6282 0 0
T3 1601 1201 0 0
T4 425 25 0 0
T5 427 27 0 0
T6 41075 36965 0 0
T24 716 316 0 0
T25 496 96 0 0
T26 759 359 0 0
T27 493 93 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1305000248 746 0 0
T2 313506 3 0 0
T3 226608 0 0 0
T6 730055 3 0 0
T7 162836 0 0 0
T9 0 2 0 0
T11 0 2 0 0
T13 0 3 0 0
T15 0 2 0 0
T17 0 2 0 0
T18 0 1 0 0
T19 0 2 0 0
T21 0 2 0 0
T24 171952 0 0 0
T25 74471 0 0 0
T26 95003 0 0 0
T27 246961 0 0 0
T28 236877 0 0 0
T29 58441 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1305000248 1303072987 0 0
T1 138503 138182 0 0
T2 313506 312336 0 0
T3 226608 226532 0 0
T4 53189 53115 0 0
T5 51284 51195 0 0
T6 730055 727214 0 0
T24 171952 171887 0 0
T25 74471 74374 0 0
T26 95003 94943 0 0
T27 246961 246903 0 0

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