Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T2,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T18,T2,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T18,T2,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T2,T30
1	0	Covered	T5,T6,T21
1	1	Covered	T18,T2,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T2,T30
0	1	Covered	T30,T104,T111
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T2,T30
0	1	Covered	T18,T2,T30
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T2,T30
1	-	Covered	T18,T2,T30

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T2,T30
DetectSt	168	Covered	T18,T2,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T18,T2,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T2,T30
DebounceSt->IdleSt	163	Covered	T2,T39,T124
DetectSt->IdleSt	186	Covered	T30,T104,T111
DetectSt->StableSt	191	Covered	T18,T2,T30
IdleSt->DebounceSt	148	Covered	T18,T2,T30
StableSt->IdleSt	206	Covered	T18,T2,T30

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T2,T30
0	1	Covered	T18,T2,T30
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T18,T2,T30
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T2,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T2,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T39,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T2,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T104,T111
DetectSt	-	-	-	-	0	1	-	Covered	T18,T2,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T2,T30
StableSt	-	-	-	-	-	-	0	Covered	T18,T2,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	304	0	0
CntIncr_A	6435794	160686	0	0
CntNoWrap_A	6435794	5784271	0	0
DetectStDropOut_A	6435794	3	0	0
DetectedOut_A	6435794	974	0	0
DetectedPulseOut_A	6435794	142	0	0
DisabledIdleSt_A	6435794	5616773	0	0
DisabledNoDetection_A	6435794	5619092	0	0
EnterDebounceSt_A	6435794	161	0	0
EnterDetectSt_A	6435794	145	0	0
EnterStableSt_A	6435794	142	0	0
PulseIsPulse_A	6435794	142	0	0
StayInStableSt	6435794	832	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6435794	7002	0	0
gen_low_level_sva.LowLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	141	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6435794	304
T2	24781	3
T3	786	0
T7	44580	0
T8	6649	0
T10	0	2
T12	0	8
T18	40704	2
T19	406	0
T20	492	0
T30	733	6
T39	0	3
T50	681	0
T52	0	4
T53	0	6
T55	527	0
T78	0	2
T96	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	6435794	160686
T2	24781	136
T3	786	0
T7	44580	0
T8	6649	0
T10	0	49
T12	0	220
T18	40704	39992
T19	406	0
T20	492	0
T30	733	202
T39	0	65
T50	681	0
T52	0	170
T53	0	147
T55	527	0
T78	0	75
T96	0	13

CntNoWrap_A

Name	Attempts	Real Successes
Total	6435794	5784271
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6435794	3
T8	6649	0
T9	21006	0
T30	733	1
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T104	0	1
T111	0	1
T112	415	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6435794	974
T2	24781	11
T3	786	0
T7	44580	0
T8	6649	0
T10	0	2
T12	0	27
T18	40704	2
T19	406	0
T20	492	0
T30	733	10
T39	0	10
T50	681	0
T52	0	16
T53	0	22
T55	527	0
T78	0	5
T96	0	2

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6435794	142
T2	24781	1
T3	786	0
T7	44580	0
T8	6649	0
T10	0	1
T12	0	4
T18	40704	1
T19	406	0
T20	492	0
T30	733	2
T39	0	1
T50	681	0
T52	0	2
T53	0	3
T55	527	0
T78	0	1
T96	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6435794	5616773
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6435794	5619092
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6435794	161
T2	24781	2
T3	786	0
T7	44580	0
T8	6649	0
T10	0	1
T12	0	4
T18	40704	1
T19	406	0
T20	492	0
T30	733	3
T39	0	2
T50	681	0
T52	0	2
T53	0	3
T55	527	0
T78	0	1
T96	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6435794	145
T2	24781	1
T3	786	0
T7	44580	0
T8	6649	0
T10	0	1
T12	0	4
T18	40704	1
T19	406	0
T20	492	0
T30	733	3
T39	0	1
T50	681	0
T52	0	2
T53	0	3
T55	527	0
T78	0	1
T96	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6435794	142
T2	24781	1
T3	786	0
T7	44580	0
T8	6649	0
T10	0	1
T12	0	4
T18	40704	1
T19	406	0
T20	492	0
T30	733	2
T39	0	1
T50	681	0
T52	0	2
T53	0	3
T55	527	0
T78	0	1
T96	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6435794	142
T2	24781	1
T3	786	0
T7	44580	0
T8	6649	0
T10	0	1
T12	0	4
T18	40704	1
T19	406	0
T20	492	0
T30	733	2
T39	0	1
T50	681	0
T52	0	2
T53	0	3
T55	527	0
T78	0	1
T96	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	6435794	832
T2	24781	10
T3	786	0
T7	44580	0
T8	6649	0
T10	0	1
T12	0	23
T18	40704	1
T19	406	0
T20	492	0
T30	733	8
T39	0	9
T50	681	0
T52	0	14
T53	0	19
T55	527	0
T78	0	4
T96	0	1

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	6435794	7002
T1	25498	12
T5	409	1
T6	502	5
T14	5102	22
T15	502	4
T16	424	2
T21	499	7
T22	490	7
T23	504	5
T24	650	2

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	6435794	5786949
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6435794	141
T2	24781	1
T3	786	0
T7	44580	0
T8	6649	0
T10	0	1
T12	0	4
T18	40704	1
T19	406	0
T20	492	0
T30	733	2
T39	0	1
T50	681	0
T52	0	2
T53	0	3
T55	527	0
T78	0	1
T96	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T12,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T29
1	0	Covered	T5,T6,T21
1	1	Covered	T7,T12,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Covered	T7,T62,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Unreachable
1	0	Covered	T7,T12,T29

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T12,T29
DetectSt	168	Covered	T7,T12,T29
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T12,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T12,T29
DebounceSt->IdleSt	163	Covered	T12,T103,T93
DetectSt->IdleSt	186	Covered	T7,T62,T92
DetectSt->StableSt	191	Covered	T7,T12,T29
IdleSt->DebounceSt	148	Covered	T7,T12,T29
StableSt->IdleSt	206	Covered	T7,T12,T29

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T12,T29
0	1	Covered	T7,T12,T29
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T29
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T12,T29
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T12,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T103,T93
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T12,T29
DetectSt	-	-	-	-	1	-	-	Covered	T7,T62,T92
DetectSt	-	-	-	-	0	1	-	Covered	T7,T12,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T12,T29
StableSt	-	-	-	-	-	-	0	Covered	T7,T12,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	182	0	0
CntIncr_A	6435794	91408	0	0
CntNoWrap_A	6435794	5784393	0	0
DetectStDropOut_A	6435794	15	0	0
DetectedOut_A	6435794	445106	0	0
DetectedPulseOut_A	6435794	54	0	0
DisabledIdleSt_A	6435794	4955395	0	0
DisabledNoDetection_A	6435794	4957769	0	0
EnterDebounceSt_A	6435794	113	0	0
EnterDetectSt_A	6435794	69	0	0
EnterStableSt_A	6435794	54	0	0
PulseIsPulse_A	6435794	54	0	0
StayInStableSt	6435794	445052	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6435794	7002	0	0
gen_low_level_sva.LowLevelEvent_A	6435794	5786949	0	0
gen_sticky_sva.StableStDropOut_A	6435794	144724	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6435794	182
T7	44580	6
T8	6649	0
T9	21006	0
T12	0	7
T29	0	2
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	4
T68	522	0
T69	527	0
T75	0	4
T76	0	2
T77	0	6
T78	0	2
T79	0	2
T80	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	6435794	91408
T7	44580	189
T8	6649	0
T9	21006	0
T12	0	297
T29	0	32
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	180
T68	522	0
T69	527	0
T75	0	190
T76	0	80
T77	0	174
T78	0	72
T79	0	71
T80	0	38

CntNoWrap_A

Name	Attempts	Real Successes
Total	6435794	5784393
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6435794	15
T7	44580	2
T8	6649	0
T9	21006	0
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	1
T68	522	0
T69	527	0
T92	0	2
T125	0	3
T126	0	1
T127	0	2
T128	0	3
T129	0	1

DetectedOut_A

Name	Attempts	Real Successes
Total	6435794	445106
T7	44580	66
T8	6649	0
T9	21006	0
T12	0	594
T29	0	138
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	1
T68	522	0
T69	527	0
T75	0	824
T76	0	239
T77	0	601
T78	0	479
T79	0	178
T80	0	333

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6435794	54
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	1
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	1
T68	522	0
T69	527	0
T75	0	2
T76	0	1
T77	0	3
T78	0	1
T79	0	1
T80	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6435794	4955395
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6435794	4957769
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6435794	113
T7	44580	3
T8	6649	0
T9	21006	0
T12	0	6
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T75	0	2
T76	0	1
T77	0	3
T78	0	1
T79	0	1
T80	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6435794	69
T7	44580	3
T8	6649	0
T9	21006	0
T12	0	1
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T75	0	2
T76	0	1
T77	0	3
T78	0	1
T79	0	1
T80	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6435794	54
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	1
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	1
T68	522	0
T69	527	0
T75	0	2
T76	0	1
T77	0	3
T78	0	1
T79	0	1
T80	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6435794	54
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	1
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	1
T68	522	0
T69	527	0
T75	0	2
T76	0	1
T77	0	3
T78	0	1
T79	0	1
T80	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	6435794	445052
T7	44580	65
T8	6649	0
T9	21006	0
T12	0	593
T29	0	137
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T75	0	822
T76	0	238
T77	0	598
T78	0	478
T79	0	177
T80	0	332
T91	0	28

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	6435794	7002
T1	25498	12
T5	409	1
T6	502	5
T14	5102	22
T15	502	4
T16	424	2
T21	499	7
T22	490	7
T23	504	5
T24	650	2

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	6435794	5786949
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6435794	144724
T7	44580	14599
T8	6649	0
T9	21006	0
T12	0	91
T29	0	119
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	56
T68	522	0
T69	527	0
T75	0	247
T76	0	135
T77	0	117
T78	0	517
T79	0	143
T80	0	138

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T21
1	1	Covered	T5,T6,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T12,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T29
1	0	Covered	T5,T6,T21
1	1	Covered	T7,T12,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Covered	T29,T75,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Unreachable
1	0	Covered	T7,T12,T29

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T12,T29
DetectSt	168	Covered	T7,T12,T29
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T12,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T12,T29
DebounceSt->IdleSt	163	Covered	T29,T75,T76
DetectSt->IdleSt	186	Covered	T29,T75,T91
DetectSt->StableSt	191	Covered	T7,T12,T29
IdleSt->DebounceSt	148	Covered	T7,T12,T29
StableSt->IdleSt	206	Covered	T7,T12,T29

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T12,T29
0	1	Covered	T7,T12,T29
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T29
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T12,T29
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T12,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T75,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T12,T29
DetectSt	-	-	-	-	1	-	-	Covered	T29,T75,T91
DetectSt	-	-	-	-	0	1	-	Covered	T7,T12,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T12,T29
StableSt	-	-	-	-	-	-	0	Covered	T7,T12,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	182	0	0
CntIncr_A	6435794	86698	0	0
CntNoWrap_A	6435794	5784393	0	0
DetectStDropOut_A	6435794	12	0	0
DetectedOut_A	6435794	178961	0	0
DetectedPulseOut_A	6435794	53	0	0
DisabledIdleSt_A	6435794	4955395	0	0
DisabledNoDetection_A	6435794	4957769	0	0
EnterDebounceSt_A	6435794	117	0	0
EnterDetectSt_A	6435794	65	0	0
EnterStableSt_A	6435794	53	0	0
PulseIsPulse_A	6435794	53	0	0
StayInStableSt	6435794	178908	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_sticky_sva.StableStDropOut_A	6435794	387387	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6435794	182
T7	44580	2
T8	6649	0
T9	21006	0
T12	0	4
T29	0	5
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	4
T68	522	0
T69	527	0
T75	0	10
T76	0	2
T77	0	6
T78	0	4
T79	0	2
T80	0	5

CntIncr_A

Name	Attempts	Real Successes
Total	6435794	86698
T7	44580	74
T8	6649	0
T9	21006	0
T12	0	93
T29	0	201
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	60
T68	522	0
T69	527	0
T75	0	424
T76	0	110
T77	0	36
T78	0	368
T79	0	88
T80	0	225

CntNoWrap_A

Name	Attempts	Real Successes
Total	6435794	5784393
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6435794	12
T29	734	1
T38	1148	0
T52	724	0
T62	760	0
T63	645	0
T75	0	2
T91	0	1
T94	446	0
T121	0	1
T127	0	3
T130	0	2
T131	0	2
T132	503	0
T133	434	0
T134	740	0
T135	421	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6435794	178961
T7	44580	361
T8	6649	0
T9	21006	0
T12	0	568
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	60
T68	522	0
T69	527	0
T77	0	87
T79	0	261
T103	0	362
T121	0	44
T122	0	17
T123	0	530

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6435794	53
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	2
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T77	0	3
T79	0	1
T103	0	1
T121	0	1
T122	0	1
T123	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6435794	4955395
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6435794	4957769
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6435794	117
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	2
T29	0	3
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T75	0	8
T76	0	2
T77	0	3
T78	0	4
T79	0	1
T80	0	5

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6435794	65
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	2
T29	0	2
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T75	0	2
T77	0	3
T79	0	1
T91	0	1
T121	0	2
T122	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6435794	53
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	2
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T77	0	3
T79	0	1
T103	0	1
T121	0	1
T122	0	1
T123	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6435794	53
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	2
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T77	0	3
T79	0	1
T103	0	1
T121	0	1
T122	0	1
T123	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	6435794	178908
T7	44580	360
T8	6649	0
T9	21006	0
T12	0	566
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	58
T68	522	0
T69	527	0
T77	0	84
T79	0	260
T103	0	361
T121	0	43
T122	0	16
T123	0	529
T136	0	420

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	6435794	5786949
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6435794	387387
T7	44580	28984
T8	6649	0
T9	21006	0
T12	0	406
T29	0	28
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	137
T68	522	0
T69	527	0
T77	0	758
T79	0	44
T103	0	236
T121	0	193
T122	0	26
T123	0	97

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T12,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T29
1	0	Covered	T5,T6,T21
1	1	Covered	T7,T12,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Covered	T77,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T29
0	1	Unreachable
1	0	Covered	T7,T12,T29

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T12,T29
DetectSt	168	Covered	T7,T12,T29
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T12,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T12,T29
DebounceSt->IdleSt	163	Covered	T77,T93,T87
DetectSt->IdleSt	186	Covered	T77,T87,T88
DetectSt->StableSt	191	Covered	T7,T12,T29
IdleSt->DebounceSt	148	Covered	T7,T12,T29
StableSt->IdleSt	206	Covered	T7,T12,T29

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T12,T29
0	1	Covered	T7,T12,T29
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T29
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T12,T29
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T12,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T93,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T12,T29
DetectSt	-	-	-	-	1	-	-	Covered	T77,T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T7,T12,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T12,T29
StableSt	-	-	-	-	-	-	0	Covered	T7,T12,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	158	0	0
CntIncr_A	6435794	10972	0	0
CntNoWrap_A	6435794	5784417	0	0
DetectStDropOut_A	6435794	7	0	0
DetectedOut_A	6435794	36491	0	0
DetectedPulseOut_A	6435794	58	0	0
DisabledIdleSt_A	6435794	4955395	0	0
DisabledNoDetection_A	6435794	4957769	0	0
EnterDebounceSt_A	6435794	93	0	0
EnterDetectSt_A	6435794	65	0	0
EnterStableSt_A	6435794	58	0	0
PulseIsPulse_A	6435794	58	0	0
StayInStableSt	6435794	36433	0	0
gen_high_event_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_sticky_sva.StableStDropOut_A	6435794	682814	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6435794	158
T7	44580	2
T8	6649	0
T9	21006	0
T12	0	4
T29	0	2
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	4
T68	522	0
T69	527	0
T75	0	4
T76	0	2
T77	0	7
T78	0	2
T79	0	2
T80	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	6435794	10972
T7	44580	5576
T8	6649	0
T9	21006	0
T12	0	93
T29	0	71
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	124
T68	522	0
T69	527	0
T75	0	190
T76	0	99
T77	0	288
T78	0	97
T79	0	13
T80	0	55

CntNoWrap_A

Name	Attempts	Real Successes
Total	6435794	5784417
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6435794	7
T77	1439	1
T78	5804	0
T79	1359	0
T87	0	1
T88	0	2
T96	6078	0
T137	0	2
T138	0	1
T139	120572	0
T140	1021	0
T141	728	0
T142	403	0
T143	11761	0
T144	737	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6435794	36491
T7	44580	23812
T8	6649	0
T9	21006	0
T12	0	655
T29	0	158
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	112
T68	522	0
T69	527	0
T75	0	985
T76	0	184
T77	0	222
T78	0	606
T79	0	60
T80	0	222

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6435794	58
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	2
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T75	0	2
T76	0	1
T77	0	2
T78	0	1
T79	0	1
T80	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6435794	4955395
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6435794	4957769
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6435794	93
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	2
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T75	0	2
T76	0	1
T77	0	4
T78	0	1
T79	0	1
T80	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6435794	65
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	2
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T75	0	2
T76	0	1
T77	0	3
T78	0	1
T79	0	1
T80	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6435794	58
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	2
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T75	0	2
T76	0	1
T77	0	2
T78	0	1
T79	0	1
T80	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6435794	58
T7	44580	1
T8	6649	0
T9	21006	0
T12	0	2
T29	0	1
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	2
T68	522	0
T69	527	0
T75	0	2
T76	0	1
T77	0	2
T78	0	1
T79	0	1
T80	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	6435794	36433
T7	44580	23811
T8	6649	0
T9	21006	0
T12	0	653
T29	0	157
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	110
T68	522	0
T69	527	0
T75	0	983
T76	0	183
T77	0	220
T78	0	605
T79	0	59
T80	0	221

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	6435794	5786949
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	6435794	5786949
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6435794	682814
T7	44580	47
T8	6649	0
T9	21006	0
T12	0	346
T29	0	74
T30	733	0
T34	2232	0
T50	681	0
T55	527	0
T58	544	0
T62	0	54
T68	522	0
T69	527	0
T75	0	113
T76	0	186
T77	0	281
T78	0	369
T79	0	322
T80	0	246

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T10,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T10,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T44
0	1	Covered	T3,T10,T41
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T44
1	-	Covered	T3,T10,T41

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T44
DetectSt	168	Covered	T3,T10,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T44
DebounceSt->IdleSt	163	Covered	T145
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T10,T44
IdleSt->DebounceSt	148	Covered	T3,T10,T44
StableSt->IdleSt	206	Covered	T3,T10,T41

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T44
0	1	Covered	T3,T10,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T44
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T145
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T41
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	65	0	0
CntIncr_A	6435794	1680	0	0
CntNoWrap_A	6435794	5784510	0	0
DetectStDropOut_A	6435794	0	0	0
DetectedOut_A	6435794	1879	0	0
DetectedPulseOut_A	6435794	32	0	0
DisabledIdleSt_A	6435794	5651742	0	0
DisabledNoDetection_A	6435794	5654066	0	0
EnterDebounceSt_A	6435794	33	0	0
EnterDetectSt_A	6435794	32	0	0
EnterStableSt_A	6435794	32	0	0
PulseIsPulse_A	6435794	32	0	0
StayInStableSt	6435794	1834	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	17	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6435794	65
T3	786	6
T7	44580	0
T8	6649	0
T9	21006	0
T10	0	2
T30	733	0
T41	0	2
T44	0	2
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T106	0	2
T121	0	4
T146	0	6
T147	0	2
T148	0	4
T149	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	6435794	1680
T3	786	117
T7	44580	0
T8	6649	0
T9	21006	0
T10	0	94
T30	733	0
T41	0	81
T44	0	17
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T106	0	77
T121	0	32
T146	0	126
T147	0	38
T148	0	142
T149	0	13

CntNoWrap_A

Name	Attempts	Real Successes
Total	6435794	5784510
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6435794	1879
T3	786	126
T7	44580	0
T8	6649	0
T9	21006	0
T10	0	139
T30	733	0
T41	0	27
T44	0	41
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T106	0	44
T121	0	108
T146	0	56
T147	0	41
T148	0	107
T149	0	87

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6435794	32
T3	786	3
T7	44580	0
T8	6649	0
T9	21006	0
T10	0	1
T30	733	0
T41	0	1
T44	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T106	0	1
T121	0	2
T146	0	3
T147	0	1
T148	0	2
T149	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6435794	5651742
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6435794	5654066
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6435794	33
T3	786	3
T7	44580	0
T8	6649	0
T9	21006	0
T10	0	1
T30	733	0
T41	0	1
T44	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T106	0	1
T121	0	2
T146	0	3
T147	0	1
T148	0	2
T149	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6435794	32
T3	786	3
T7	44580	0
T8	6649	0
T9	21006	0
T10	0	1
T30	733	0
T41	0	1
T44	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T106	0	1
T121	0	2
T146	0	3
T147	0	1
T148	0	2
T149	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6435794	32
T3	786	3
T7	44580	0
T8	6649	0
T9	21006	0
T10	0	1
T30	733	0
T41	0	1
T44	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T106	0	1
T121	0	2
T146	0	3
T147	0	1
T148	0	2
T149	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6435794	32
T3	786	3
T7	44580	0
T8	6649	0
T9	21006	0
T10	0	1
T30	733	0
T41	0	1
T44	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T106	0	1
T121	0	2
T146	0	3
T147	0	1
T148	0	2
T149	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	6435794	1834
T3	786	122
T7	44580	0
T8	6649	0
T9	21006	0
T10	0	138
T30	733	0
T41	0	26
T44	0	39
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T106	0	42
T121	0	104
T146	0	53
T147	0	39
T148	0	105
T149	0	86

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	6435794	5786949
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6435794	17
T3	786	2
T7	44580	0
T8	6649	0
T9	21006	0
T10	0	1
T30	733	0
T41	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T146	0	3
T148	0	2
T149	0	1
T150	0	1
T151	0	2
T152	0	1
T153	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T11,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T6,T21,T22
1	1	Covered	T3,T11,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T44
0	1	Covered	T3
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T44
0	1	Covered	T3,T44,T42
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T44
1	-	Covered	T3,T44,T42

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T44
DetectSt	168	Covered	T3,T11,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T11,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T44
DebounceSt->IdleSt	163	Covered	T154,T146,T155
DetectSt->IdleSt	186	Covered	T3
DetectSt->StableSt	191	Covered	T3,T11,T44
IdleSt->DebounceSt	148	Covered	T3,T11,T44
StableSt->IdleSt	206	Covered	T3,T44,T42

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T44
0	1	Covered	T3,T11,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T44
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T154,T146,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T44
DetectSt	-	-	-	-	1	-	-	Covered	T3
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T44,T42
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	108	0	0
CntIncr_A	6435794	27740	0	0
CntNoWrap_A	6435794	5784467	0	0
DetectStDropOut_A	6435794	1	0	0
DetectedOut_A	6435794	4619	0	0
DetectedPulseOut_A	6435794	50	0	0
DisabledIdleSt_A	6435794	5647739	0	0
DisabledNoDetection_A	6435794	5650064	0	0
EnterDebounceSt_A	6435794	57	0	0
EnterDetectSt_A	6435794	51	0	0
EnterStableSt_A	6435794	50	0	0
PulseIsPulse_A	6435794	50	0	0
StayInStableSt	6435794	4541	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6435794	2579	0	0
gen_low_level_sva.LowLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	20	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6435794	108
T3	786	6
T7	44580	0
T8	6649	0
T9	21006	0
T11	0	2
T30	733	0
T38	0	2
T41	0	6
T42	0	2
T44	0	2
T45	0	2
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T83	0	2
T156	0	2
T157	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	6435794	27740
T3	786	117
T7	44580	0
T8	6649	0
T9	21006	0
T11	0	92
T30	733	0
T38	0	99
T41	0	214
T42	0	89
T44	0	17
T45	0	66
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T83	0	31
T156	0	40
T157	0	69

CntNoWrap_A

Name	Attempts	Real Successes
Total	6435794	5784467
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6435794	1
T3	786	1
T7	44580	0
T8	6649	0
T9	21006	0
T30	733	0
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6435794	4619
T3	786	12
T7	44580	0
T8	6649	0
T9	21006	0
T11	0	42
T30	733	0
T38	0	118
T41	0	651
T42	0	194
T44	0	58
T45	0	381
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T83	0	78
T156	0	89
T157	0	41

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6435794	50
T3	786	2
T7	44580	0
T8	6649	0
T9	21006	0
T11	0	1
T30	733	0
T38	0	1
T41	0	3
T42	0	1
T44	0	1
T45	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T83	0	1
T156	0	1
T157	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6435794	5647739
T1	25498	25049
T4	555	154
T5	409	8
T6	502	101
T14	5102	4701
T15	502	101
T21	499	98
T22	490	89
T23	504	103
T24	650	249

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6435794	5650064
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6435794	57
T3	786	3
T7	44580	0
T8	6649	0
T9	21006	0
T11	0	1
T30	733	0
T38	0	1
T41	0	3
T42	0	1
T44	0	1
T45	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T83	0	1
T156	0	1
T157	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6435794	51
T3	786	3
T7	44580	0
T8	6649	0
T9	21006	0
T11	0	1
T30	733	0
T38	0	1
T41	0	3
T42	0	1
T44	0	1
T45	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T83	0	1
T156	0	1
T157	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6435794	50
T3	786	2
T7	44580	0
T8	6649	0
T9	21006	0
T11	0	1
T30	733	0
T38	0	1
T41	0	3
T42	0	1
T44	0	1
T45	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T83	0	1
T156	0	1
T157	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6435794	50
T3	786	2
T7	44580	0
T8	6649	0
T9	21006	0
T11	0	1
T30	733	0
T38	0	1
T41	0	3
T42	0	1
T44	0	1
T45	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T83	0	1
T156	0	1
T157	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	6435794	4541
T3	786	10
T7	44580	0
T8	6649	0
T9	21006	0
T11	0	40
T30	733	0
T38	0	117
T41	0	646
T42	0	193
T44	0	57
T45	0	379
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T83	0	76
T156	0	87
T157	0	39

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	6435794	2579
T1	25498	0
T3	0	3
T6	502	4
T14	5102	0
T15	502	5
T16	424	1
T17	507	8
T19	0	1
T20	0	3
T21	499	5
T22	490	4
T23	504	6
T24	650	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	6435794	5786949
T1	25498	25059
T4	555	155
T5	409	9
T6	502	102
T14	5102	4702
T15	502	102
T21	499	99
T22	490	90
T23	504	104
T24	650	250

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6435794	20
T3	786	2
T7	44580	0
T8	6649	0
T9	21006	0
T30	733	0
T38	0	1
T41	0	1
T42	0	1
T44	0	1
T50	681	0
T55	527	0
T58	544	0
T68	522	0
T69	527	0
T122	0	1
T146	0	1
T158	0	1
T159	0	2
T160	0	1

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr