Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T21
1	1	Covered	T4,T6,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T44,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T12,T44,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T44,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T44
1	0	Covered	T4,T6,T21
1	1	Covered	T12,T44,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T44,T42
0	1	Covered	T90,T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T44,T42
0	1	Covered	T12,T44,T42
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T44,T42
1	-	Covered	T12,T44,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T44,T42
DetectSt	168	Covered	T12,T44,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T44,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T44,T42
DebounceSt->IdleSt	163	Covered	T148,T161
DetectSt->IdleSt	186	Covered	T90,T151
DetectSt->StableSt	191	Covered	T12,T44,T42
IdleSt->DebounceSt	148	Covered	T12,T44,T42
StableSt->IdleSt	206	Covered	T12,T44,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T44,T42
0	1	Covered	T12,T44,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T44,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T44,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T21
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T44,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T148
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T44,T42
DetectSt	-	-	-	-	1	-	-	Covered	T90,T151
DetectSt	-	-	-	-	0	1	-	Covered	T12,T44,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T44,T42
StableSt	-	-	-	-	-	-	0	Covered	T12,T44,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	91	0	0
CntIncr_A	6435794	2393	0	0
CntNoWrap_A	6435794	5784484	0	0
DetectStDropOut_A	6435794	2	0	0
DetectedOut_A	6435794	2637	0	0
DetectedPulseOut_A	6435794	43	0	0
DisabledIdleSt_A	6435794	5451840	0	0
DisabledNoDetection_A	6435794	5454157	0	0
EnterDebounceSt_A	6435794	47	0	0
EnterDetectSt_A	6435794	45	0	0
EnterStableSt_A	6435794	43	0	0
PulseIsPulse_A	6435794	43	0	0
StayInStableSt	6435794	2573	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	91	0	0
T12	13125	2	0	0
T13	7313	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T41	0	6	0	0
T42	0	2	0	0
T44	569	4	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	4	0	0
T122	0	2	0	0
T162	0	2	0	0
T163	0	2	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2393	0	0
T12	13125	35	0	0
T13	7313	0	0	0
T38	0	99	0	0
T39	0	60	0	0
T41	0	201	0	0
T42	0	89	0	0
T44	569	34	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	29	0	0
T122	0	51	0	0
T162	0	19	0	0
T163	0	70	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784484	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2	0	0
T90	6029	1	0	0
T109	33271	0	0	0
T148	1031	0	0	0
T151	0	1	0	0
T169	1658	0	0	0
T170	44557	0	0	0
T171	405	0	0	0
T172	502	0	0	0
T173	531	0	0	0
T174	20147	0	0	0
T175	440	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2637	0	0
T12	13125	18	0	0
T13	7313	0	0	0
T38	0	258	0	0
T39	0	45	0	0
T41	0	246	0	0
T42	0	40	0	0
T44	569	80	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	116	0	0
T122	0	96	0	0
T162	0	43	0	0
T163	0	40	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	43	0	0
T12	13125	1	0	0
T13	7313	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	3	0	0
T42	0	1	0	0
T44	569	2	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	2	0	0
T122	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5451840	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5454157	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	47	0	0
T12	13125	1	0	0
T13	7313	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	3	0	0
T42	0	1	0	0
T44	569	2	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	2	0	0
T122	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	45	0	0
T12	13125	1	0	0
T13	7313	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	3	0	0
T42	0	1	0	0
T44	569	2	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	2	0	0
T122	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	43	0	0
T12	13125	1	0	0
T13	7313	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	3	0	0
T42	0	1	0	0
T44	569	2	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	2	0	0
T122	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	43	0	0
T12	13125	1	0	0
T13	7313	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	3	0	0
T42	0	1	0	0
T44	569	2	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	2	0	0
T122	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2573	0	0
T12	13125	17	0	0
T13	7313	0	0	0
T38	0	257	0	0
T39	0	43	0	0
T41	0	242	0	0
T42	0	39	0	0
T44	569	77	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	113	0	0
T122	0	95	0	0
T162	0	41	0	0
T163	0	39	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	20	0	0
T12	13125	1	0	0
T13	7313	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	569	1	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	1	0	0
T122	0	1	0	0
T146	0	2	0	0
T163	0	1	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T38,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T42,T38,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T38,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T38,T43
1	0	Covered	T4,T6,T21
1	1	Covered	T42,T38,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T42,T38,T43
0	1	Covered	T83,T150,T153
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T38,T43
0	1	Covered	T42,T38,T39
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T38,T43
1	-	Covered	T42,T38,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T42,T38,T43
DetectSt	168	Covered	T42,T38,T43
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T42,T38,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T42,T38,T43
DebounceSt->IdleSt	163	Covered	T161,T176
DetectSt->IdleSt	186	Covered	T83,T150,T153
DetectSt->StableSt	191	Covered	T42,T38,T43
IdleSt->DebounceSt	148	Covered	T42,T38,T43
StableSt->IdleSt	206	Covered	T42,T38,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T38,T43
0	1	Covered	T42,T38,T43
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T38,T43
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T38,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T38,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T161
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T38,T43
DetectSt	-	-	-	-	1	-	-	Covered	T83,T150,T153
DetectSt	-	-	-	-	0	1	-	Covered	T42,T38,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T42,T38,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	109	0	0
CntIncr_A	6435794	84077	0	0
CntNoWrap_A	6435794	5784466	0	0
DetectStDropOut_A	6435794	3	0	0
DetectedOut_A	6435794	28746	0	0
DetectedPulseOut_A	6435794	51	0	0
DisabledIdleSt_A	6435794	5451271	0	0
DisabledNoDetection_A	6435794	5453601	0	0
EnterDebounceSt_A	6435794	56	0	0
EnterDetectSt_A	6435794	54	0	0
EnterStableSt_A	6435794	51	0	0
PulseIsPulse_A	6435794	51	0	0
StayInStableSt	6435794	28674	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6435794	2936	0	0
gen_low_level_sva.LowLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	109	0	0
T35	19093	0	0	0
T36	17035	0	0	0
T38	0	4	0	0
T39	0	10	0	0
T41	0	6	0	0
T42	993	4	0	0
T43	0	2	0	0
T47	7197	0	0	0
T64	492	0	0	0
T72	1099	0	0	0
T73	475	0	0	0
T83	0	2	0	0
T121	0	4	0	0
T146	0	4	0	0
T157	0	2	0	0
T163	0	4	0	0
T177	550	0	0	0
T178	820	0	0	0
T179	522	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	84077	0	0
T35	19093	0	0	0
T36	17035	0	0	0
T38	0	198	0	0
T39	0	236	0	0
T41	0	217	0	0
T42	993	178	0	0
T43	0	55032	0	0
T47	7197	0	0	0
T64	492	0	0	0
T72	1099	0	0	0
T73	475	0	0	0
T83	0	31	0	0
T121	0	20	0	0
T146	0	68	0	0
T157	0	69	0	0
T163	0	140	0	0
T177	550	0	0	0
T178	820	0	0	0
T179	522	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784466	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	3	0	0
T54	11897	0	0	0
T67	494	0	0	0
T83	1808	1	0	0
T150	0	1	0	0
T153	0	1	0	0
T180	423	0	0	0
T181	21763	0	0	0
T182	669	0	0	0
T183	6912	0	0	0
T184	433	0	0	0
T185	490	0	0	0
T186	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	28746	0	0
T35	19093	0	0	0
T36	17035	0	0	0
T38	0	182	0	0
T39	0	217	0	0
T41	0	183	0	0
T42	993	274	0	0
T43	0	42	0	0
T47	7197	0	0	0
T64	492	0	0	0
T72	1099	0	0	0
T73	475	0	0	0
T121	0	101	0	0
T146	0	160	0	0
T157	0	43	0	0
T160	0	137	0	0
T163	0	460	0	0
T177	550	0	0	0
T178	820	0	0	0
T179	522	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	51	0	0
T35	19093	0	0	0
T36	17035	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T41	0	3	0	0
T42	993	2	0	0
T43	0	1	0	0
T47	7197	0	0	0
T64	492	0	0	0
T72	1099	0	0	0
T73	475	0	0	0
T121	0	2	0	0
T146	0	2	0	0
T157	0	1	0	0
T160	0	1	0	0
T163	0	2	0	0
T177	550	0	0	0
T178	820	0	0	0
T179	522	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5451271	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5453601	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	56	0	0
T35	19093	0	0	0
T36	17035	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T41	0	3	0	0
T42	993	2	0	0
T43	0	1	0	0
T47	7197	0	0	0
T64	492	0	0	0
T72	1099	0	0	0
T73	475	0	0	0
T83	0	1	0	0
T121	0	2	0	0
T146	0	2	0	0
T157	0	1	0	0
T163	0	2	0	0
T177	550	0	0	0
T178	820	0	0	0
T179	522	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	54	0	0
T35	19093	0	0	0
T36	17035	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T41	0	3	0	0
T42	993	2	0	0
T43	0	1	0	0
T47	7197	0	0	0
T64	492	0	0	0
T72	1099	0	0	0
T73	475	0	0	0
T83	0	1	0	0
T121	0	2	0	0
T146	0	2	0	0
T157	0	1	0	0
T163	0	2	0	0
T177	550	0	0	0
T178	820	0	0	0
T179	522	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	51	0	0
T35	19093	0	0	0
T36	17035	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T41	0	3	0	0
T42	993	2	0	0
T43	0	1	0	0
T47	7197	0	0	0
T64	492	0	0	0
T72	1099	0	0	0
T73	475	0	0	0
T121	0	2	0	0
T146	0	2	0	0
T157	0	1	0	0
T160	0	1	0	0
T163	0	2	0	0
T177	550	0	0	0
T178	820	0	0	0
T179	522	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	51	0	0
T35	19093	0	0	0
T36	17035	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T41	0	3	0	0
T42	993	2	0	0
T43	0	1	0	0
T47	7197	0	0	0
T64	492	0	0	0
T72	1099	0	0	0
T73	475	0	0	0
T121	0	2	0	0
T146	0	2	0	0
T157	0	1	0	0
T160	0	1	0	0
T163	0	2	0	0
T177	550	0	0	0
T178	820	0	0	0
T179	522	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	28674	0	0
T35	19093	0	0	0
T36	17035	0	0	0
T38	0	179	0	0
T39	0	210	0	0
T41	0	179	0	0
T42	993	271	0	0
T43	0	40	0	0
T47	7197	0	0	0
T64	492	0	0	0
T72	1099	0	0	0
T73	475	0	0	0
T121	0	98	0	0
T146	0	157	0	0
T157	0	42	0	0
T160	0	136	0	0
T163	0	457	0	0
T177	550	0	0	0
T178	820	0	0	0
T179	522	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2936	0	0
T1	25498	0	0	0
T3	0	1	0	0
T4	555	3	0	0
T5	409	0	0	0
T6	502	6	0	0
T14	5102	0	0	0
T15	502	5	0	0
T16	0	2	0	0
T17	0	7	0	0
T20	0	4	0	0
T21	499	4	0	0
T22	490	4	0	0
T23	504	4	0	0
T24	650	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	28	0	0
T35	19093	0	0	0
T36	17035	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T41	0	2	0	0
T42	993	1	0	0
T47	7197	0	0	0
T64	492	0	0	0
T72	1099	0	0	0
T73	475	0	0	0
T121	0	1	0	0
T146	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T163	0	1	0	0
T177	550	0	0	0
T178	820	0	0	0
T179	522	0	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T21
1	1	Covered	T5,T6,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T5,T6,T21
1	1	Covered	T3,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T89,T90,T188
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T3,T12,T44
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T12
1	-	Covered	T3,T12,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T12
DetectSt	168	Covered	T3,T11,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T12
DebounceSt->IdleSt	163	Covered	T12,T90,T189
DetectSt->IdleSt	186	Covered	T89,T90,T188
DetectSt->StableSt	191	Covered	T3,T11,T12
IdleSt->DebounceSt	148	Covered	T3,T11,T12
StableSt->IdleSt	206	Covered	T3,T12,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T12
0	1	Covered	T3,T11,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T21
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T90,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T89,T90,T188
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T12,T44
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	107	0	0
CntIncr_A	6435794	93795	0	0
CntNoWrap_A	6435794	5784468	0	0
DetectStDropOut_A	6435794	3	0	0
DetectedOut_A	6435794	20231	0	0
DetectedPulseOut_A	6435794	48	0	0
DisabledIdleSt_A	6435794	5571301	0	0
DisabledNoDetection_A	6435794	5573622	0	0
EnterDebounceSt_A	6435794	57	0	0
EnterDetectSt_A	6435794	51	0	0
EnterStableSt_A	6435794	48	0	0
PulseIsPulse_A	6435794	48	0	0
StayInStableSt	6435794	20162	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	107	0	0
T3	786	2	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	2	0	0
T12	0	3	0	0
T30	733	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T41	0	10	0	0
T43	0	2	0	0
T44	0	2	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T73	0	2	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	93795	0	0
T3	786	39	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	92	0	0
T12	0	70	0	0
T30	733	0	0	0
T38	0	198	0	0
T39	0	103	0	0
T41	0	360	0	0
T43	0	55032	0	0
T44	0	17	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T73	0	19	0	0
T183	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784468	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	3	0	0
T89	37966	1	0	0
T90	0	1	0	0
T107	18845	0	0	0
T125	2026	0	0	0
T126	1087	0	0	0
T188	0	1	0	0
T190	22468	0	0	0
T191	830	0	0	0
T192	583	0	0	0
T193	14353	0	0	0
T194	506	0	0	0
T195	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	20231	0	0
T3	786	130	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	43	0	0
T12	0	18	0	0
T30	733	0	0	0
T38	0	257	0	0
T39	0	157	0	0
T41	0	784	0	0
T43	0	6811	0	0
T44	0	7	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T73	0	38	0	0
T183	0	53	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	48	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	5	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T73	0	1	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5571301	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5573622	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	57	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	5	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T73	0	1	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	51	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	5	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T73	0	1	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	48	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	5	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T73	0	1	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	48	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	5	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T73	0	1	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	20162	0	0
T3	786	129	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	41	0	0
T12	0	17	0	0
T30	733	0	0	0
T38	0	255	0	0
T39	0	155	0	0
T41	0	776	0	0
T43	0	6810	0	0
T44	0	6	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T73	0	36	0	0
T183	0	51	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	25	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T12	0	1	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T146	0	2	0	0
T163	0	1	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T5,T6,T21
1	1	Covered	T3,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T12
0	1	Covered	T12,T38,T41
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T12
1	-	Covered	T12,T38,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T12
DetectSt	168	Covered	T3,T10,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T12
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T10,T12
IdleSt->DebounceSt	148	Covered	T3,T10,T12
StableSt->IdleSt	206	Covered	T10,T12,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T12
0	1	Covered	T3,T10,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T12
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T38,T41
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	90	0	0
CntIncr_A	6435794	57612	0	0
CntNoWrap_A	6435794	5784485	0	0
DetectStDropOut_A	6435794	0	0	0
DetectedOut_A	6435794	4037	0	0
DetectedPulseOut_A	6435794	45	0	0
DisabledIdleSt_A	6435794	5649007	0	0
DisabledNoDetection_A	6435794	5651323	0	0
EnterDebounceSt_A	6435794	45	0	0
EnterDetectSt_A	6435794	45	0	0
EnterStableSt_A	6435794	45	0	0
PulseIsPulse_A	6435794	45	0	0
StayInStableSt	6435794	3964	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6435794	6601	0	0
gen_low_level_sva.LowLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	90	0	0
T3	786	2	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T10	0	2	0	0
T12	0	4	0	0
T30	733	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T121	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	57612	0	0
T3	786	39	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T10	0	94	0	0
T12	0	70	0	0
T30	733	0	0	0
T38	0	198	0	0
T39	0	103	0	0
T41	0	65	0	0
T42	0	89	0	0
T43	0	55032	0	0
T44	0	17	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T121	0	164	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784485	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	4037	0	0
T3	786	168	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T10	0	274	0	0
T12	0	76	0	0
T30	733	0	0	0
T38	0	83	0	0
T39	0	209	0	0
T41	0	108	0	0
T42	0	212	0	0
T43	0	42	0	0
T44	0	118	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T121	0	232	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	45	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T121	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5649007	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5651323	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	45	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T121	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	45	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	45	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T121	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	45	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T121	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	3964	0	0
T3	786	166	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T10	0	272	0	0
T12	0	73	0	0
T30	733	0	0	0
T38	0	80	0	0
T39	0	205	0	0
T41	0	107	0	0
T42	0	210	0	0
T43	0	40	0	0
T44	0	116	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T121	0	229	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	6601	0	0
T1	25498	11	0	0
T5	409	1	0	0
T6	502	6	0	0
T14	5102	20	0	0
T15	502	5	0	0
T16	424	5	0	0
T21	499	8	0	0
T22	490	8	0	0
T23	504	5	0	0
T24	650	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	15	0	0
T12	13125	1	0	0
T13	7313	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	569	0	0	0
T48	21789	0	0	0
T59	789	0	0	0
T90	0	1	0	0
T121	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T149	0	2	0	0
T151	0	1	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T21,T22
1	1	Covered	T5,T6,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T11,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T42
1	0	Covered	T5,T6,T21
1	1	Covered	T3,T11,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T42
0	1	Covered	T3,T72,T40
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T42
1	-	Covered	T3,T72,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T42
DetectSt	168	Covered	T3,T11,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T11,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T42
DebounceSt->IdleSt	163	Covered	T73,T103,T198
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T11,T42
IdleSt->DebounceSt	148	Covered	T3,T11,T42
StableSt->IdleSt	206	Covered	T3,T72,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T42
0	1	Covered	T3,T11,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T21
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T73,T103,T198
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T72,T40
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	130	0	0
CntIncr_A	6435794	62897	0	0
CntNoWrap_A	6435794	5784445	0	0
DetectStDropOut_A	6435794	0	0	0
DetectedOut_A	6435794	62857	0	0
DetectedPulseOut_A	6435794	63	0	0
DisabledIdleSt_A	6435794	5446360	0	0
DisabledNoDetection_A	6435794	5448676	0	0
EnterDebounceSt_A	6435794	67	0	0
EnterDetectSt_A	6435794	63	0	0
EnterStableSt_A	6435794	63	0	0
PulseIsPulse_A	6435794	63	0	0
StayInStableSt	6435794	62769	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	130	0	0
T3	786	4	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	2	0	0
T30	733	0	0	0
T38	0	4	0	0
T39	0	2	0	0
T40	0	4	0	0
T41	0	10	0	0
T42	0	2	0	0
T45	0	2	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	6	0	0
T73	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	62897	0	0
T3	786	78	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	92	0	0
T30	733	0	0	0
T38	0	198	0	0
T39	0	73	0	0
T40	0	58	0	0
T41	0	360	0	0
T42	0	89	0	0
T45	0	66	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	264	0	0
T73	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784445	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	62857	0	0
T3	786	210	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	137	0	0
T30	733	0	0	0
T38	0	177	0	0
T39	0	259	0	0
T40	0	84	0	0
T41	0	276	0	0
T42	0	58	0	0
T45	0	255	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	290	0	0
T121	0	293	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	63	0	0
T3	786	2	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	5	0	0
T42	0	1	0	0
T45	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	3	0	0
T121	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5446360	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5448676	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	67	0	0
T3	786	2	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	5	0	0
T42	0	1	0	0
T45	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	3	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	63	0	0
T3	786	2	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	5	0	0
T42	0	1	0	0
T45	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	3	0	0
T121	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	63	0	0
T3	786	2	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	5	0	0
T42	0	1	0	0
T45	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	3	0	0
T121	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	63	0	0
T3	786	2	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T30	733	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	5	0	0
T42	0	1	0	0
T45	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	3	0	0
T121	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	62769	0	0
T3	786	207	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	135	0	0
T30	733	0	0	0
T38	0	175	0	0
T39	0	257	0	0
T40	0	81	0	0
T41	0	271	0	0
T42	0	56	0	0
T45	0	253	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	286	0	0
T121	0	288	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	36	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T30	733	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	5	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0
T146	0	3	0	0
T163	0	1	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T40,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T12,T40,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T40,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T44,T40
1	0	Covered	T5,T6,T21
1	1	Covered	T12,T40,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T40,T41
0	1	Covered	T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T40,T41
0	1	Covered	T12,T40,T146
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T40,T41
1	-	Covered	T12,T40,T146

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T40,T41
DetectSt	168	Covered	T12,T40,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T40,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T40,T41
DebounceSt->IdleSt	163	Covered	T146
DetectSt->IdleSt	186	Covered	T88
DetectSt->StableSt	191	Covered	T12,T40,T41
IdleSt->DebounceSt	148	Covered	T12,T40,T41
StableSt->IdleSt	206	Covered	T12,T40,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T40,T41
0	1	Covered	T12,T40,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T40,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T40,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T40,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T146
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T40,T41
DetectSt	-	-	-	-	1	-	-	Covered	T88
DetectSt	-	-	-	-	0	1	-	Covered	T12,T40,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T40,T146
StableSt	-	-	-	-	-	-	0	Covered	T12,T40,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	59	0	0
CntIncr_A	6435794	1506	0	0
CntNoWrap_A	6435794	5784516	0	0
DetectStDropOut_A	6435794	1	0	0
DetectedOut_A	6435794	2416	0	0
DetectedPulseOut_A	6435794	28	0	0
DisabledIdleSt_A	6435794	5414253	0	0
DisabledNoDetection_A	6435794	5416583	0	0
EnterDebounceSt_A	6435794	30	0	0
EnterDetectSt_A	6435794	29	0	0
EnterStableSt_A	6435794	28	0	0
PulseIsPulse_A	6435794	28	0	0
StayInStableSt	6435794	2374	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6435794	6365	0	0
gen_low_level_sva.LowLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	59	0	0
T12	13125	4	0	0
T13	7313	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T44	569	0	0	0
T48	21789	0	0	0
T56	0	2	0	0
T59	789	0	0	0
T87	0	2	0	0
T88	0	2	0	0
T90	0	2	0	0
T146	0	7	0	0
T148	0	4	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1506	0	0
T12	13125	70	0	0
T13	7313	0	0	0
T40	0	29	0	0
T41	0	55	0	0
T44	569	0	0	0
T48	21789	0	0	0
T56	0	29	0	0
T59	789	0	0	0
T87	0	22	0	0
T88	0	36	0	0
T90	0	93	0	0
T146	0	197	0	0
T148	0	142	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T187	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784516	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1	0	0
T88	68196	1	0	0
T108	14314	0	0	0
T199	30748	0	0	0
T200	2018	0	0	0
T201	490	0	0	0
T202	403	0	0	0
T203	698	0	0	0
T204	723	0	0	0
T205	425	0	0	0
T206	726	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2416	0	0
T12	13125	77	0	0
T13	7313	0	0	0
T40	0	9	0	0
T41	0	207	0	0
T44	569	0	0	0
T48	21789	0	0	0
T56	0	10	0	0
T59	789	0	0	0
T87	0	84	0	0
T90	0	265	0	0
T146	0	232	0	0
T148	0	215	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T187	0	68	0	0
T198	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	28	0	0
T12	13125	2	0	0
T13	7313	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	569	0	0	0
T48	21789	0	0	0
T56	0	1	0	0
T59	789	0	0	0
T87	0	1	0	0
T90	0	1	0	0
T146	0	3	0	0
T148	0	2	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T187	0	1	0	0
T198	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5414253	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5416583	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	30	0	0
T12	13125	2	0	0
T13	7313	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	569	0	0	0
T48	21789	0	0	0
T56	0	1	0	0
T59	789	0	0	0
T87	0	1	0	0
T88	0	1	0	0
T90	0	1	0	0
T146	0	4	0	0
T148	0	2	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	29	0	0
T12	13125	2	0	0
T13	7313	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	569	0	0	0
T48	21789	0	0	0
T56	0	1	0	0
T59	789	0	0	0
T87	0	1	0	0
T88	0	1	0	0
T90	0	1	0	0
T146	0	3	0	0
T148	0	2	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	28	0	0
T12	13125	2	0	0
T13	7313	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	569	0	0	0
T48	21789	0	0	0
T56	0	1	0	0
T59	789	0	0	0
T87	0	1	0	0
T90	0	1	0	0
T146	0	3	0	0
T148	0	2	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T187	0	1	0	0
T198	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	28	0	0
T12	13125	2	0	0
T13	7313	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	569	0	0	0
T48	21789	0	0	0
T56	0	1	0	0
T59	789	0	0	0
T87	0	1	0	0
T90	0	1	0	0
T146	0	3	0	0
T148	0	2	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T187	0	1	0	0
T198	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2374	0	0
T12	13125	74	0	0
T13	7313	0	0	0
T40	0	8	0	0
T41	0	205	0	0
T44	569	0	0	0
T48	21789	0	0	0
T56	0	9	0	0
T59	789	0	0	0
T87	0	82	0	0
T90	0	263	0	0
T146	0	228	0	0
T148	0	212	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T187	0	66	0	0
T198	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	6365	0	0
T1	25498	9	0	0
T5	409	1	0	0
T6	502	4	0	0
T14	5102	25	0	0
T15	502	6	0	0
T16	424	2	0	0
T17	0	5	0	0
T21	499	8	0	0
T22	490	6	0	0
T23	504	4	0	0
T24	650	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	12	0	0
T12	13125	1	0	0
T13	7313	0	0	0
T40	0	1	0	0
T44	569	0	0	0
T48	21789	0	0	0
T59	789	0	0	0
T145	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T197	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0