Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T21
1	1	Covered	T5,T6,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T46,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T46,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T46,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T6,T21
1	1	Covered	T10,T46,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T46,T45
0	1	Covered	T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T46,T45
0	1	Covered	T10,T45,T38
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T46,T45
1	-	Covered	T10,T45,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T46,T45
DetectSt	168	Covered	T10,T46,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T46,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T46,T45
DebounceSt->IdleSt	163	Covered	T41,T209,T148
DetectSt->IdleSt	186	Covered	T151
DetectSt->StableSt	191	Covered	T10,T46,T45
IdleSt->DebounceSt	148	Covered	T10,T46,T45
StableSt->IdleSt	206	Covered	T10,T45,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T46,T45
0	1	Covered	T10,T46,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T46,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T46,T45
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T21
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T46,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T209,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T46,T45
DetectSt	-	-	-	-	1	-	-	Covered	T151
DetectSt	-	-	-	-	0	1	-	Covered	T10,T46,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T45,T38
StableSt	-	-	-	-	-	-	0	Covered	T10,T46,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	138	0	0
CntIncr_A	6435794	5976	0	0
CntNoWrap_A	6435794	5784437	0	0
DetectStDropOut_A	6435794	1	0	0
DetectedOut_A	6435794	5823	0	0
DetectedPulseOut_A	6435794	66	0	0
DisabledIdleSt_A	6435794	5684999	0	0
DisabledNoDetection_A	6435794	5687319	0	0
EnterDebounceSt_A	6435794	73	0	0
EnterDetectSt_A	6435794	67	0	0
EnterStableSt_A	6435794	66	0	0
PulseIsPulse_A	6435794	66	0	0
StayInStableSt	6435794	5727	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	138	0	0
T10	37590	4	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	2	0	0
T39	0	6	0	0
T41	0	13	0	0
T45	0	2	0	0
T46	0	2	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	10	0	0
T122	0	2	0	0
T162	0	2	0	0
T164	423	0	0	0
T183	0	2	0	0
T210	422	0	0	0
T211	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5976	0	0
T10	37590	188	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	99	0	0
T39	0	176	0	0
T41	0	470	0	0
T45	0	66	0	0
T46	0	12	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	197	0	0
T122	0	59	0	0
T162	0	19	0	0
T164	423	0	0	0
T183	0	12	0	0
T210	422	0	0	0
T211	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784437	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1	0	0
T138	1691	0	0	0
T151	6939	1	0	0
T212	4970	0	0	0
T213	627	0	0	0
T214	12691	0	0	0
T215	785	0	0	0
T216	502	0	0	0
T217	13813	0	0	0
T218	21576	0	0	0
T219	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5823	0	0
T10	37590	426	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	382	0	0
T39	0	190	0	0
T41	0	321	0	0
T45	0	276	0	0
T46	0	50	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	506	0	0
T122	0	5	0	0
T162	0	76	0	0
T164	423	0	0	0
T183	0	53	0	0
T210	422	0	0	0
T211	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	66	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T41	0	6	0	0
T45	0	1	0	0
T46	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	5	0	0
T122	0	1	0	0
T162	0	1	0	0
T164	423	0	0	0
T183	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5684999	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5687319	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	73	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T41	0	7	0	0
T45	0	1	0	0
T46	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	5	0	0
T122	0	1	0	0
T162	0	1	0	0
T164	423	0	0	0
T183	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	67	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T41	0	6	0	0
T45	0	1	0	0
T46	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	5	0	0
T122	0	1	0	0
T162	0	1	0	0
T164	423	0	0	0
T183	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	66	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T41	0	6	0	0
T45	0	1	0	0
T46	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	5	0	0
T122	0	1	0	0
T162	0	1	0	0
T164	423	0	0	0
T183	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	66	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T41	0	6	0	0
T45	0	1	0	0
T46	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	5	0	0
T122	0	1	0	0
T162	0	1	0	0
T164	423	0	0	0
T183	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5727	0	0
T10	37590	423	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	381	0	0
T39	0	186	0	0
T41	0	312	0	0
T45	0	275	0	0
T46	0	48	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	499	0	0
T122	0	4	0	0
T162	0	74	0	0
T164	423	0	0	0
T183	0	51	0	0
T210	422	0	0	0
T211	424	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	34	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	3	0	0
T45	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T89	0	1	0	0
T121	0	3	0	0
T122	0	1	0	0
T146	0	2	0	0
T164	423	0	0	0
T191	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T40,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T40,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T40,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T6,T21,T22
1	1	Covered	T10,T40,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T38
0	1	Covered	T10,T41,T121
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T40,T38
1	-	Covered	T10,T41,T121

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T40,T38
DetectSt	168	Covered	T10,T40,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T40,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T40,T38
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T40,T38
IdleSt->DebounceSt	148	Covered	T10,T40,T38
StableSt->IdleSt	206	Covered	T10,T39,T139

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T40,T38
0	1	Covered	T10,T40,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T40,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T40,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T40,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T40,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T40,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T41,T121
StableSt	-	-	-	-	-	-	0	Covered	T10,T40,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	74	0	0
CntIncr_A	6435794	60751	0	0
CntNoWrap_A	6435794	5784501	0	0
DetectStDropOut_A	6435794	0	0	0
DetectedOut_A	6435794	2569	0	0
DetectedPulseOut_A	6435794	37	0	0
DisabledIdleSt_A	6435794	5568620	0	0
DisabledNoDetection_A	6435794	5570938	0	0
EnterDebounceSt_A	6435794	37	0	0
EnterDetectSt_A	6435794	37	0	0
EnterStableSt_A	6435794	37	0	0
PulseIsPulse_A	6435794	37	0	0
StayInStableSt	6435794	2511	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6435794	6207	0	0
gen_low_level_sva.LowLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	74	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	6	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	6	0	0
T122	0	2	0	0
T139	0	2	0	0
T146	0	4	0	0
T164	423	0	0	0
T196	0	2	0	0
T210	422	0	0	0
T211	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	60751	0	0
T10	37590	94	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	99	0	0
T39	0	30	0	0
T40	0	29	0	0
T41	0	230	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	102	0	0
T122	0	59	0	0
T139	0	58576	0	0
T146	0	117	0	0
T164	423	0	0	0
T196	0	19	0	0
T210	422	0	0	0
T211	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784501	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2569	0	0
T10	37590	42	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	157	0	0
T39	0	154	0	0
T40	0	46	0	0
T41	0	173	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	242	0	0
T122	0	46	0	0
T139	0	42	0	0
T146	0	189	0	0
T164	423	0	0	0
T196	0	41	0	0
T210	422	0	0	0
T211	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	37	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	3	0	0
T122	0	1	0	0
T139	0	1	0	0
T146	0	2	0	0
T164	423	0	0	0
T196	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5568620	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5570938	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	37	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	3	0	0
T122	0	1	0	0
T139	0	1	0	0
T146	0	2	0	0
T164	423	0	0	0
T196	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	37	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	3	0	0
T122	0	1	0	0
T139	0	1	0	0
T146	0	2	0	0
T164	423	0	0	0
T196	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	37	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	3	0	0
T122	0	1	0	0
T139	0	1	0	0
T146	0	2	0	0
T164	423	0	0	0
T196	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	37	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	3	0	0
T122	0	1	0	0
T139	0	1	0	0
T146	0	2	0	0
T164	423	0	0	0
T196	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2511	0	0
T10	37590	41	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	155	0	0
T39	0	152	0	0
T40	0	44	0	0
T41	0	170	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	238	0	0
T122	0	44	0	0
T139	0	40	0	0
T146	0	185	0	0
T164	423	0	0	0
T196	0	39	0	0
T210	422	0	0	0
T211	424	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	6207	0	0
T1	25498	15	0	0
T2	0	11	0	0
T6	502	5	0	0
T14	5102	27	0	0
T15	502	7	0	0
T16	424	2	0	0
T17	507	6	0	0
T21	499	6	0	0
T22	490	5	0	0
T23	504	7	0	0
T24	650	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	14	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T41	0	3	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T88	0	1	0	0
T90	0	1	0	0
T109	0	1	0	0
T121	0	2	0	0
T148	0	1	0	0
T160	0	1	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0
T220	0	1	0	0
T221	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T21
1	1	Covered	T5,T6,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T46,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T46,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T45,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T44,T46
1	0	Covered	T5,T6,T21
1	1	Covered	T10,T46,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T45,T38
0	1	Covered	T41,T151,T220
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T45,T38
0	1	Covered	T10,T45,T38
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T45,T38
1	-	Covered	T10,T45,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T46,T45
DetectSt	168	Covered	T10,T45,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T45,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T45,T38
DebounceSt->IdleSt	163	Covered	T46,T41,T207
DetectSt->IdleSt	186	Covered	T41,T151,T220
DetectSt->StableSt	191	Covered	T10,T45,T38
IdleSt->DebounceSt	148	Covered	T10,T46,T45
StableSt->IdleSt	206	Covered	T10,T45,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T46,T45
0	1	Covered	T10,T46,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T45,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T46,T45
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T21
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T45,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T41,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T46,T45
DetectSt	-	-	-	-	1	-	-	Covered	T41,T151,T220
DetectSt	-	-	-	-	0	1	-	Covered	T10,T45,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T45,T38
StableSt	-	-	-	-	-	-	0	Covered	T10,T45,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	132	0	0
CntIncr_A	6435794	141802	0	0
CntNoWrap_A	6435794	5784443	0	0
DetectStDropOut_A	6435794	3	0	0
DetectedOut_A	6435794	114062	0	0
DetectedPulseOut_A	6435794	61	0	0
DisabledIdleSt_A	6435794	5410267	0	0
DisabledNoDetection_A	6435794	5412586	0	0
EnterDebounceSt_A	6435794	68	0	0
EnterDetectSt_A	6435794	64	0	0
EnterStableSt_A	6435794	61	0	0
PulseIsPulse_A	6435794	61	0	0
StayInStableSt	6435794	113977	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	132	0	0
T10	37590	4	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T41	0	9	0	0
T43	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	4	0	0
T139	0	2	0	0
T156	0	2	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	141802	0	0
T10	37590	188	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	99	0	0
T39	0	60	0	0
T41	0	347	0	0
T43	0	55032	0	0
T45	0	66	0	0
T46	0	12	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	38	0	0
T139	0	58576	0	0
T156	0	40	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784443	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	3	0	0
T41	22832	1	0	0
T115	511	0	0	0
T116	12314	0	0	0
T117	504	0	0	0
T118	486	0	0	0
T119	413	0	0	0
T120	15590	0	0	0
T151	0	1	0	0
T220	0	1	0	0
T222	406	0	0	0
T223	7669	0	0	0
T224	658	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	114062	0	0
T10	37590	84	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	152	0	0
T39	0	158	0	0
T41	0	312	0	0
T43	0	61887	0	0
T45	0	43	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	27	0	0
T122	0	46	0	0
T139	0	42	0	0
T156	0	89	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	61	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	2	0	0
T122	0	1	0	0
T139	0	1	0	0
T156	0	1	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5410267	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5412586	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	68	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	5	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	2	0	0
T139	0	1	0	0
T156	0	1	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	64	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	4	0	0
T43	0	1	0	0
T45	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	2	0	0
T122	0	1	0	0
T139	0	1	0	0
T156	0	1	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	61	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	2	0	0
T122	0	1	0	0
T139	0	1	0	0
T156	0	1	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	61	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	2	0	0
T122	0	1	0	0
T139	0	1	0	0
T156	0	1	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	113977	0	0
T10	37590	81	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	151	0	0
T39	0	156	0	0
T41	0	308	0	0
T43	0	61885	0	0
T45	0	42	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	25	0	0
T122	0	44	0	0
T139	0	40	0	0
T156	0	87	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	35	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T45	0	1	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T121	0	2	0	0
T146	0	3	0	0
T159	0	1	0	0
T160	0	1	0	0
T164	423	0	0	0
T187	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T44,T73
1	0	Covered	T6,T21,T22
1	1	Covered	T10,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T38,T39
0	1	Covered	T188
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T41
0	1	Covered	T10,T39,T41
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T39,T41
1	-	Covered	T10,T39,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T38,T39
DetectSt	168	Covered	T10,T38,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T38,T39
DebounceSt->IdleSt	163	Covered	T189,T188
DetectSt->IdleSt	186	Covered	T188
DetectSt->StableSt	191	Covered	T10,T38,T39
IdleSt->DebounceSt	148	Covered	T10,T38,T39
StableSt->IdleSt	206	Covered	T10,T39,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T38,T39
0	1	Covered	T10,T38,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T38,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T189,T188
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T188
DetectSt	-	-	-	-	0	1	-	Covered	T10,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T39,T41
StableSt	-	-	-	-	-	-	0	Covered	T38,T39,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	86	0	0
CntIncr_A	6435794	2375	0	0
CntNoWrap_A	6435794	5784489	0	0
DetectStDropOut_A	6435794	1	0	0
DetectedOut_A	6435794	2641	0	0
DetectedPulseOut_A	6435794	41	0	0
DisabledIdleSt_A	6435794	5766827	0	0
DisabledNoDetection_A	6435794	5769147	0	0
EnterDebounceSt_A	6435794	44	0	0
EnterDetectSt_A	6435794	42	0	0
EnterStableSt_A	6435794	41	0	0
PulseIsPulse_A	6435794	41	0	0
StayInStableSt	6435794	2577	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6435794	6323	0	0
gen_low_level_sva.LowLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	86	0	0
T10	37590	2	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T41	0	8	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T106	0	2	0	0
T109	0	2	0	0
T121	0	6	0	0
T146	0	6	0	0
T154	0	2	0	0
T162	0	4	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2375	0	0
T10	37590	94	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	99	0	0
T39	0	60	0	0
T41	0	266	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T106	0	77	0	0
T109	0	92	0	0
T121	0	48	0	0
T146	0	151	0	0
T154	0	27	0	0
T162	0	119	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784489	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1	0	0
T188	11535	1	0	0
T225	707	0	0	0
T226	3385	0	0	0
T227	2026	0	0	0
T228	491	0	0	0
T229	522	0	0	0
T230	22744	0	0	0
T231	422	0	0	0
T232	402	0	0	0
T233	4545	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2641	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	45	0	0
T39	0	67	0	0
T41	0	349	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T106	0	45	0	0
T109	0	137	0	0
T121	0	142	0	0
T146	0	73	0	0
T154	0	40	0	0
T162	0	83	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	41	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	4	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T106	0	1	0	0
T109	0	1	0	0
T121	0	3	0	0
T146	0	3	0	0
T154	0	1	0	0
T162	0	2	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5766827	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5769147	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	44	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	4	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T106	0	1	0	0
T109	0	1	0	0
T121	0	3	0	0
T146	0	3	0	0
T154	0	1	0	0
T162	0	2	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	42	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	4	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T106	0	1	0	0
T109	0	1	0	0
T121	0	3	0	0
T146	0	3	0	0
T154	0	1	0	0
T162	0	2	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	41	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	4	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T106	0	1	0	0
T109	0	1	0	0
T121	0	3	0	0
T146	0	3	0	0
T154	0	1	0	0
T162	0	2	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	41	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	4	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T106	0	1	0	0
T109	0	1	0	0
T121	0	3	0	0
T146	0	3	0	0
T154	0	1	0	0
T162	0	2	0	0
T164	423	0	0	0
T210	422	0	0	0
T211	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	2577	0	0
T38	1148	43	0	0
T39	0	64	0	0
T41	0	343	0	0
T43	117328	0	0	0
T53	703	0	0	0
T66	493	0	0	0
T75	1919	0	0	0
T106	0	43	0	0
T109	0	136	0	0
T121	0	138	0	0
T135	421	0	0	0
T146	0	69	0	0
T154	0	38	0	0
T155	0	37	0	0
T162	0	79	0	0
T234	403	0	0	0
T235	419	0	0	0
T236	438	0	0	0
T237	768	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	6323	0	0
T1	25498	9	0	0
T2	0	14	0	0
T6	502	5	0	0
T14	5102	24	0	0
T15	502	2	0	0
T16	424	4	0	0
T17	507	4	0	0
T21	499	8	0	0
T22	490	10	0	0
T23	504	4	0	0
T24	650	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	16	0	0
T10	37590	1	0	0
T11	638	0	0	0
T12	13125	0	0	0
T39	0	1	0	0
T41	0	2	0	0
T59	789	0	0	0
T60	494	0	0	0
T70	522	0	0	0
T71	523	0	0	0
T109	0	1	0	0
T121	0	2	0	0
T146	0	2	0	0
T150	0	1	0	0
T164	423	0	0	0
T207	0	1	0	0
T210	422	0	0	0
T211	424	0	0	0
T238	0	1	0	0
T239	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T21
1	1	Covered	T5,T6,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T44,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T44,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T44,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T44,T73
1	0	Covered	T5,T6,T21
1	1	Covered	T11,T44,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T44,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T44,T38
0	1	Covered	T11,T44,T38
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T44,T38
1	-	Covered	T11,T44,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T44,T38
DetectSt	168	Covered	T11,T44,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T44,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T44,T38
DebounceSt->IdleSt	163	Covered	T148,T176
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T44,T38
IdleSt->DebounceSt	148	Covered	T11,T44,T38
StableSt->IdleSt	206	Covered	T11,T44,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T44,T38
0	1	Covered	T11,T44,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T44,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T44,T38
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T21
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T44,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T148
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T44,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T44,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T44,T38
StableSt	-	-	-	-	-	-	0	Covered	T11,T44,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	99	0	0
CntIncr_A	6435794	4260	0	0
CntNoWrap_A	6435794	5784476	0	0
DetectStDropOut_A	6435794	0	0	0
DetectedOut_A	6435794	5549	0	0
DetectedPulseOut_A	6435794	49	0	0
DisabledIdleSt_A	6435794	5689286	0	0
DisabledNoDetection_A	6435794	5691613	0	0
EnterDebounceSt_A	6435794	51	0	0
EnterDetectSt_A	6435794	49	0	0
EnterStableSt_A	6435794	49	0	0
PulseIsPulse_A	6435794	49	0	0
StayInStableSt	6435794	5476	0	0
gen_high_level_sva.HighLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	99	0	0
T11	638	2	0	0
T12	13125	0	0	0
T13	7313	0	0	0
T38	0	4	0	0
T41	0	2	0	0
T44	569	2	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	6	0	0
T154	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0
T163	0	4	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T196	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	4260	0	0
T11	638	92	0	0
T12	13125	0	0	0
T13	7313	0	0	0
T38	0	198	0	0
T41	0	55	0	0
T44	569	17	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	174	0	0
T154	0	27	0	0
T158	0	90	0	0
T159	0	43	0	0
T163	0	140	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T196	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784476	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5549	0	0
T11	638	2	0	0
T12	13125	0	0	0
T13	7313	0	0	0
T38	0	461	0	0
T41	0	10	0	0
T44	569	64	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	292	0	0
T154	0	41	0	0
T158	0	171	0	0
T159	0	20	0	0
T163	0	323	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T196	0	158	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	49	0	0
T11	638	1	0	0
T12	13125	0	0	0
T13	7313	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T44	569	1	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	3	0	0
T154	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T163	0	2	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T196	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5689286	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5691613	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	51	0	0
T11	638	1	0	0
T12	13125	0	0	0
T13	7313	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T44	569	1	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	3	0	0
T154	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T163	0	2	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T196	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	49	0	0
T11	638	1	0	0
T12	13125	0	0	0
T13	7313	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T44	569	1	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	3	0	0
T154	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T163	0	2	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T196	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	49	0	0
T11	638	1	0	0
T12	13125	0	0	0
T13	7313	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T44	569	1	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	3	0	0
T154	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T163	0	2	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T196	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	49	0	0
T11	638	1	0	0
T12	13125	0	0	0
T13	7313	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T44	569	1	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	3	0	0
T154	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T163	0	2	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T196	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5476	0	0
T11	638	1	0	0
T12	13125	0	0	0
T13	7313	0	0	0
T38	0	458	0	0
T41	0	9	0	0
T44	569	63	0	0
T48	21789	0	0	0
T59	789	0	0	0
T121	0	289	0	0
T154	0	39	0	0
T158	0	169	0	0
T159	0	19	0	0
T163	0	320	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T196	0	156	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	23	0	0
T11	638	1	0	0
T12	13125	0	0	0
T13	7313	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	569	1	0	0
T48	21789	0	0	0
T59	789	0	0	0
T88	0	1	0	0
T89	0	1	0	0
T121	0	3	0	0
T146	0	3	0	0
T159	0	1	0	0
T163	0	1	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T5,T6,T21
1	1	Covered	T3,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T12,T121,T163
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T12
1	-	Covered	T12,T121,T163

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T12
DetectSt	168	Covered	T3,T11,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T12
DebounceSt->IdleSt	163	Covered	T38
DetectSt->IdleSt	186	Covered	T151
DetectSt->StableSt	191	Covered	T3,T11,T12
IdleSt->DebounceSt	148	Covered	T3,T11,T12
StableSt->IdleSt	206	Covered	T12,T121,T103

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T12
0	1	Covered	T3,T11,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T38
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T151
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T121,T163
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6435794	73	0	0
CntIncr_A	6435794	26760	0	0
CntNoWrap_A	6435794	5784502	0	0
DetectStDropOut_A	6435794	1	0	0
DetectedOut_A	6435794	50675	0	0
DetectedPulseOut_A	6435794	35	0	0
DisabledIdleSt_A	6435794	5525718	0	0
DisabledNoDetection_A	6435794	5528035	0	0
EnterDebounceSt_A	6435794	37	0	0
EnterDetectSt_A	6435794	36	0	0
EnterStableSt_A	6435794	35	0	0
PulseIsPulse_A	6435794	35	0	0
StayInStableSt	6435794	50620	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6435794	7002	0	0
gen_low_level_sva.LowLevelEvent_A	6435794	5786949	0	0
gen_not_sticky_sva.StableStDropOut_A	6435794	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	73	0	0
T3	786	2	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T30	733	0	0	0
T38	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	2	0	0
T83	0	2	0	0
T103	0	2	0	0
T121	0	6	0	0
T157	0	2	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	26760	0	0
T3	786	39	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	92	0	0
T12	0	35	0	0
T30	733	0	0	0
T38	0	99	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	88	0	0
T83	0	31	0	0
T103	0	99	0	0
T121	0	183	0	0
T157	0	69	0	0
T159	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5784502	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	1	0	0
T138	1691	0	0	0
T151	6939	1	0	0
T212	4970	0	0	0
T213	627	0	0	0
T214	12691	0	0	0
T215	785	0	0	0
T216	502	0	0	0
T217	13813	0	0	0
T218	21576	0	0	0
T219	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	50675	0	0
T3	786	42	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	42	0	0
T12	0	17	0	0
T30	733	0	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	289	0	0
T83	0	47	0	0
T103	0	44	0	0
T121	0	407	0	0
T157	0	41	0	0
T159	0	194	0	0
T163	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	35	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T30	733	0	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	1	0	0
T83	0	1	0	0
T103	0	1	0	0
T121	0	3	0	0
T157	0	1	0	0
T159	0	1	0	0
T163	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5525718	0	0
T1	25498	25049	0	0
T4	555	154	0	0
T5	409	8	0	0
T6	502	101	0	0
T14	5102	4701	0	0
T15	502	101	0	0
T21	499	98	0	0
T22	490	89	0	0
T23	504	103	0	0
T24	650	249	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5528035	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	37	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T30	733	0	0	0
T38	0	1	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	1	0	0
T83	0	1	0	0
T103	0	1	0	0
T121	0	3	0	0
T157	0	1	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	36	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T30	733	0	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	1	0	0
T83	0	1	0	0
T103	0	1	0	0
T121	0	3	0	0
T157	0	1	0	0
T159	0	1	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	35	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T30	733	0	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	1	0	0
T83	0	1	0	0
T103	0	1	0	0
T121	0	3	0	0
T157	0	1	0	0
T159	0	1	0	0
T163	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	35	0	0
T3	786	1	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T30	733	0	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	1	0	0
T83	0	1	0	0
T103	0	1	0	0
T121	0	3	0	0
T157	0	1	0	0
T159	0	1	0	0
T163	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	50620	0	0
T3	786	40	0	0
T7	44580	0	0	0
T8	6649	0	0	0
T9	21006	0	0	0
T11	0	40	0	0
T12	0	16	0	0
T30	733	0	0	0
T50	681	0	0	0
T55	527	0	0	0
T58	544	0	0	0
T68	522	0	0	0
T69	527	0	0	0
T72	0	287	0	0
T83	0	45	0	0
T103	0	42	0	0
T121	0	403	0	0
T157	0	39	0	0
T159	0	192	0	0
T163	0	56	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	7002	0	0
T1	25498	12	0	0
T5	409	1	0	0
T6	502	5	0	0
T14	5102	22	0	0
T15	502	4	0	0
T16	424	2	0	0
T21	499	7	0	0
T22	490	7	0	0
T23	504	5	0	0
T24	650	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	5786949	0	0
T1	25498	25059	0	0
T4	555	155	0	0
T5	409	9	0	0
T6	502	102	0	0
T14	5102	4702	0	0
T15	502	102	0	0
T21	499	99	0	0
T22	490	90	0	0
T23	504	104	0	0
T24	650	250	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6435794	13	0	0
T12	13125	1	0	0
T13	7313	0	0	0
T44	569	0	0	0
T48	21789	0	0	0
T59	789	0	0	0
T109	0	1	0	0
T121	0	2	0	0
T146	0	2	0	0
T148	0	2	0	0
T152	0	1	0	0
T163	0	1	0	0
T164	423	0	0	0
T165	636	0	0	0
T166	402	0	0	0
T167	412	0	0	0
T168	502	0	0	0
T221	0	1	0	0
T240	0	1	0	0
T241	0	1	0	0