SYSRST_CTRL Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	11.480s	2.112ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	14.050s	2.469ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	8.330s	2.217ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	9.040s	2.518ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	21.860s	4.026ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	11.250s	2.030ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	5.156m	74.729ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	21.620s	3.334ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	11.490s	2.080ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	11.250s	2.030ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	21.620s	3.334ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	10.163m	193.421ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	8.345m	167.911ms	89	100	89.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	5.638m	124.680ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	32.670m	517.119ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	12.940s	2.512ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	11.800s	2.020ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	13.772m	1.287s	48	50	96.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	15.360s	2.613ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	7.424m	2.674s	48	50	96.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	31.330s	33.853ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	9.477m	150.921ms	49	50	98.00
V2	alert_test	sysrst_ctrl_alert_test	10.590s	2.012ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	11.380s	2.013ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	13.930s	2.045ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	13.930s	2.045ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	21.860s	4.026ms	5	5	100.00
		sysrst_ctrl_csr_rw	11.250s	2.030ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	21.620s	3.334ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	47.230s	7.910ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	21.860s	4.026ms	5	5	100.00
		sysrst_ctrl_csr_rw	11.250s	2.030ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	21.620s	3.334ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	47.230s	7.910ms	20	20	100.00
V2		TOTAL			676	692	97.69
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.563m	22.010ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	3.334m	42.478ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	3.334m	42.478ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	37.230s	2.609s	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			914	932	98.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.97	99.09	97.45	100.00	92.31	99.37	98.84	91.76

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 4 failures:

Test sysrst_ctrl_ultra_low_pwr has 2 failures.

0.sysrst_ctrl_ultra_low_pwr.100768724474307863893254060449742626609905677980046843002879835831070125173125
Line 371, in log /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2368638621 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2501138621 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 8991138621 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 11911138621 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 11920726526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

7.sysrst_ctrl_ultra_low_pwr.21868575771941204511720857435926022600048147354606853874860747541016070313297
Line 371, in log /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 286309089135 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 1140166589135 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1140166589135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_stress_all has 1 failures.

2.sysrst_ctrl_stress_all.102919218732119044281810826140270130609178801227701850725428019676523795358643
Line 372, in log /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4172011657 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 4534511657 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 7394511657 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 7424449682 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_auto_blk_key_output_vseq
  UVM_INFO @ 9419969682 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:76) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Starting the body from auto_blk_key_output_vseq

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

24.sysrst_ctrl_stress_all_with_rand_reset.89434607140927235467705586401334890898376125854378158290367069409767582240851
Line 446, in log /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 22399483472 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 22996983472 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 22996983472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 4 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 4 failures.

39.sysrst_ctrl_combo_detect_with_pre_cond.34785162207263060097264263407190756615097382676425945882808100256617570468060
Line 400, in log /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 58922726862 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 58922726862 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 58922726862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

55.sysrst_ctrl_combo_detect_with_pre_cond.49194329654558460089299224557065775088659452763071325204573533536730575138366
Line 397, in log /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 18819061213 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 18819061213 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 18819061213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

23.sysrst_ctrl_combo_detect_with_pre_cond.44513679977884535327940999972617234643021559030253889707603603512065640869609
Line 384, in log /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 15420052524 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 15435052524 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 15455052524 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_ERROR @ 15655253158 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4])
  UVM_INFO @ 15655253158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

70.sysrst_ctrl_combo_detect_with_pre_cond.72446417160541050550450174409991532067282804478618300535046530178604291974451
Line 386, in log /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 21748995472 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 21858995472 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 21878995472 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_ERROR @ 21904112832 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8])
  UVM_INFO @ 21904112832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

Job timed out after * minutes has 2 failures:
- Test sysrst_ctrl_ec_pwr_on_rst has 2 failures.
  - 26.sysrst_ctrl_ec_pwr_on_rst.28236303826652366173462147312678934724721355120649207434186888784137478147065
    Log /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  Job timed out after 60 minutes
```
  - 48.sysrst_ctrl_ec_pwr_on_rst.84057538512664332883682771775980020052011021330921917112791289071559245680392
    Log /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (cip_base_vseq.sv:101) [sysrst_ctrl_common_vseq] wait timeout occurred! has 1 failures:
- Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
  - 13.sysrst_ctrl_stress_all_with_rand_reset.96590617372812657063362929495264772335291002958804148166991979060132056361096
    Line 386, in log /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15437739254 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] wait timeout occurred!
  UVM_INFO @ 15437739254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-* has 1 failures: