Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78	95.65	90.91		83.33	95.24	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78	95.65	90.91		83.33	95.24	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	95.65	90.91		83.33	95.24	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	95.65	90.91		83.33	95.24	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T12 T13 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T27 T28 T24 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T16 T27 T28 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T16 T27 T28 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T27 T28 T24 
149        1/1                    cnt_en = 1'b1;
           Tests:       T27 T28 T24 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T27 T28 T24 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T27 T28 T24 
163        1/1                    state_d = IdleSt;
           Tests:       T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T27 T28 T24 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T27 T28 T24 
167        1/1                    if (trigger_active) begin
           Tests:       T27 T28 T24 
168        1/1                      state_d = DetectSt;
           Tests:       T28 T24 T56 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T27 T61 T109 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T28 T24 T56 
182        1/1                  cnt_en = 1'b1;
           Tests:       T28 T24 T56 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T28 T24 T56 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T28 T24 T56 
191        1/1                      state_d = StableSt;
           Tests:       T28 T24 T56 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T28 T24 T56 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T28 T24 T56 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T28 T24 T56 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T28 T24 T56 
206        1/1                    state_d = IdleSt;
           Tests:       T28 T24 T56 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T28 T24 T56 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T13
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T27,T28,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T27,T28,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T28,T24,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T24
1	0	Covered	T4,T12,T13
1	1	Covered	T27,T28,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T24,T56
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T24,T56
0	1	Covered	T28,T56,T60
1	0	Covered	T24

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T24,T56
1	-	Covered	T28,T56,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T28,T24
DetectSt	168	Covered	T28,T24,T56
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T28,T24,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T24,T56
DebounceSt->IdleSt	163	Covered	T27,T30,T61
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T28,T24,T56
IdleSt->DebounceSt	148	Covered	T27,T28,T24
StableSt->IdleSt	206	Covered	T28,T24,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T28,T24
0	1	Covered	T27,T28,T24
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T24,T56
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T28,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T30
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T24,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T61,T109
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T28,T24
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T28,T24,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T24,T56
StableSt	-	-	-	-	-	-	0	Covered	T28,T24,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	188	0	0
CntIncr_A	4787552	110983	0	0
CntNoWrap_A	4787552	4321353	0	0
DetectStDropOut_A	4787552	0	0	0
DetectedOut_A	4787552	559	0	0
DetectedPulseOut_A	4787552	85	0	0
DisabledIdleSt_A	4787552	4206214	0	0
DisabledNoDetection_A	4787552	4208012	0	0
EnterDebounceSt_A	4787552	106	0	0
EnterDetectSt_A	4787552	85	0	0
EnterStableSt_A	4787552	85	0	0
PulseIsPulse_A	4787552	85	0	0
StayInStableSt	4787552	474	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4787552	5235	0	0
gen_low_level_sva.LowLevelEvent_A	4787552	4323375	0	0
gen_not_sticky_sva.StableStDropOut_A	4787552	84	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	188	0	0
T9	1405	0	0	0
T24	0	2	0	0
T27	710	2	0	0
T28	0	6	0	0
T29	457	0	0	0
T30	0	1	0	0
T53	432	0	0	0
T54	443	0	0	0
T56	0	2	0	0
T60	0	4	0	0
T61	0	2	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T79	503	0	0	0
T107	0	6	0	0
T108	0	2	0	0
T109	0	3	0	0
T110	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	110983	0	0
T9	1405	0	0	0
T24	0	16	0	0
T27	710	97	0	0
T28	0	279	0	0
T29	457	0	0	0
T30	0	29	0	0
T53	432	0	0	0
T54	443	0	0	0
T56	0	79	0	0
T60	0	125	0	0
T61	0	179	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T79	503	0	0	0
T107	0	128	0	0
T108	0	29	0	0
T109	0	92	0	0
T110	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4321353	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	559	0	0
T10	1200	0	0	0
T23	1982	0	0	0
T24	7077	3	0	0
T28	799	15	0	0
T55	461	0	0	0
T56	0	9	0	0
T60	0	10	0	0
T64	405	0	0	0
T65	425	0	0	0
T81	522	0	0	0
T82	530	0	0	0
T107	0	12	0	0
T108	0	9	0	0
T109	0	8	0	0
T132	0	4	0	0
T133	0	8	0	0
T134	0	21	0	0
T135	426	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	85	0	0
T10	1200	0	0	0
T23	1982	0	0	0
T24	7077	1	0	0
T28	799	3	0	0
T55	461	0	0	0
T56	0	1	0	0
T60	0	2	0	0
T64	405	0	0	0
T65	425	0	0	0
T81	522	0	0	0
T82	530	0	0	0
T107	0	3	0	0
T108	0	1	0	0
T109	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	426	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4206214	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4208012	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	106	0	0
T9	1405	0	0	0
T24	0	1	0	0
T27	710	2	0	0
T28	0	3	0	0
T29	457	0	0	0
T30	0	1	0	0
T53	432	0	0	0
T54	443	0	0	0
T56	0	1	0	0
T60	0	2	0	0
T61	0	2	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T79	503	0	0	0
T107	0	3	0	0
T108	0	1	0	0
T109	0	2	0	0
T110	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	85	0	0
T10	1200	0	0	0
T23	1982	0	0	0
T24	7077	1	0	0
T28	799	3	0	0
T55	461	0	0	0
T56	0	1	0	0
T60	0	2	0	0
T64	405	0	0	0
T65	425	0	0	0
T81	522	0	0	0
T82	530	0	0	0
T107	0	3	0	0
T108	0	1	0	0
T109	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	426	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	85	0	0
T10	1200	0	0	0
T23	1982	0	0	0
T24	7077	1	0	0
T28	799	3	0	0
T55	461	0	0	0
T56	0	1	0	0
T60	0	2	0	0
T64	405	0	0	0
T65	425	0	0	0
T81	522	0	0	0
T82	530	0	0	0
T107	0	3	0	0
T108	0	1	0	0
T109	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	426	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	85	0	0
T10	1200	0	0	0
T23	1982	0	0	0
T24	7077	1	0	0
T28	799	3	0	0
T55	461	0	0	0
T56	0	1	0	0
T60	0	2	0	0
T64	405	0	0	0
T65	425	0	0	0
T81	522	0	0	0
T82	530	0	0	0
T107	0	3	0	0
T108	0	1	0	0
T109	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	426	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	474	0	0
T10	1200	0	0	0
T23	1982	0	0	0
T24	7077	2	0	0
T28	799	12	0	0
T55	461	0	0	0
T56	0	8	0	0
T60	0	8	0	0
T64	405	0	0	0
T65	425	0	0	0
T81	522	0	0	0
T82	530	0	0	0
T107	0	9	0	0
T108	0	8	0	0
T109	0	7	0	0
T132	0	2	0	0
T133	0	7	0	0
T134	0	19	0	0
T135	426	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	5235	0	0
T2	485	0	0	0
T3	1755	8	0	0
T4	510	4	0	0
T5	519	1	0	0
T7	0	10	0	0
T12	450	7	0	0
T13	422	3	0	0
T14	761	0	0	0
T15	492	7	0	0
T16	670	3	0	0
T17	408	0	0	0
T25	0	14	0	0
T26	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	84	0	0
T10	1200	0	0	0
T23	1982	0	0	0
T24	7077	0	0	0
T28	799	3	0	0
T55	461	0	0	0
T56	0	1	0	0
T60	0	2	0	0
T64	405	0	0	0
T65	425	0	0	0
T81	522	0	0	0
T82	530	0	0	0
T94	0	2	0	0
T107	0	3	0	0
T108	0	1	0	0
T109	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	426	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T12 T13 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T6 T24 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T3 T6 T23 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T3 T6 T23 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T6 T24 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T6 T24 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T24 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T6 T24 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T6 T24 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T6 T18 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T6 T18 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T6 T18 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T66 T96 T139 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T6 T18 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T18 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T6 T18 
186        1/1                    state_d = IdleSt;
           Tests:       T68 T93 T106 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T68 T93 T106 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T6 T18 
191        1/1                      state_d = StableSt;
           Tests:       T3 T6 T18 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T6 T18 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T6 T18 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T6 T18 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T6 T18 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T6 T18 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T6 T18 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T13
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T6,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T6,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T6,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T24
1	0	Covered	T4,T12,T13
1	1	Covered	T3,T6,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T18
0	1	Covered	T68,T93,T106
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T18
0	1	Unreachable
1	0	Covered	T3,T6,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T24
DetectSt	168	Covered	T3,T6,T18
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T6,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T18
DebounceSt->IdleSt	163	Covered	T24,T30,T66
DetectSt->IdleSt	186	Covered	T68,T93,T106
DetectSt->StableSt	191	Covered	T3,T6,T18
IdleSt->DebounceSt	148	Covered	T3,T6,T24
StableSt->IdleSt	206	Covered	T3,T6,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T6,T24
0	1	Covered	T3,T6,T24
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T18
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T66,T96,T139
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T24
DetectSt	-	-	-	-	1	-	-	Covered	T68,T93,T106
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T18
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	140	0	0
CntIncr_A	4787552	42981	0	0
CntNoWrap_A	4787552	4321401	0	0
DetectStDropOut_A	4787552	8	0	0
DetectedOut_A	4787552	39307	0	0
DetectedPulseOut_A	4787552	40	0	0
DisabledIdleSt_A	4787552	4146964	0	0
DisabledNoDetection_A	4787552	4148798	0	0
EnterDebounceSt_A	4787552	92	0	0
EnterDetectSt_A	4787552	48	0	0
EnterStableSt_A	4787552	40	0	0
PulseIsPulse_A	4787552	40	0	0
StayInStableSt	4787552	39267	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4787552	5235	0	0
gen_low_level_sva.LowLevelEvent_A	4787552	4323375	0	0
gen_sticky_sva.StableStDropOut_A	4787552	5274	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	140	0	0
T3	1755	2	0	0
T5	519	0	0	0
T6	0	6	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	2	0	0
T24	0	2	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	2	0	0
T58	0	2	0	0
T62	419	0	0	0
T63	422	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	10	0	0
T92	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	42981	0	0
T3	1755	88	0	0
T5	519	0	0	0
T6	0	294	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	11	0	0
T24	0	55	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	72	0	0
T58	0	73	0	0
T62	419	0	0	0
T63	422	0	0	0
T66	0	28	0	0
T67	0	99	0	0
T68	0	75	0	0
T92	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4321401	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1352	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	8	0	0
T40	11828	0	0	0
T68	1109	2	0	0
T93	0	2	0	0
T106	0	2	0	0
T140	0	2	0	0
T141	427	0	0	0
T142	557	0	0	0
T143	1346	0	0	0
T144	780	0	0	0
T145	502	0	0	0
T146	2503	0	0	0
T147	403	0	0	0
T148	442	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	39307	0	0
T3	1755	23	0	0
T5	519	0	0	0
T6	0	2392	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	68	0	0
T25	3498	0	0	0
T26	522	0	0	0
T58	0	291	0	0
T62	419	0	0	0
T63	422	0	0	0
T67	0	279	0	0
T68	0	66	0	0
T92	0	173	0	0
T94	0	215	0	0
T95	0	32452	0	0
T136	0	189	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	40	0	0
T3	1755	1	0	0
T5	519	0	0	0
T6	0	3	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	1	0	0
T25	3498	0	0	0
T26	522	0	0	0
T58	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T67	0	1	0	0
T68	0	3	0	0
T92	0	2	0	0
T94	0	2	0	0
T95	0	1	0	0
T136	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4146964	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1170	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4148798	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1171	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	92	0	0
T3	1755	1	0	0
T5	519	0	0	0
T6	0	3	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	1	0	0
T24	0	2	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	2	0	0
T58	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	5	0	0
T92	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	48	0	0
T3	1755	1	0	0
T5	519	0	0	0
T6	0	3	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	1	0	0
T25	3498	0	0	0
T26	522	0	0	0
T58	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T67	0	1	0	0
T68	0	5	0	0
T92	0	2	0	0
T94	0	2	0	0
T95	0	1	0	0
T136	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	40	0	0
T3	1755	1	0	0
T5	519	0	0	0
T6	0	3	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	1	0	0
T25	3498	0	0	0
T26	522	0	0	0
T58	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T67	0	1	0	0
T68	0	3	0	0
T92	0	2	0	0
T94	0	2	0	0
T95	0	1	0	0
T136	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	40	0	0
T3	1755	1	0	0
T5	519	0	0	0
T6	0	3	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	1	0	0
T25	3498	0	0	0
T26	522	0	0	0
T58	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T67	0	1	0	0
T68	0	3	0	0
T92	0	2	0	0
T94	0	2	0	0
T95	0	1	0	0
T136	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	39267	0	0
T3	1755	22	0	0
T5	519	0	0	0
T6	0	2389	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	67	0	0
T25	3498	0	0	0
T26	522	0	0	0
T58	0	290	0	0
T62	419	0	0	0
T63	422	0	0	0
T67	0	278	0	0
T68	0	63	0	0
T92	0	171	0	0
T94	0	213	0	0
T95	0	32451	0	0
T136	0	188	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	5235	0	0
T2	485	0	0	0
T3	1755	8	0	0
T4	510	4	0	0
T5	519	1	0	0
T7	0	10	0	0
T12	450	7	0	0
T13	422	3	0	0
T14	761	0	0	0
T15	492	7	0	0
T16	670	3	0	0
T17	408	0	0	0
T25	0	14	0	0
T26	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	5274	0	0
T3	1755	51	0	0
T5	519	0	0	0
T6	0	269	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	485	0	0
T25	3498	0	0	0
T26	522	0	0	0
T58	0	64	0	0
T62	419	0	0	0
T63	422	0	0	0
T67	0	89	0	0
T68	0	336	0	0
T92	0	149	0	0
T94	0	291	0	0
T95	0	89	0	0
T136	0	56	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T12 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T12 T13 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T6 T24 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T3 T6 T23 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T3 T6 T23 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T12 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T12 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T12 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T12 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T12 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T12 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T12 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T12 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T6 T24 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T6 T24 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T24 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T6 T24 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T6 T24 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T6 T18 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T6 T18 
168        1/1                      state_d = DetectSt;
           Tests:       T6 T18 T58 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T3 T67 T94 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T6 T18 T58 
182        1/1                  cnt_en = 1'b1;
           Tests:       T6 T18 T58 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T6 T18 T58 
186        1/1                    state_d = IdleSt;
           Tests:       T94 T95 T105 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T94 T95 T105 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T6 T18 T58 
191        1/1                      state_d = StableSt;
           Tests:       T6 T18 T58 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T6 T18 T58 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T6 T18 T58 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T6 T18 T58 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T6 T18 T58 
206        1/1                    state_d = IdleSt;
           Tests:       T6 T18 T58 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T6 T18 T58 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T4,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T4,T12,T13
1	1	Covered	T4,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T6,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T6,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T18,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T24
1	0	Covered	T4,T12,T13
1	1	Covered	T3,T6,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T18,T58
0	1	Covered	T94,T95,T105
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T18,T58
0	1	Unreachable
1	0	Covered	T6,T18,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T24
DetectSt	168	Covered	T6,T18,T58
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T6,T18,T58

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T18,T58
DebounceSt->IdleSt	163	Covered	T3,T24,T30
DetectSt->IdleSt	186	Covered	T94,T95,T105
DetectSt->StableSt	191	Covered	T6,T18,T58
IdleSt->DebounceSt	148	Covered	T3,T6,T24
StableSt->IdleSt	206	Covered	T6,T18,T58

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T6,T24
0	1	Covered	T3,T6,T24
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T18,T58
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T18,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T67,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T24
DetectSt	-	-	-	-	1	-	-	Covered	T94,T95,T105
DetectSt	-	-	-	-	0	1	-	Covered	T6,T18,T58
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T18,T58
StableSt	-	-	-	-	-	-	0	Covered	T6,T18,T58
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	134	0	0
CntIncr_A	4787552	29069	0	0
CntNoWrap_A	4787552	4321407	0	0
DetectStDropOut_A	4787552	13	0	0
DetectedOut_A	4787552	41988	0	0
DetectedPulseOut_A	4787552	45	0	0
DisabledIdleSt_A	4787552	4146964	0	0
DisabledNoDetection_A	4787552	4148798	0	0
EnterDebounceSt_A	4787552	76	0	0
EnterDetectSt_A	4787552	58	0	0
EnterStableSt_A	4787552	45	0	0
PulseIsPulse_A	4787552	45	0	0
StayInStableSt	4787552	41943	0	0
gen_high_level_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_sticky_sva.StableStDropOut_A	4787552	60999	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	134	0	0
T3	1755	1	0	0
T5	519	0	0	0
T6	0	6	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	2	0	0
T24	0	2	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	2	0	0
T58	0	2	0	0
T62	419	0	0	0
T63	422	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	6	0	0
T92	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	29069	0	0
T3	1755	83	0	0
T5	519	0	0	0
T6	0	69	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	76	0	0
T24	0	55	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	73	0	0
T58	0	19	0	0
T62	419	0	0	0
T63	422	0	0	0
T66	0	44	0	0
T67	0	52	0	0
T68	0	75	0	0
T92	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4321407	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1353	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	13	0	0
T94	6392	1	0	0
T95	69565	2	0	0
T105	0	1	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	4	0	0
T152	874	0	0	0
T153	848	0	0	0
T154	9809	0	0	0
T155	3513	0	0	0
T156	522	0	0	0
T157	619	0	0	0
T158	651	0	0	0
T159	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	41988	0	0
T6	3456	379	0	0
T18	0	405	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	88	0	0
T66	0	19	0	0
T68	0	306	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T92	0	119	0	0
T94	0	122	0	0
T96	0	59	0	0
T110	406	0	0	0
T136	0	79	0	0
T138	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	45	0	0
T6	3456	3	0	0
T18	0	1	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	1	0	0
T66	0	1	0	0
T68	0	3	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T92	0	2	0	0
T94	0	2	0	0
T96	0	1	0	0
T110	406	0	0	0
T136	0	1	0	0
T138	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4146964	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1170	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4148798	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1171	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	76	0	0
T3	1755	1	0	0
T5	519	0	0	0
T6	0	3	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	1	0	0
T24	0	2	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	2	0	0
T58	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	3	0	0
T92	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	58	0	0
T6	3456	3	0	0
T18	0	1	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	1	0	0
T66	0	1	0	0
T68	0	3	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T92	0	2	0	0
T94	0	3	0	0
T95	0	2	0	0
T96	0	1	0	0
T110	406	0	0	0
T136	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	45	0	0
T6	3456	3	0	0
T18	0	1	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	1	0	0
T66	0	1	0	0
T68	0	3	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T92	0	2	0	0
T94	0	2	0	0
T96	0	1	0	0
T110	406	0	0	0
T136	0	1	0	0
T138	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	45	0	0
T6	3456	3	0	0
T18	0	1	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	1	0	0
T66	0	1	0	0
T68	0	3	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T92	0	2	0	0
T94	0	2	0	0
T96	0	1	0	0
T110	406	0	0	0
T136	0	1	0	0
T138	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	41943	0	0
T6	3456	376	0	0
T18	0	404	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	87	0	0
T66	0	18	0	0
T68	0	303	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T92	0	117	0	0
T94	0	120	0	0
T96	0	58	0	0
T110	406	0	0	0
T136	0	78	0	0
T138	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	60999	0	0
T6	3456	2491	0	0
T18	0	78	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	320	0	0
T66	0	80	0	0
T68	0	192	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T92	0	205	0	0
T94	0	76	0	0
T96	0	274	0	0
T110	406	0	0	0
T136	0	219	0	0
T138	0	21875	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T12 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T4 T12 T13 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T6 T24 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T3 T6 T23 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T3 T6 T23 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T12 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T12 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T12 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T12 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T12 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T12 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T12 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T12 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T6 T24 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T6 T24 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T24 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T6 T24 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T6 T24 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T6 T18 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T6 T18 
168        1/1                      state_d = DetectSt;
           Tests:       T6 T18 T58 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T3 T92 T96 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T6 T18 T58 
182        1/1                  cnt_en = 1'b1;
           Tests:       T6 T18 T58 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T6 T18 T58 
186        1/1                    state_d = IdleSt;
           Tests:       T92 T97 T98 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T92 T97 T98 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T6 T18 T58 
191        1/1                      state_d = StableSt;
           Tests:       T6 T18 T58 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T6 T18 T58 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T6 T18 T58 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T6 T18 T58 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T6 T18 T58 
206        1/1                    state_d = IdleSt;
           Tests:       T6 T18 T58 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T6 T18 T58 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T4,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T6,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T6,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T18,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T24
1	0	Covered	T4,T12,T13
1	1	Covered	T3,T6,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T18,T58
0	1	Covered	T92,T97,T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T18,T58
0	1	Unreachable
1	0	Covered	T6,T18,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T24
DetectSt	168	Covered	T6,T18,T58
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T6,T18,T58

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T18,T58
DebounceSt->IdleSt	163	Covered	T3,T24,T30
DetectSt->IdleSt	186	Covered	T92,T97,T98
DetectSt->StableSt	191	Covered	T6,T18,T58
IdleSt->DebounceSt	148	Covered	T3,T6,T24
StableSt->IdleSt	206	Covered	T6,T18,T58

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		19	19	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T6,T24
0	1	Covered	T3,T6,T24
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T18,T58
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T18,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T92,T96
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T24
DetectSt	-	-	-	-	1	-	-	Covered	T92,T97,T98
DetectSt	-	-	-	-	0	1	-	Covered	T6,T18,T58
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T18,T58
StableSt	-	-	-	-	-	-	0	Covered	T6,T18,T58
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	140	0	0
CntIncr_A	4787552	26377	0	0
CntNoWrap_A	4787552	4321401	0	0
DetectStDropOut_A	4787552	10	0	0
DetectedOut_A	4787552	6013	0	0
DetectedPulseOut_A	4787552	39	0	0
DisabledIdleSt_A	4787552	4146964	0	0
DisabledNoDetection_A	4787552	4148798	0	0
EnterDebounceSt_A	4787552	91	0	0
EnterDetectSt_A	4787552	49	0	0
EnterStableSt_A	4787552	39	0	0
PulseIsPulse_A	4787552	39	0	0
StayInStableSt	4787552	5974	0	0
gen_high_event_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_high_level_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_sticky_sva.StableStDropOut_A	4787552	137993	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	140	0	0
T3	1755	1	0	0
T5	519	0	0	0
T6	0	6	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	2	0	0
T24	0	2	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	2	0	0
T58	0	2	0	0
T62	419	0	0	0
T63	422	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	6	0	0
T92	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	26377	0	0
T3	1755	52	0	0
T5	519	0	0	0
T6	0	222	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	41	0	0
T24	0	56	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	76	0	0
T58	0	66	0	0
T62	419	0	0	0
T63	422	0	0	0
T66	0	56	0	0
T67	0	98	0	0
T68	0	96	0	0
T92	0	228	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4321401	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1353	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	10	0	0
T86	11246	0	0	0
T92	1070	4	0	0
T97	0	2	0	0
T98	0	1	0	0
T136	1709	0	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	485	0	0	0
T164	426	0	0	0
T165	502	0	0	0
T166	852	0	0	0
T167	499	0	0	0
T168	2283	0	0	0
T169	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	6013	0	0
T6	3456	1596	0	0
T18	0	250	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	302	0	0
T66	0	43	0	0
T67	0	161	0	0
T68	0	282	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T94	0	168	0	0
T95	0	78	0	0
T110	406	0	0	0
T136	0	67	0	0
T137	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	39	0	0
T6	3456	3	0	0
T18	0	1	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T94	0	2	0	0
T95	0	1	0	0
T110	406	0	0	0
T136	0	1	0	0
T137	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4146964	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1170	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4148798	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1171	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	91	0	0
T3	1755	1	0	0
T5	519	0	0	0
T6	0	3	0	0
T7	1860	0	0	0
T8	518	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T18	0	1	0	0
T24	0	2	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	2	0	0
T58	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T92	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	49	0	0
T6	3456	3	0	0
T18	0	1	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T92	0	4	0	0
T94	0	2	0	0
T95	0	1	0	0
T110	406	0	0	0
T136	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	39	0	0
T6	3456	3	0	0
T18	0	1	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T94	0	2	0	0
T95	0	1	0	0
T110	406	0	0	0
T136	0	1	0	0
T137	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	39	0	0
T6	3456	3	0	0
T18	0	1	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T94	0	2	0	0
T95	0	1	0	0
T110	406	0	0	0
T136	0	1	0	0
T137	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	5974	0	0
T6	3456	1593	0	0
T18	0	249	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	301	0	0
T66	0	42	0	0
T67	0	160	0	0
T68	0	279	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T94	0	166	0	0
T95	0	77	0	0
T97	0	34	0	0
T110	406	0	0	0
T136	0	66	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	137993	0	0
T6	3456	1151	0	0
T18	0	278	0	0
T27	710	0	0	0
T53	432	0	0	0
T54	443	0	0	0
T58	0	76	0	0
T66	0	50	0	0
T67	0	226	0	0
T68	0	236	0	0
T69	728	0	0	0
T71	491	0	0	0
T72	499	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T94	0	351	0	0
T95	0	39413	0	0
T110	406	0	0	0
T136	0	268	0	0
T137	0	33	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T4 T2 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T24 T10 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T5 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T5 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T24 T10 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T24 T10 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T24 T10 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T24 T10 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T24 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 
165        1/1                  end else if (cnt_done) begin
           Tests:       T24 T10 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T11 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T10 T11 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T10 T11 T30 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T170 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T10 T11 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T10 T11 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T10 T11 T30 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T10 T11 T30 
191        1/1                      state_d = StableSt;
           Tests:       T10 T11 T30 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T10 T11 T30 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T10 T11 T30 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T10 T11 T30 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T10 T11 T30 
206        1/1                    state_d = IdleSt;
           Tests:       T10 T11 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T10 T11 T47 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T10,T11,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T24,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T24,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T47
0	1	Covered	T10,T11,T47
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T30
1	-	Covered	T10,T11,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T10,T11
DetectSt	168	Covered	T10,T11,T30
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T10,T11,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T30
DebounceSt->IdleSt	163	Covered	T24,T170
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T11,T30
IdleSt->DebounceSt	148	Covered	T24,T10,T11
StableSt->IdleSt	206	Covered	T10,T11,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T10,T11
0	1	Covered	T24,T10,T11
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T30
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T170
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T10,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T11,T30
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	60	0	0
CntIncr_A	4787552	1770	0	0
CntNoWrap_A	4787552	4321481	0	0
DetectStDropOut_A	4787552	0	0	0
DetectedOut_A	4787552	2468	0	0
DetectedPulseOut_A	4787552	29	0	0
DisabledIdleSt_A	4787552	4211275	0	0
DisabledNoDetection_A	4787552	4213077	0	0
EnterDebounceSt_A	4787552	31	0	0
EnterDetectSt_A	4787552	29	0	0
EnterStableSt_A	4787552	29	0	0
PulseIsPulse_A	4787552	29	0	0
StayInStableSt	4787552	2427	0	0
gen_high_level_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_not_sticky_sva.StableStDropOut_A	4787552	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	60	0	0
T10	1200	4	0	0
T11	684	4	0	0
T24	7077	1	0	0
T30	0	2	0	0
T44	0	2	0	0
T47	0	4	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	4	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	1770	0	0
T10	1200	172	0	0
T11	684	54	0	0
T24	7077	27	0	0
T30	0	33	0	0
T44	0	42	0	0
T47	0	82	0	0
T48	0	29	0	0
T49	0	60	0	0
T50	0	34	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T171	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4321481	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	2468	0	0
T10	1200	81	0	0
T11	684	80	0	0
T18	1005	0	0	0
T30	0	1	0	0
T44	0	40	0	0
T47	0	80	0	0
T48	0	98	0	0
T49	0	221	0	0
T50	0	78	0	0
T55	461	0	0	0
T56	674	0	0	0
T57	446	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T124	0	94	0	0
T171	0	212	0	0
T172	704	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	29	0	0
T10	1200	2	0	0
T11	684	2	0	0
T18	1005	0	0	0
T30	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T57	446	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T124	0	1	0	0
T171	0	1	0	0
T172	704	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4211275	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4213077	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	31	0	0
T10	1200	2	0	0
T11	684	2	0	0
T24	7077	1	0	0
T30	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	29	0	0
T10	1200	2	0	0
T11	684	2	0	0
T18	1005	0	0	0
T30	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T57	446	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T124	0	1	0	0
T171	0	1	0	0
T172	704	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	29	0	0
T10	1200	2	0	0
T11	684	2	0	0
T18	1005	0	0	0
T30	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T57	446	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T124	0	1	0	0
T171	0	1	0	0
T172	704	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	29	0	0
T10	1200	2	0	0
T11	684	2	0	0
T18	1005	0	0	0
T30	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T57	446	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T124	0	1	0	0
T171	0	1	0	0
T172	704	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	2427	0	0
T10	1200	79	0	0
T11	684	78	0	0
T18	1005	0	0	0
T44	0	38	0	0
T47	0	77	0	0
T48	0	97	0	0
T49	0	219	0	0
T50	0	75	0	0
T55	461	0	0	0
T56	674	0	0	0
T57	446	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T124	0	93	0	0
T153	0	79	0	0
T171	0	211	0	0
T172	704	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	16	0	0
T10	1200	2	0	0
T11	684	2	0	0
T18	1005	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T55	461	0	0	0
T56	674	0	0	0
T57	446	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T124	0	1	0	0
T138	0	2	0	0
T153	0	1	0	0
T171	0	1	0	0
T172	704	0	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T4 T2 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T5 T24 T10 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T5 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T5 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T5 T24 T10 
149        1/1                    cnt_en = 1'b1;
           Tests:       T5 T24 T10 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T5 T24 T10 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T5 T24 T10 
163        1/1                    state_d = IdleSt;
           Tests:       T24 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 
165        1/1                  end else if (cnt_done) begin
           Tests:       T5 T24 T10 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T5 T10 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T5 T10 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T5 T10 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T11 T47 T49 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T5 T10 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T5 T10 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T5 T10 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T47 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T47 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T5 T10 T11 
191        1/1                      state_d = StableSt;
           Tests:       T5 T10 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T5 T10 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T5 T10 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T5 T10 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T5 T10 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T10 T30 T50 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T5 T10 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T24,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T24,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T10
1	0	Covered	T4,T12,T13
1	1	Covered	T5,T24,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T11
0	1	Covered	T47
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T11
0	1	Covered	T10,T50,T171
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T10,T11
1	-	Covered	T10,T50,T171

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T24,T10
DetectSt	168	Covered	T5,T10,T11
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T10,T11
DebounceSt->IdleSt	163	Covered	T24,T11,T47
DetectSt->IdleSt	186	Covered	T47
DetectSt->StableSt	191	Covered	T5,T10,T11
IdleSt->DebounceSt	148	Covered	T5,T24,T10
StableSt->IdleSt	206	Covered	T10,T30,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T24,T10
0	1	Covered	T5,T24,T10
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T24,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T47,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T24,T10
DetectSt	-	-	-	-	1	-	-	Covered	T47
DetectSt	-	-	-	-	0	1	-	Covered	T5,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T30,T50
StableSt	-	-	-	-	-	-	0	Covered	T5,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	73	0	0
CntIncr_A	4787552	62892	0	0
CntNoWrap_A	4787552	4321468	0	0
DetectStDropOut_A	4787552	1	0	0
DetectedOut_A	4787552	54228	0	0
DetectedPulseOut_A	4787552	32	0	0
DisabledIdleSt_A	4787552	4199043	0	0
DisabledNoDetection_A	4787552	4200851	0	0
EnterDebounceSt_A	4787552	40	0	0
EnterDetectSt_A	4787552	33	0	0
EnterStableSt_A	4787552	32	0	0
PulseIsPulse_A	4787552	32	0	0
StayInStableSt	4787552	54181	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	4787552	1618	0	0
gen_low_level_sva.LowLevelEvent_A	4787552	4323375	0	0
gen_not_sticky_sva.StableStDropOut_A	4787552	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	73	0	0
T5	519	2	0	0
T6	3456	0	0	0
T7	1860	0	0	0
T8	518	0	0	0
T10	0	6	0	0
T11	0	4	0	0
T24	0	1	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	2	0	0
T47	0	3	0	0
T49	0	1	0	0
T50	0	4	0	0
T51	0	2	0	0
T62	419	0	0	0
T63	422	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T171	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	62892	0	0
T5	519	34	0	0
T6	3456	0	0	0
T7	1860	0	0	0
T8	518	0	0	0
T10	0	258	0	0
T11	0	81	0	0
T24	0	27	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	33	0	0
T47	0	82	0	0
T49	0	60	0	0
T50	0	34	0	0
T51	0	41	0	0
T62	419	0	0	0
T63	422	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T171	0	180	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4321468	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	1	0	0
T44	1888	0	0	0
T47	784	1	0	0
T59	780	0	0	0
T75	1925	0	0	0
T130	482	0	0	0
T174	422	0	0	0
T175	666	0	0	0
T176	8404	0	0	0
T177	404	0	0	0
T178	8434	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	54228	0	0
T5	519	41	0	0
T6	3456	0	0	0
T7	1860	0	0	0
T8	518	0	0	0
T10	0	275	0	0
T11	0	91	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	2	0	0
T48	0	61	0	0
T50	0	70	0	0
T51	0	111	0	0
T62	419	0	0	0
T63	422	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T171	0	93	0	0
T179	0	65	0	0
T180	0	25	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	32	0	0
T5	519	1	0	0
T6	3456	0	0	0
T7	1860	0	0	0
T8	518	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	1	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T171	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4199043	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4200851	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	40	0	0
T5	519	1	0	0
T6	3456	0	0	0
T7	1860	0	0	0
T8	518	0	0	0
T10	0	3	0	0
T11	0	3	0	0
T24	0	1	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T171	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	33	0	0
T5	519	1	0	0
T6	3456	0	0	0
T7	1860	0	0	0
T8	518	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T171	0	2	0	0
T179	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	32	0	0
T5	519	1	0	0
T6	3456	0	0	0
T7	1860	0	0	0
T8	518	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	1	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T171	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	32	0	0
T5	519	1	0	0
T6	3456	0	0	0
T7	1860	0	0	0
T8	518	0	0	0
T10	0	3	0	0
T11	0	1	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	1	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T62	419	0	0	0
T63	422	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T171	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	54181	0	0
T5	519	39	0	0
T6	3456	0	0	0
T7	1860	0	0	0
T8	518	0	0	0
T10	0	271	0	0
T11	0	89	0	0
T25	3498	0	0	0
T26	522	0	0	0
T30	0	1	0	0
T48	0	58	0	0
T50	0	68	0	0
T51	0	109	0	0
T62	419	0	0	0
T63	422	0	0	0
T77	522	0	0	0
T78	503	0	0	0
T171	0	90	0	0
T179	0	63	0	0
T180	0	24	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	1618	0	0
T2	485	0	0	0
T3	1755	0	0	0
T4	510	4	0	0
T5	519	1	0	0
T7	0	13	0	0
T12	450	3	0	0
T13	422	1	0	0
T14	761	0	0	0
T15	492	5	0	0
T16	670	0	0	0
T17	408	0	0	0
T25	0	14	0	0
T26	0	6	0	0
T62	0	2	0	0
T63	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	16	0	0
T10	1200	2	0	0
T11	684	0	0	0
T18	1005	0	0	0
T48	0	1	0	0
T50	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T57	446	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	704	0	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	1	0	0