Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T1 T4 T2
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T4 T2
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T4 T2
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T4 T2
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T3 T5 T6
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
105 1/1 cnt_q <= '0;
Tests: T1 T4 T2
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T2
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T4 T2
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T4 T2
129 1/1 cnt_en = 1'b0;
Tests: T1 T4 T2
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T4 T2
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T4 T2
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T4 T2
139
140 1/1 unique case (state_q)
Tests: T1 T4 T2
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T4 T2
148 1/1 state_d = DebounceSt;
Tests: T3 T5 T6
149 1/1 cnt_en = 1'b1;
Tests: T3 T5 T6
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T3 T5 T6
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T3 T5 T6
163 1/1 state_d = IdleSt;
Tests: T24 T30
164 1/1 cnt_clr = 1'b1;
Tests: T24 T30
165 1/1 end else if (cnt_done) begin
Tests: T3 T5 T6
166 1/1 cnt_clr = 1'b1;
Tests: T3 T5 T6
167 1/1 if (trigger_active) begin
Tests: T3 T5 T6
168 1/1 state_d = DetectSt;
Tests: T3 T5 T6
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T27 T11 T66
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T3 T5 T6
182 1/1 cnt_en = 1'b1;
Tests: T3 T5 T6
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T3 T5 T6
186 1/1 state_d = IdleSt;
Tests: T47 T68 T93
187 1/1 cnt_clr = 1'b1;
Tests: T47 T68 T93
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T3 T5 T6
191 1/1 state_d = StableSt;
Tests: T3 T5 T6
192 1/1 cnt_clr = 1'b1;
Tests: T3 T5 T6
193 1/1 event_detected_o = 1'b1;
Tests: T3 T5 T6
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T3 T5 T6
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T3 T5 T6
206 1/1 state_d = IdleSt;
Tests: T3 T6 T28
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T3 T5 T6
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T2
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T2
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T1 T4 T2
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T4 T2
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T4 T2
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T4 T2
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T3 T6 T24
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
105 1/1 cnt_q <= '0;
Tests: T1 T4 T2
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T2
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T4 T2
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T4 T2
129 1/1 cnt_en = 1'b0;
Tests: T1 T4 T2
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T4 T2
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T4 T2
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T4 T2
139
140 1/1 unique case (state_q)
Tests: T1 T4 T2
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T4 T2
148 1/1 state_d = DebounceSt;
Tests: T3 T6 T24
149 1/1 cnt_en = 1'b1;
Tests: T3 T6 T24
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T3 T6 T24
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T3 T6 T24
163 1/1 state_d = IdleSt;
Tests: T24 T30
164 1/1 cnt_clr = 1'b1;
Tests: T24 T30
165 1/1 end else if (cnt_done) begin
Tests: T3 T6 T24
166 1/1 cnt_clr = 1'b1;
Tests: T3 T6 T10
167 1/1 if (trigger_active) begin
Tests: T3 T6 T10
168 1/1 state_d = DetectSt;
Tests: T6 T10 T11
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T3 T5 T11
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T6 T10 T11
182 1/1 cnt_en = 1'b1;
Tests: T6 T10 T11
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T6 T10 T11
186 1/1 state_d = IdleSt;
Tests: T44 T94 T95
187 1/1 cnt_clr = 1'b1;
Tests: T44 T94 T95
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T6 T10 T11
191 1/1 state_d = StableSt;
Tests: T6 T10 T11
192 1/1 cnt_clr = 1'b1;
Tests: T6 T10 T11
193 1/1 event_detected_o = 1'b1;
Tests: T6 T10 T11
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T6 T10 T11
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T6 T10 T11
206 1/1 state_d = IdleSt;
Tests: T6 T10 T11
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T6 T10 T11
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T2
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T2
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T12 T13
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T4 T12 T13
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T3 T6 T24
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T3 T6 T23
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T3 T6 T23
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
105 1/1 cnt_q <= '0;
Tests: T1 T4 T2
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T2
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T12 T13
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T12 T13
129 1/1 cnt_en = 1'b0;
Tests: T4 T12 T13
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T12 T13
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T12 T13
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T12 T13
139
140 1/1 unique case (state_q)
Tests: T4 T12 T13
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T12 T13
148 1/1 state_d = DebounceSt;
Tests: T3 T6 T24
149 1/1 cnt_en = 1'b1;
Tests: T3 T6 T24
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T3 T6 T24
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T3 T6 T24
163 1/1 state_d = IdleSt;
Tests: T24 T30
164 1/1 cnt_clr = 1'b1;
Tests: T24 T30
165 1/1 end else if (cnt_done) begin
Tests: T3 T6 T24
166 1/1 cnt_clr = 1'b1;
Tests: T3 T6 T18
167 1/1 if (trigger_active) begin
Tests: T3 T6 T18
168 1/1 state_d = DetectSt;
Tests: T6 T18 T58
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T3 T92 T96
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T6 T18 T58
182 1/1 cnt_en = 1'b1;
Tests: T6 T18 T58
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T6 T18 T58
186 1/1 state_d = IdleSt;
Tests: T92 T97 T98
187 1/1 cnt_clr = 1'b1;
Tests: T92 T97 T98
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T6 T18 T58
191 1/1 state_d = StableSt;
Tests: T6 T18 T58
192 1/1 cnt_clr = 1'b1;
Tests: T6 T18 T58
193 1/1 event_detected_o = 1'b1;
Tests: T6 T18 T58
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T6 T18 T58
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T6 T18 T58
206 1/1 state_d = IdleSt;
Tests: T6 T18 T58
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T6 T18 T58
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T2
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T2
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T24 T30 T31
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T24 T30 T31
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T8 T29
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T5
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T5
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
105 1/1 cnt_q <= '0;
Tests: T1 T4 T2
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T2
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T8 T29
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T8 T29
129 1/1 cnt_en = 1'b0;
Tests: T1 T8 T29
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T8 T29
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T8 T29
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T8 T29
139
140 1/1 unique case (state_q)
Tests: T1 T8 T29
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T8 T29
148 1/1 state_d = DebounceSt;
Tests: T1 T8 T29
149 1/1 cnt_en = 1'b1;
Tests: T1 T8 T29
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T8 T29
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T8 T29
163 1/1 state_d = IdleSt;
Tests: T24 T30
164 1/1 cnt_clr = 1'b1;
Tests: T24 T30
165 1/1 end else if (cnt_done) begin
Tests: T1 T8 T29
166 1/1 cnt_clr = 1'b1;
Tests: T1 T8 T29
167 1/1 if (trigger_active) begin
Tests: T1 T8 T29
168 1/1 state_d = DetectSt;
Tests: T1 T8 T29
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T24 T30 T99
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T8 T29
182 1/1 cnt_en = 1'b1;
Tests: T1 T8 T29
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T8 T29
186 1/1 state_d = IdleSt;
Tests: T24 T30 T31
187 1/1 cnt_clr = 1'b1;
Tests: T24 T30 T31
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T8 T29
191 1/1 state_d = StableSt;
Tests: T1 T8 T29
192 1/1 cnt_clr = 1'b1;
Tests: T1 T8 T29
193 1/1 event_detected_o = 1'b1;
Tests: T1 T8 T29
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T8 T29
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T8 T29
206 1/1 state_d = IdleSt;
Tests: T24 T30 T31
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T8 T29
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T2
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T2
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T1 T2 T7
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T4 T2
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T4 T2
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T4 T2
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T2 T7
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T5
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T5
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
105 1/1 cnt_q <= '0;
Tests: T1 T4 T2
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T2
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T4 T2
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T4 T2
129 1/1 cnt_en = 1'b0;
Tests: T1 T4 T2
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T4 T2
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T4 T2
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T4 T2
139
140 1/1 unique case (state_q)
Tests: T1 T4 T2
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T4 T2
148 1/1 state_d = DebounceSt;
Tests: T1 T2 T7
149 1/1 cnt_en = 1'b1;
Tests: T1 T2 T7
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T2 T7
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T2 T7
163 1/1 state_d = IdleSt;
Tests: T24 T30
164 1/1 cnt_clr = 1'b1;
Tests: T24 T30
165 1/1 end else if (cnt_done) begin
Tests: T1 T2 T7
166 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T7
167 1/1 if (trigger_active) begin
Tests: T1 T2 T7
168 1/1 state_d = DetectSt;
Tests: T1 T2 T7
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T53 T54 T29
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T2 T7
182 1/1 cnt_en = 1'b1;
Tests: T1 T2 T7
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T2 T7
186 1/1 state_d = IdleSt;
Tests: T24 T30 T40
187 1/1 cnt_clr = 1'b1;
Tests: T24 T30 T40
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T2 T7
191 1/1 state_d = StableSt;
Tests: T1 T2 T7
192 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T7
193 1/1 event_detected_o = 1'b1;
Tests: T1 T2 T7
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T2 T7
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T2 T7
206 1/1 state_d = IdleSt;
Tests: T1 T2 T7
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T2 T7
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T2
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T2
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T2
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T7 |
| 1 | Covered | T1,T4,T2 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T7 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T1,T4,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T7 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T7 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T7 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T7 |
| 1 | 0 | Covered | T25,T7,T9 |
| 1 | 1 | Covered | T1,T2,T7 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T7 |
| 0 | 1 | Covered | T24,T40,T41 |
| 1 | 0 | Covered | T24,T30 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T7 |
| 0 | 1 | Covered | T1,T2,T7 |
| 1 | 0 | Covered | T24,T30,T100 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T2,T7 |
| 1 | - | Covered | T1,T2,T7 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T4,T2 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T2 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T1,T4,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T5,T27,T28 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T5,T27,T28 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T5,T28,T24 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T27,T28 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T5,T27,T28 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T28,T24 |
| 0 | 1 | Covered | T47 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T28,T24 |
| 0 | 1 | Covered | T28,T10,T56 |
| 1 | 0 | Covered | T24,T30 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T5,T28,T24 |
| 1 | - | Covered | T28,T10,T56 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T24,T30,T31 |
| 1 | Covered | T1,T4,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T8,T29 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T8,T29 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T8,T29 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T24,T30,T31 |
| 1 | 0 | Covered | T24,T30,T31 |
| 1 | 1 | Covered | T1,T8,T29 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T8,T29 |
| 0 | 1 | Covered | T24,T30,T31 |
| 1 | 0 | Covered | T24,T30,T31 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T8,T29 |
| 0 | 1 | Covered | T24,T30,T31 |
| 1 | 0 | Covered | T101,T102,T103 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T8,T29 |
| 1 | - | Covered | T24,T30,T31 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T4,T12,T13 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T6,T24 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T6,T24 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T6,T18,T58 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T6,T24 |
| 1 | 0 | Covered | T4,T12,T13 |
| 1 | 1 | Covered | T3,T6,T24 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T18,T58 |
| 0 | 1 | Covered | T92,T97,T98 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T18,T58 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T6,T18,T58 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T4,T2 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T2 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T1,T4,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T9,T24,T10 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T9,T24,T10 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T9,T10,T11 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T9,T24 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T9,T24,T10 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T9,T10,T11 |
| 0 | 1 | Covered | T44,T104 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T9,T10,T11 |
| 0 | 1 | Covered | T10,T11,T47 |
| 1 | 0 | Covered | T30 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T9,T10,T11 |
| 1 | - | Covered | T10,T11,T47 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T4,T12,T13 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T2 |
| 1 | 0 | Covered | T4,T12,T13 |
| 1 | 1 | Covered | T4,T12,T13 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T6,T24 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T6,T24 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T6,T18,T58 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T6,T24 |
| 1 | 0 | Covered | T4,T12,T13 |
| 1 | 1 | Covered | T3,T6,T24 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T18,T58 |
| 0 | 1 | Covered | T94,T95,T105 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T18,T58 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T6,T18,T58 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T12,T13 |
| 1 | Covered | T1,T4,T2 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T12,T13 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T1,T4,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T6,T24 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T6,T24 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T3,T6,T18 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T6,T24 |
| 1 | 0 | Covered | T4,T12,T13 |
| 1 | 1 | Covered | T3,T6,T24 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T6,T18 |
| 0 | 1 | Covered | T68,T93,T106 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T6,T18 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T6,T18 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DebounceSt |
148 |
Covered |
T5,T27,T28 |
| DetectSt |
168 |
Covered |
T5,T28,T24 |
| IdleSt |
163 |
Covered |
T1,T4,T2 |
| StableSt |
191 |
Covered |
T5,T28,T24 |
| transitions | Line No. | Covered | Tests |
| DebounceSt->DetectSt |
168 |
Covered |
T5,T28,T24 |
| DebounceSt->IdleSt |
163 |
Covered |
T5,T27,T9 |
| DetectSt->IdleSt |
186 |
Covered |
T24,T30,T47 |
| DetectSt->StableSt |
191 |
Covered |
T5,T28,T24 |
| IdleSt->DebounceSt |
148 |
Covered |
T5,T27,T28 |
| StableSt->IdleSt |
206 |
Covered |
T28,T24,T10 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T5,T27,T28 |
| 0 |
1 |
Covered |
T5,T27,T28 |
| 0 |
0 |
Covered |
T1,T4,T2 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T28,T24 |
| 0 |
Covered |
T1,T4,T2 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T2 |
| 0 |
Covered |
T1,T4,T2 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T27,T28 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T2 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T24,T30 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T5,T28,T24 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T5,T27,T11 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T5,T27,T28 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T24,T30,T47 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T5,T28,T24 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T2,T7 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T28,T24,T10 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T5,T28,T24 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T2 |
| 0 |
Covered |
T1,T4,T2 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T2 |
| 0 |
Covered |
T1,T4,T2 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T3,T8 |
| 0 |
1 |
Covered |
T1,T3,T8 |
| 0 |
0 |
Covered |
T1,T4,T2 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T8,T6 |
| 0 |
Covered |
T1,T4,T2 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T2 |
| 0 |
Covered |
T1,T4,T2 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T8 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T12,T13 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T24,T30 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T1,T8,T6 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T3,T24,T30 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T3,T8 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T24,T30,T31 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T1,T8,T6 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T8,T29 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T6,T24,T18 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T8,T6 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T2 |
| 0 |
Covered |
T1,T4,T2 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
16370 |
0 |
0 |
| T1 |
1018 |
4 |
0 |
0 |
| T2 |
970 |
2 |
0 |
0 |
| T3 |
3510 |
0 |
0 |
0 |
| T4 |
1020 |
0 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T8 |
0 |
4 |
0 |
0 |
| T9 |
1405 |
0 |
0 |
0 |
| T12 |
900 |
0 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
1522 |
0 |
0 |
0 |
| T15 |
984 |
0 |
0 |
0 |
| T16 |
1340 |
0 |
0 |
0 |
| T17 |
816 |
0 |
0 |
0 |
| T24 |
7077 |
26 |
0 |
0 |
| T27 |
710 |
2 |
0 |
0 |
| T28 |
0 |
6 |
0 |
0 |
| T29 |
457 |
3 |
0 |
0 |
| T30 |
0 |
17 |
0 |
0 |
| T31 |
0 |
8 |
0 |
0 |
| T53 |
432 |
1 |
0 |
0 |
| T54 |
443 |
1 |
0 |
0 |
| T55 |
0 |
3 |
0 |
0 |
| T56 |
0 |
2 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T60 |
0 |
4 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T69 |
728 |
0 |
0 |
0 |
| T71 |
491 |
0 |
0 |
0 |
| T72 |
499 |
0 |
0 |
0 |
| T79 |
503 |
0 |
0 |
0 |
| T84 |
0 |
2 |
0 |
0 |
| T107 |
0 |
6 |
0 |
0 |
| T108 |
0 |
2 |
0 |
0 |
| T109 |
0 |
3 |
0 |
0 |
| T110 |
406 |
0 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
928305 |
0 |
0 |
| T1 |
1018 |
46 |
0 |
0 |
| T2 |
970 |
25 |
0 |
0 |
| T3 |
3510 |
0 |
0 |
0 |
| T4 |
1020 |
0 |
0 |
0 |
| T7 |
0 |
25 |
0 |
0 |
| T8 |
0 |
46 |
0 |
0 |
| T9 |
1405 |
0 |
0 |
0 |
| T12 |
900 |
0 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
1522 |
0 |
0 |
0 |
| T15 |
984 |
0 |
0 |
0 |
| T16 |
1340 |
0 |
0 |
0 |
| T17 |
816 |
0 |
0 |
0 |
| T24 |
7077 |
609 |
0 |
0 |
| T27 |
710 |
97 |
0 |
0 |
| T28 |
0 |
279 |
0 |
0 |
| T29 |
457 |
41 |
0 |
0 |
| T30 |
0 |
590 |
0 |
0 |
| T31 |
0 |
208 |
0 |
0 |
| T53 |
432 |
20 |
0 |
0 |
| T54 |
443 |
20 |
0 |
0 |
| T55 |
0 |
41 |
0 |
0 |
| T56 |
0 |
79 |
0 |
0 |
| T57 |
0 |
20 |
0 |
0 |
| T60 |
0 |
125 |
0 |
0 |
| T61 |
0 |
179 |
0 |
0 |
| T69 |
728 |
0 |
0 |
0 |
| T71 |
491 |
0 |
0 |
0 |
| T72 |
499 |
0 |
0 |
0 |
| T79 |
503 |
0 |
0 |
0 |
| T84 |
0 |
21 |
0 |
0 |
| T107 |
0 |
128 |
0 |
0 |
| T108 |
0 |
29 |
0 |
0 |
| T109 |
0 |
92 |
0 |
0 |
| T110 |
406 |
0 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
112343696 |
0 |
0 |
| T1 |
13234 |
2804 |
0 |
0 |
| T2 |
12610 |
2182 |
0 |
0 |
| T3 |
45630 |
35200 |
0 |
0 |
| T4 |
13260 |
2834 |
0 |
0 |
| T12 |
11700 |
1274 |
0 |
0 |
| T13 |
10972 |
546 |
0 |
0 |
| T14 |
19786 |
9360 |
0 |
0 |
| T15 |
12792 |
2366 |
0 |
0 |
| T16 |
17420 |
6994 |
0 |
0 |
| T17 |
10608 |
182 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
2234 |
0 |
0 |
| T10 |
1200 |
0 |
0 |
0 |
| T11 |
684 |
0 |
0 |
0 |
| T24 |
7077 |
1 |
0 |
0 |
| T30 |
0 |
1 |
0 |
0 |
| T31 |
0 |
1 |
0 |
0 |
| T37 |
0 |
9 |
0 |
0 |
| T39 |
0 |
2 |
0 |
0 |
| T40 |
11828 |
4 |
0 |
0 |
| T41 |
22514 |
10 |
0 |
0 |
| T55 |
461 |
0 |
0 |
0 |
| T56 |
674 |
0 |
0 |
0 |
| T64 |
405 |
0 |
0 |
0 |
| T65 |
425 |
0 |
0 |
0 |
| T73 |
493 |
0 |
0 |
0 |
| T82 |
530 |
0 |
0 |
0 |
| T85 |
0 |
3 |
0 |
0 |
| T87 |
0 |
17 |
0 |
0 |
| T88 |
0 |
16 |
0 |
0 |
| T89 |
0 |
18 |
0 |
0 |
| T90 |
415 |
0 |
0 |
0 |
| T111 |
0 |
23 |
0 |
0 |
| T112 |
0 |
3 |
0 |
0 |
| T113 |
0 |
4 |
0 |
0 |
| T114 |
0 |
3 |
0 |
0 |
| T115 |
0 |
9 |
0 |
0 |
| T116 |
0 |
3 |
0 |
0 |
| T117 |
0 |
4 |
0 |
0 |
| T118 |
0 |
1 |
0 |
0 |
| T119 |
0 |
9 |
0 |
0 |
| T120 |
0 |
5 |
0 |
0 |
| T121 |
32156 |
0 |
0 |
0 |
| T122 |
407 |
0 |
0 |
0 |
| T123 |
1256 |
0 |
0 |
0 |
| T124 |
883 |
0 |
0 |
0 |
| T125 |
502 |
0 |
0 |
0 |
| T126 |
832 |
0 |
0 |
0 |
| T127 |
2511 |
0 |
0 |
0 |
| T128 |
423 |
0 |
0 |
0 |
| T129 |
496 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
585904 |
0 |
0 |
| T1 |
1018 |
86 |
0 |
0 |
| T2 |
970 |
3 |
0 |
0 |
| T3 |
3510 |
0 |
0 |
0 |
| T4 |
1020 |
0 |
0 |
0 |
| T7 |
0 |
3 |
0 |
0 |
| T8 |
0 |
97 |
0 |
0 |
| T10 |
2400 |
0 |
0 |
0 |
| T11 |
684 |
0 |
0 |
0 |
| T12 |
900 |
0 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
1522 |
0 |
0 |
0 |
| T15 |
984 |
0 |
0 |
0 |
| T16 |
1340 |
0 |
0 |
0 |
| T17 |
816 |
0 |
0 |
0 |
| T23 |
1982 |
0 |
0 |
0 |
| T24 |
14154 |
393 |
0 |
0 |
| T28 |
799 |
15 |
0 |
0 |
| T29 |
0 |
32 |
0 |
0 |
| T30 |
0 |
471 |
0 |
0 |
| T55 |
922 |
35 |
0 |
0 |
| T56 |
0 |
9 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T60 |
0 |
10 |
0 |
0 |
| T64 |
810 |
0 |
0 |
0 |
| T65 |
850 |
0 |
0 |
0 |
| T81 |
522 |
0 |
0 |
0 |
| T82 |
1060 |
0 |
0 |
0 |
| T84 |
0 |
86 |
0 |
0 |
| T107 |
0 |
12 |
0 |
0 |
| T108 |
0 |
9 |
0 |
0 |
| T109 |
0 |
8 |
0 |
0 |
| T130 |
0 |
3 |
0 |
0 |
| T131 |
0 |
4 |
0 |
0 |
| T132 |
0 |
4 |
0 |
0 |
| T133 |
0 |
8 |
0 |
0 |
| T134 |
0 |
21 |
0 |
0 |
| T135 |
426 |
0 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
4985 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
970 |
1 |
0 |
0 |
| T3 |
3510 |
0 |
0 |
0 |
| T4 |
1020 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
0 |
2 |
0 |
0 |
| T10 |
2400 |
0 |
0 |
0 |
| T11 |
684 |
0 |
0 |
0 |
| T12 |
900 |
0 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
1522 |
0 |
0 |
0 |
| T15 |
984 |
0 |
0 |
0 |
| T16 |
1340 |
0 |
0 |
0 |
| T17 |
816 |
0 |
0 |
0 |
| T23 |
1982 |
0 |
0 |
0 |
| T24 |
14154 |
7 |
0 |
0 |
| T28 |
799 |
3 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
6 |
0 |
0 |
| T55 |
922 |
1 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T64 |
810 |
0 |
0 |
0 |
| T65 |
850 |
0 |
0 |
0 |
| T81 |
522 |
0 |
0 |
0 |
| T82 |
1060 |
0 |
0 |
0 |
| T84 |
0 |
2 |
0 |
0 |
| T107 |
0 |
3 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T109 |
0 |
1 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
| T132 |
0 |
2 |
0 |
0 |
| T133 |
0 |
1 |
0 |
0 |
| T134 |
0 |
2 |
0 |
0 |
| T135 |
426 |
0 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
107961215 |
0 |
0 |
| T1 |
13234 |
2622 |
0 |
0 |
| T2 |
12610 |
2103 |
0 |
0 |
| T3 |
45630 |
34652 |
0 |
0 |
| T4 |
13260 |
2834 |
0 |
0 |
| T12 |
11700 |
1274 |
0 |
0 |
| T13 |
10972 |
546 |
0 |
0 |
| T14 |
19786 |
9360 |
0 |
0 |
| T15 |
12792 |
2366 |
0 |
0 |
| T16 |
17420 |
6994 |
0 |
0 |
| T17 |
10608 |
182 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
108005446 |
0 |
0 |
| T1 |
13234 |
2646 |
0 |
0 |
| T2 |
12610 |
2128 |
0 |
0 |
| T3 |
45630 |
34678 |
0 |
0 |
| T4 |
13260 |
2860 |
0 |
0 |
| T12 |
11700 |
1300 |
0 |
0 |
| T13 |
10972 |
572 |
0 |
0 |
| T14 |
19786 |
9386 |
0 |
0 |
| T15 |
12792 |
2392 |
0 |
0 |
| T16 |
17420 |
7020 |
0 |
0 |
| T17 |
10608 |
208 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
8403 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
970 |
1 |
0 |
0 |
| T3 |
3510 |
0 |
0 |
0 |
| T4 |
1020 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
0 |
2 |
0 |
0 |
| T9 |
1405 |
0 |
0 |
0 |
| T12 |
900 |
0 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
1522 |
0 |
0 |
0 |
| T15 |
984 |
0 |
0 |
0 |
| T16 |
1340 |
0 |
0 |
0 |
| T17 |
816 |
0 |
0 |
0 |
| T24 |
7077 |
15 |
0 |
0 |
| T27 |
710 |
2 |
0 |
0 |
| T28 |
0 |
3 |
0 |
0 |
| T29 |
457 |
2 |
0 |
0 |
| T30 |
0 |
10 |
0 |
0 |
| T31 |
0 |
4 |
0 |
0 |
| T53 |
432 |
1 |
0 |
0 |
| T54 |
443 |
1 |
0 |
0 |
| T55 |
0 |
2 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T69 |
728 |
0 |
0 |
0 |
| T71 |
491 |
0 |
0 |
0 |
| T72 |
499 |
0 |
0 |
0 |
| T79 |
503 |
0 |
0 |
0 |
| T84 |
0 |
1 |
0 |
0 |
| T107 |
0 |
3 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T109 |
0 |
2 |
0 |
0 |
| T110 |
406 |
0 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
7975 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
970 |
1 |
0 |
0 |
| T3 |
3510 |
0 |
0 |
0 |
| T4 |
1020 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
0 |
2 |
0 |
0 |
| T10 |
2400 |
0 |
0 |
0 |
| T11 |
684 |
0 |
0 |
0 |
| T12 |
900 |
0 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
1522 |
0 |
0 |
0 |
| T15 |
984 |
0 |
0 |
0 |
| T16 |
1340 |
0 |
0 |
0 |
| T17 |
816 |
0 |
0 |
0 |
| T23 |
1982 |
0 |
0 |
0 |
| T24 |
14154 |
11 |
0 |
0 |
| T28 |
799 |
3 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
10 |
0 |
0 |
| T55 |
922 |
1 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T64 |
810 |
0 |
0 |
0 |
| T65 |
850 |
0 |
0 |
0 |
| T81 |
522 |
0 |
0 |
0 |
| T82 |
1060 |
0 |
0 |
0 |
| T84 |
0 |
2 |
0 |
0 |
| T107 |
0 |
3 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T109 |
0 |
1 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
| T132 |
0 |
2 |
0 |
0 |
| T133 |
0 |
1 |
0 |
0 |
| T134 |
0 |
2 |
0 |
0 |
| T135 |
426 |
0 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
4985 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
970 |
1 |
0 |
0 |
| T3 |
3510 |
0 |
0 |
0 |
| T4 |
1020 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
0 |
2 |
0 |
0 |
| T10 |
2400 |
0 |
0 |
0 |
| T11 |
684 |
0 |
0 |
0 |
| T12 |
900 |
0 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
1522 |
0 |
0 |
0 |
| T15 |
984 |
0 |
0 |
0 |
| T16 |
1340 |
0 |
0 |
0 |
| T17 |
816 |
0 |
0 |
0 |
| T23 |
1982 |
0 |
0 |
0 |
| T24 |
14154 |
7 |
0 |
0 |
| T28 |
799 |
3 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
6 |
0 |
0 |
| T55 |
922 |
1 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T64 |
810 |
0 |
0 |
0 |
| T65 |
850 |
0 |
0 |
0 |
| T81 |
522 |
0 |
0 |
0 |
| T82 |
1060 |
0 |
0 |
0 |
| T84 |
0 |
2 |
0 |
0 |
| T107 |
0 |
3 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T109 |
0 |
1 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
| T132 |
0 |
2 |
0 |
0 |
| T133 |
0 |
1 |
0 |
0 |
| T134 |
0 |
2 |
0 |
0 |
| T135 |
426 |
0 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
4985 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
970 |
1 |
0 |
0 |
| T3 |
3510 |
0 |
0 |
0 |
| T4 |
1020 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
0 |
2 |
0 |
0 |
| T10 |
2400 |
0 |
0 |
0 |
| T11 |
684 |
0 |
0 |
0 |
| T12 |
900 |
0 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
1522 |
0 |
0 |
0 |
| T15 |
984 |
0 |
0 |
0 |
| T16 |
1340 |
0 |
0 |
0 |
| T17 |
816 |
0 |
0 |
0 |
| T23 |
1982 |
0 |
0 |
0 |
| T24 |
14154 |
7 |
0 |
0 |
| T28 |
799 |
3 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
6 |
0 |
0 |
| T55 |
922 |
1 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T64 |
810 |
0 |
0 |
0 |
| T65 |
850 |
0 |
0 |
0 |
| T81 |
522 |
0 |
0 |
0 |
| T82 |
1060 |
0 |
0 |
0 |
| T84 |
0 |
2 |
0 |
0 |
| T107 |
0 |
3 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T109 |
0 |
1 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
| T132 |
0 |
2 |
0 |
0 |
| T133 |
0 |
1 |
0 |
0 |
| T134 |
0 |
2 |
0 |
0 |
| T135 |
426 |
0 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
124476352 |
580253 |
0 |
0 |
| T1 |
1018 |
83 |
0 |
0 |
| T2 |
970 |
2 |
0 |
0 |
| T3 |
3510 |
0 |
0 |
0 |
| T4 |
1020 |
0 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T8 |
0 |
94 |
0 |
0 |
| T10 |
2400 |
0 |
0 |
0 |
| T11 |
684 |
0 |
0 |
0 |
| T12 |
900 |
0 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
1522 |
0 |
0 |
0 |
| T15 |
984 |
0 |
0 |
0 |
| T16 |
1340 |
0 |
0 |
0 |
| T17 |
816 |
0 |
0 |
0 |
| T23 |
1982 |
0 |
0 |
0 |
| T24 |
14154 |
386 |
0 |
0 |
| T28 |
799 |
12 |
0 |
0 |
| T29 |
0 |
30 |
0 |
0 |
| T30 |
0 |
465 |
0 |
0 |
| T55 |
922 |
33 |
0 |
0 |
| T56 |
0 |
8 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T60 |
0 |
8 |
0 |
0 |
| T64 |
810 |
0 |
0 |
0 |
| T65 |
850 |
0 |
0 |
0 |
| T81 |
522 |
0 |
0 |
0 |
| T82 |
1060 |
0 |
0 |
0 |
| T84 |
0 |
83 |
0 |
0 |
| T107 |
0 |
9 |
0 |
0 |
| T108 |
0 |
8 |
0 |
0 |
| T109 |
0 |
7 |
0 |
0 |
| T130 |
0 |
2 |
0 |
0 |
| T131 |
0 |
3 |
0 |
0 |
| T132 |
0 |
2 |
0 |
0 |
| T133 |
0 |
7 |
0 |
0 |
| T134 |
0 |
19 |
0 |
0 |
| T135 |
426 |
0 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
43087968 |
38893 |
0 |
0 |
| T1 |
1527 |
3 |
0 |
0 |
| T2 |
4365 |
3 |
0 |
0 |
| T3 |
15795 |
32 |
0 |
0 |
| T4 |
4590 |
35 |
0 |
0 |
| T5 |
3114 |
6 |
0 |
0 |
| T6 |
0 |
14 |
0 |
0 |
| T7 |
0 |
113 |
0 |
0 |
| T8 |
0 |
2 |
0 |
0 |
| T12 |
4050 |
55 |
0 |
0 |
| T13 |
3798 |
24 |
0 |
0 |
| T14 |
6849 |
2 |
0 |
0 |
| T15 |
4428 |
63 |
0 |
0 |
| T16 |
6030 |
9 |
0 |
0 |
| T17 |
3672 |
0 |
0 |
0 |
| T25 |
0 |
119 |
0 |
0 |
| T26 |
0 |
47 |
0 |
0 |
| T62 |
0 |
3 |
0 |
0 |
| T63 |
0 |
4 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
23937760 |
21616875 |
0 |
0 |
| T1 |
2545 |
545 |
0 |
0 |
| T2 |
2425 |
425 |
0 |
0 |
| T3 |
8775 |
6775 |
0 |
0 |
| T4 |
2550 |
550 |
0 |
0 |
| T12 |
2250 |
250 |
0 |
0 |
| T13 |
2110 |
110 |
0 |
0 |
| T14 |
3805 |
1805 |
0 |
0 |
| T15 |
2460 |
460 |
0 |
0 |
| T16 |
3350 |
1350 |
0 |
0 |
| T17 |
2040 |
40 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
81388384 |
73497375 |
0 |
0 |
| T1 |
8653 |
1853 |
0 |
0 |
| T2 |
8245 |
1445 |
0 |
0 |
| T3 |
29835 |
23035 |
0 |
0 |
| T4 |
8670 |
1870 |
0 |
0 |
| T12 |
7650 |
850 |
0 |
0 |
| T13 |
7174 |
374 |
0 |
0 |
| T14 |
12937 |
6137 |
0 |
0 |
| T15 |
8364 |
1564 |
0 |
0 |
| T16 |
11390 |
4590 |
0 |
0 |
| T17 |
6936 |
136 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
43087968 |
38910375 |
0 |
0 |
| T1 |
4581 |
981 |
0 |
0 |
| T2 |
4365 |
765 |
0 |
0 |
| T3 |
15795 |
12195 |
0 |
0 |
| T4 |
4590 |
990 |
0 |
0 |
| T12 |
4050 |
450 |
0 |
0 |
| T13 |
3798 |
198 |
0 |
0 |
| T14 |
6849 |
3249 |
0 |
0 |
| T15 |
4428 |
828 |
0 |
0 |
| T16 |
6030 |
2430 |
0 |
0 |
| T17 |
3672 |
72 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
110113696 |
4117 |
0 |
0 |
| T1 |
509 |
1 |
0 |
0 |
| T2 |
485 |
1 |
0 |
0 |
| T3 |
1755 |
0 |
0 |
0 |
| T4 |
510 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T8 |
0 |
1 |
0 |
0 |
| T10 |
2400 |
0 |
0 |
0 |
| T11 |
684 |
0 |
0 |
0 |
| T12 |
450 |
0 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
761 |
0 |
0 |
0 |
| T15 |
492 |
0 |
0 |
0 |
| T16 |
670 |
0 |
0 |
0 |
| T17 |
408 |
0 |
0 |
0 |
| T23 |
1982 |
0 |
0 |
0 |
| T24 |
14154 |
5 |
0 |
0 |
| T28 |
799 |
3 |
0 |
0 |
| T40 |
0 |
1 |
0 |
0 |
| T55 |
922 |
0 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T64 |
810 |
0 |
0 |
0 |
| T65 |
850 |
0 |
0 |
0 |
| T81 |
522 |
0 |
0 |
0 |
| T82 |
1060 |
0 |
0 |
0 |
| T84 |
0 |
1 |
0 |
0 |
| T91 |
0 |
2 |
0 |
0 |
| T94 |
0 |
2 |
0 |
0 |
| T107 |
0 |
3 |
0 |
0 |
| T108 |
0 |
1 |
0 |
0 |
| T109 |
0 |
1 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
| T132 |
0 |
2 |
0 |
0 |
| T133 |
0 |
1 |
0 |
0 |
| T134 |
0 |
2 |
0 |
0 |
| T135 |
426 |
0 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
14362656 |
204266 |
0 |
0 |
| T3 |
1755 |
51 |
0 |
0 |
| T5 |
519 |
0 |
0 |
0 |
| T6 |
6912 |
3911 |
0 |
0 |
| T7 |
1860 |
0 |
0 |
0 |
| T8 |
518 |
0 |
0 |
0 |
| T16 |
670 |
0 |
0 |
0 |
| T17 |
408 |
0 |
0 |
0 |
| T18 |
0 |
841 |
0 |
0 |
| T25 |
3498 |
0 |
0 |
0 |
| T26 |
522 |
0 |
0 |
0 |
| T27 |
1420 |
0 |
0 |
0 |
| T53 |
864 |
0 |
0 |
0 |
| T54 |
886 |
0 |
0 |
0 |
| T58 |
0 |
460 |
0 |
0 |
| T62 |
419 |
0 |
0 |
0 |
| T63 |
422 |
0 |
0 |
0 |
| T66 |
0 |
130 |
0 |
0 |
| T67 |
0 |
315 |
0 |
0 |
| T68 |
0 |
764 |
0 |
0 |
| T69 |
1456 |
0 |
0 |
0 |
| T71 |
982 |
0 |
0 |
0 |
| T72 |
998 |
0 |
0 |
0 |
| T77 |
1044 |
0 |
0 |
0 |
| T78 |
1006 |
0 |
0 |
0 |
| T92 |
0 |
354 |
0 |
0 |
| T94 |
0 |
718 |
0 |
0 |
| T95 |
0 |
39502 |
0 |
0 |
| T96 |
0 |
274 |
0 |
0 |
| T110 |
812 |
0 |
0 |
0 |
| T136 |
0 |
543 |
0 |
0 |
| T137 |
0 |
33 |
0 |
0 |
| T138 |
0 |
21875 |
0 |
0 |
