Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T24 T30 T31 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T24 T30 T31 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T8 T29 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T5 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T5 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T8 T29 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T8 T29 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T8 T29 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T8 T29 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T8 T29 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T8 T29 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T8 T29 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T8 T29 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T8 T29 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T8 T29 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T8 T29 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T8 T29 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T8 T29 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T8 T29 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T8 T29 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T8 T29 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T24 T30 T99 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T8 T29 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T8 T29 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T8 T29 
186        1/1                    state_d = IdleSt;
           Tests:       T24 T30 T31 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 T31 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T8 T29 
191        1/1                      state_d = StableSt;
           Tests:       T1 T8 T29 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T8 T29 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T8 T29 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T8 T29 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T8 T29 
206        1/1                    state_d = IdleSt;
           Tests:       T24 T30 T52 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T8 T29 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T30,T31
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T8,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T8,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T8,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T30,T31
1	0	Covered	T24,T30,T31
1	1	Covered	T1,T8,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T29
0	1	Covered	T24,T30,T31
1	0	Covered	T24,T30,T31

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T29
0	1	Covered	T24,T30,T52
1	0	Covered	T227

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T29
1	-	Covered	T24,T30,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T29
DetectSt	168	Covered	T1,T8,T29
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T8,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T29
DebounceSt->IdleSt	163	Covered	T24,T30,T99
DetectSt->IdleSt	186	Covered	T24,T30,T31
DetectSt->StableSt	191	Covered	T1,T8,T29
IdleSt->DebounceSt	148	Covered	T1,T8,T29
StableSt->IdleSt	206	Covered	T24,T30,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T8,T29
0	1	Covered	T1,T8,T29
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T29
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T29
IdleSt	0	-	-	-	-	-	-	Covered	T24,T30,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T30,T99
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T29
DetectSt	-	-	-	-	1	-	-	Covered	T24,T30,T31
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T29
DetectSt	-	-	-	-	0	0	-	Covered	T1,T8,T29
StableSt	-	-	-	-	-	-	1	Covered	T24,T30,T52
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	2850	0	0
CntIncr_A	4787552	95362	0	0
CntNoWrap_A	4787552	4318691	0	0
DetectStDropOut_A	4787552	456	0	0
DetectedOut_A	4787552	67631	0	0
DetectedPulseOut_A	4787552	832	0	0
DisabledIdleSt_A	4787552	3919576	0	0
DisabledNoDetection_A	4787552	3921220	0	0
EnterDebounceSt_A	4787552	1436	0	0
EnterDetectSt_A	4787552	1415	0	0
EnterStableSt_A	4787552	832	0	0
PulseIsPulse_A	4787552	832	0	0
StayInStableSt	4787552	66698	0	0
gen_high_event_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_high_level_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_not_sticky_sva.StableStDropOut_A	4787552	730	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	2850	0	0
T1	509	2	0	0
T2	485	0	0	0
T3	1755	0	0	0
T4	510	0	0	0
T8	0	2	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	16	0	0
T29	0	2	0	0
T30	0	16	0	0
T31	0	8	0	0
T37	0	52	0	0
T55	0	2	0	0
T84	0	2	0	0
T85	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	95362	0	0
T1	509	21	0	0
T2	485	0	0	0
T3	1755	0	0	0
T4	510	0	0	0
T8	0	21	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	425	0	0
T29	0	21	0	0
T30	0	561	0	0
T31	0	208	0	0
T37	0	1652	0	0
T55	0	21	0	0
T84	0	21	0	0
T85	0	147	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4318691	0	0
T1	509	106	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	456	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T37	0	9	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T85	0	3	0	0
T87	0	17	0	0
T88	0	16	0	0
T89	0	18	0	0
T90	415	0	0	0
T111	0	23	0	0
T113	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	67631	0	0
T1	509	83	0	0
T2	485	0	0	0
T3	1755	0	0	0
T4	510	0	0	0
T8	0	93	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	312	0	0
T29	0	32	0	0
T30	0	401	0	0
T52	0	1413	0	0
T55	0	35	0	0
T84	0	82	0	0
T228	0	262	0	0
T229	0	1364	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	832	0	0
T1	509	1	0	0
T2	485	0	0	0
T3	1755	0	0	0
T4	510	0	0	0
T8	0	1	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	5	0	0
T29	0	1	0	0
T30	0	5	0	0
T52	0	11	0	0
T55	0	1	0	0
T84	0	1	0	0
T228	0	14	0	0
T229	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	3919576	0	0
T1	509	4	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	3921220	0	0
T1	509	4	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	1436	0	0
T1	509	1	0	0
T2	485	0	0	0
T3	1755	0	0	0
T4	510	0	0	0
T8	0	1	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	9	0	0
T29	0	1	0	0
T30	0	9	0	0
T31	0	4	0	0
T37	0	26	0	0
T55	0	1	0	0
T84	0	1	0	0
T85	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	1415	0	0
T1	509	1	0	0
T2	485	0	0	0
T3	1755	0	0	0
T4	510	0	0	0
T8	0	1	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	7	0	0
T29	0	1	0	0
T30	0	7	0	0
T31	0	4	0	0
T37	0	26	0	0
T55	0	1	0	0
T84	0	1	0	0
T85	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	832	0	0
T1	509	1	0	0
T2	485	0	0	0
T3	1755	0	0	0
T4	510	0	0	0
T8	0	1	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	5	0	0
T29	0	1	0	0
T30	0	5	0	0
T52	0	11	0	0
T55	0	1	0	0
T84	0	1	0	0
T228	0	14	0	0
T229	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	832	0	0
T1	509	1	0	0
T2	485	0	0	0
T3	1755	0	0	0
T4	510	0	0	0
T8	0	1	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	5	0	0
T29	0	1	0	0
T30	0	5	0	0
T52	0	11	0	0
T55	0	1	0	0
T84	0	1	0	0
T228	0	14	0	0
T229	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	66698	0	0
T1	509	81	0	0
T2	485	0	0	0
T3	1755	0	0	0
T4	510	0	0	0
T8	0	91	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	307	0	0
T29	0	30	0	0
T30	0	396	0	0
T52	0	1399	0	0
T55	0	33	0	0
T84	0	80	0	0
T228	0	248	0	0
T229	0	1346	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	730	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	5	0	0
T30	0	5	0	0
T52	0	8	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T101	0	26	0	0
T228	0	14	0	0
T229	0	8	0	0
T230	0	8	0	0
T231	0	12	0	0
T232	0	25	0	0
T233	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T2 T7 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T2 T7 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T5 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T5 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T2 T7 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T2 T7 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T2 T7 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T2 T7 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T2 T7 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T7 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T2 T7 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T2 T7 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T53 T54 T29 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T2 T7 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T2 T7 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T2 T7 
186        1/1                    state_d = IdleSt;
           Tests:       T24 T30 T41 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 T41 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T2 T7 
191        1/1                      state_d = StableSt;
           Tests:       T1 T2 T7 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T2 T7 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T2 T7 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T2 T7 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T2 T7 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T2 T7 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T2 T7 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T25,T7,T9
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T41,T112,T39
1	0	Covered	T24,T30

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T24,T100

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T7
1	-	Covered	T1,T2,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T53,T54,T29
DetectSt->IdleSt	186	Covered	T24,T30,T41
DetectSt->StableSt	191	Covered	T1,T2,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T54,T29
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T24,T30,T41
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	664	0	0
CntIncr_A	4787552	34648	0	0
CntNoWrap_A	4787552	4320877	0	0
DetectStDropOut_A	4787552	46	0	0
DetectedOut_A	4787552	9849	0	0
DetectedPulseOut_A	4787552	254	0	0
DisabledIdleSt_A	4787552	4019252	0	0
DisabledNoDetection_A	4787552	4020495	0	0
EnterDebounceSt_A	4787552	361	0	0
EnterDetectSt_A	4787552	305	0	0
EnterStableSt_A	4787552	254	0	0
PulseIsPulse_A	4787552	254	0	0
StayInStableSt	4787552	9562	0	0
gen_high_level_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_not_sticky_sva.StableStDropOut_A	4787552	218	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	664	0	0
T1	509	2	0	0
T2	485	2	0	0
T3	1755	0	0	0
T4	510	0	0	0
T7	0	2	0	0
T8	0	2	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	8	0	0
T29	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	34648	0	0
T1	509	25	0	0
T2	485	25	0	0
T3	1755	0	0	0
T4	510	0	0	0
T7	0	25	0	0
T8	0	25	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	168	0	0
T29	0	20	0	0
T53	0	20	0	0
T54	0	20	0	0
T55	0	20	0	0
T57	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4320877	0	0
T1	509	106	0	0
T2	485	82	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	46	0	0
T39	0	2	0	0
T41	22514	2	0	0
T112	0	3	0	0
T114	0	3	0	0
T115	0	7	0	0
T116	0	2	0	0
T117	0	4	0	0
T118	0	1	0	0
T119	0	9	0	0
T120	0	5	0	0
T121	32156	0	0	0
T122	407	0	0	0
T123	1256	0	0	0
T124	883	0	0	0
T125	502	0	0	0
T126	832	0	0	0
T127	2511	0	0	0
T128	423	0	0	0
T129	496	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	9849	0	0
T1	509	3	0	0
T2	485	3	0	0
T3	1755	0	0	0
T4	510	0	0	0
T7	0	3	0	0
T8	0	4	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	78	0	0
T30	0	70	0	0
T58	0	3	0	0
T84	0	4	0	0
T130	0	3	0	0
T131	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	254	0	0
T1	509	1	0	0
T2	485	1	0	0
T3	1755	0	0	0
T4	510	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	1	0	0
T30	0	1	0	0
T58	0	1	0	0
T84	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4019252	0	0
T1	509	26	0	0
T2	485	3	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4020495	0	0
T1	509	26	0	0
T2	485	3	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	361	0	0
T1	509	1	0	0
T2	485	1	0	0
T3	1755	0	0	0
T4	510	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	5	0	0
T29	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	305	0	0
T1	509	1	0	0
T2	485	1	0	0
T3	1755	0	0	0
T4	510	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	3	0	0
T30	0	3	0	0
T58	0	1	0	0
T84	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	254	0	0
T1	509	1	0	0
T2	485	1	0	0
T3	1755	0	0	0
T4	510	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	1	0	0
T30	0	1	0	0
T58	0	1	0	0
T84	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	254	0	0
T1	509	1	0	0
T2	485	1	0	0
T3	1755	0	0	0
T4	510	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	1	0	0
T30	0	1	0	0
T58	0	1	0	0
T84	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	9562	0	0
T1	509	2	0	0
T2	485	2	0	0
T3	1755	0	0	0
T4	510	0	0	0
T7	0	2	0	0
T8	0	3	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T24	0	77	0	0
T30	0	69	0	0
T58	0	2	0	0
T84	0	3	0	0
T130	0	2	0	0
T131	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	218	0	0
T1	509	1	0	0
T2	485	1	0	0
T3	1755	0	0	0
T4	510	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	450	0	0	0
T13	422	0	0	0
T14	761	0	0	0
T15	492	0	0	0
T16	670	0	0	0
T17	408	0	0	0
T40	0	1	0	0
T58	0	1	0	0
T84	0	1	0	0
T91	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T24 T30 T31 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T24 T30 T31 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T24 T30 T31 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T5 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T5 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T24 T30 T31 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T24 T30 T31 
129        1/1              cnt_en = 1'b0;
           Tests:       T24 T30 T31 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T24 T30 T31 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T24 T30 T31 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T24 T30 T31 
139                     
140        1/1              unique case (state_q)
           Tests:       T24 T30 T31 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T24 T30 T31 
148        1/1                    state_d = DebounceSt;
           Tests:       T24 T30 T31 
149        1/1                    cnt_en = 1'b1;
           Tests:       T24 T30 T31 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T24 T30 T31 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T24 T30 T31 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T24 T30 T31 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 T31 
167        1/1                    if (trigger_active) begin
           Tests:       T24 T30 T31 
168        1/1                      state_d = DetectSt;
           Tests:       T24 T30 T31 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T24 T30 T99 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T24 T30 T31 
182        1/1                  cnt_en = 1'b1;
           Tests:       T24 T30 T31 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T24 T30 T31 
186        1/1                    state_d = IdleSt;
           Tests:       T24 T30 T85 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 T85 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T24 T30 T31 
191        1/1                      state_d = StableSt;
           Tests:       T24 T30 T31 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T24 T30 T31 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T24 T30 T31 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T24 T30 T31 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T24 T30 T31 
206        1/1                    state_d = IdleSt;
           Tests:       T24 T30 T31 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T24 T30 T31 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T30,T31
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T30,T31
1	0	Covered	T24,T30,T31
1	1	Covered	T24,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T30,T31
0	1	Covered	T24,T30,T85
1	0	Covered	T24,T30,T52

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T30,T31
0	1	Covered	T24,T30,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T30,T31
1	-	Covered	T24,T30,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T30,T31
DetectSt	168	Covered	T24,T30,T31
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T24,T30,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T30,T31
DebounceSt->IdleSt	163	Covered	T24,T30,T99
DetectSt->IdleSt	186	Covered	T24,T30,T85
DetectSt->StableSt	191	Covered	T24,T30,T31
IdleSt->DebounceSt	148	Covered	T24,T30,T31
StableSt->IdleSt	206	Covered	T24,T30,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T30,T31
0	1	Covered	T24,T30,T31
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T30,T31
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T24,T30,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T30,T99
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T24,T30,T85
DetectSt	-	-	-	-	0	1	-	Covered	T24,T30,T31
DetectSt	-	-	-	-	0	0	-	Covered	T24,T30,T31
StableSt	-	-	-	-	-	-	1	Covered	T24,T30,T31
StableSt	-	-	-	-	-	-	0	Covered	T24,T30,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	3263	0	0
CntIncr_A	4787552	100068	0	0
CntNoWrap_A	4787552	4318278	0	0
DetectStDropOut_A	4787552	545	0	0
DetectedOut_A	4787552	71176	0	0
DetectedPulseOut_A	4787552	854	0	0
DisabledIdleSt_A	4787552	3913391	0	0
DisabledNoDetection_A	4787552	3915042	0	0
EnterDebounceSt_A	4787552	1640	0	0
EnterDetectSt_A	4787552	1623	0	0
EnterStableSt_A	4787552	854	0	0
PulseIsPulse_A	4787552	854	0	0
StayInStableSt	4787552	70227	0	0
gen_high_event_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_high_level_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_not_sticky_sva.StableStDropOut_A	4787552	759	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	3263	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	16	0	0
T30	0	16	0	0
T31	0	24	0	0
T37	0	54	0	0
T52	0	44	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T85	0	46	0	0
T86	0	44	0	0
T87	0	16	0	0
T88	0	42	0	0
T89	0	54	0	0
T90	415	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	100068	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	432	0	0
T30	0	422	0	0
T31	0	588	0	0
T37	0	1323	0	0
T52	0	1166	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T85	0	1149	0	0
T86	0	1100	0	0
T87	0	387	0	0
T88	0	1130	0	0
T89	0	1269	0	0
T90	415	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4318278	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	545	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	1	0	0
T30	0	1	0	0
T43	0	2	0	0
T52	0	20	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T85	0	23	0	0
T87	0	8	0	0
T88	0	21	0	0
T89	0	27	0	0
T90	415	0	0	0
T111	0	17	0	0
T229	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	71176	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	369	0	0
T30	0	366	0	0
T31	0	1995	0	0
T37	0	1724	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	1396	0	0
T90	415	0	0	0
T228	0	554	0	0
T230	0	1176	0	0
T231	0	961	0	0
T232	0	520	0	0
T234	0	1456	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	854	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	5	0	0
T30	0	5	0	0
T31	0	12	0	0
T37	0	27	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	22	0	0
T90	415	0	0	0
T228	0	13	0	0
T230	0	24	0	0
T231	0	19	0	0
T232	0	14	0	0
T234	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	3913391	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	3915042	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	1640	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	9	0	0
T30	0	9	0	0
T31	0	12	0	0
T37	0	27	0	0
T52	0	22	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T85	0	23	0	0
T86	0	22	0	0
T87	0	8	0	0
T88	0	21	0	0
T89	0	27	0	0
T90	415	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	1623	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	7	0	0
T30	0	7	0	0
T31	0	12	0	0
T37	0	27	0	0
T52	0	22	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T85	0	23	0	0
T86	0	22	0	0
T87	0	8	0	0
T88	0	21	0	0
T89	0	27	0	0
T90	415	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	854	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	5	0	0
T30	0	5	0	0
T31	0	12	0	0
T37	0	27	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	22	0	0
T90	415	0	0	0
T228	0	13	0	0
T230	0	24	0	0
T231	0	19	0	0
T232	0	14	0	0
T234	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	854	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	5	0	0
T30	0	5	0	0
T31	0	12	0	0
T37	0	27	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	22	0	0
T90	415	0	0	0
T228	0	13	0	0
T230	0	24	0	0
T231	0	19	0	0
T232	0	14	0	0
T234	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	70227	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	364	0	0
T30	0	361	0	0
T31	0	1980	0	0
T37	0	1691	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	1373	0	0
T90	415	0	0	0
T228	0	541	0	0
T230	0	1150	0	0
T231	0	940	0	0
T232	0	506	0	0
T234	0	1447	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	759	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	5	0	0
T30	0	5	0	0
T31	0	9	0	0
T37	0	21	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	21	0	0
T90	415	0	0	0
T228	0	13	0	0
T230	0	22	0	0
T231	0	17	0	0
T232	0	14	0	0
T234	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T24 T30 T31 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T24 T30 T31 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T5 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T5 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T24 T30 T31 
149        1/1                    cnt_en = 1'b1;
           Tests:       T24 T30 T31 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T24 T30 T31 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T24 T30 T31 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T24 T30 T31 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 T31 
167        1/1                    if (trigger_active) begin
           Tests:       T24 T30 T31 
168        1/1                      state_d = DetectSt;
           Tests:       T24 T30 T31 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T91 T41 T121 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T24 T30 T31 
182        1/1                  cnt_en = 1'b1;
           Tests:       T24 T30 T31 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T24 T30 T31 
186        1/1                    state_d = IdleSt;
           Tests:       T24 T30 T40 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 T40 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T24 T30 T31 
191        1/1                      state_d = StableSt;
           Tests:       T24 T30 T31 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T24 T30 T31 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T24 T30 T31 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T24 T30 T31 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T24 T30 T31 
206        1/1                    state_d = IdleSt;
           Tests:       T24 T30 T37 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T24 T30 T31 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T30,T31
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T30,T31
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T30,T31
1	0	Covered	T25,T7,T9
1	1	Covered	T24,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T30,T31
0	1	Covered	T40,T41,T121
1	0	Covered	T24,T30

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T30,T31
0	1	Covered	T37,T91,T86
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T30,T31
1	-	Covered	T24,T37,T91

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T30,T31
DetectSt	168	Covered	T24,T30,T31
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T24,T30,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T30,T31
DebounceSt->IdleSt	163	Covered	T24,T30,T91
DetectSt->IdleSt	186	Covered	T24,T30,T40
DetectSt->StableSt	191	Covered	T24,T30,T31
IdleSt->DebounceSt	148	Covered	T24,T30,T31
StableSt->IdleSt	206	Covered	T24,T30,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T30,T31
0	1	Covered	T24,T30,T31
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T30,T31
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T91,T41,T121
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T24,T30,T40
DetectSt	-	-	-	-	0	1	-	Covered	T24,T30,T31
DetectSt	-	-	-	-	0	0	-	Covered	T24,T30,T31
StableSt	-	-	-	-	-	-	1	Covered	T24,T30,T37
StableSt	-	-	-	-	-	-	0	Covered	T24,T30,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	683	0	0
CntIncr_A	4787552	38318	0	0
CntNoWrap_A	4787552	4320858	0	0
DetectStDropOut_A	4787552	50	0	0
DetectedOut_A	4787552	11951	0	0
DetectedPulseOut_A	4787552	268	0	0
DisabledIdleSt_A	4787552	4003720	0	0
DisabledNoDetection_A	4787552	4004971	0	0
EnterDebounceSt_A	4787552	361	0	0
EnterDetectSt_A	4787552	322	0	0
EnterStableSt_A	4787552	268	0	0
PulseIsPulse_A	4787552	268	0	0
StayInStableSt	4787552	11650	0	0
gen_high_level_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_not_sticky_sva.StableStDropOut_A	4787552	233	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	683	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	8	0	0
T30	0	8	0	0
T31	0	6	0	0
T37	0	10	0	0
T40	0	8	0	0
T41	0	18	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	2	0	0
T90	415	0	0	0
T91	0	7	0	0
T121	0	11	0	0
T154	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	38318	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	224	0	0
T30	0	229	0	0
T31	0	276	0	0
T37	0	395	0	0
T40	0	763	0	0
T41	0	456	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	40	0	0
T90	415	0	0	0
T91	0	272	0	0
T121	0	604	0	0
T154	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4320858	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	50	0	0
T40	11828	4	0	0
T41	0	8	0	0
T42	0	5	0	0
T52	17200	0	0	0
T91	11901	0	0	0
T115	0	2	0	0
T116	0	1	0	0
T121	0	5	0	0
T145	502	0	0	0
T146	2503	0	0	0
T147	403	0	0	0
T148	442	0	0	0
T235	0	2	0	0
T236	0	7	0	0
T237	0	5	0	0
T238	0	1	0	0
T239	572	0	0	0
T240	493	0	0	0
T241	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	11951	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	79	0	0
T30	0	70	0	0
T31	0	161	0	0
T37	0	353	0	0
T38	0	50	0	0
T39	0	16	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	81	0	0
T90	415	0	0	0
T91	0	141	0	0
T114	0	15	0	0
T230	0	123	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	268	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	1	0	0
T30	0	1	0	0
T31	0	3	0	0
T37	0	5	0	0
T38	0	4	0	0
T39	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	1	0	0
T90	415	0	0	0
T91	0	3	0	0
T114	0	2	0	0
T230	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4003720	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4004971	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	361	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	5	0	0
T30	0	5	0	0
T31	0	3	0	0
T37	0	5	0	0
T40	0	4	0	0
T41	0	10	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	1	0	0
T90	415	0	0	0
T91	0	4	0	0
T121	0	6	0	0
T154	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	322	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	3	0	0
T30	0	3	0	0
T31	0	3	0	0
T37	0	5	0	0
T40	0	4	0	0
T41	0	8	0	0
T42	0	5	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	1	0	0
T90	415	0	0	0
T91	0	3	0	0
T121	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	268	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	1	0	0
T30	0	1	0	0
T31	0	3	0	0
T37	0	5	0	0
T38	0	4	0	0
T39	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	1	0	0
T90	415	0	0	0
T91	0	3	0	0
T114	0	2	0	0
T230	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	268	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	1	0	0
T30	0	1	0	0
T31	0	3	0	0
T37	0	5	0	0
T38	0	4	0	0
T39	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	1	0	0
T90	415	0	0	0
T91	0	3	0	0
T114	0	2	0	0
T230	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	11650	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	78	0	0
T30	0	69	0	0
T31	0	155	0	0
T37	0	348	0	0
T38	0	46	0	0
T39	0	14	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	80	0	0
T90	415	0	0	0
T91	0	138	0	0
T114	0	13	0	0
T230	0	121	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	233	0	0
T37	22671	5	0	0
T38	0	4	0	0
T39	0	2	0	0
T85	5206	0	0	0
T86	0	1	0	0
T91	0	3	0	0
T109	688	0	0	0
T114	0	2	0	0
T117	0	4	0	0
T230	0	2	0	0
T231	0	2	0	0
T234	0	3	0	0
T242	426	0	0	0
T243	403	0	0	0
T244	870	0	0	0
T245	411	0	0	0
T246	492	0	0	0
T247	528	0	0	0
T248	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T24 T30 T31 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T24 T30 T31 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T24 T30 T31 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T5 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T5 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T24 T30 T31 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T24 T30 T31 
129        1/1              cnt_en = 1'b0;
           Tests:       T24 T30 T31 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T24 T30 T31 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T24 T30 T31 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T24 T30 T31 
139                     
140        1/1              unique case (state_q)
           Tests:       T24 T30 T31 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T24 T30 T31 
148        1/1                    state_d = DebounceSt;
           Tests:       T24 T30 T31 
149        1/1                    cnt_en = 1'b1;
           Tests:       T24 T30 T31 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T24 T30 T31 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T24 T30 T31 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T24 T30 T31 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 T31 
167        1/1                    if (trigger_active) begin
           Tests:       T24 T30 T31 
168        1/1                      state_d = DetectSt;
           Tests:       T24 T30 T31 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T24 T30 T99 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T24 T30 T31 
182        1/1                  cnt_en = 1'b1;
           Tests:       T24 T30 T31 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T24 T30 T31 
186        1/1                    state_d = IdleSt;
           Tests:       T24 T30 T31 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 T31 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T24 T30 T31 
191        1/1                      state_d = StableSt;
           Tests:       T24 T30 T37 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T24 T30 T37 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T24 T30 T37 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T24 T30 T37 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T24 T30 T37 
206        1/1                    state_d = IdleSt;
           Tests:       T24 T30 T37 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T24 T30 T37 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T30,T31
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T30,T31
1	0	Covered	T24,T30,T31
1	1	Covered	T24,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T30,T31
0	1	Covered	T24,T30,T31
1	0	Covered	T24,T30,T31

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T30,T37
0	1	Covered	T24,T30,T37
1	0	Covered	T101,T102

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T30,T37
1	-	Covered	T24,T30,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T30,T31
DetectSt	168	Covered	T24,T30,T31
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T24,T30,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T30,T31
DebounceSt->IdleSt	163	Covered	T24,T30,T99
DetectSt->IdleSt	186	Covered	T24,T30,T31
DetectSt->StableSt	191	Covered	T24,T30,T37
IdleSt->DebounceSt	148	Covered	T24,T30,T31
StableSt->IdleSt	206	Covered	T24,T30,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T30,T31
0	1	Covered	T24,T30,T31
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T30,T31
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T24,T30,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T30,T99
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T24,T30,T31
DetectSt	-	-	-	-	0	1	-	Covered	T24,T30,T37
DetectSt	-	-	-	-	0	0	-	Covered	T24,T30,T31
StableSt	-	-	-	-	-	-	1	Covered	T24,T30,T37
StableSt	-	-	-	-	-	-	0	Covered	T24,T30,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	3093	0	0
CntIncr_A	4787552	100212	0	0
CntNoWrap_A	4787552	4318448	0	0
DetectStDropOut_A	4787552	507	0	0
DetectedOut_A	4787552	68096	0	0
DetectedPulseOut_A	4787552	864	0	0
DisabledIdleSt_A	4787552	3920273	0	0
DisabledNoDetection_A	4787552	3921939	0	0
EnterDebounceSt_A	4787552	1554	0	0
EnterDetectSt_A	4787552	1539	0	0
EnterStableSt_A	4787552	864	0	0
PulseIsPulse_A	4787552	864	0	0
StayInStableSt	4787552	67152	0	0
gen_high_event_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_high_level_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_not_sticky_sva.StableStDropOut_A	4787552	750	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	3093	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	16	0	0
T30	0	16	0	0
T31	0	44	0	0
T37	0	40	0	0
T52	0	20	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T85	0	50	0	0
T86	0	38	0	0
T87	0	60	0	0
T88	0	42	0	0
T89	0	46	0	0
T90	415	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	100212	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	566	0	0
T30	0	421	0	0
T31	0	1150	0	0
T37	0	1080	0	0
T52	0	300	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T85	0	1246	0	0
T86	0	1045	0	0
T87	0	1469	0	0
T88	0	1130	0	0
T89	0	1086	0	0
T90	415	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4318448	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	507	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	1	0	0
T30	0	1	0	0
T31	0	16	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T85	0	25	0	0
T87	0	30	0	0
T88	0	21	0	0
T89	0	23	0	0
T90	415	0	0	0
T113	0	6	0	0
T234	0	18	0	0
T249	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	68096	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	356	0	0
T30	0	359	0	0
T37	0	2086	0	0
T43	0	172	0	0
T52	0	1195	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	647	0	0
T90	415	0	0	0
T111	0	1270	0	0
T228	0	2294	0	0
T229	0	2803	0	0
T230	0	831	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	864	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	5	0	0
T30	0	5	0	0
T37	0	20	0	0
T43	0	8	0	0
T52	0	10	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	19	0	0
T90	415	0	0	0
T111	0	4	0	0
T228	0	28	0	0
T229	0	22	0	0
T230	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	3920273	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	3921939	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	1554	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	9	0	0
T30	0	9	0	0
T31	0	22	0	0
T37	0	20	0	0
T52	0	10	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T85	0	25	0	0
T86	0	19	0	0
T87	0	30	0	0
T88	0	21	0	0
T89	0	23	0	0
T90	415	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	1539	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	7	0	0
T30	0	7	0	0
T31	0	22	0	0
T37	0	20	0	0
T52	0	10	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T85	0	25	0	0
T86	0	19	0	0
T87	0	30	0	0
T88	0	21	0	0
T89	0	23	0	0
T90	415	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	864	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	5	0	0
T30	0	5	0	0
T37	0	20	0	0
T43	0	8	0	0
T52	0	10	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	19	0	0
T90	415	0	0	0
T111	0	4	0	0
T228	0	28	0	0
T229	0	22	0	0
T230	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	864	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	5	0	0
T30	0	5	0	0
T37	0	20	0	0
T43	0	8	0	0
T52	0	10	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	19	0	0
T90	415	0	0	0
T111	0	4	0	0
T228	0	28	0	0
T229	0	22	0	0
T230	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	67152	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	351	0	0
T30	0	354	0	0
T37	0	2062	0	0
T43	0	164	0	0
T52	0	1181	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	626	0	0
T90	415	0	0	0
T111	0	1266	0	0
T228	0	2266	0	0
T229	0	2775	0	0
T230	0	818	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	750	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	5	0	0
T30	0	5	0	0
T37	0	16	0	0
T43	0	8	0	0
T52	0	6	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	17	0	0
T90	415	0	0	0
T111	0	4	0	0
T228	0	28	0	0
T229	0	16	0	0
T230	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T24 T30 T31 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T24 T30 T37 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T5 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T5 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T24 T30 T37 
149        1/1                    cnt_en = 1'b1;
           Tests:       T24 T30 T37 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T24 T30 T37 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T24 T30 T37 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T24 T30 T37 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 T37 
167        1/1                    if (trigger_active) begin
           Tests:       T24 T30 T37 
168        1/1                      state_d = DetectSt;
           Tests:       T24 T30 T37 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T41 T121 T154 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T24 T30 T37 
182        1/1                  cnt_en = 1'b1;
           Tests:       T24 T30 T37 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T24 T30 T37 
186        1/1                    state_d = IdleSt;
           Tests:       T24 T30 T155 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T30 T155 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T24 T30 T37 
191        1/1                      state_d = StableSt;
           Tests:       T24 T30 T37 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T24 T30 T37 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T24 T30 T37 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T24 T30 T37 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T24 T30 T37 
206        1/1                    state_d = IdleSt;
           Tests:       T24 T30 T40 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T24 T30 T37 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T30,T31
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T30,T31
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T37

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T24,T30,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T30,T37
1	0	Covered	T25,T7,T9
1	1	Covered	T24,T30,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T30,T37
0	1	Covered	T24,T155,T42
1	0	Covered	T24,T30

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T30,T37
0	1	Covered	T24,T40,T91
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T30,T37
1	-	Covered	T24,T40,T91

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T30,T37
DetectSt	168	Covered	T24,T30,T37
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T24,T30,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T30,T37
DebounceSt->IdleSt	163	Covered	T24,T30,T41
DetectSt->IdleSt	186	Covered	T24,T30,T155
DetectSt->StableSt	191	Covered	T24,T30,T37
IdleSt->DebounceSt	148	Covered	T24,T30,T37
StableSt->IdleSt	206	Covered	T24,T30,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T30,T37
0	1	Covered	T24,T30,T37
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T30,T37
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T30,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T30,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T121,T154
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T30,T37
DetectSt	-	-	-	-	1	-	-	Covered	T24,T30,T155
DetectSt	-	-	-	-	0	1	-	Covered	T24,T30,T37
DetectSt	-	-	-	-	0	0	-	Covered	T24,T30,T37
StableSt	-	-	-	-	-	-	1	Covered	T24,T30,T40
StableSt	-	-	-	-	-	-	0	Covered	T24,T30,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	4787552	705	0	0
CntIncr_A	4787552	38024	0	0
CntNoWrap_A	4787552	4320836	0	0
DetectStDropOut_A	4787552	37	0	0
DetectedOut_A	4787552	11923	0	0
DetectedPulseOut_A	4787552	293	0	0
DisabledIdleSt_A	4787552	4022269	0	0
DisabledNoDetection_A	4787552	4023549	0	0
EnterDebounceSt_A	4787552	372	0	0
EnterDetectSt_A	4787552	333	0	0
EnterStableSt_A	4787552	293	0	0
PulseIsPulse_A	4787552	293	0	0
StayInStableSt	4787552	11596	0	0
gen_high_level_sva.HighLevelEvent_A	4787552	4323375	0	0
gen_not_sticky_sva.StableStDropOut_A	4787552	257	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	705	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	8	0	0
T30	0	8	0	0
T37	0	4	0	0
T40	0	4	0	0
T41	0	19	0	0
T52	0	4	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	4	0	0
T90	415	0	0	0
T91	0	4	0	0
T121	0	9	0	0
T154	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	38024	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	204	0	0
T30	0	222	0	0
T37	0	196	0	0
T40	0	356	0	0
T41	0	443	0	0
T52	0	86	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	128	0	0
T90	415	0	0	0
T91	0	230	0	0
T121	0	463	0	0
T154	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4320836	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	37	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	1	0	0
T42	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T118	0	1	0	0
T119	0	1	0	0
T155	0	1	0	0
T250	0	6	0	0
T251	0	6	0	0
T252	0	5	0	0
T253	0	11	0	0
T254	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	11923	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	78	0	0
T30	0	71	0	0
T37	0	100	0	0
T40	0	24	0	0
T41	0	45	0	0
T52	0	143	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	114	0	0
T90	415	0	0	0
T91	0	20	0	0
T111	0	122	0	0
T121	0	36	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	293	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	1	0	0
T30	0	1	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	9	0	0
T52	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	2	0	0
T90	415	0	0	0
T91	0	2	0	0
T111	0	2	0	0
T121	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4022269	0	0
T1	509	108	0	0
T2	485	84	0	0
T3	1755	1354	0	0
T4	510	109	0	0
T12	450	49	0	0
T13	422	21	0	0
T14	761	360	0	0
T15	492	91	0	0
T16	670	269	0	0
T17	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4023549	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	372	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	5	0	0
T30	0	5	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	10	0	0
T52	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	2	0	0
T90	415	0	0	0
T91	0	2	0	0
T121	0	5	0	0
T154	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	333	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	3	0	0
T30	0	3	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	9	0	0
T52	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	2	0	0
T90	415	0	0	0
T91	0	2	0	0
T121	0	4	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	293	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	1	0	0
T30	0	1	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	9	0	0
T52	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	2	0	0
T90	415	0	0	0
T91	0	2	0	0
T111	0	2	0	0
T121	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	293	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	1	0	0
T30	0	1	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	9	0	0
T52	0	2	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	2	0	0
T90	415	0	0	0
T91	0	2	0	0
T111	0	2	0	0
T121	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	11596	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	77	0	0
T30	0	70	0	0
T37	0	96	0	0
T40	0	22	0	0
T41	0	36	0	0
T52	0	139	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T86	0	110	0	0
T90	415	0	0	0
T91	0	18	0	0
T111	0	120	0	0
T121	0	32	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	4323375	0	0
T1	509	109	0	0
T2	485	85	0	0
T3	1755	1355	0	0
T4	510	110	0	0
T12	450	50	0	0
T13	422	22	0	0
T14	761	361	0	0
T15	492	92	0	0
T16	670	270	0	0
T17	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4787552	257	0	0
T10	1200	0	0	0
T11	684	0	0	0
T24	7077	1	0	0
T38	0	1	0	0
T39	0	9	0	0
T40	0	2	0	0
T41	0	9	0	0
T55	461	0	0	0
T56	674	0	0	0
T64	405	0	0	0
T65	425	0	0	0
T73	493	0	0	0
T82	530	0	0	0
T90	415	0	0	0
T91	0	2	0	0
T111	0	1	0	0
T121	0	4	0	0
T228	0	4	0	0
T229	0	3	0	0