| T138 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.2725914734 |
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Sep 11 05:00:06 AM UTC 24 |
Sep 11 05:00:24 AM UTC 24 |
127129186024 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.728069419 |
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Sep 11 05:00:17 AM UTC 24 |
Sep 11 05:00:25 AM UTC 24 |
2014634603 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2817238908 |
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Sep 11 05:00:20 AM UTC 24 |
Sep 11 05:00:25 AM UTC 24 |
4523209331 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.2454587053 |
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Sep 11 05:00:23 AM UTC 24 |
Sep 11 05:00:25 AM UTC 24 |
2174227159 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2504952346 |
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Sep 11 05:00:12 AM UTC 24 |
Sep 11 05:00:25 AM UTC 24 |
7097327336 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.265007583 |
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Sep 11 05:00:20 AM UTC 24 |
Sep 11 05:00:26 AM UTC 24 |
3633401627 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1122492215 |
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Sep 11 05:00:24 AM UTC 24 |
Sep 11 05:00:27 AM UTC 24 |
2731570771 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.2802635516 |
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Sep 11 05:00:18 AM UTC 24 |
Sep 11 05:00:27 AM UTC 24 |
2456241293 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1406715928 |
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Sep 11 05:00:24 AM UTC 24 |
Sep 11 05:00:28 AM UTC 24 |
2762858742 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3366744426 |
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Sep 11 05:00:17 AM UTC 24 |
Sep 11 05:00:29 AM UTC 24 |
6846929916 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1571214400 |
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Sep 11 05:00:25 AM UTC 24 |
Sep 11 05:00:29 AM UTC 24 |
7002693527 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.141848115 |
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Sep 11 05:00:24 AM UTC 24 |
Sep 11 05:00:30 AM UTC 24 |
2520464794 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.4285328068 |
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Sep 11 05:00:24 AM UTC 24 |
Sep 11 05:00:30 AM UTC 24 |
3416907678 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.3787180042 |
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Sep 11 05:00:18 AM UTC 24 |
Sep 11 05:00:30 AM UTC 24 |
2510525684 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1902444404 |
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Sep 11 05:00:20 AM UTC 24 |
Sep 11 05:00:31 AM UTC 24 |
3762148911 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.70568170 |
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Sep 11 05:00:23 AM UTC 24 |
Sep 11 05:00:31 AM UTC 24 |
2466509262 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.2932952198 |
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Sep 11 05:00:28 AM UTC 24 |
Sep 11 05:00:32 AM UTC 24 |
2059496746 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.561326225 |
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Sep 11 05:00:28 AM UTC 24 |
Sep 11 05:00:32 AM UTC 24 |
2121256787 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.2673391319 |
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Sep 11 05:00:23 AM UTC 24 |
Sep 11 05:00:34 AM UTC 24 |
2008733263 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.868666264 |
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Sep 11 05:00:17 AM UTC 24 |
Sep 11 05:00:35 AM UTC 24 |
8932847278 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.575954859 |
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Sep 11 05:00:29 AM UTC 24 |
Sep 11 05:00:35 AM UTC 24 |
2468701435 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.2891146733 |
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Sep 11 05:00:31 AM UTC 24 |
Sep 11 05:00:35 AM UTC 24 |
2620558801 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1917407871 |
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Sep 11 05:00:31 AM UTC 24 |
Sep 11 05:00:36 AM UTC 24 |
5807651938 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.4075573776 |
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Sep 11 05:00:25 AM UTC 24 |
Sep 11 05:00:36 AM UTC 24 |
4602823152 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3940026059 |
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Sep 11 05:00:22 AM UTC 24 |
Sep 11 05:00:37 AM UTC 24 |
18568398929 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.1673663384 |
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Sep 11 05:00:24 AM UTC 24 |
Sep 11 05:00:38 AM UTC 24 |
2216851551 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.305427545 |
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Sep 11 05:00:42 AM UTC 24 |
Sep 11 05:00:47 AM UTC 24 |
2117036124 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.1808303039 |
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Sep 11 05:00:36 AM UTC 24 |
Sep 11 05:00:39 AM UTC 24 |
2049601488 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3294383609 |
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Sep 11 05:00:36 AM UTC 24 |
Sep 11 05:00:40 AM UTC 24 |
2491937474 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2663908286 |
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Sep 11 05:00:31 AM UTC 24 |
Sep 11 05:00:41 AM UTC 24 |
3970988472 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1791291675 |
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Sep 11 05:00:30 AM UTC 24 |
Sep 11 05:00:41 AM UTC 24 |
2235280062 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2687250022 |
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Sep 11 04:59:51 AM UTC 24 |
Sep 11 05:00:41 AM UTC 24 |
32511076114 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.3540132965 |
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Sep 11 05:00:30 AM UTC 24 |
Sep 11 05:00:41 AM UTC 24 |
2512592195 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.2326223268 |
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Sep 11 05:00:37 AM UTC 24 |
Sep 11 05:00:41 AM UTC 24 |
2219707997 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.847006300 |
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Sep 11 05:00:37 AM UTC 24 |
Sep 11 05:00:42 AM UTC 24 |
2533944591 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.1077736748 |
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Sep 11 05:00:32 AM UTC 24 |
Sep 11 05:00:42 AM UTC 24 |
2896738975 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.436883067 |
|
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Sep 11 05:00:36 AM UTC 24 |
Sep 11 05:00:43 AM UTC 24 |
2114041956 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.43974344 |
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Sep 11 05:00:22 AM UTC 24 |
Sep 11 05:00:43 AM UTC 24 |
6550369714 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3074178618 |
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Sep 11 04:58:31 AM UTC 24 |
Sep 11 05:00:45 AM UTC 24 |
48208619044 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1421191743 |
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Sep 11 05:00:38 AM UTC 24 |
Sep 11 05:00:45 AM UTC 24 |
4014798814 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1102219817 |
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Sep 11 05:00:42 AM UTC 24 |
Sep 11 05:00:46 AM UTC 24 |
2043657524 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.1274730385 |
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Sep 11 05:00:43 AM UTC 24 |
Sep 11 05:00:47 AM UTC 24 |
2239115975 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.522696816 |
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Sep 11 05:00:43 AM UTC 24 |
Sep 11 05:00:48 AM UTC 24 |
2521165697 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2245208612 |
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Sep 11 05:00:39 AM UTC 24 |
Sep 11 05:00:48 AM UTC 24 |
5658318532 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.62990159 |
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Sep 11 05:00:43 AM UTC 24 |
Sep 11 05:00:49 AM UTC 24 |
2626576180 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.342951041 |
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Sep 11 05:00:44 AM UTC 24 |
Sep 11 05:00:49 AM UTC 24 |
2874572017 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3628876914 |
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Sep 11 05:00:37 AM UTC 24 |
Sep 11 05:00:50 AM UTC 24 |
2610775923 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.49454487 |
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Sep 11 05:00:17 AM UTC 24 |
Sep 11 05:00:50 AM UTC 24 |
46639841052 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2599565136 |
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Sep 11 05:00:34 AM UTC 24 |
Sep 11 05:00:50 AM UTC 24 |
6849397685 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.4229936436 |
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Sep 11 05:00:42 AM UTC 24 |
Sep 11 05:00:51 AM UTC 24 |
2477648976 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.4241750903 |
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Sep 11 04:59:36 AM UTC 24 |
Sep 11 05:00:51 AM UTC 24 |
51226965703 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3619402206 |
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Sep 11 05:00:45 AM UTC 24 |
Sep 11 05:00:52 AM UTC 24 |
3463101553 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1423755602 |
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Sep 11 05:00:48 AM UTC 24 |
Sep 11 05:00:52 AM UTC 24 |
4999949862 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2622246297 |
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Sep 11 05:00:45 AM UTC 24 |
Sep 11 05:00:52 AM UTC 24 |
11750124374 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.2300336534 |
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Sep 11 05:00:50 AM UTC 24 |
Sep 11 05:00:53 AM UTC 24 |
2038476710 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.4239924925 |
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Sep 11 05:00:12 AM UTC 24 |
Sep 11 05:00:54 AM UTC 24 |
45760859820 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.1315133490 |
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Sep 11 05:00:51 AM UTC 24 |
Sep 11 05:00:55 AM UTC 24 |
2451238746 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.1073566197 |
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Sep 11 05:00:51 AM UTC 24 |
Sep 11 05:00:55 AM UTC 24 |
2531493114 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2673781878 |
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Sep 11 05:00:52 AM UTC 24 |
Sep 11 05:00:56 AM UTC 24 |
2789506920 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3212739468 |
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Sep 11 05:00:51 AM UTC 24 |
Sep 11 05:00:56 AM UTC 24 |
2633988911 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.614386938 |
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Sep 11 05:00:49 AM UTC 24 |
Sep 11 05:00:56 AM UTC 24 |
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| T186 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.3393270608 |
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Sep 11 05:00:39 AM UTC 24 |
Sep 11 05:00:58 AM UTC 24 |
4467670443 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3563238343 |
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Sep 11 05:00:42 AM UTC 24 |
Sep 11 05:00:58 AM UTC 24 |
6406831476 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.1252236773 |
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Sep 11 05:00:51 AM UTC 24 |
Sep 11 05:00:59 AM UTC 24 |
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| T183 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3556108864 |
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Sep 11 05:00:55 AM UTC 24 |
Sep 11 05:00:59 AM UTC 24 |
4978560524 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.1106279117 |
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Sep 11 05:00:50 AM UTC 24 |
Sep 11 05:01:00 AM UTC 24 |
2108942187 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.566377548 |
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Sep 11 05:00:50 AM UTC 24 |
Sep 11 05:01:00 AM UTC 24 |
7290555285 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1980746453 |
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Sep 11 05:00:57 AM UTC 24 |
Sep 11 05:01:00 AM UTC 24 |
2128312990 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.1767029174 |
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Sep 11 04:59:59 AM UTC 24 |
Sep 11 05:01:00 AM UTC 24 |
121935051183 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.3220340615 |
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Sep 11 05:00:58 AM UTC 24 |
Sep 11 05:01:01 AM UTC 24 |
2202227723 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.3046639222 |
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Sep 11 05:00:57 AM UTC 24 |
Sep 11 05:01:01 AM UTC 24 |
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| T491 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.2645949719 |
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Sep 11 05:00:57 AM UTC 24 |
Sep 11 05:01:05 AM UTC 24 |
2451066130 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2802184527 |
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Sep 11 05:00:42 AM UTC 24 |
Sep 11 05:01:06 AM UTC 24 |
6893728821 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3053202456 |
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Sep 11 05:00:26 AM UTC 24 |
Sep 11 05:01:07 AM UTC 24 |
127933046810 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.432607939 |
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Sep 11 05:00:59 AM UTC 24 |
Sep 11 05:01:07 AM UTC 24 |
2609111339 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1853238780 |
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Sep 11 05:01:00 AM UTC 24 |
Sep 11 05:01:09 AM UTC 24 |
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| T113 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3845215783 |
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Sep 11 05:00:32 AM UTC 24 |
Sep 11 05:01:11 AM UTC 24 |
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| T495 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.4107032865 |
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Sep 11 05:01:07 AM UTC 24 |
Sep 11 05:01:12 AM UTC 24 |
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| T496 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.1616765597 |
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Sep 11 05:01:02 AM UTC 24 |
Sep 11 05:01:13 AM UTC 24 |
3346034368 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.2475833521 |
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Sep 11 05:00:59 AM UTC 24 |
Sep 11 05:01:14 AM UTC 24 |
2512435343 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.291552054 |
|
|
Sep 11 05:01:07 AM UTC 24 |
Sep 11 05:01:14 AM UTC 24 |
2113317334 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.96378315 |
|
|
Sep 11 05:01:02 AM UTC 24 |
Sep 11 05:01:14 AM UTC 24 |
2069826477 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.3341297577 |
|
|
Sep 11 05:01:11 AM UTC 24 |
Sep 11 05:01:16 AM UTC 24 |
2525881490 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.1627925891 |
|
|
Sep 11 04:59:36 AM UTC 24 |
Sep 11 05:01:16 AM UTC 24 |
171586739087 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2392768168 |
|
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Sep 11 05:01:02 AM UTC 24 |
Sep 11 05:01:18 AM UTC 24 |
4244975255 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1294108817 |
|
|
Sep 11 05:01:15 AM UTC 24 |
Sep 11 05:01:18 AM UTC 24 |
3285383566 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3281010859 |
|
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Sep 11 05:01:13 AM UTC 24 |
Sep 11 05:01:21 AM UTC 24 |
2617672739 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3960994621 |
|
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Sep 11 05:01:00 AM UTC 24 |
Sep 11 05:01:21 AM UTC 24 |
4475561619 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.2975083763 |
|
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Sep 11 05:01:10 AM UTC 24 |
Sep 11 05:01:21 AM UTC 24 |
2074536276 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.4154458937 |
|
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Sep 11 05:01:08 AM UTC 24 |
Sep 11 05:01:21 AM UTC 24 |
2459079835 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1008945153 |
|
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Sep 11 05:00:56 AM UTC 24 |
Sep 11 05:01:22 AM UTC 24 |
10767759316 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.4102911310 |
|
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Sep 11 05:00:02 AM UTC 24 |
Sep 11 05:01:24 AM UTC 24 |
99454137557 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.658780288 |
|
|
Sep 11 05:01:22 AM UTC 24 |
Sep 11 05:01:25 AM UTC 24 |
2175607089 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2008236792 |
|
|
Sep 11 05:01:14 AM UTC 24 |
Sep 11 05:01:26 AM UTC 24 |
5451267909 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.1862721130 |
|
|
Sep 11 05:00:39 AM UTC 24 |
Sep 11 05:01:27 AM UTC 24 |
64721201992 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3785034847 |
|
|
Sep 11 05:01:19 AM UTC 24 |
Sep 11 05:01:27 AM UTC 24 |
4040119600 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2793577244 |
|
|
Sep 11 05:01:17 AM UTC 24 |
Sep 11 05:01:27 AM UTC 24 |
3272882743 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.611310890 |
|
|
Sep 11 05:01:02 AM UTC 24 |
Sep 11 05:01:27 AM UTC 24 |
24614774312 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.3636179049 |
|
|
Sep 11 05:01:22 AM UTC 24 |
Sep 11 05:01:28 AM UTC 24 |
2017815157 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2104919300 |
|
|
Sep 11 05:01:14 AM UTC 24 |
Sep 11 05:01:30 AM UTC 24 |
3439210876 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.678508560 |
|
|
Sep 11 05:01:25 AM UTC 24 |
Sep 11 05:01:30 AM UTC 24 |
2598704529 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.2774952666 |
|
|
Sep 11 05:01:19 AM UTC 24 |
Sep 11 05:01:30 AM UTC 24 |
11223520519 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.688436751 |
|
|
Sep 11 05:01:22 AM UTC 24 |
Sep 11 05:01:30 AM UTC 24 |
2444769416 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2883020227 |
|
|
Sep 11 05:01:27 AM UTC 24 |
Sep 11 05:01:32 AM UTC 24 |
3671240477 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.4152212342 |
|
|
Sep 11 05:00:15 AM UTC 24 |
Sep 11 05:01:32 AM UTC 24 |
165805601140 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.3927805808 |
|
|
Sep 11 05:01:22 AM UTC 24 |
Sep 11 05:01:32 AM UTC 24 |
2112503303 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.937595169 |
|
|
Sep 11 05:01:02 AM UTC 24 |
Sep 11 05:01:35 AM UTC 24 |
93225051040 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3119128973 |
|
|
Sep 11 04:58:53 AM UTC 24 |
Sep 11 05:01:36 AM UTC 24 |
59174542710 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.765465957 |
|
|
Sep 11 05:01:23 AM UTC 24 |
Sep 11 05:01:36 AM UTC 24 |
2514648033 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3052994540 |
|
|
Sep 11 05:01:28 AM UTC 24 |
Sep 11 05:01:37 AM UTC 24 |
3728862166 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.3712708386 |
|
|
Sep 11 05:01:28 AM UTC 24 |
Sep 11 05:01:38 AM UTC 24 |
3266051392 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2777999879 |
|
|
Sep 11 05:01:25 AM UTC 24 |
Sep 11 05:01:38 AM UTC 24 |
2609819851 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2488689711 |
|
|
Sep 11 05:01:32 AM UTC 24 |
Sep 11 05:01:39 AM UTC 24 |
2018067522 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2660106414 |
|
|
Sep 11 05:01:33 AM UTC 24 |
Sep 11 05:01:40 AM UTC 24 |
2620676988 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.523428496 |
|
|
Sep 11 05:01:37 AM UTC 24 |
Sep 11 05:01:41 AM UTC 24 |
2831106758 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.2274674606 |
|
|
Sep 11 05:01:39 AM UTC 24 |
Sep 11 05:01:42 AM UTC 24 |
4662763829 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3710610505 |
|
|
Sep 11 05:01:31 AM UTC 24 |
Sep 11 05:01:42 AM UTC 24 |
2114246079 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.2244068124 |
|
|
Sep 11 05:01:31 AM UTC 24 |
Sep 11 05:01:43 AM UTC 24 |
2014136306 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.2465891566 |
|
|
Sep 11 05:01:31 AM UTC 24 |
Sep 11 05:01:43 AM UTC 24 |
2453765136 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2256779405 |
|
|
Sep 11 05:00:56 AM UTC 24 |
Sep 11 05:01:45 AM UTC 24 |
14492747428 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.3477562580 |
|
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Sep 11 05:01:32 AM UTC 24 |
Sep 11 05:01:46 AM UTC 24 |
2510693936 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.2565050267 |
|
|
Sep 11 04:59:23 AM UTC 24 |
Sep 11 05:01:46 AM UTC 24 |
191230929934 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2274585653 |
|
|
Sep 11 05:01:29 AM UTC 24 |
Sep 11 05:01:46 AM UTC 24 |
16432920846 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.1820988262 |
|
|
Sep 11 05:01:42 AM UTC 24 |
Sep 11 05:01:46 AM UTC 24 |
2139787809 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2184702798 |
|
|
Sep 11 05:01:37 AM UTC 24 |
Sep 11 05:01:47 AM UTC 24 |
3790868953 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2286664338 |
|
|
Sep 11 05:01:38 AM UTC 24 |
Sep 11 05:01:47 AM UTC 24 |
12093320482 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1503693501 |
|
|
Sep 11 05:01:43 AM UTC 24 |
Sep 11 05:01:48 AM UTC 24 |
2214027121 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.400855918 |
|
|
Sep 11 05:01:41 AM UTC 24 |
Sep 11 05:01:49 AM UTC 24 |
2016718484 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1642585305 |
|
|
Sep 11 05:00:55 AM UTC 24 |
Sep 11 05:01:49 AM UTC 24 |
67368606624 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.3260418529 |
|
|
Sep 11 05:01:43 AM UTC 24 |
Sep 11 05:01:50 AM UTC 24 |
2516271356 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.3530853521 |
|
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Sep 11 05:01:43 AM UTC 24 |
Sep 11 05:01:51 AM UTC 24 |
2439612072 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2364182996 |
|
|
Sep 11 05:01:40 AM UTC 24 |
Sep 11 05:01:52 AM UTC 24 |
2644992222 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3663325521 |
|
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Sep 11 05:01:47 AM UTC 24 |
Sep 11 05:01:52 AM UTC 24 |
5482409052 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.450007320 |
|
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Sep 11 05:01:44 AM UTC 24 |
Sep 11 05:01:54 AM UTC 24 |
2614724600 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.710145392 |
|
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Sep 11 05:01:50 AM UTC 24 |
Sep 11 05:01:54 AM UTC 24 |
2488880770 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.3418319796 |
|
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Sep 11 05:01:50 AM UTC 24 |
Sep 11 05:01:55 AM UTC 24 |
2130760594 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.3241050891 |
|
|
Sep 11 05:01:49 AM UTC 24 |
Sep 11 05:01:55 AM UTC 24 |
2023017855 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.3658764129 |
|
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Sep 11 05:01:47 AM UTC 24 |
Sep 11 05:01:57 AM UTC 24 |
6069110120 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.454319866 |
|
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Sep 11 05:01:55 AM UTC 24 |
Sep 11 05:01:59 AM UTC 24 |
3011169628 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3296357845 |
|
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Sep 11 05:01:54 AM UTC 24 |
Sep 11 05:01:59 AM UTC 24 |
3624985423 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.514341323 |
|
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Sep 11 05:01:56 AM UTC 24 |
Sep 11 05:02:00 AM UTC 24 |
2556363381 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.918831389 |
|
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Sep 11 05:01:45 AM UTC 24 |
Sep 11 05:02:01 AM UTC 24 |
4641923806 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3128794909 |
|
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Sep 11 05:01:17 AM UTC 24 |
Sep 11 05:02:01 AM UTC 24 |
26090726859 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3876639968 |
|
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Sep 11 05:01:46 AM UTC 24 |
Sep 11 05:02:02 AM UTC 24 |
3844046947 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.3689134466 |
|
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Sep 11 05:01:51 AM UTC 24 |
Sep 11 05:02:04 AM UTC 24 |
2260170722 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.3427424113 |
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Sep 11 05:01:53 AM UTC 24 |
Sep 11 05:02:04 AM UTC 24 |
2513340976 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.1467192795 |
|
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Sep 11 05:02:03 AM UTC 24 |
Sep 11 05:02:05 AM UTC 24 |
2280536663 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.745538420 |
|
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Sep 11 05:02:01 AM UTC 24 |
Sep 11 05:02:06 AM UTC 24 |
2131134667 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1323575302 |
|
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Sep 11 05:01:53 AM UTC 24 |
Sep 11 05:02:06 AM UTC 24 |
2610943214 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3311026847 |
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Sep 11 05:01:48 AM UTC 24 |
Sep 11 05:02:07 AM UTC 24 |
5168389009 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1243031268 |
|
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Sep 11 05:02:01 AM UTC 24 |
Sep 11 05:02:07 AM UTC 24 |
2461312069 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.580844599 |
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Sep 11 05:02:00 AM UTC 24 |
Sep 11 05:02:08 AM UTC 24 |
2013194680 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.1566733690 |
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Sep 11 05:00:27 AM UTC 24 |
Sep 11 05:02:29 AM UTC 24 |
175783402445 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2476164549 |
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Sep 11 05:01:58 AM UTC 24 |
Sep 11 05:02:09 AM UTC 24 |
6083597492 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3968788679 |
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Sep 11 05:02:04 AM UTC 24 |
Sep 11 05:02:10 AM UTC 24 |
2621365701 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.3958564144 |
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Sep 11 05:01:41 AM UTC 24 |
Sep 11 05:02:11 AM UTC 24 |
9131044377 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.3594129181 |
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Sep 11 05:02:27 AM UTC 24 |
Sep 11 05:02:31 AM UTC 24 |
2055913621 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3135726136 |
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Sep 11 05:02:06 AM UTC 24 |
Sep 11 05:02:12 AM UTC 24 |
3422604890 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2517257490 |
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Sep 11 05:00:21 AM UTC 24 |
Sep 11 05:02:13 AM UTC 24 |
34431129983 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.935945600 |
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Sep 11 05:02:03 AM UTC 24 |
Sep 11 05:02:13 AM UTC 24 |
2512602905 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3827083808 |
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Sep 11 05:02:10 AM UTC 24 |
Sep 11 05:02:14 AM UTC 24 |
2062109905 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2782128650 |
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Sep 11 05:02:09 AM UTC 24 |
Sep 11 05:02:14 AM UTC 24 |
13829837540 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.2890186098 |
|
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Sep 11 05:02:10 AM UTC 24 |
Sep 11 05:02:14 AM UTC 24 |
2471575227 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2497925274 |
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Sep 11 05:02:06 AM UTC 24 |
Sep 11 05:02:15 AM UTC 24 |
4492549536 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.1951108866 |
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Sep 11 05:01:48 AM UTC 24 |
Sep 11 05:02:15 AM UTC 24 |
16438005992 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3997853273 |
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Sep 11 05:01:55 AM UTC 24 |
Sep 11 05:02:16 AM UTC 24 |
157839095565 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.3155219819 |
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Sep 11 05:02:12 AM UTC 24 |
Sep 11 05:02:18 AM UTC 24 |
2518529466 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1871888412 |
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Sep 11 05:02:14 AM UTC 24 |
Sep 11 05:02:18 AM UTC 24 |
2625635429 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2760443998 |
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Sep 11 05:02:15 AM UTC 24 |
Sep 11 05:02:19 AM UTC 24 |
3089120404 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.628806278 |
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Sep 11 05:02:10 AM UTC 24 |
Sep 11 05:02:19 AM UTC 24 |
2111276334 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.3823829165 |
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Sep 11 05:01:47 AM UTC 24 |
Sep 11 05:02:19 AM UTC 24 |
40812300320 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.873029256 |
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Sep 11 04:58:32 AM UTC 24 |
Sep 11 05:02:20 AM UTC 24 |
66618169232 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.1373276469 |
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Sep 11 05:02:11 AM UTC 24 |
Sep 11 05:02:20 AM UTC 24 |
2130092174 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2519762039 |
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Sep 11 05:02:15 AM UTC 24 |
Sep 11 05:02:21 AM UTC 24 |
3624828538 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.4020062702 |
|
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Sep 11 04:59:41 AM UTC 24 |
Sep 11 05:02:21 AM UTC 24 |
109222394142 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.919415914 |
|
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Sep 11 05:02:07 AM UTC 24 |
Sep 11 05:02:21 AM UTC 24 |
2703205567 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1664974873 |
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Sep 11 05:01:28 AM UTC 24 |
Sep 11 05:02:25 AM UTC 24 |
66079852906 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.564818078 |
|
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Sep 11 05:02:20 AM UTC 24 |
Sep 11 05:02:25 AM UTC 24 |
2493527848 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.617237994 |
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Sep 11 05:02:22 AM UTC 24 |
Sep 11 05:02:25 AM UTC 24 |
3422379845 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1099922595 |
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Sep 11 05:02:19 AM UTC 24 |
Sep 11 05:02:26 AM UTC 24 |
2012673721 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.608651968 |
|
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Sep 11 05:02:20 AM UTC 24 |
Sep 11 05:02:28 AM UTC 24 |
2210133397 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.73239297 |
|
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Sep 11 05:02:16 AM UTC 24 |
Sep 11 05:02:28 AM UTC 24 |
10055756275 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2380004898 |
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Sep 11 05:01:56 AM UTC 24 |
Sep 11 05:02:28 AM UTC 24 |
59759138413 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.105383700 |
|
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Sep 11 05:02:19 AM UTC 24 |
Sep 11 05:02:28 AM UTC 24 |
2108189921 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.1450533813 |
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Sep 11 05:02:20 AM UTC 24 |
Sep 11 05:02:28 AM UTC 24 |
2515120546 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.4017740074 |
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Sep 11 05:02:14 AM UTC 24 |
Sep 11 05:02:28 AM UTC 24 |
3538962283 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.4063124139 |
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Sep 11 05:02:23 AM UTC 24 |
Sep 11 05:02:29 AM UTC 24 |
3370863165 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3843096321 |
|
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Sep 11 05:02:21 AM UTC 24 |
Sep 11 05:02:30 AM UTC 24 |
2609682197 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3821763724 |
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Sep 11 04:59:42 AM UTC 24 |
Sep 11 05:02:32 AM UTC 24 |
69636368459 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.2720042147 |
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Sep 11 05:02:28 AM UTC 24 |
Sep 11 05:02:32 AM UTC 24 |
2236588984 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.121718904 |
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Sep 11 05:02:28 AM UTC 24 |
Sep 11 05:02:32 AM UTC 24 |
2484840827 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.193073035 |
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Sep 11 05:02:17 AM UTC 24 |
Sep 11 05:02:33 AM UTC 24 |
6148687594 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.4145735213 |
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Sep 11 05:02:30 AM UTC 24 |
Sep 11 05:02:33 AM UTC 24 |
2542980820 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1964109142 |
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Sep 11 05:00:11 AM UTC 24 |
Sep 11 05:02:33 AM UTC 24 |
48533164682 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2315576886 |
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Sep 11 05:02:30 AM UTC 24 |
Sep 11 05:02:35 AM UTC 24 |
3603664668 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.2756075941 |
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Sep 11 05:02:32 AM UTC 24 |
Sep 11 05:02:35 AM UTC 24 |
2839106858 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3469861920 |
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Sep 11 05:02:26 AM UTC 24 |
Sep 11 05:02:35 AM UTC 24 |
2774707552 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.2666512079 |
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Sep 11 05:02:25 AM UTC 24 |
Sep 11 05:02:36 AM UTC 24 |
2466909977 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.2208449148 |
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Sep 11 05:01:56 AM UTC 24 |
Sep 11 05:02:37 AM UTC 24 |
63208537847 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.2758489166 |
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Sep 11 05:02:28 AM UTC 24 |
Sep 11 05:02:37 AM UTC 24 |
2113274332 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1793554892 |
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Sep 11 05:02:08 AM UTC 24 |
Sep 11 05:02:38 AM UTC 24 |
13311505956 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1717696338 |
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Sep 11 05:02:22 AM UTC 24 |
Sep 11 05:02:38 AM UTC 24 |
4461354120 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.1249135337 |
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Sep 11 05:02:34 AM UTC 24 |
Sep 11 05:02:39 AM UTC 24 |
2029889662 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.821282800 |
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Sep 11 05:01:47 AM UTC 24 |
Sep 11 05:02:40 AM UTC 24 |
26334266305 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.4012995774 |
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Sep 11 05:02:30 AM UTC 24 |
Sep 11 05:02:40 AM UTC 24 |
4979471426 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2708154115 |
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Sep 11 05:02:36 AM UTC 24 |
Sep 11 05:02:40 AM UTC 24 |
2633484302 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.3910071145 |
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Sep 11 05:02:16 AM UTC 24 |
Sep 11 05:02:41 AM UTC 24 |
75597815729 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.807309014 |
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Sep 11 05:02:33 AM UTC 24 |
Sep 11 05:02:41 AM UTC 24 |
2014693751 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.225554697 |
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Sep 11 05:02:34 AM UTC 24 |
Sep 11 05:02:41 AM UTC 24 |
2458759892 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3476452893 |
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Sep 11 05:02:38 AM UTC 24 |
Sep 11 05:02:42 AM UTC 24 |
6479895622 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1866928021 |
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Sep 11 05:02:30 AM UTC 24 |
Sep 11 05:02:42 AM UTC 24 |
2608946818 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.563583824 |
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Sep 11 05:02:30 AM UTC 24 |
Sep 11 05:02:43 AM UTC 24 |
5142692173 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.2527305865 |
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Sep 11 05:02:41 AM UTC 24 |
Sep 11 05:02:45 AM UTC 24 |
2134646463 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.2833551777 |
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Sep 11 05:02:36 AM UTC 24 |
Sep 11 05:02:46 AM UTC 24 |
2508557441 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.2461833348 |
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Sep 11 05:02:34 AM UTC 24 |
Sep 11 05:02:47 AM UTC 24 |
2112575888 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.2919299705 |
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Sep 11 05:02:43 AM UTC 24 |
Sep 11 05:02:47 AM UTC 24 |
2532418657 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.4013384767 |
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Sep 11 05:02:41 AM UTC 24 |
Sep 11 05:02:48 AM UTC 24 |
2144245201 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2702431244 |
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Sep 11 05:02:43 AM UTC 24 |
Sep 11 05:02:49 AM UTC 24 |
2614541809 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.345460158 |
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Sep 11 05:02:41 AM UTC 24 |
Sep 11 05:02:49 AM UTC 24 |
2467514218 ps |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.3160491010 |
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Sep 11 05:02:40 AM UTC 24 |
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| T605 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1998471592 |
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Sep 11 05:02:33 AM UTC 24 |
Sep 11 05:02:50 AM UTC 24 |
3816173520 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.716391019 |
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Sep 11 05:01:28 AM UTC 24 |
Sep 11 05:02:51 AM UTC 24 |
114369770184 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1609562055 |
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Sep 11 05:02:43 AM UTC 24 |
Sep 11 05:02:53 AM UTC 24 |
3666510343 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3671606862 |
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Sep 11 05:01:16 AM UTC 24 |
Sep 11 05:02:54 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2897609692 |
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Sep 11 05:02:46 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.1840024984 |
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Sep 11 05:02:50 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.4009652468 |
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Sep 11 05:02:49 AM UTC 24 |
Sep 11 05:02:56 AM UTC 24 |
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| T610 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.1213260559 |
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Sep 11 05:02:52 AM UTC 24 |
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| T611 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3853278047 |
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Sep 11 05:02:39 AM UTC 24 |
Sep 11 05:02:57 AM UTC 24 |
8787232456 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.1128955344 |
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Sep 11 05:02:39 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.3884523751 |
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Sep 11 05:02:48 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.3789842909 |
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Sep 11 05:02:40 AM UTC 24 |
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12149596305 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.4019864517 |
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Sep 11 05:02:37 AM UTC 24 |
Sep 11 05:03:00 AM UTC 24 |
4689325150 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.1910918381 |
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Sep 11 05:02:52 AM UTC 24 |
Sep 11 05:03:00 AM UTC 24 |
2515064343 ps |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.471796798 |
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Sep 11 04:58:03 AM UTC 24 |
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| T614 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1738252977 |
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Sep 11 05:02:26 AM UTC 24 |
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14197558905 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.4070390794 |
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Sep 11 05:02:50 AM UTC 24 |
Sep 11 05:03:00 AM UTC 24 |
2456505273 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1040065115 |
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Sep 11 05:02:56 AM UTC 24 |
Sep 11 05:03:01 AM UTC 24 |
6486455367 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2781669539 |
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|
Sep 11 05:03:01 AM UTC 24 |
Sep 11 05:03:03 AM UTC 24 |
2155915349 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.2324763079 |
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Sep 11 05:03:02 AM UTC 24 |
Sep 11 05:03:05 AM UTC 24 |
2180695558 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3154637485 |
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Sep 11 05:02:55 AM UTC 24 |
Sep 11 05:03:07 AM UTC 24 |
3403671490 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3648491197 |
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Sep 11 05:02:54 AM UTC 24 |
Sep 11 05:03:08 AM UTC 24 |
2609483063 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3917286747 |
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|
Sep 11 05:02:55 AM UTC 24 |
Sep 11 05:03:09 AM UTC 24 |
2603945417 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3105832121 |
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Sep 11 05:03:04 AM UTC 24 |
Sep 11 05:03:10 AM UTC 24 |
3725327912 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.3709639229 |
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Sep 11 05:03:01 AM UTC 24 |
Sep 11 05:03:10 AM UTC 24 |
2456779191 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1269491288 |
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Sep 11 04:59:29 AM UTC 24 |
Sep 11 05:03:10 AM UTC 24 |
67311181465 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.2687525891 |
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|
Sep 11 05:03:00 AM UTC 24 |
Sep 11 05:03:12 AM UTC 24 |
2013313434 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2508813692 |
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|
Sep 11 05:02:48 AM UTC 24 |
Sep 11 05:03:12 AM UTC 24 |
12650919824 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1440852555 |
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Sep 11 05:03:06 AM UTC 24 |
Sep 11 05:03:12 AM UTC 24 |
11799558509 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.2558275261 |
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Sep 11 05:03:02 AM UTC 24 |
Sep 11 05:03:12 AM UTC 24 |
2514081840 ps |