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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.81 99.07 97.83 100.00 92.31 99.33 98.84 83.26


Total test records in report: 912
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T33 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2495049587 Sep 11 05:07:05 AM UTC 24 Sep 11 05:07:10 AM UTC 24 2119678874 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1018806942 Sep 11 05:07:09 AM UTC 24 Sep 11 05:07:13 AM UTC 24 2135810333 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1957865821 Sep 11 05:07:08 AM UTC 24 Sep 11 05:07:13 AM UTC 24 4059039315 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2556257600 Sep 11 05:07:04 AM UTC 24 Sep 11 05:07:15 AM UTC 24 2032128615 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2059132434 Sep 11 05:07:06 AM UTC 24 Sep 11 05:07:15 AM UTC 24 2091981983 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2686690420 Sep 11 05:07:01 AM UTC 24 Sep 11 05:07:15 AM UTC 24 4012648797 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.497335517 Sep 11 05:07:07 AM UTC 24 Sep 11 05:07:16 AM UTC 24 2012836832 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1519653038 Sep 11 05:07:13 AM UTC 24 Sep 11 05:07:17 AM UTC 24 2085448826 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2367459396 Sep 11 05:07:15 AM UTC 24 Sep 11 05:07:18 AM UTC 24 2034950186 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4044453341 Sep 11 05:07:11 AM UTC 24 Sep 11 05:07:18 AM UTC 24 3120673564 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1202193323 Sep 11 05:07:16 AM UTC 24 Sep 11 05:07:20 AM UTC 24 6243248435 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1559246313 Sep 11 05:07:16 AM UTC 24 Sep 11 05:07:21 AM UTC 24 2083592368 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2537059134 Sep 11 05:07:14 AM UTC 24 Sep 11 05:07:21 AM UTC 24 2216249547 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.377101775 Sep 11 05:07:17 AM UTC 24 Sep 11 05:07:22 AM UTC 24 2098971424 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2651712385 Sep 11 05:07:12 AM UTC 24 Sep 11 05:07:23 AM UTC 24 4749896854 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4133985793 Sep 11 05:07:20 AM UTC 24 Sep 11 05:07:23 AM UTC 24 4110516379 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3253008724 Sep 11 05:07:22 AM UTC 24 Sep 11 05:07:26 AM UTC 24 4751047481 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1450414108 Sep 11 05:07:20 AM UTC 24 Sep 11 05:07:27 AM UTC 24 2015657802 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.985231274 Sep 11 05:07:23 AM UTC 24 Sep 11 05:07:27 AM UTC 24 2080398549 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.4204318549 Sep 11 05:07:23 AM UTC 24 Sep 11 05:07:28 AM UTC 24 4075007397 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.945447604 Sep 11 05:07:17 AM UTC 24 Sep 11 05:07:28 AM UTC 24 2072399408 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2310132626 Sep 11 05:07:17 AM UTC 24 Sep 11 05:07:29 AM UTC 24 7410740827 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.210439908 Sep 11 05:07:23 AM UTC 24 Sep 11 05:07:30 AM UTC 24 2245998591 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2231670378 Sep 11 05:07:23 AM UTC 24 Sep 11 05:07:31 AM UTC 24 2111911997 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.4104962217 Sep 11 05:07:17 AM UTC 24 Sep 11 05:07:32 AM UTC 24 2870703359 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.808500449 Sep 11 05:07:21 AM UTC 24 Sep 11 05:07:32 AM UTC 24 2064652647 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.506386724 Sep 11 05:07:24 AM UTC 24 Sep 11 05:07:32 AM UTC 24 2060744022 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2877816204 Sep 11 05:07:30 AM UTC 24 Sep 11 05:07:33 AM UTC 24 2054236699 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.811396257 Sep 11 05:07:14 AM UTC 24 Sep 11 05:07:34 AM UTC 24 22502040567 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3199432124 Sep 11 05:07:22 AM UTC 24 Sep 11 05:07:34 AM UTC 24 2803718671 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1071104438 Sep 11 05:07:30 AM UTC 24 Sep 11 05:07:35 AM UTC 24 2053927724 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3862303462 Sep 11 05:07:28 AM UTC 24 Sep 11 05:07:36 AM UTC 24 2038770561 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1330983906 Sep 11 05:07:05 AM UTC 24 Sep 11 05:07:36 AM UTC 24 5124003012 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2007109485 Sep 11 05:07:31 AM UTC 24 Sep 11 05:07:36 AM UTC 24 5252072582 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.4143539030 Sep 11 05:07:33 AM UTC 24 Sep 11 05:07:37 AM UTC 24 2274787685 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2486346648 Sep 11 05:07:45 AM UTC 24 Sep 11 05:07:57 AM UTC 24 2012520361 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1854748248 Sep 11 05:07:33 AM UTC 24 Sep 11 05:07:37 AM UTC 24 2025286000 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.199389204 Sep 11 05:07:32 AM UTC 24 Sep 11 05:07:38 AM UTC 24 2255743779 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.4021817991 Sep 11 05:07:35 AM UTC 24 Sep 11 05:07:40 AM UTC 24 2191412470 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3505307147 Sep 11 05:07:29 AM UTC 24 Sep 11 05:07:40 AM UTC 24 2030023380 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1752284349 Sep 11 05:07:35 AM UTC 24 Sep 11 05:07:41 AM UTC 24 4713908135 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2278478482 Sep 11 05:07:35 AM UTC 24 Sep 11 05:07:41 AM UTC 24 2086038282 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3165667411 Sep 11 05:07:17 AM UTC 24 Sep 11 05:07:41 AM UTC 24 77411368198 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.1178874921 Sep 11 05:07:28 AM UTC 24 Sep 11 05:07:42 AM UTC 24 4434867551 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.59012312 Sep 11 05:07:28 AM UTC 24 Sep 11 05:07:42 AM UTC 24 2909440478 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1092362333 Sep 11 05:07:38 AM UTC 24 Sep 11 05:07:44 AM UTC 24 2051142291 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.1000213880 Sep 11 05:07:37 AM UTC 24 Sep 11 05:07:44 AM UTC 24 2070416976 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.191010611 Sep 11 05:07:06 AM UTC 24 Sep 11 05:07:44 AM UTC 24 22304669229 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.282435980 Sep 11 05:07:40 AM UTC 24 Sep 11 05:07:44 AM UTC 24 2022534232 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2014949145 Sep 11 05:07:37 AM UTC 24 Sep 11 05:07:45 AM UTC 24 2012798348 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1531253507 Sep 11 05:07:32 AM UTC 24 Sep 11 05:07:46 AM UTC 24 2065345212 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.39039097 Sep 11 05:07:43 AM UTC 24 Sep 11 05:07:46 AM UTC 24 2103837230 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3641514726 Sep 11 05:07:43 AM UTC 24 Sep 11 05:07:46 AM UTC 24 2044872110 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3920863504 Sep 11 05:07:41 AM UTC 24 Sep 11 05:07:47 AM UTC 24 2053924322 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.4187122384 Sep 11 05:07:38 AM UTC 24 Sep 11 05:07:47 AM UTC 24 2061807402 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1691141953 Sep 11 05:07:42 AM UTC 24 Sep 11 05:07:48 AM UTC 24 2251621792 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1814464724 Sep 11 05:07:44 AM UTC 24 Sep 11 05:07:48 AM UTC 24 2222403238 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2379589924 Sep 11 05:07:37 AM UTC 24 Sep 11 05:07:49 AM UTC 24 9674791089 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2652893382 Sep 11 05:07:45 AM UTC 24 Sep 11 05:07:49 AM UTC 24 2111306027 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1854094003 Sep 11 05:07:45 AM UTC 24 Sep 11 05:07:51 AM UTC 24 4414146403 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3595953665 Sep 11 05:07:46 AM UTC 24 Sep 11 05:07:52 AM UTC 24 2225378674 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2974419621 Sep 11 05:07:43 AM UTC 24 Sep 11 05:07:52 AM UTC 24 2039799418 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.285845786 Sep 11 05:07:40 AM UTC 24 Sep 11 05:07:53 AM UTC 24 2046014619 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.368186943 Sep 11 05:07:48 AM UTC 24 Sep 11 05:07:53 AM UTC 24 2033140325 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.231196299 Sep 11 05:07:18 AM UTC 24 Sep 11 05:07:53 AM UTC 24 42518181993 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2883006729 Sep 11 05:07:50 AM UTC 24 Sep 11 05:07:55 AM UTC 24 2030096653 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3903535917 Sep 11 05:07:49 AM UTC 24 Sep 11 05:07:56 AM UTC 24 2466867177 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.925520495 Sep 11 05:07:41 AM UTC 24 Sep 11 05:07:56 AM UTC 24 9592122203 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1539841812 Sep 11 05:07:48 AM UTC 24 Sep 11 05:07:56 AM UTC 24 2036765457 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.835886821 Sep 11 05:07:52 AM UTC 24 Sep 11 05:07:57 AM UTC 24 4798308262 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3612593144 Sep 11 05:07:53 AM UTC 24 Sep 11 05:07:57 AM UTC 24 2038382862 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1889634065 Sep 11 05:07:26 AM UTC 24 Sep 11 05:07:57 AM UTC 24 34453372461 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1641970998 Sep 11 05:07:45 AM UTC 24 Sep 11 05:07:58 AM UTC 24 2042197950 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.4206674875 Sep 11 05:07:50 AM UTC 24 Sep 11 05:07:59 AM UTC 24 2033432146 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3864761025 Sep 11 05:07:22 AM UTC 24 Sep 11 05:07:59 AM UTC 24 39681706671 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.794100011 Sep 11 05:07:57 AM UTC 24 Sep 11 05:07:59 AM UTC 24 2100882051 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3708922068 Sep 11 05:07:56 AM UTC 24 Sep 11 05:08:01 AM UTC 24 2076190900 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.49429630 Sep 11 05:07:53 AM UTC 24 Sep 11 05:08:01 AM UTC 24 2096656968 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.563413452 Sep 11 05:07:49 AM UTC 24 Sep 11 05:08:02 AM UTC 24 2075494231 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2369625196 Sep 11 05:07:58 AM UTC 24 Sep 11 05:08:03 AM UTC 24 2141762349 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2838762695 Sep 11 05:07:52 AM UTC 24 Sep 11 05:08:03 AM UTC 24 2061897673 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2968093002 Sep 11 05:07:55 AM UTC 24 Sep 11 05:08:04 AM UTC 24 2062753033 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2254612184 Sep 11 05:07:58 AM UTC 24 Sep 11 05:08:04 AM UTC 24 2066359127 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2972103941 Sep 11 05:08:00 AM UTC 24 Sep 11 05:08:04 AM UTC 24 2201308285 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3379339077 Sep 11 05:08:00 AM UTC 24 Sep 11 05:08:05 AM UTC 24 4140777300 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1463557103 Sep 11 05:07:57 AM UTC 24 Sep 11 05:08:05 AM UTC 24 2077832670 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2428826554 Sep 11 05:07:58 AM UTC 24 Sep 11 05:08:07 AM UTC 24 2040857148 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2727884892 Sep 11 05:08:02 AM UTC 24 Sep 11 05:08:07 AM UTC 24 2016799741 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2691213659 Sep 11 05:08:00 AM UTC 24 Sep 11 05:08:08 AM UTC 24 5644347912 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3352593555 Sep 11 05:08:04 AM UTC 24 Sep 11 05:08:08 AM UTC 24 2098686693 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3499070461 Sep 11 05:07:33 AM UTC 24 Sep 11 05:08:09 AM UTC 24 22329709554 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2756222122 Sep 11 05:08:04 AM UTC 24 Sep 11 05:08:09 AM UTC 24 2164541427 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1058899243 Sep 11 05:06:59 AM UTC 24 Sep 11 05:08:09 AM UTC 24 22210665911 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3030600992 Sep 11 05:08:05 AM UTC 24 Sep 11 05:08:09 AM UTC 24 2032163353 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2858672830 Sep 11 05:07:59 AM UTC 24 Sep 11 05:08:10 AM UTC 24 2009598191 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2730120037 Sep 11 05:07:59 AM UTC 24 Sep 11 05:08:10 AM UTC 24 2046766747 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2003379271 Sep 11 05:08:06 AM UTC 24 Sep 11 05:08:11 AM UTC 24 2076534896 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2421393584 Sep 11 05:08:09 AM UTC 24 Sep 11 05:08:11 AM UTC 24 2057032114 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2061041041 Sep 11 05:08:02 AM UTC 24 Sep 11 05:08:11 AM UTC 24 2052904240 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.301997273 Sep 11 05:07:43 AM UTC 24 Sep 11 05:08:12 AM UTC 24 9766783404 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3094133710 Sep 11 05:07:58 AM UTC 24 Sep 11 05:08:13 AM UTC 24 5327145086 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3579479660 Sep 11 05:08:06 AM UTC 24 Sep 11 05:08:13 AM UTC 24 4930322862 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.253968882 Sep 11 05:07:48 AM UTC 24 Sep 11 05:08:14 AM UTC 24 9925220265 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3110459420 Sep 11 05:08:10 AM UTC 24 Sep 11 05:08:14 AM UTC 24 2099080751 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2450307977 Sep 11 05:07:04 AM UTC 24 Sep 11 05:08:15 AM UTC 24 67911153445 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2009785298 Sep 11 05:08:11 AM UTC 24 Sep 11 05:08:15 AM UTC 24 2053501965 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.246060550 Sep 11 05:08:05 AM UTC 24 Sep 11 05:08:15 AM UTC 24 2028776671 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1477261547 Sep 11 05:08:11 AM UTC 24 Sep 11 05:08:15 AM UTC 24 2055631460 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2870686504 Sep 11 05:08:10 AM UTC 24 Sep 11 05:08:17 AM UTC 24 2078261587 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3483931084 Sep 11 05:08:13 AM UTC 24 Sep 11 05:08:17 AM UTC 24 2048411437 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2570425574 Sep 11 05:08:07 AM UTC 24 Sep 11 05:08:17 AM UTC 24 2094199553 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1959834477 Sep 11 05:08:10 AM UTC 24 Sep 11 05:08:18 AM UTC 24 2137335853 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1174925505 Sep 11 05:08:16 AM UTC 24 Sep 11 05:08:18 AM UTC 24 2066639559 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3030965060 Sep 11 05:08:16 AM UTC 24 Sep 11 05:08:18 AM UTC 24 2070025713 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1337211694 Sep 11 05:08:15 AM UTC 24 Sep 11 05:08:19 AM UTC 24 2050646995 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.867131096 Sep 11 05:08:12 AM UTC 24 Sep 11 05:08:19 AM UTC 24 2066521536 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3155411806 Sep 11 05:08:16 AM UTC 24 Sep 11 05:08:19 AM UTC 24 2040406829 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3985912018 Sep 11 05:07:56 AM UTC 24 Sep 11 05:08:20 AM UTC 24 9668797895 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3146820241 Sep 11 05:08:12 AM UTC 24 Sep 11 05:08:21 AM UTC 24 2013401432 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.639496953 Sep 11 05:08:17 AM UTC 24 Sep 11 05:08:21 AM UTC 24 2039637136 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1647235153 Sep 11 05:08:18 AM UTC 24 Sep 11 05:08:21 AM UTC 24 2038537802 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3852282427 Sep 11 05:08:13 AM UTC 24 Sep 11 05:08:21 AM UTC 24 2012285924 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3337156077 Sep 11 05:08:18 AM UTC 24 Sep 11 05:08:22 AM UTC 24 2055985493 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3470330817 Sep 11 05:08:19 AM UTC 24 Sep 11 05:08:23 AM UTC 24 2060047158 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.640185295 Sep 11 05:07:48 AM UTC 24 Sep 11 05:08:23 AM UTC 24 22230567262 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3554125686 Sep 11 05:08:16 AM UTC 24 Sep 11 05:08:23 AM UTC 24 2016147023 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2713438898 Sep 11 05:08:18 AM UTC 24 Sep 11 05:08:24 AM UTC 24 2023621380 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.89734263 Sep 11 05:08:19 AM UTC 24 Sep 11 05:08:25 AM UTC 24 2017012594 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1579543440 Sep 11 05:08:21 AM UTC 24 Sep 11 05:08:25 AM UTC 24 2032561947 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2186967542 Sep 11 05:08:22 AM UTC 24 Sep 11 05:08:25 AM UTC 24 2083346210 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1695023140 Sep 11 05:08:04 AM UTC 24 Sep 11 05:08:26 AM UTC 24 43146139314 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2421309301 Sep 11 05:07:53 AM UTC 24 Sep 11 05:08:26 AM UTC 24 22324122936 ps
T883 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2893607014 Sep 11 05:08:22 AM UTC 24 Sep 11 05:08:26 AM UTC 24 2039931434 ps
T884 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2367076355 Sep 11 05:08:23 AM UTC 24 Sep 11 05:08:27 AM UTC 24 2050207842 ps
T885 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1604432362 Sep 11 05:08:16 AM UTC 24 Sep 11 05:08:27 AM UTC 24 2012972224 ps
T886 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.244343979 Sep 11 05:08:23 AM UTC 24 Sep 11 05:08:28 AM UTC 24 2023631690 ps
T887 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1020732249 Sep 11 05:08:18 AM UTC 24 Sep 11 05:08:28 AM UTC 24 2010085969 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1077681751 Sep 11 05:08:21 AM UTC 24 Sep 11 05:08:28 AM UTC 24 2012720608 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2607998783 Sep 11 05:08:22 AM UTC 24 Sep 11 05:08:28 AM UTC 24 2018616380 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.4219846877 Sep 11 05:08:16 AM UTC 24 Sep 11 05:08:28 AM UTC 24 2012885730 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2922526729 Sep 11 05:08:21 AM UTC 24 Sep 11 05:08:28 AM UTC 24 2011994185 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2189691870 Sep 11 05:08:25 AM UTC 24 Sep 11 05:08:29 AM UTC 24 2036063389 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.4010851641 Sep 11 05:08:22 AM UTC 24 Sep 11 05:08:30 AM UTC 24 2014080829 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2394743812 Sep 11 05:08:25 AM UTC 24 Sep 11 05:08:31 AM UTC 24 2013450176 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1612885495 Sep 11 05:08:25 AM UTC 24 Sep 11 05:08:33 AM UTC 24 2013807881 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3320119701 Sep 11 05:08:22 AM UTC 24 Sep 11 05:08:33 AM UTC 24 2014818829 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1996380489 Sep 11 05:08:02 AM UTC 24 Sep 11 05:08:34 AM UTC 24 43077074447 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.4282459190 Sep 11 05:07:58 AM UTC 24 Sep 11 05:08:35 AM UTC 24 22221613213 ps
T899 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2615220022 Sep 11 05:08:10 AM UTC 24 Sep 11 05:08:35 AM UTC 24 7871660195 ps
T900 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.947414527 Sep 11 05:07:57 AM UTC 24 Sep 11 05:08:37 AM UTC 24 22219228646 ps
T901 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3292833127 Sep 11 05:08:07 AM UTC 24 Sep 11 05:08:41 AM UTC 24 22247852142 ps
T902 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.237177844 Sep 11 05:07:49 AM UTC 24 Sep 11 05:08:42 AM UTC 24 22245620680 ps
T903 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3769215761 Sep 11 05:08:03 AM UTC 24 Sep 11 05:08:43 AM UTC 24 10587011326 ps
T904 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2301031673 Sep 11 05:07:45 AM UTC 24 Sep 11 05:08:44 AM UTC 24 22160041094 ps
T905 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1274374729 Sep 11 05:08:12 AM UTC 24 Sep 11 05:08:48 AM UTC 24 9057600481 ps
T906 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2164894530 Sep 11 05:07:29 AM UTC 24 Sep 11 05:09:26 AM UTC 24 42389323124 ps
T907 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.4012447555 Sep 11 05:07:36 AM UTC 24 Sep 11 05:09:35 AM UTC 24 42391564425 ps
T908 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.587836298 Sep 11 05:07:09 AM UTC 24 Sep 11 05:09:38 AM UTC 24 39452136936 ps
T909 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2602533568 Sep 11 05:07:39 AM UTC 24 Sep 11 05:09:40 AM UTC 24 42390803931 ps
T910 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3665576247 Sep 11 05:07:23 AM UTC 24 Sep 11 05:09:50 AM UTC 24 42482580728 ps
T911 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3139603298 Sep 11 05:07:42 AM UTC 24 Sep 11 05:09:55 AM UTC 24 42419972536 ps
T912 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.56614117 Sep 11 05:08:11 AM UTC 24 Sep 11 05:10:30 AM UTC 24 42380645602 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2786818663
Short name T4
Test name
Test status
Simulation time 2554259805 ps
CPU time 1.66 seconds
Started Sep 11 04:57:43 AM UTC 24
Finished Sep 11 04:57:46 AM UTC 24
Peak memory 208184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786818663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.2786818663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1110028096
Short name T30
Test name
Test status
Simulation time 37206320768 ps
CPU time 27.62 seconds
Started Sep 11 04:58:09 AM UTC 24
Finished Sep 11 04:58:38 AM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110028096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.1110028096
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_feature_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3813791682
Short name T7
Test name
Test status
Simulation time 9302677289 ps
CPU time 7.62 seconds
Started Sep 11 04:57:51 AM UTC 24
Finished Sep 11 04:58:00 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813791682 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.3813791682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2603203008
Short name T58
Test name
Test status
Simulation time 63783153230 ps
CPU time 10.66 seconds
Started Sep 11 04:58:32 AM UTC 24
Finished Sep 11 04:58:44 AM UTC 24
Peak memory 226732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2603203008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.2603203008
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.252292424
Short name T24
Test name
Test status
Simulation time 35387319021 ps
CPU time 35.11 seconds
Started Sep 11 04:57:48 AM UTC 24
Finished Sep 11 04:58:25 AM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252292424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.252292424
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.623605765
Short name T37
Test name
Test status
Simulation time 113356598637 ps
CPU time 72.88 seconds
Started Sep 11 04:58:09 AM UTC 24
Finished Sep 11 04:59:23 AM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623605765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_with_pre_cond.623605765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.811396257
Short name T268
Test name
Test status
Simulation time 22502040567 ps
CPU time 18.7 seconds
Started Sep 11 05:07:14 AM UTC 24
Finished Sep 11 05:07:34 AM UTC 24
Peak memory 211152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811396257 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.811396257
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3053202456
Short name T229
Test name
Test status
Simulation time 127933046810 ps
CPU time 38.36 seconds
Started Sep 11 05:00:26 AM UTC 24
Finished Sep 11 05:01:07 AM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053202456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_with_pre_cond.3053202456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.308724556
Short name T370
Test name
Test status
Simulation time 109334552730 ps
CPU time 61.94 seconds
Started Sep 11 05:03:17 AM UTC 24
Finished Sep 11 05:04:21 AM UTC 24
Peak memory 210176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308724556 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.308724556
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.517956087
Short name T91
Test name
Test status
Simulation time 59507118606 ps
CPU time 43.12 seconds
Started Sep 11 04:58:52 AM UTC 24
Finished Sep 11 04:59:37 AM UTC 24
Peak memory 210176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517956087 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.517956087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1003023454
Short name T25
Test name
Test status
Simulation time 17496102402 ps
CPU time 7.56 seconds
Started Sep 11 04:57:51 AM UTC 24
Finished Sep 11 04:58:00 AM UTC 24
Peak memory 220468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1003023454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.1003023454
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2742431725
Short name T94
Test name
Test status
Simulation time 31959712891 ps
CPU time 19.61 seconds
Started Sep 11 04:59:37 AM UTC 24
Finished Sep 11 04:59:58 AM UTC 24
Peak memory 220912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2742431725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.2742431725
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.1767029174
Short name T39
Test name
Test status
Simulation time 121935051183 ps
CPU time 60.21 seconds
Started Sep 11 04:59:59 AM UTC 24
Finished Sep 11 05:01:00 AM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767029174 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.1767029174
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2877202892
Short name T47
Test name
Test status
Simulation time 3920211567 ps
CPU time 12.66 seconds
Started Sep 11 04:58:31 AM UTC 24
Finished Sep 11 04:58:45 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877202892 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.2877202892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4044453341
Short name T274
Test name
Test status
Simulation time 3120673564 ps
CPU time 6.75 seconds
Started Sep 11 05:07:11 AM UTC 24
Finished Sep 11 05:07:18 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044453341 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.4044453341
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.4152212342
Short name T322
Test name
Test status
Simulation time 165805601140 ps
CPU time 74.62 seconds
Started Sep 11 05:00:15 AM UTC 24
Finished Sep 11 05:01:32 AM UTC 24
Peak memory 210224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152212342 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.4152212342
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.1310407163
Short name T176
Test name
Test status
Simulation time 42022130347 ps
CPU time 56.04 seconds
Started Sep 11 04:57:53 AM UTC 24
Finished Sep 11 04:58:50 AM UTC 24
Peak memory 240272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310407163 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.1310407163
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2679177954
Short name T80
Test name
Test status
Simulation time 2528415338 ps
CPU time 4.14 seconds
Started Sep 11 04:58:15 AM UTC 24
Finished Sep 11 04:58:20 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679177954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.2679177954
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3119128973
Short name T231
Test name
Test status
Simulation time 59174542710 ps
CPU time 159.61 seconds
Started Sep 11 04:58:53 AM UTC 24
Finished Sep 11 05:01:36 AM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119128973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_with_pre_cond.3119128973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3465953286
Short name T61
Test name
Test status
Simulation time 3782750567 ps
CPU time 14.98 seconds
Started Sep 11 04:58:51 AM UTC 24
Finished Sep 11 04:59:07 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465953286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.3465953286
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.2725914734
Short name T138
Test name
Test status
Simulation time 127129186024 ps
CPU time 17.26 seconds
Started Sep 11 05:00:06 AM UTC 24
Finished Sep 11 05:00:24 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725914734 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.2725914734
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.4124322654
Short name T340
Test name
Test status
Simulation time 120505705194 ps
CPU time 80 seconds
Started Sep 11 05:02:16 AM UTC 24
Finished Sep 11 05:03:38 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124322654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_with_pre_cond.4124322654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2059132434
Short name T265
Test name
Test status
Simulation time 2091981983 ps
CPU time 8.23 seconds
Started Sep 11 05:07:06 AM UTC 24
Finished Sep 11 05:07:15 AM UTC 24
Peak memory 211276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059132434 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.2059132434
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1910095480
Short name T92
Test name
Test status
Simulation time 5352624706 ps
CPU time 7.65 seconds
Started Sep 11 04:59:35 AM UTC 24
Finished Sep 11 04:59:44 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910095480 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.1910095480
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.716391019
Short name T260
Test name
Test status
Simulation time 114369770184 ps
CPU time 81.07 seconds
Started Sep 11 05:01:28 AM UTC 24
Finished Sep 11 05:02:51 AM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716391019 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.716391019
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.637818074
Short name T44
Test name
Test status
Simulation time 9442283249 ps
CPU time 25.07 seconds
Started Sep 11 04:58:22 AM UTC 24
Finished Sep 11 04:58:48 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637818074 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.637818074
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.1293539049
Short name T241
Test name
Test status
Simulation time 2508831706 ps
CPU time 9.34 seconds
Started Sep 11 04:59:27 AM UTC 24
Finished Sep 11 04:59:37 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293539049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.1293539049
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.1826127800
Short name T369
Test name
Test status
Simulation time 15880044627 ps
CPU time 15.25 seconds
Started Sep 11 05:03:26 AM UTC 24
Finished Sep 11 05:03:43 AM UTC 24
Peak memory 209924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826127800 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.1826127800
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3997853273
Short name T106
Test name
Test status
Simulation time 157839095565 ps
CPU time 20.08 seconds
Started Sep 11 05:01:55 AM UTC 24
Finished Sep 11 05:02:16 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997853273 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.3997853273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.231196299
Short name T270
Test name
Test status
Simulation time 42518181993 ps
CPU time 33.31 seconds
Started Sep 11 05:07:18 AM UTC 24
Finished Sep 11 05:07:53 AM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231196299 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.231196299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.803987032
Short name T104
Test name
Test status
Simulation time 4132134262 ps
CPU time 5.32 seconds
Started Sep 11 05:04:41 AM UTC 24
Finished Sep 11 05:04:47 AM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803987032 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.803987032
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.279388407
Short name T327
Test name
Test status
Simulation time 151539179929 ps
CPU time 68.86 seconds
Started Sep 11 05:02:07 AM UTC 24
Finished Sep 11 05:03:18 AM UTC 24
Peak memory 210420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279388407 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.279388407
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3074178618
Short name T38
Test name
Test status
Simulation time 48208619044 ps
CPU time 131.3 seconds
Started Sep 11 04:58:31 AM UTC 24
Finished Sep 11 05:00:45 AM UTC 24
Peak memory 210100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074178618 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.3074178618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2881006862
Short name T286
Test name
Test status
Simulation time 2531956515 ps
CPU time 3.5 seconds
Started Sep 11 04:58:50 AM UTC 24
Finished Sep 11 04:58:54 AM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881006862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.2881006862
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.3158188485
Short name T17
Test name
Test status
Simulation time 2044479999 ps
CPU time 2.63 seconds
Started Sep 11 04:57:55 AM UTC 24
Finished Sep 11 04:57:58 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158188485 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.3158188485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2687250022
Short name T111
Test name
Test status
Simulation time 32511076114 ps
CPU time 48.85 seconds
Started Sep 11 04:59:51 AM UTC 24
Finished Sep 11 05:00:41 AM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687250022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_with_pre_cond.2687250022
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.252441735
Short name T237
Test name
Test status
Simulation time 70785682314 ps
CPU time 222.95 seconds
Started Sep 11 04:59:51 AM UTC 24
Finished Sep 11 05:03:37 AM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252441735 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.252441735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.1128955344
Short name T170
Test name
Test status
Simulation time 4481204365 ps
CPU time 16.94 seconds
Started Sep 11 05:02:39 AM UTC 24
Finished Sep 11 05:02:57 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128955344 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.1128955344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1330983906
Short name T22
Test name
Test status
Simulation time 5124003012 ps
CPU time 29.76 seconds
Started Sep 11 05:07:05 AM UTC 24
Finished Sep 11 05:07:36 AM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330983906 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.1330983906
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.413989170
Short name T324
Test name
Test status
Simulation time 85588410689 ps
CPU time 229.53 seconds
Started Sep 11 05:00:46 AM UTC 24
Finished Sep 11 05:04:39 AM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413989170 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.413989170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.1566733690
Short name T188
Test name
Test status
Simulation time 175783402445 ps
CPU time 119.58 seconds
Started Sep 11 05:00:27 AM UTC 24
Finished Sep 11 05:02:29 AM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566733690 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.1566733690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1870998956
Short name T5
Test name
Test status
Simulation time 2595728477 ps
CPU time 10.78 seconds
Started Sep 11 04:57:47 AM UTC 24
Finished Sep 11 04:57:59 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870998956 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.1870998956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3821763724
Short name T257
Test name
Test status
Simulation time 69636368459 ps
CPU time 167.17 seconds
Started Sep 11 04:59:42 AM UTC 24
Finished Sep 11 05:02:32 AM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821763724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_with_pre_cond.3821763724
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1643687651
Short name T338
Test name
Test status
Simulation time 79919379401 ps
CPU time 45.91 seconds
Started Sep 11 05:06:54 AM UTC 24
Finished Sep 11 05:07:42 AM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643687651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_with_pre_cond.1643687651
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.937670876
Short name T102
Test name
Test status
Simulation time 91753392301 ps
CPU time 242.62 seconds
Started Sep 11 05:00:06 AM UTC 24
Finished Sep 11 05:04:12 AM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937670876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_with_pre_cond.937670876
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.191010611
Short name T269
Test name
Test status
Simulation time 22304669229 ps
CPU time 36.71 seconds
Started Sep 11 05:07:06 AM UTC 24
Finished Sep 11 05:07:44 AM UTC 24
Peak memory 211276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191010611 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.191010611
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3469765855
Short name T410
Test name
Test status
Simulation time 8425001617 ps
CPU time 2.64 seconds
Started Sep 11 04:59:59 AM UTC 24
Finished Sep 11 05:00:02 AM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469765855 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.3469765855
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.1925148252
Short name T208
Test name
Test status
Simulation time 77859606216 ps
CPU time 112.55 seconds
Started Sep 11 05:02:57 AM UTC 24
Finished Sep 11 05:04:52 AM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925148252 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.1925148252
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.2110482641
Short name T108
Test name
Test status
Simulation time 9129000424 ps
CPU time 23.16 seconds
Started Sep 11 04:58:53 AM UTC 24
Finished Sep 11 04:59:18 AM UTC 24
Peak memory 210324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110482641 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.2110482641
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.193390536
Short name T259
Test name
Test status
Simulation time 81822725962 ps
CPU time 230.84 seconds
Started Sep 11 05:05:41 AM UTC 24
Finished Sep 11 05:09:35 AM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193390536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_with_pre_cond.193390536
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.24976456
Short name T255
Test name
Test status
Simulation time 94520174020 ps
CPU time 333.11 seconds
Started Sep 11 05:01:39 AM UTC 24
Finished Sep 11 05:07:16 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24976456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_with_pre_cond.24976456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1269491288
Short name T358
Test name
Test status
Simulation time 67311181465 ps
CPU time 218.35 seconds
Started Sep 11 04:59:29 AM UTC 24
Finished Sep 11 05:03:10 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269491288 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.1269491288
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1664974873
Short name T233
Test name
Test status
Simulation time 66079852906 ps
CPU time 55.04 seconds
Started Sep 11 05:01:28 AM UTC 24
Finished Sep 11 05:02:25 AM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664974873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_with_pre_cond.1664974873
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1257860278
Short name T328
Test name
Test status
Simulation time 45564304537 ps
CPU time 66.41 seconds
Started Sep 11 05:06:08 AM UTC 24
Finished Sep 11 05:07:16 AM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257860278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_with_pre_cond.1257860278
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.1881438890
Short name T155
Test name
Test status
Simulation time 17565513856 ps
CPU time 58.24 seconds
Started Sep 11 04:58:59 AM UTC 24
Finished Sep 11 04:59:59 AM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881438890 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.1881438890
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1814464724
Short name T817
Test name
Test status
Simulation time 2222403238 ps
CPU time 3.01 seconds
Started Sep 11 05:07:44 AM UTC 24
Finished Sep 11 05:07:48 AM UTC 24
Peak memory 211304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814464724 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.1814464724
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2467012302
Short name T26
Test name
Test status
Simulation time 2612591585 ps
CPU time 13.15 seconds
Started Sep 11 04:57:45 AM UTC 24
Finished Sep 11 04:57:59 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467012302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.2467012302
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.1627925891
Short name T114
Test name
Test status
Simulation time 171586739087 ps
CPU time 98.26 seconds
Started Sep 11 04:59:36 AM UTC 24
Finished Sep 11 05:01:16 AM UTC 24
Peak memory 210224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627925891 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.1627925891
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.4020062702
Short name T336
Test name
Test status
Simulation time 109222394142 ps
CPU time 158.14 seconds
Started Sep 11 04:59:41 AM UTC 24
Finished Sep 11 05:02:21 AM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020062702 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.4020062702
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.1203296119
Short name T326
Test name
Test status
Simulation time 118838905058 ps
CPU time 318.79 seconds
Started Sep 11 04:59:46 AM UTC 24
Finished Sep 11 05:05:09 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203296119 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.1203296119
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.49454487
Short name T228
Test name
Test status
Simulation time 46639841052 ps
CPU time 32.33 seconds
Started Sep 11 05:00:17 AM UTC 24
Finished Sep 11 05:00:50 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49454487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_with_pre_cond.49454487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.3484719322
Short name T41
Test name
Test status
Simulation time 112576559146 ps
CPU time 92.37 seconds
Started Sep 11 04:58:19 AM UTC 24
Finished Sep 11 04:59:53 AM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484719322 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.3484719322
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3845215783
Short name T113
Test name
Test status
Simulation time 57626889769 ps
CPU time 36.88 seconds
Started Sep 11 05:00:32 AM UTC 24
Finished Sep 11 05:01:11 AM UTC 24
Peak memory 210228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845215783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_with_pre_cond.3845215783
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.937595169
Short name T230
Test name
Test status
Simulation time 93225051040 ps
CPU time 32.51 seconds
Started Sep 11 05:01:02 AM UTC 24
Finished Sep 11 05:01:35 AM UTC 24
Peak memory 210236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937595169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_with_pre_cond.937595169
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.922576376
Short name T339
Test name
Test status
Simulation time 122788636039 ps
CPU time 367.08 seconds
Started Sep 11 05:02:08 AM UTC 24
Finished Sep 11 05:08:20 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922576376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_with_pre_cond.922576376
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1525678053
Short name T368
Test name
Test status
Simulation time 19012812630 ps
CPU time 19.18 seconds
Started Sep 11 05:04:00 AM UTC 24
Finished Sep 11 05:04:20 AM UTC 24
Peak memory 226744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1525678053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.1525678053
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1962589623
Short name T373
Test name
Test status
Simulation time 540539908169 ps
CPU time 46.04 seconds
Started Sep 11 05:04:53 AM UTC 24
Finished Sep 11 05:05:40 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962589623 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.1962589623
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3253757067
Short name T354
Test name
Test status
Simulation time 61167106378 ps
CPU time 71.61 seconds
Started Sep 11 05:05:25 AM UTC 24
Finished Sep 11 05:06:39 AM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253757067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_with_pre_cond.3253757067
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.308197936
Short name T355
Test name
Test status
Simulation time 30184180549 ps
CPU time 52.89 seconds
Started Sep 11 05:06:28 AM UTC 24
Finished Sep 11 05:07:23 AM UTC 24
Peak memory 210564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308197936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_with_pre_cond.308197936
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2936246180
Short name T348
Test name
Test status
Simulation time 186441918853 ps
CPU time 479.61 seconds
Started Sep 11 04:59:24 AM UTC 24
Finished Sep 11 05:07:29 AM UTC 24
Peak memory 212980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936246180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_with_pre_cond.2936246180
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2753646997
Short name T337
Test name
Test status
Simulation time 136168275244 ps
CPU time 211.69 seconds
Started Sep 11 05:06:46 AM UTC 24
Finished Sep 11 05:10:21 AM UTC 24
Peak memory 210228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753646997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_with_pre_cond.2753646997
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.687350353
Short name T367
Test name
Test status
Simulation time 25860515188 ps
CPU time 24.67 seconds
Started Sep 11 05:06:56 AM UTC 24
Finished Sep 11 05:07:22 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687350353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_with_pre_cond.687350353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.876297588
Short name T163
Test name
Test status
Simulation time 2424357166 ps
CPU time 2.63 seconds
Started Sep 11 04:59:41 AM UTC 24
Finished Sep 11 04:59:44 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876297588 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.876297588
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.2644216617
Short name T11
Test name
Test status
Simulation time 3420508322 ps
CPU time 9.55 seconds
Started Sep 11 04:58:21 AM UTC 24
Finished Sep 11 04:58:31 AM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644216617 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.2644216617
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2118374616
Short name T227
Test name
Test status
Simulation time 83353974701 ps
CPU time 85.3 seconds
Started Sep 11 05:05:54 AM UTC 24
Finished Sep 11 05:07:21 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118374616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_with_pre_cond.2118374616
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1772544586
Short name T32
Test name
Test status
Simulation time 2528795073 ps
CPU time 3.46 seconds
Started Sep 11 05:07:04 AM UTC 24
Finished Sep 11 05:07:08 AM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772544586 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.1772544586
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2450307977
Short name T857
Test name
Test status
Simulation time 67911153445 ps
CPU time 69.04 seconds
Started Sep 11 05:07:04 AM UTC 24
Finished Sep 11 05:08:15 AM UTC 24
Peak memory 211196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450307977 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.2450307977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2686690420
Short name T36
Test name
Test status
Simulation time 4012648797 ps
CPU time 13.81 seconds
Started Sep 11 05:07:01 AM UTC 24
Finished Sep 11 05:07:15 AM UTC 24
Peak memory 211132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686690420 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.2686690420
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2495049587
Short name T33
Test name
Test status
Simulation time 2119678874 ps
CPU time 4.36 seconds
Started Sep 11 05:07:05 AM UTC 24
Finished Sep 11 05:07:10 AM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2495049587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2495049587
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2556257600
Short name T317
Test name
Test status
Simulation time 2032128615 ps
CPU time 9.84 seconds
Started Sep 11 05:07:04 AM UTC 24
Finished Sep 11 05:07:15 AM UTC 24
Peak memory 210932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556257600 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.2556257600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3223311735
Short name T791
Test name
Test status
Simulation time 2030998289 ps
CPU time 2.45 seconds
Started Sep 11 05:07:01 AM UTC 24
Finished Sep 11 05:07:04 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223311735 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.3223311735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.785125044
Short name T278
Test name
Test status
Simulation time 2075819592 ps
CPU time 6.95 seconds
Started Sep 11 05:06:59 AM UTC 24
Finished Sep 11 05:07:07 AM UTC 24
Peak memory 211104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785125044 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.785125044
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1058899243
Short name T363
Test name
Test status
Simulation time 22210665911 ps
CPU time 68.27 seconds
Started Sep 11 05:06:59 AM UTC 24
Finished Sep 11 05:08:09 AM UTC 24
Peak memory 211300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058899243 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.1058899243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.587836298
Short name T908
Test name
Test status
Simulation time 39452136936 ps
CPU time 146.36 seconds
Started Sep 11 05:07:09 AM UTC 24
Finished Sep 11 05:09:38 AM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587836298 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.587836298
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1957865821
Short name T35
Test name
Test status
Simulation time 4059039315 ps
CPU time 3.67 seconds
Started Sep 11 05:07:08 AM UTC 24
Finished Sep 11 05:07:13 AM UTC 24
Peak memory 211064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957865821 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.1957865821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1519653038
Short name T277
Test name
Test status
Simulation time 2085448826 ps
CPU time 3.54 seconds
Started Sep 11 05:07:13 AM UTC 24
Finished Sep 11 05:07:17 AM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1519653038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_csr_mem_rw_with_rand_reset.1519653038
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1018806942
Short name T34
Test name
Test status
Simulation time 2135810333 ps
CPU time 2.32 seconds
Started Sep 11 05:07:09 AM UTC 24
Finished Sep 11 05:07:13 AM UTC 24
Peak memory 211068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018806942 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.1018806942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.497335517
Short name T792
Test name
Test status
Simulation time 2012836832 ps
CPU time 8.18 seconds
Started Sep 11 05:07:07 AM UTC 24
Finished Sep 11 05:07:16 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497335517 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.497335517
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2651712385
Short name T19
Test name
Test status
Simulation time 4749896854 ps
CPU time 9.94 seconds
Started Sep 11 05:07:12 AM UTC 24
Finished Sep 11 05:07:23 AM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651712385 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.2651712385
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1641970998
Short name T829
Test name
Test status
Simulation time 2042197950 ps
CPU time 10.92 seconds
Started Sep 11 05:07:45 AM UTC 24
Finished Sep 11 05:07:58 AM UTC 24
Peak memory 211004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1641970998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1641970998
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2652893382
Short name T312
Test name
Test status
Simulation time 2111306027 ps
CPU time 2.58 seconds
Started Sep 11 05:07:45 AM UTC 24
Finished Sep 11 05:07:49 AM UTC 24
Peak memory 211008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652893382 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.2652893382
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2486346648
Short name T802
Test name
Test status
Simulation time 2012520361 ps
CPU time 10.18 seconds
Started Sep 11 05:07:45 AM UTC 24
Finished Sep 11 05:07:57 AM UTC 24
Peak memory 210672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486346648 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.2486346648
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1854094003
Short name T819
Test name
Test status
Simulation time 4414146403 ps
CPU time 4.19 seconds
Started Sep 11 05:07:45 AM UTC 24
Finished Sep 11 05:07:51 AM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854094003 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.1854094003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2301031673
Short name T904
Test name
Test status
Simulation time 22160041094 ps
CPU time 56.91 seconds
Started Sep 11 05:07:45 AM UTC 24
Finished Sep 11 05:08:44 AM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301031673 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.2301031673
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.563413452
Short name T834
Test name
Test status
Simulation time 2075494231 ps
CPU time 11.78 seconds
Started Sep 11 05:07:49 AM UTC 24
Finished Sep 11 05:08:02 AM UTC 24
Peak memory 211136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=563413452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.sysrst_ctrl_csr_mem_rw_with_rand_reset.563413452
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1539841812
Short name T826
Test name
Test status
Simulation time 2036765457 ps
CPU time 7.26 seconds
Started Sep 11 05:07:48 AM UTC 24
Finished Sep 11 05:07:56 AM UTC 24
Peak memory 210932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539841812 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.1539841812
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.368186943
Short name T822
Test name
Test status
Simulation time 2033140325 ps
CPU time 4.06 seconds
Started Sep 11 05:07:48 AM UTC 24
Finished Sep 11 05:07:53 AM UTC 24
Peak memory 211064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368186943 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.368186943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.253968882
Short name T855
Test name
Test status
Simulation time 9925220265 ps
CPU time 25.15 seconds
Started Sep 11 05:07:48 AM UTC 24
Finished Sep 11 05:08:14 AM UTC 24
Peak memory 211248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253968882 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.253968882
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3595953665
Short name T820
Test name
Test status
Simulation time 2225378674 ps
CPU time 3.99 seconds
Started Sep 11 05:07:46 AM UTC 24
Finished Sep 11 05:07:52 AM UTC 24
Peak memory 211304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595953665 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.3595953665
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.640185295
Short name T362
Test name
Test status
Simulation time 22230567262 ps
CPU time 34.1 seconds
Started Sep 11 05:07:48 AM UTC 24
Finished Sep 11 05:08:23 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640185295 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.640185295
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2838762695
Short name T836
Test name
Test status
Simulation time 2061897673 ps
CPU time 10.17 seconds
Started Sep 11 05:07:52 AM UTC 24
Finished Sep 11 05:08:03 AM UTC 24
Peak memory 211080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2838762695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2838762695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.4206674875
Short name T316
Test name
Test status
Simulation time 2033432146 ps
CPU time 7.79 seconds
Started Sep 11 05:07:50 AM UTC 24
Finished Sep 11 05:07:59 AM UTC 24
Peak memory 211068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206674875 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.4206674875
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2883006729
Short name T823
Test name
Test status
Simulation time 2030096653 ps
CPU time 3.5 seconds
Started Sep 11 05:07:50 AM UTC 24
Finished Sep 11 05:07:55 AM UTC 24
Peak memory 210596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883006729 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.2883006729
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.835886821
Short name T827
Test name
Test status
Simulation time 4798308262 ps
CPU time 3.64 seconds
Started Sep 11 05:07:52 AM UTC 24
Finished Sep 11 05:07:57 AM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835886821 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.835886821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3903535917
Short name T824
Test name
Test status
Simulation time 2466867177 ps
CPU time 5.64 seconds
Started Sep 11 05:07:49 AM UTC 24
Finished Sep 11 05:07:56 AM UTC 24
Peak memory 221316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903535917 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.3903535917
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.237177844
Short name T902
Test name
Test status
Simulation time 22245620680 ps
CPU time 51.36 seconds
Started Sep 11 05:07:49 AM UTC 24
Finished Sep 11 05:08:42 AM UTC 24
Peak memory 211280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237177844 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.237177844
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3708922068
Short name T832
Test name
Test status
Simulation time 2076190900 ps
CPU time 3.93 seconds
Started Sep 11 05:07:56 AM UTC 24
Finished Sep 11 05:08:01 AM UTC 24
Peak memory 211008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3708922068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3708922068
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2968093002
Short name T837
Test name
Test status
Simulation time 2062753033 ps
CPU time 7.9 seconds
Started Sep 11 05:07:55 AM UTC 24
Finished Sep 11 05:08:04 AM UTC 24
Peak memory 211004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968093002 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.2968093002
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3612593144
Short name T828
Test name
Test status
Simulation time 2038382862 ps
CPU time 2.69 seconds
Started Sep 11 05:07:53 AM UTC 24
Finished Sep 11 05:07:57 AM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612593144 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.3612593144
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3985912018
Short name T870
Test name
Test status
Simulation time 9668797895 ps
CPU time 23.6 seconds
Started Sep 11 05:07:56 AM UTC 24
Finished Sep 11 05:08:20 AM UTC 24
Peak memory 211244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985912018 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.3985912018
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.49429630
Short name T833
Test name
Test status
Simulation time 2096656968 ps
CPU time 6.68 seconds
Started Sep 11 05:07:53 AM UTC 24
Finished Sep 11 05:08:01 AM UTC 24
Peak memory 211280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49429630 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.49429630
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2421309301
Short name T364
Test name
Test status
Simulation time 22324122936 ps
CPU time 31.63 seconds
Started Sep 11 05:07:53 AM UTC 24
Finished Sep 11 05:08:26 AM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421309301 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.2421309301
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2254612184
Short name T838
Test name
Test status
Simulation time 2066359127 ps
CPU time 4.73 seconds
Started Sep 11 05:07:58 AM UTC 24
Finished Sep 11 05:08:04 AM UTC 24
Peak memory 211008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2254612184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2254612184
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2428826554
Short name T314
Test name
Test status
Simulation time 2040857148 ps
CPU time 7.86 seconds
Started Sep 11 05:07:58 AM UTC 24
Finished Sep 11 05:08:07 AM UTC 24
Peak memory 211072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428826554 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.2428826554
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.794100011
Short name T831
Test name
Test status
Simulation time 2100882051 ps
CPU time 1.51 seconds
Started Sep 11 05:07:57 AM UTC 24
Finished Sep 11 05:07:59 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794100011 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.794100011
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3094133710
Short name T853
Test name
Test status
Simulation time 5327145086 ps
CPU time 13.55 seconds
Started Sep 11 05:07:58 AM UTC 24
Finished Sep 11 05:08:13 AM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094133710 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.3094133710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1463557103
Short name T841
Test name
Test status
Simulation time 2077832670 ps
CPU time 7.38 seconds
Started Sep 11 05:07:57 AM UTC 24
Finished Sep 11 05:08:05 AM UTC 24
Peak memory 211220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463557103 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.1463557103
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.947414527
Short name T900
Test name
Test status
Simulation time 22219228646 ps
CPU time 39.19 seconds
Started Sep 11 05:07:57 AM UTC 24
Finished Sep 11 05:08:37 AM UTC 24
Peak memory 211344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947414527 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.947414527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2972103941
Short name T839
Test name
Test status
Simulation time 2201308285 ps
CPU time 2.62 seconds
Started Sep 11 05:08:00 AM UTC 24
Finished Sep 11 05:08:04 AM UTC 24
Peak memory 211072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2972103941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2972103941
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2730120037
Short name T848
Test name
Test status
Simulation time 2046766747 ps
CPU time 9.41 seconds
Started Sep 11 05:07:59 AM UTC 24
Finished Sep 11 05:08:10 AM UTC 24
Peak memory 210932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730120037 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.2730120037
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2858672830
Short name T847
Test name
Test status
Simulation time 2009598191 ps
CPU time 9.43 seconds
Started Sep 11 05:07:59 AM UTC 24
Finished Sep 11 05:08:10 AM UTC 24
Peak memory 210672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858672830 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.2858672830
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2691213659
Short name T843
Test name
Test status
Simulation time 5644347912 ps
CPU time 6.56 seconds
Started Sep 11 05:08:00 AM UTC 24
Finished Sep 11 05:08:08 AM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691213659 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.2691213659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2369625196
Short name T835
Test name
Test status
Simulation time 2141762349 ps
CPU time 4.23 seconds
Started Sep 11 05:07:58 AM UTC 24
Finished Sep 11 05:08:03 AM UTC 24
Peak memory 211088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369625196 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.2369625196
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.4282459190
Short name T898
Test name
Test status
Simulation time 22221613213 ps
CPU time 35.31 seconds
Started Sep 11 05:07:58 AM UTC 24
Finished Sep 11 05:08:35 AM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282459190 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.4282459190
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3352593555
Short name T844
Test name
Test status
Simulation time 2098686693 ps
CPU time 3.55 seconds
Started Sep 11 05:08:04 AM UTC 24
Finished Sep 11 05:08:08 AM UTC 24
Peak memory 211004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3352593555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3352593555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2061041041
Short name T851
Test name
Test status
Simulation time 2052904240 ps
CPU time 8.69 seconds
Started Sep 11 05:08:02 AM UTC 24
Finished Sep 11 05:08:11 AM UTC 24
Peak memory 210936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061041041 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.2061041041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2727884892
Short name T842
Test name
Test status
Simulation time 2016799741 ps
CPU time 4.36 seconds
Started Sep 11 05:08:02 AM UTC 24
Finished Sep 11 05:08:07 AM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727884892 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.2727884892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3769215761
Short name T903
Test name
Test status
Simulation time 10587011326 ps
CPU time 38.66 seconds
Started Sep 11 05:08:03 AM UTC 24
Finished Sep 11 05:08:43 AM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769215761 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.3769215761
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3379339077
Short name T840
Test name
Test status
Simulation time 4140777300 ps
CPU time 3.44 seconds
Started Sep 11 05:08:00 AM UTC 24
Finished Sep 11 05:08:05 AM UTC 24
Peak memory 211192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379339077 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.3379339077
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1996380489
Short name T897
Test name
Test status
Simulation time 43077074447 ps
CPU time 30.64 seconds
Started Sep 11 05:08:02 AM UTC 24
Finished Sep 11 05:08:34 AM UTC 24
Peak memory 211276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996380489 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.1996380489
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2003379271
Short name T849
Test name
Test status
Simulation time 2076534896 ps
CPU time 3.41 seconds
Started Sep 11 05:08:06 AM UTC 24
Finished Sep 11 05:08:11 AM UTC 24
Peak memory 211008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2003379271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2003379271
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.246060550
Short name T859
Test name
Test status
Simulation time 2028776671 ps
CPU time 8.97 seconds
Started Sep 11 05:08:05 AM UTC 24
Finished Sep 11 05:08:15 AM UTC 24
Peak memory 210924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246060550 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.246060550
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3030600992
Short name T846
Test name
Test status
Simulation time 2032163353 ps
CPU time 3.21 seconds
Started Sep 11 05:08:05 AM UTC 24
Finished Sep 11 05:08:09 AM UTC 24
Peak memory 210812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030600992 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.3030600992
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3579479660
Short name T854
Test name
Test status
Simulation time 4930322862 ps
CPU time 5.92 seconds
Started Sep 11 05:08:06 AM UTC 24
Finished Sep 11 05:08:13 AM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579479660 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.3579479660
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2756222122
Short name T845
Test name
Test status
Simulation time 2164541427 ps
CPU time 4.18 seconds
Started Sep 11 05:08:04 AM UTC 24
Finished Sep 11 05:08:09 AM UTC 24
Peak memory 211280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756222122 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.2756222122
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1695023140
Short name T882
Test name
Test status
Simulation time 43146139314 ps
CPU time 21.01 seconds
Started Sep 11 05:08:04 AM UTC 24
Finished Sep 11 05:08:26 AM UTC 24
Peak memory 211220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695023140 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.1695023140
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2870686504
Short name T861
Test name
Test status
Simulation time 2078261587 ps
CPU time 5.82 seconds
Started Sep 11 05:08:10 AM UTC 24
Finished Sep 11 05:08:17 AM UTC 24
Peak memory 211080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2870686504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2870686504
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3110459420
Short name T856
Test name
Test status
Simulation time 2099080751 ps
CPU time 3.74 seconds
Started Sep 11 05:08:10 AM UTC 24
Finished Sep 11 05:08:14 AM UTC 24
Peak memory 211072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110459420 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.3110459420
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2421393584
Short name T850
Test name
Test status
Simulation time 2057032114 ps
CPU time 1.69 seconds
Started Sep 11 05:08:09 AM UTC 24
Finished Sep 11 05:08:11 AM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421393584 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.2421393584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2615220022
Short name T899
Test name
Test status
Simulation time 7871660195 ps
CPU time 23.76 seconds
Started Sep 11 05:08:10 AM UTC 24
Finished Sep 11 05:08:35 AM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615220022 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.2615220022
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2570425574
Short name T863
Test name
Test status
Simulation time 2094199553 ps
CPU time 8.49 seconds
Started Sep 11 05:08:07 AM UTC 24
Finished Sep 11 05:08:17 AM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570425574 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.2570425574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3292833127
Short name T901
Test name
Test status
Simulation time 22247852142 ps
CPU time 31.92 seconds
Started Sep 11 05:08:07 AM UTC 24
Finished Sep 11 05:08:41 AM UTC 24
Peak memory 211192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292833127 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.3292833127
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.867131096
Short name T868
Test name
Test status
Simulation time 2066521536 ps
CPU time 6 seconds
Started Sep 11 05:08:12 AM UTC 24
Finished Sep 11 05:08:19 AM UTC 24
Peak memory 211072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=867131096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.sysrst_ctrl_csr_mem_rw_with_rand_reset.867131096
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1477261547
Short name T860
Test name
Test status
Simulation time 2055631460 ps
CPU time 3.23 seconds
Started Sep 11 05:08:11 AM UTC 24
Finished Sep 11 05:08:15 AM UTC 24
Peak memory 211136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477261547 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.1477261547
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2009785298
Short name T858
Test name
Test status
Simulation time 2053501965 ps
CPU time 2.82 seconds
Started Sep 11 05:08:11 AM UTC 24
Finished Sep 11 05:08:15 AM UTC 24
Peak memory 210596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009785298 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.2009785298
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1274374729
Short name T905
Test name
Test status
Simulation time 9057600481 ps
CPU time 34.35 seconds
Started Sep 11 05:08:12 AM UTC 24
Finished Sep 11 05:08:48 AM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274374729 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.1274374729
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1959834477
Short name T864
Test name
Test status
Simulation time 2137335853 ps
CPU time 6.69 seconds
Started Sep 11 05:08:10 AM UTC 24
Finished Sep 11 05:08:18 AM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959834477 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.1959834477
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.56614117
Short name T912
Test name
Test status
Simulation time 42380645602 ps
CPU time 136.75 seconds
Started Sep 11 05:08:11 AM UTC 24
Finished Sep 11 05:10:30 AM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56614117 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.56614117
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.4104962217
Short name T307
Test name
Test status
Simulation time 2870703359 ps
CPU time 13.16 seconds
Started Sep 11 05:07:17 AM UTC 24
Finished Sep 11 05:07:32 AM UTC 24
Peak memory 211144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104962217 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.4104962217
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3165667411
Short name T366
Test name
Test status
Simulation time 77411368198 ps
CPU time 22.54 seconds
Started Sep 11 05:07:17 AM UTC 24
Finished Sep 11 05:07:41 AM UTC 24
Peak memory 211276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165667411 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.3165667411
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1202193323
Short name T275
Test name
Test status
Simulation time 6243248435 ps
CPU time 3.16 seconds
Started Sep 11 05:07:16 AM UTC 24
Finished Sep 11 05:07:20 AM UTC 24
Peak memory 211060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202193323 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.1202193323
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.377101775
Short name T281
Test name
Test status
Simulation time 2098971424 ps
CPU time 3.81 seconds
Started Sep 11 05:07:17 AM UTC 24
Finished Sep 11 05:07:22 AM UTC 24
Peak memory 211008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=377101775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
sysrst_ctrl_csr_mem_rw_with_rand_reset.377101775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1559246313
Short name T276
Test name
Test status
Simulation time 2083592368 ps
CPU time 3.54 seconds
Started Sep 11 05:07:16 AM UTC 24
Finished Sep 11 05:07:21 AM UTC 24
Peak memory 211004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559246313 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.1559246313
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2367459396
Short name T793
Test name
Test status
Simulation time 2034950186 ps
CPU time 2.35 seconds
Started Sep 11 05:07:15 AM UTC 24
Finished Sep 11 05:07:18 AM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367459396 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.2367459396
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2310132626
Short name T21
Test name
Test status
Simulation time 7410740827 ps
CPU time 10.93 seconds
Started Sep 11 05:07:17 AM UTC 24
Finished Sep 11 05:07:29 AM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310132626 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.2310132626
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2537059134
Short name T266
Test name
Test status
Simulation time 2216249547 ps
CPU time 5.81 seconds
Started Sep 11 05:07:14 AM UTC 24
Finished Sep 11 05:07:21 AM UTC 24
Peak memory 211248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537059134 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.2537059134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3146820241
Short name T871
Test name
Test status
Simulation time 2013401432 ps
CPU time 7.92 seconds
Started Sep 11 05:08:12 AM UTC 24
Finished Sep 11 05:08:21 AM UTC 24
Peak memory 210680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146820241 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.3146820241
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3483931084
Short name T862
Test name
Test status
Simulation time 2048411437 ps
CPU time 2.39 seconds
Started Sep 11 05:08:13 AM UTC 24
Finished Sep 11 05:08:17 AM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483931084 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.3483931084
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3852282427
Short name T874
Test name
Test status
Simulation time 2012285924 ps
CPU time 7.01 seconds
Started Sep 11 05:08:13 AM UTC 24
Finished Sep 11 05:08:21 AM UTC 24
Peak memory 210928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852282427 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.3852282427
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1337211694
Short name T867
Test name
Test status
Simulation time 2050646995 ps
CPU time 3.33 seconds
Started Sep 11 05:08:15 AM UTC 24
Finished Sep 11 05:08:19 AM UTC 24
Peak memory 210596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337211694 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.1337211694
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.4219846877
Short name T890
Test name
Test status
Simulation time 2012885730 ps
CPU time 11.24 seconds
Started Sep 11 05:08:16 AM UTC 24
Finished Sep 11 05:08:28 AM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219846877 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.4219846877
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1174925505
Short name T865
Test name
Test status
Simulation time 2066639559 ps
CPU time 1.06 seconds
Started Sep 11 05:08:16 AM UTC 24
Finished Sep 11 05:08:18 AM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174925505 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.1174925505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3155411806
Short name T869
Test name
Test status
Simulation time 2040406829 ps
CPU time 2.6 seconds
Started Sep 11 05:08:16 AM UTC 24
Finished Sep 11 05:08:19 AM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155411806 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.3155411806
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3030965060
Short name T866
Test name
Test status
Simulation time 2070025713 ps
CPU time 1.57 seconds
Started Sep 11 05:08:16 AM UTC 24
Finished Sep 11 05:08:18 AM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030965060 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.3030965060
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3554125686
Short name T877
Test name
Test status
Simulation time 2016147023 ps
CPU time 6.14 seconds
Started Sep 11 05:08:16 AM UTC 24
Finished Sep 11 05:08:23 AM UTC 24
Peak memory 210592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554125686 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.3554125686
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1604432362
Short name T885
Test name
Test status
Simulation time 2012972224 ps
CPU time 10.39 seconds
Started Sep 11 05:08:16 AM UTC 24
Finished Sep 11 05:08:27 AM UTC 24
Peak memory 210848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604432362 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.1604432362
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3199432124
Short name T309
Test name
Test status
Simulation time 2803718671 ps
CPU time 10.93 seconds
Started Sep 11 05:07:22 AM UTC 24
Finished Sep 11 05:07:34 AM UTC 24
Peak memory 211308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199432124 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.3199432124
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3864761025
Short name T830
Test name
Test status
Simulation time 39681706671 ps
CPU time 36.09 seconds
Started Sep 11 05:07:22 AM UTC 24
Finished Sep 11 05:07:59 AM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864761025 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.3864761025
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4133985793
Short name T320
Test name
Test status
Simulation time 4110516379 ps
CPU time 2.46 seconds
Started Sep 11 05:07:20 AM UTC 24
Finished Sep 11 05:07:23 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133985793 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.4133985793
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2231670378
Short name T797
Test name
Test status
Simulation time 2111911997 ps
CPU time 7.12 seconds
Started Sep 11 05:07:23 AM UTC 24
Finished Sep 11 05:07:31 AM UTC 24
Peak memory 211004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2231670378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2231670378
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.808500449
Short name T318
Test name
Test status
Simulation time 2064652647 ps
CPU time 9.91 seconds
Started Sep 11 05:07:21 AM UTC 24
Finished Sep 11 05:07:32 AM UTC 24
Peak memory 211008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808500449 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.808500449
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1450414108
Short name T794
Test name
Test status
Simulation time 2015657802 ps
CPU time 5.86 seconds
Started Sep 11 05:07:20 AM UTC 24
Finished Sep 11 05:07:27 AM UTC 24
Peak memory 210816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450414108 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.1450414108
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3253008724
Short name T20
Test name
Test status
Simulation time 4751047481 ps
CPU time 3.52 seconds
Started Sep 11 05:07:22 AM UTC 24
Finished Sep 11 05:07:26 AM UTC 24
Peak memory 211136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253008724 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.3253008724
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.945447604
Short name T267
Test name
Test status
Simulation time 2072399408 ps
CPU time 9.81 seconds
Started Sep 11 05:07:17 AM UTC 24
Finished Sep 11 05:07:28 AM UTC 24
Peak memory 211280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945447604 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.945447604
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.639496953
Short name T872
Test name
Test status
Simulation time 2039637136 ps
CPU time 3.23 seconds
Started Sep 11 05:08:17 AM UTC 24
Finished Sep 11 05:08:21 AM UTC 24
Peak memory 210600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639496953 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.639496953
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1647235153
Short name T873
Test name
Test status
Simulation time 2038537802 ps
CPU time 2.09 seconds
Started Sep 11 05:08:18 AM UTC 24
Finished Sep 11 05:08:21 AM UTC 24
Peak memory 210672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647235153 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.1647235153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2713438898
Short name T878
Test name
Test status
Simulation time 2023621380 ps
CPU time 4.79 seconds
Started Sep 11 05:08:18 AM UTC 24
Finished Sep 11 05:08:24 AM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713438898 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.2713438898
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1020732249
Short name T887
Test name
Test status
Simulation time 2010085969 ps
CPU time 8.32 seconds
Started Sep 11 05:08:18 AM UTC 24
Finished Sep 11 05:08:28 AM UTC 24
Peak memory 210672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020732249 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.1020732249
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3337156077
Short name T875
Test name
Test status
Simulation time 2055985493 ps
CPU time 2.72 seconds
Started Sep 11 05:08:18 AM UTC 24
Finished Sep 11 05:08:22 AM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337156077 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.3337156077
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3470330817
Short name T876
Test name
Test status
Simulation time 2060047158 ps
CPU time 2.04 seconds
Started Sep 11 05:08:19 AM UTC 24
Finished Sep 11 05:08:23 AM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470330817 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.3470330817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.89734263
Short name T879
Test name
Test status
Simulation time 2017012594 ps
CPU time 4.1 seconds
Started Sep 11 05:08:19 AM UTC 24
Finished Sep 11 05:08:25 AM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89734263 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.89734263
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1579543440
Short name T880
Test name
Test status
Simulation time 2032561947 ps
CPU time 3.09 seconds
Started Sep 11 05:08:21 AM UTC 24
Finished Sep 11 05:08:25 AM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579543440 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.1579543440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1077681751
Short name T888
Test name
Test status
Simulation time 2012720608 ps
CPU time 5.97 seconds
Started Sep 11 05:08:21 AM UTC 24
Finished Sep 11 05:08:28 AM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077681751 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.1077681751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2922526729
Short name T891
Test name
Test status
Simulation time 2011994185 ps
CPU time 6.48 seconds
Started Sep 11 05:08:21 AM UTC 24
Finished Sep 11 05:08:28 AM UTC 24
Peak memory 210544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922526729 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.2922526729
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.59012312
Short name T310
Test name
Test status
Simulation time 2909440478 ps
CPU time 12.93 seconds
Started Sep 11 05:07:28 AM UTC 24
Finished Sep 11 05:07:42 AM UTC 24
Peak memory 211248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59012312 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.59012312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1889634065
Short name T313
Test name
Test status
Simulation time 34453372461 ps
CPU time 29.16 seconds
Started Sep 11 05:07:26 AM UTC 24
Finished Sep 11 05:07:57 AM UTC 24
Peak memory 211320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889634065 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.1889634065
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.4204318549
Short name T796
Test name
Test status
Simulation time 4075007397 ps
CPU time 3.74 seconds
Started Sep 11 05:07:23 AM UTC 24
Finished Sep 11 05:07:28 AM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204318549 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.4204318549
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3862303462
Short name T799
Test name
Test status
Simulation time 2038770561 ps
CPU time 6.89 seconds
Started Sep 11 05:07:28 AM UTC 24
Finished Sep 11 05:07:36 AM UTC 24
Peak memory 211084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3862303462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_csr_mem_rw_with_rand_reset.3862303462
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.506386724
Short name T308
Test name
Test status
Simulation time 2060744022 ps
CPU time 6.95 seconds
Started Sep 11 05:07:24 AM UTC 24
Finished Sep 11 05:07:32 AM UTC 24
Peak memory 211004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506386724 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.506386724
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.985231274
Short name T795
Test name
Test status
Simulation time 2080398549 ps
CPU time 2.37 seconds
Started Sep 11 05:07:23 AM UTC 24
Finished Sep 11 05:07:27 AM UTC 24
Peak memory 210824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985231274 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.985231274
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.1178874921
Short name T807
Test name
Test status
Simulation time 4434867551 ps
CPU time 12.74 seconds
Started Sep 11 05:07:28 AM UTC 24
Finished Sep 11 05:07:42 AM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178874921 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.1178874921
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.210439908
Short name T279
Test name
Test status
Simulation time 2245998591 ps
CPU time 5.96 seconds
Started Sep 11 05:07:23 AM UTC 24
Finished Sep 11 05:07:30 AM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210439908 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.210439908
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3665576247
Short name T910
Test name
Test status
Simulation time 42482580728 ps
CPU time 143.91 seconds
Started Sep 11 05:07:23 AM UTC 24
Finished Sep 11 05:09:50 AM UTC 24
Peak memory 211204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665576247 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.3665576247
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2186967542
Short name T881
Test name
Test status
Simulation time 2083346210 ps
CPU time 1.84 seconds
Started Sep 11 05:08:22 AM UTC 24
Finished Sep 11 05:08:25 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186967542 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.2186967542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2607998783
Short name T889
Test name
Test status
Simulation time 2018616380 ps
CPU time 4.88 seconds
Started Sep 11 05:08:22 AM UTC 24
Finished Sep 11 05:08:28 AM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607998783 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.2607998783
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3320119701
Short name T896
Test name
Test status
Simulation time 2014818829 ps
CPU time 9.6 seconds
Started Sep 11 05:08:22 AM UTC 24
Finished Sep 11 05:08:33 AM UTC 24
Peak memory 210644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320119701 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.3320119701
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.4010851641
Short name T893
Test name
Test status
Simulation time 2014080829 ps
CPU time 6.63 seconds
Started Sep 11 05:08:22 AM UTC 24
Finished Sep 11 05:08:30 AM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010851641 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.4010851641
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2893607014
Short name T883
Test name
Test status
Simulation time 2039931434 ps
CPU time 3.14 seconds
Started Sep 11 05:08:22 AM UTC 24
Finished Sep 11 05:08:26 AM UTC 24
Peak memory 210596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893607014 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.2893607014
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.244343979
Short name T886
Test name
Test status
Simulation time 2023631690 ps
CPU time 3.29 seconds
Started Sep 11 05:08:23 AM UTC 24
Finished Sep 11 05:08:28 AM UTC 24
Peak memory 210596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244343979 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.244343979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2367076355
Short name T884
Test name
Test status
Simulation time 2050207842 ps
CPU time 2.3 seconds
Started Sep 11 05:08:23 AM UTC 24
Finished Sep 11 05:08:27 AM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367076355 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.2367076355
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1612885495
Short name T895
Test name
Test status
Simulation time 2013807881 ps
CPU time 7.19 seconds
Started Sep 11 05:08:25 AM UTC 24
Finished Sep 11 05:08:33 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612885495 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.1612885495
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2189691870
Short name T892
Test name
Test status
Simulation time 2036063389 ps
CPU time 2.95 seconds
Started Sep 11 05:08:25 AM UTC 24
Finished Sep 11 05:08:29 AM UTC 24
Peak memory 211000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189691870 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.2189691870
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2394743812
Short name T894
Test name
Test status
Simulation time 2013450176 ps
CPU time 5.25 seconds
Started Sep 11 05:08:25 AM UTC 24
Finished Sep 11 05:08:31 AM UTC 24
Peak memory 210920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394743812 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.2394743812
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1531253507
Short name T811
Test name
Test status
Simulation time 2065345212 ps
CPU time 11.75 seconds
Started Sep 11 05:07:32 AM UTC 24
Finished Sep 11 05:07:46 AM UTC 24
Peak memory 211188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1531253507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_csr_mem_rw_with_rand_reset.1531253507
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1071104438
Short name T319
Test name
Test status
Simulation time 2053927724 ps
CPU time 3.51 seconds
Started Sep 11 05:07:30 AM UTC 24
Finished Sep 11 05:07:35 AM UTC 24
Peak memory 210932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071104438 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.1071104438
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2877816204
Short name T798
Test name
Test status
Simulation time 2054236699 ps
CPU time 2.19 seconds
Started Sep 11 05:07:30 AM UTC 24
Finished Sep 11 05:07:33 AM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877816204 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.2877816204
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2007109485
Short name T800
Test name
Test status
Simulation time 5252072582 ps
CPU time 3.18 seconds
Started Sep 11 05:07:31 AM UTC 24
Finished Sep 11 05:07:36 AM UTC 24
Peak memory 211172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007109485 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.2007109485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3505307147
Short name T804
Test name
Test status
Simulation time 2030023380 ps
CPU time 9.99 seconds
Started Sep 11 05:07:29 AM UTC 24
Finished Sep 11 05:07:40 AM UTC 24
Peak memory 211140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505307147 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.3505307147
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2164894530
Short name T906
Test name
Test status
Simulation time 42389323124 ps
CPU time 115.32 seconds
Started Sep 11 05:07:29 AM UTC 24
Finished Sep 11 05:09:26 AM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164894530 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.2164894530
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.4021817991
Short name T365
Test name
Test status
Simulation time 2191412470 ps
CPU time 4.02 seconds
Started Sep 11 05:07:35 AM UTC 24
Finished Sep 11 05:07:40 AM UTC 24
Peak memory 211068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4021817991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_csr_mem_rw_with_rand_reset.4021817991
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.4143539030
Short name T801
Test name
Test status
Simulation time 2274787685 ps
CPU time 1.5 seconds
Started Sep 11 05:07:33 AM UTC 24
Finished Sep 11 05:07:37 AM UTC 24
Peak memory 209668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143539030 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.4143539030
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1854748248
Short name T803
Test name
Test status
Simulation time 2025286000 ps
CPU time 2.27 seconds
Started Sep 11 05:07:33 AM UTC 24
Finished Sep 11 05:07:37 AM UTC 24
Peak memory 210600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854748248 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.1854748248
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1752284349
Short name T805
Test name
Test status
Simulation time 4713908135 ps
CPU time 4.95 seconds
Started Sep 11 05:07:35 AM UTC 24
Finished Sep 11 05:07:41 AM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752284349 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.1752284349
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.199389204
Short name T280
Test name
Test status
Simulation time 2255743779 ps
CPU time 4.19 seconds
Started Sep 11 05:07:32 AM UTC 24
Finished Sep 11 05:07:38 AM UTC 24
Peak memory 211200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199389204 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.199389204
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3499070461
Short name T361
Test name
Test status
Simulation time 22329709554 ps
CPU time 33.72 seconds
Started Sep 11 05:07:33 AM UTC 24
Finished Sep 11 05:08:09 AM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499070461 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.3499070461
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1092362333
Short name T808
Test name
Test status
Simulation time 2051142291 ps
CPU time 5 seconds
Started Sep 11 05:07:38 AM UTC 24
Finished Sep 11 05:07:44 AM UTC 24
Peak memory 210692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1092362333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_csr_mem_rw_with_rand_reset.1092362333
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.1000213880
Short name T311
Test name
Test status
Simulation time 2070416976 ps
CPU time 6.06 seconds
Started Sep 11 05:07:37 AM UTC 24
Finished Sep 11 05:07:44 AM UTC 24
Peak memory 211004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000213880 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.1000213880
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2014949145
Short name T810
Test name
Test status
Simulation time 2012798348 ps
CPU time 6.66 seconds
Started Sep 11 05:07:37 AM UTC 24
Finished Sep 11 05:07:45 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014949145 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.2014949145
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2379589924
Short name T818
Test name
Test status
Simulation time 9674791089 ps
CPU time 11.11 seconds
Started Sep 11 05:07:37 AM UTC 24
Finished Sep 11 05:07:49 AM UTC 24
Peak memory 211264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379589924 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.2379589924
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2278478482
Short name T806
Test name
Test status
Simulation time 2086038282 ps
CPU time 5.16 seconds
Started Sep 11 05:07:35 AM UTC 24
Finished Sep 11 05:07:41 AM UTC 24
Peak memory 211156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278478482 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.2278478482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.4012447555
Short name T907
Test name
Test status
Simulation time 42391564425 ps
CPU time 116.96 seconds
Started Sep 11 05:07:36 AM UTC 24
Finished Sep 11 05:09:35 AM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012447555 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.4012447555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3920863504
Short name T814
Test name
Test status
Simulation time 2053924322 ps
CPU time 3.94 seconds
Started Sep 11 05:07:41 AM UTC 24
Finished Sep 11 05:07:47 AM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3920863504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_csr_mem_rw_with_rand_reset.3920863504
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.285845786
Short name T315
Test name
Test status
Simulation time 2046014619 ps
CPU time 11.19 seconds
Started Sep 11 05:07:40 AM UTC 24
Finished Sep 11 05:07:53 AM UTC 24
Peak memory 211008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285845786 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.285845786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.282435980
Short name T809
Test name
Test status
Simulation time 2022534232 ps
CPU time 3.09 seconds
Started Sep 11 05:07:40 AM UTC 24
Finished Sep 11 05:07:44 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282435980 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.282435980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.925520495
Short name T825
Test name
Test status
Simulation time 9592122203 ps
CPU time 13.17 seconds
Started Sep 11 05:07:41 AM UTC 24
Finished Sep 11 05:07:56 AM UTC 24
Peak memory 211084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925520495 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.925520495
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.4187122384
Short name T815
Test name
Test status
Simulation time 2061807402 ps
CPU time 8.27 seconds
Started Sep 11 05:07:38 AM UTC 24
Finished Sep 11 05:07:47 AM UTC 24
Peak memory 211036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187122384 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.4187122384
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2602533568
Short name T909
Test name
Test status
Simulation time 42390803931 ps
CPU time 118.25 seconds
Started Sep 11 05:07:39 AM UTC 24
Finished Sep 11 05:09:40 AM UTC 24
Peak memory 211320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602533568 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.2602533568
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2974419621
Short name T821
Test name
Test status
Simulation time 2039799418 ps
CPU time 7.94 seconds
Started Sep 11 05:07:43 AM UTC 24
Finished Sep 11 05:07:52 AM UTC 24
Peak memory 211084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2974419621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2974419621
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.39039097
Short name T812
Test name
Test status
Simulation time 2103837230 ps
CPU time 2.4 seconds
Started Sep 11 05:07:43 AM UTC 24
Finished Sep 11 05:07:46 AM UTC 24
Peak memory 211080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39039097 -assert nopostproc +UVM_TESTNAME=sy
srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.39039097
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3641514726
Short name T813
Test name
Test status
Simulation time 2044872110 ps
CPU time 2.55 seconds
Started Sep 11 05:07:43 AM UTC 24
Finished Sep 11 05:07:46 AM UTC 24
Peak memory 210600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641514726 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.3641514726
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.301997273
Short name T852
Test name
Test status
Simulation time 9766783404 ps
CPU time 28.15 seconds
Started Sep 11 05:07:43 AM UTC 24
Finished Sep 11 05:08:12 AM UTC 24
Peak memory 211244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301997273 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.301997273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1691141953
Short name T816
Test name
Test status
Simulation time 2251621792 ps
CPU time 5.28 seconds
Started Sep 11 05:07:42 AM UTC 24
Finished Sep 11 05:07:48 AM UTC 24
Peak memory 210600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691141953 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.1691141953
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3139603298
Short name T911
Test name
Test status
Simulation time 42419972536 ps
CPU time 131.08 seconds
Started Sep 11 05:07:42 AM UTC 24
Finished Sep 11 05:09:55 AM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139603298 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.3139603298
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.4157163160
Short name T16
Test name
Test status
Simulation time 3352087255 ps
CPU time 9.81 seconds
Started Sep 11 04:57:46 AM UTC 24
Finished Sep 11 04:57:57 AM UTC 24
Peak memory 210324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157163160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.4157163160
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1169873179
Short name T154
Test name
Test status
Simulation time 49044717439 ps
CPU time 129.26 seconds
Started Sep 11 04:57:47 AM UTC 24
Finished Sep 11 04:59:59 AM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169873179 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.1169873179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2489974867
Short name T2
Test name
Test status
Simulation time 2427780010 ps
CPU time 4.69 seconds
Started Sep 11 04:57:41 AM UTC 24
Finished Sep 11 04:57:46 AM UTC 24
Peak memory 209896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489974867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2489974867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2451645094
Short name T1
Test name
Test status
Simulation time 2544818672 ps
CPU time 3.29 seconds
Started Sep 11 04:57:41 AM UTC 24
Finished Sep 11 04:57:45 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451645094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2451645094
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.4247524903
Short name T31
Test name
Test status
Simulation time 66199806642 ps
CPU time 48.12 seconds
Started Sep 11 04:57:48 AM UTC 24
Finished Sep 11 04:58:38 AM UTC 24
Peak memory 210560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247524903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_with_pre_cond.4247524903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.312989667
Short name T14
Test name
Test status
Simulation time 3808951392 ps
CPU time 4.26 seconds
Started Sep 11 04:57:46 AM UTC 24
Finished Sep 11 04:57:52 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312989667 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.312989667
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.2381385183
Short name T15
Test name
Test status
Simulation time 2461854169 ps
CPU time 13.95 seconds
Started Sep 11 04:57:39 AM UTC 24
Finished Sep 11 04:57:54 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381385183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.2381385183
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.4226894673
Short name T12
Test name
Test status
Simulation time 2253509053 ps
CPU time 2.96 seconds
Started Sep 11 04:57:43 AM UTC 24
Finished Sep 11 04:57:47 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226894673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.4226894673
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.2355617661
Short name T13
Test name
Test status
Simulation time 2114316133 ps
CPU time 7.96 seconds
Started Sep 11 04:57:39 AM UTC 24
Finished Sep 11 04:57:48 AM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355617661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2355617661
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3523536135
Short name T3
Test name
Test status
Simulation time 8773504902 ps
CPU time 8.19 seconds
Started Sep 11 04:57:46 AM UTC 24
Finished Sep 11 04:57:56 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523536135 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.3523536135
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.3569012289
Short name T110
Test name
Test status
Simulation time 2032284963 ps
CPU time 3.67 seconds
Started Sep 11 04:58:10 AM UTC 24
Finished Sep 11 04:58:15 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569012289 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.3569012289
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1061701128
Short name T27
Test name
Test status
Simulation time 3552968671 ps
CPU time 5.77 seconds
Started Sep 11 04:58:01 AM UTC 24
Finished Sep 11 04:58:08 AM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061701128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.1061701128
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.471796798
Short name T236
Test name
Test status
Simulation time 97206835851 ps
CPU time 292.33 seconds
Started Sep 11 04:58:03 AM UTC 24
Finished Sep 11 05:03:00 AM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471796798 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.471796798
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2511416595
Short name T53
Test name
Test status
Simulation time 2160726694 ps
CPU time 10.73 seconds
Started Sep 11 04:57:58 AM UTC 24
Finished Sep 11 04:58:10 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511416595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2511416595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4055146716
Short name T8
Test name
Test status
Simulation time 2592842449 ps
CPU time 2.13 seconds
Started Sep 11 04:57:58 AM UTC 24
Finished Sep 11 04:58:01 AM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055146716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4055146716
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3612089799
Short name T69
Test name
Test status
Simulation time 3638638097 ps
CPU time 10.63 seconds
Started Sep 11 04:58:01 AM UTC 24
Finished Sep 11 04:58:13 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612089799 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.3612089799
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.602925808
Short name T10
Test name
Test status
Simulation time 6004004740 ps
CPU time 21.19 seconds
Started Sep 11 04:58:06 AM UTC 24
Finished Sep 11 04:58:29 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602925808 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.602925808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3451980052
Short name T77
Test name
Test status
Simulation time 2608504110 ps
CPU time 6.83 seconds
Started Sep 11 04:58:00 AM UTC 24
Finished Sep 11 04:58:08 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451980052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.3451980052
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.1418327075
Short name T71
Test name
Test status
Simulation time 2460722795 ps
CPU time 11.39 seconds
Started Sep 11 04:57:57 AM UTC 24
Finished Sep 11 04:58:09 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418327075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.1418327075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.4233079836
Short name T62
Test name
Test status
Simulation time 2101391175 ps
CPU time 2.81 seconds
Started Sep 11 04:57:59 AM UTC 24
Finished Sep 11 04:58:03 AM UTC 24
Peak memory 209804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233079836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.4233079836
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.709313606
Short name T78
Test name
Test status
Simulation time 2515339447 ps
CPU time 6.95 seconds
Started Sep 11 04:58:00 AM UTC 24
Finished Sep 11 04:58:08 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709313606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.709313606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.1009360112
Short name T285
Test name
Test status
Simulation time 42009614020 ps
CPU time 132.21 seconds
Started Sep 11 04:58:09 AM UTC 24
Finished Sep 11 05:00:23 AM UTC 24
Peak memory 240336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009360112 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.1009360112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.41455712
Short name T63
Test name
Test status
Simulation time 2114562671 ps
CPU time 7.85 seconds
Started Sep 11 04:57:57 AM UTC 24
Finished Sep 11 04:58:06 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41455712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.41455712
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.2988331099
Short name T735
Test name
Test status
Simulation time 147909336072 ps
CPU time 407.22 seconds
Started Sep 11 04:58:09 AM UTC 24
Finished Sep 11 05:05:01 AM UTC 24
Peak memory 212816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988331099 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.2988331099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2833003555
Short name T9
Test name
Test status
Simulation time 7027355622 ps
CPU time 7.33 seconds
Started Sep 11 04:58:09 AM UTC 24
Finished Sep 11 04:58:17 AM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2833003555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.2833003555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3129007705
Short name T6
Test name
Test status
Simulation time 17281115578 ps
CPU time 4.28 seconds
Started Sep 11 04:58:02 AM UTC 24
Finished Sep 11 04:58:08 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129007705 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.3129007705
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.2906838329
Short name T377
Test name
Test status
Simulation time 2013581957 ps
CPU time 5.33 seconds
Started Sep 11 04:59:30 AM UTC 24
Finished Sep 11 04:59:37 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906838329 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.2906838329
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.4020815531
Short name T411
Test name
Test status
Simulation time 18596441544 ps
CPU time 32.52 seconds
Started Sep 11 04:59:29 AM UTC 24
Finished Sep 11 05:00:03 AM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020815531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.4020815531
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.119460728
Short name T88
Test name
Test status
Simulation time 26587545497 ps
CPU time 36.71 seconds
Started Sep 11 04:59:29 AM UTC 24
Finished Sep 11 05:00:07 AM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119460728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_with_pre_cond.119460728
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3898765951
Short name T166
Test name
Test status
Simulation time 4264599901 ps
CPU time 17.39 seconds
Started Sep 11 04:59:28 AM UTC 24
Finished Sep 11 04:59:46 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898765951 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.3898765951
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.1851484528
Short name T48
Test name
Test status
Simulation time 3296424724 ps
CPU time 10.25 seconds
Started Sep 11 04:59:29 AM UTC 24
Finished Sep 11 04:59:40 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851484528 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.1851484528
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3676148914
Short name T142
Test name
Test status
Simulation time 2789346176 ps
CPU time 1.54 seconds
Started Sep 11 04:59:27 AM UTC 24
Finished Sep 11 04:59:29 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676148914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.3676148914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.777795024
Short name T395
Test name
Test status
Simulation time 2482457777 ps
CPU time 10.33 seconds
Started Sep 11 04:59:25 AM UTC 24
Finished Sep 11 04:59:37 AM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777795024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.777795024
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.2462415020
Short name T148
Test name
Test status
Simulation time 2207747558 ps
CPU time 6.44 seconds
Started Sep 11 04:59:27 AM UTC 24
Finished Sep 11 04:59:34 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462415020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.2462415020
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.2036968168
Short name T141
Test name
Test status
Simulation time 2139615231 ps
CPU time 2.17 seconds
Started Sep 11 04:59:25 AM UTC 24
Finished Sep 11 04:59:29 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036968168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.2036968168
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.92183814
Short name T131
Test name
Test status
Simulation time 14196839474 ps
CPU time 6.32 seconds
Started Sep 11 04:59:29 AM UTC 24
Finished Sep 11 04:59:37 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92183814 -assert nopostproc +UVM_TESTNA
ME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.92183814
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2245917501
Short name T239
Test name
Test status
Simulation time 2860405413 ps
CPU time 4.64 seconds
Started Sep 11 04:59:29 AM UTC 24
Finished Sep 11 04:59:35 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2245917501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.2245917501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1544105030
Short name T220
Test name
Test status
Simulation time 2025297622 ps
CPU time 2.36 seconds
Started Sep 11 04:59:37 AM UTC 24
Finished Sep 11 04:59:41 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544105030 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.1544105030
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3002955011
Short name T133
Test name
Test status
Simulation time 3756469675 ps
CPU time 7.67 seconds
Started Sep 11 04:59:33 AM UTC 24
Finished Sep 11 04:59:41 AM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002955011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.3002955011
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.4241750903
Short name T43
Test name
Test status
Simulation time 51226965703 ps
CPU time 73.73 seconds
Started Sep 11 04:59:36 AM UTC 24
Finished Sep 11 05:00:51 AM UTC 24
Peak memory 210560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241750903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_with_pre_cond.4241750903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.1339479745
Short name T46
Test name
Test status
Simulation time 2769268791 ps
CPU time 3.4 seconds
Started Sep 11 04:59:36 AM UTC 24
Finished Sep 11 04:59:40 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339479745 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.1339479745
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2189938701
Short name T224
Test name
Test status
Simulation time 2611034904 ps
CPU time 9.62 seconds
Started Sep 11 04:59:32 AM UTC 24
Finished Sep 11 04:59:42 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189938701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.2189938701
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.3579331670
Short name T240
Test name
Test status
Simulation time 2466969757 ps
CPU time 3.57 seconds
Started Sep 11 04:59:30 AM UTC 24
Finished Sep 11 04:59:35 AM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579331670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3579331670
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.3480269921
Short name T396
Test name
Test status
Simulation time 2029261700 ps
CPU time 7.24 seconds
Started Sep 11 04:59:31 AM UTC 24
Finished Sep 11 04:59:40 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480269921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.3480269921
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.3675843473
Short name T225
Test name
Test status
Simulation time 2510423261 ps
CPU time 9.95 seconds
Started Sep 11 04:59:31 AM UTC 24
Finished Sep 11 04:59:42 AM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675843473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.3675843473
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.3321574694
Short name T379
Test name
Test status
Simulation time 2117003368 ps
CPU time 5.94 seconds
Started Sep 11 04:59:30 AM UTC 24
Finished Sep 11 04:59:37 AM UTC 24
Peak memory 209808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321574694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.3321574694
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2806597710
Short name T168
Test name
Test status
Simulation time 11418160067 ps
CPU time 9.44 seconds
Started Sep 11 04:59:37 AM UTC 24
Finished Sep 11 04:59:48 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806597710 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.2806597710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1704364522
Short name T400
Test name
Test status
Simulation time 2016291294 ps
CPU time 6.32 seconds
Started Sep 11 04:59:42 AM UTC 24
Finished Sep 11 04:59:49 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704364522 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.1704364522
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2631797262
Short name T134
Test name
Test status
Simulation time 3727552450 ps
CPU time 7.61 seconds
Started Sep 11 04:59:41 AM UTC 24
Finished Sep 11 04:59:49 AM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631797262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.2631797262
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2215864513
Short name T399
Test name
Test status
Simulation time 3079719263 ps
CPU time 7.25 seconds
Started Sep 11 04:59:41 AM UTC 24
Finished Sep 11 04:59:49 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215864513 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.2215864513
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2436488679
Short name T398
Test name
Test status
Simulation time 2608437043 ps
CPU time 8.76 seconds
Started Sep 11 04:59:38 AM UTC 24
Finished Sep 11 04:59:48 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436488679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.2436488679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.3126064741
Short name T221
Test name
Test status
Simulation time 2477678354 ps
CPU time 2.37 seconds
Started Sep 11 04:59:37 AM UTC 24
Finished Sep 11 04:59:41 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126064741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.3126064741
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.786885445
Short name T222
Test name
Test status
Simulation time 2264447079 ps
CPU time 2.34 seconds
Started Sep 11 04:59:37 AM UTC 24
Finished Sep 11 04:59:41 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786885445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.786885445
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.2680804577
Short name T165
Test name
Test status
Simulation time 2510185684 ps
CPU time 6.78 seconds
Started Sep 11 04:59:38 AM UTC 24
Finished Sep 11 04:59:46 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680804577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.2680804577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.2869304918
Short name T397
Test name
Test status
Simulation time 2129972768 ps
CPU time 2.13 seconds
Started Sep 11 04:59:37 AM UTC 24
Finished Sep 11 04:59:40 AM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869304918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.2869304918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.2432518159
Short name T127
Test name
Test status
Simulation time 12556427992 ps
CPU time 14.02 seconds
Started Sep 11 04:59:42 AM UTC 24
Finished Sep 11 04:59:57 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432518159 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.2432518159
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.538611484
Short name T152
Test name
Test status
Simulation time 4369967847 ps
CPU time 14.97 seconds
Started Sep 11 04:59:42 AM UTC 24
Finished Sep 11 04:59:58 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=538611484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.538611484
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4201638844
Short name T136
Test name
Test status
Simulation time 8547637704 ps
CPU time 2.36 seconds
Started Sep 11 04:59:41 AM UTC 24
Finished Sep 11 04:59:44 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201638844 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.4201638844
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.2806267740
Short name T404
Test name
Test status
Simulation time 2035862559 ps
CPU time 3 seconds
Started Sep 11 04:59:47 AM UTC 24
Finished Sep 11 04:59:51 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806267740 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.2806267740
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.829748819
Short name T432
Test name
Test status
Simulation time 45203034907 ps
CPU time 34 seconds
Started Sep 11 04:59:45 AM UTC 24
Finished Sep 11 05:00:20 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829748819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.829748819
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2554622516
Short name T342
Test name
Test status
Simulation time 180599352301 ps
CPU time 236.55 seconds
Started Sep 11 04:59:46 AM UTC 24
Finished Sep 11 05:03:46 AM UTC 24
Peak memory 210176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554622516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_with_pre_cond.2554622516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3971601279
Short name T403
Test name
Test status
Simulation time 4705437219 ps
CPU time 5.12 seconds
Started Sep 11 04:59:45 AM UTC 24
Finished Sep 11 04:59:51 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971601279 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.3971601279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.1958226069
Short name T153
Test name
Test status
Simulation time 4240896913 ps
CPU time 11.19 seconds
Started Sep 11 04:59:46 AM UTC 24
Finished Sep 11 04:59:58 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958226069 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.1958226069
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3565170346
Short name T401
Test name
Test status
Simulation time 2629558753 ps
CPU time 4.08 seconds
Started Sep 11 04:59:44 AM UTC 24
Finished Sep 11 04:59:50 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565170346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.3565170346
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.1085922344
Short name T167
Test name
Test status
Simulation time 2497083160 ps
CPU time 3.38 seconds
Started Sep 11 04:59:42 AM UTC 24
Finished Sep 11 04:59:47 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085922344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.1085922344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.1090013124
Short name T402
Test name
Test status
Simulation time 2089719425 ps
CPU time 5.36 seconds
Started Sep 11 04:59:43 AM UTC 24
Finished Sep 11 04:59:50 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090013124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.1090013124
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.3959091704
Short name T169
Test name
Test status
Simulation time 2523987031 ps
CPU time 3.85 seconds
Started Sep 11 04:59:43 AM UTC 24
Finished Sep 11 04:59:48 AM UTC 24
Peak memory 210016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959091704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.3959091704
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.1014359833
Short name T164
Test name
Test status
Simulation time 2132569118 ps
CPU time 2.06 seconds
Started Sep 11 04:59:42 AM UTC 24
Finished Sep 11 04:59:45 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014359833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.1014359833
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2139073616
Short name T123
Test name
Test status
Simulation time 6282073185 ps
CPU time 7.15 seconds
Started Sep 11 04:59:47 AM UTC 24
Finished Sep 11 04:59:55 AM UTC 24
Peak memory 209928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139073616 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.2139073616
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.249293978
Short name T300
Test name
Test status
Simulation time 4839896518 ps
CPU time 18.04 seconds
Started Sep 11 04:59:46 AM UTC 24
Finished Sep 11 05:00:05 AM UTC 24
Peak memory 220784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=249293978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.249293978
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1890935942
Short name T95
Test name
Test status
Simulation time 347828847592 ps
CPU time 11.28 seconds
Started Sep 11 04:59:46 AM UTC 24
Finished Sep 11 04:59:58 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890935942 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.1890935942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.44274389
Short name T122
Test name
Test status
Simulation time 2038937345 ps
CPU time 2.24 seconds
Started Sep 11 04:59:52 AM UTC 24
Finished Sep 11 04:59:55 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44274389 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.44274389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.14581188
Short name T157
Test name
Test status
Simulation time 3100781879 ps
CPU time 7.85 seconds
Started Sep 11 04:59:51 AM UTC 24
Finished Sep 11 04:59:59 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14581188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.14581188
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.657875904
Short name T124
Test name
Test status
Simulation time 4415741051 ps
CPU time 4.13 seconds
Started Sep 11 04:59:51 AM UTC 24
Finished Sep 11 04:59:56 AM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657875904 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.657875904
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1191893410
Short name T156
Test name
Test status
Simulation time 2612177767 ps
CPU time 8.83 seconds
Started Sep 11 04:59:49 AM UTC 24
Finished Sep 11 04:59:59 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191893410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1191893410
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.3000813928
Short name T294
Test name
Test status
Simulation time 2486679356 ps
CPU time 2.56 seconds
Started Sep 11 04:59:48 AM UTC 24
Finished Sep 11 04:59:52 AM UTC 24
Peak memory 210104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000813928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.3000813928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.1847047466
Short name T406
Test name
Test status
Simulation time 2121420317 ps
CPU time 8.43 seconds
Started Sep 11 04:59:48 AM UTC 24
Finished Sep 11 04:59:58 AM UTC 24
Peak memory 209948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847047466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.1847047466
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.2710007748
Short name T125
Test name
Test status
Simulation time 2509512453 ps
CPU time 5.97 seconds
Started Sep 11 04:59:49 AM UTC 24
Finished Sep 11 04:59:56 AM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710007748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.2710007748
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.1928437741
Short name T405
Test name
Test status
Simulation time 2127517668 ps
CPU time 3.25 seconds
Started Sep 11 04:59:47 AM UTC 24
Finished Sep 11 04:59:51 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928437741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.1928437741
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.897003434
Short name T292
Test name
Test status
Simulation time 13732403760 ps
CPU time 28.53 seconds
Started Sep 11 04:59:52 AM UTC 24
Finished Sep 11 05:00:22 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897003434 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.897003434
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.404255518
Short name T290
Test name
Test status
Simulation time 19205721893 ps
CPU time 16.91 seconds
Started Sep 11 04:59:52 AM UTC 24
Finished Sep 11 05:00:10 AM UTC 24
Peak memory 220716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=404255518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.404255518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1056934578
Short name T407
Test name
Test status
Simulation time 2096435148 ps
CPU time 1.48 seconds
Started Sep 11 04:59:59 AM UTC 24
Finished Sep 11 05:00:01 AM UTC 24
Peak memory 208236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056934578 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.1056934578
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.833421565
Short name T158
Test name
Test status
Simulation time 3257415527 ps
CPU time 1.71 seconds
Started Sep 11 04:59:57 AM UTC 24
Finished Sep 11 05:00:00 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833421565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.833421565
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3132732852
Short name T126
Test name
Test status
Simulation time 4159447559 ps
CPU time 13.33 seconds
Started Sep 11 04:59:56 AM UTC 24
Finished Sep 11 05:00:11 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132732852 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.3132732852
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.225800656
Short name T198
Test name
Test status
Simulation time 3006909387 ps
CPU time 6.87 seconds
Started Sep 11 04:59:59 AM UTC 24
Finished Sep 11 05:00:07 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225800656 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.225800656
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1926353490
Short name T159
Test name
Test status
Simulation time 2613261291 ps
CPU time 3.97 seconds
Started Sep 11 04:59:56 AM UTC 24
Finished Sep 11 05:00:01 AM UTC 24
Peak memory 209924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926353490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.1926353490
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.3056574877
Short name T129
Test name
Test status
Simulation time 2482326884 ps
CPU time 2.5 seconds
Started Sep 11 04:59:54 AM UTC 24
Finished Sep 11 04:59:58 AM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056574877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.3056574877
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3765627068
Short name T409
Test name
Test status
Simulation time 2043524776 ps
CPU time 5.46 seconds
Started Sep 11 04:59:55 AM UTC 24
Finished Sep 11 05:00:02 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765627068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3765627068
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2425520990
Short name T415
Test name
Test status
Simulation time 2509193782 ps
CPU time 8.53 seconds
Started Sep 11 04:59:56 AM UTC 24
Finished Sep 11 05:00:06 AM UTC 24
Peak memory 209736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425520990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2425520990
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.1927827749
Short name T408
Test name
Test status
Simulation time 2110773986 ps
CPU time 7.41 seconds
Started Sep 11 04:59:53 AM UTC 24
Finished Sep 11 05:00:02 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927827749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.1927827749
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1325522029
Short name T289
Test name
Test status
Simulation time 2308236182 ps
CPU time 7.38 seconds
Started Sep 11 04:59:59 AM UTC 24
Finished Sep 11 05:00:07 AM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1325522029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.1325522029
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2156033769
Short name T296
Test name
Test status
Simulation time 4945331154 ps
CPU time 2.18 seconds
Started Sep 11 04:59:59 AM UTC 24
Finished Sep 11 05:00:02 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156033769 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.2156033769
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.1892355231
Short name T416
Test name
Test status
Simulation time 2037954196 ps
CPU time 3.04 seconds
Started Sep 11 05:00:06 AM UTC 24
Finished Sep 11 05:00:10 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892355231 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.1892355231
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1534729203
Short name T428
Test name
Test status
Simulation time 3436158672 ps
CPU time 13.27 seconds
Started Sep 11 05:00:01 AM UTC 24
Finished Sep 11 05:00:19 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534729203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.1534729203
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.4102911310
Short name T115
Test name
Test status
Simulation time 99454137557 ps
CPU time 77.81 seconds
Started Sep 11 05:00:02 AM UTC 24
Finished Sep 11 05:01:24 AM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102911310 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.4102911310
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1164471676
Short name T429
Test name
Test status
Simulation time 4178644646 ps
CPU time 14.14 seconds
Started Sep 11 05:00:00 AM UTC 24
Finished Sep 11 05:00:19 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164471676 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.1164471676
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.1386954670
Short name T179
Test name
Test status
Simulation time 3695230680 ps
CPU time 1.06 seconds
Started Sep 11 05:00:06 AM UTC 24
Finished Sep 11 05:00:08 AM UTC 24
Peak memory 208236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386954670 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.1386954670
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3589572235
Short name T423
Test name
Test status
Simulation time 2614516133 ps
CPU time 10.01 seconds
Started Sep 11 05:00:00 AM UTC 24
Finished Sep 11 05:00:15 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589572235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3589572235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.3761552439
Short name T414
Test name
Test status
Simulation time 2472335743 ps
CPU time 3.31 seconds
Started Sep 11 05:00:00 AM UTC 24
Finished Sep 11 05:00:04 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761552439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.3761552439
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.1408790370
Short name T413
Test name
Test status
Simulation time 2071185980 ps
CPU time 2.49 seconds
Started Sep 11 05:00:00 AM UTC 24
Finished Sep 11 05:00:03 AM UTC 24
Peak memory 209792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408790370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.1408790370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2418331110
Short name T419
Test name
Test status
Simulation time 2512781433 ps
CPU time 7.79 seconds
Started Sep 11 05:00:00 AM UTC 24
Finished Sep 11 05:00:13 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418331110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.2418331110
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.2283653766
Short name T412
Test name
Test status
Simulation time 2118085358 ps
CPU time 3.31 seconds
Started Sep 11 04:59:59 AM UTC 24
Finished Sep 11 05:00:03 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283653766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.2283653766
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.854422258
Short name T438
Test name
Test status
Simulation time 5227953396 ps
CPU time 16.52 seconds
Started Sep 11 05:00:06 AM UTC 24
Finished Sep 11 05:00:23 AM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=854422258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.854422258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2373510072
Short name T137
Test name
Test status
Simulation time 3225888656 ps
CPU time 9.72 seconds
Started Sep 11 05:00:02 AM UTC 24
Finished Sep 11 05:00:16 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373510072 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.2373510072
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.3957753256
Short name T435
Test name
Test status
Simulation time 2011622235 ps
CPU time 9.54 seconds
Started Sep 11 05:00:12 AM UTC 24
Finished Sep 11 05:00:22 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957753256 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.3957753256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1662400496
Short name T420
Test name
Test status
Simulation time 3766396366 ps
CPU time 3.37 seconds
Started Sep 11 05:00:08 AM UTC 24
Finished Sep 11 05:00:13 AM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662400496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1662400496
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.3343957744
Short name T261
Test name
Test status
Simulation time 63709727959 ps
CPU time 186.74 seconds
Started Sep 11 05:00:08 AM UTC 24
Finished Sep 11 05:03:18 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343957744 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.3343957744
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1964109142
Short name T258
Test name
Test status
Simulation time 48533164682 ps
CPU time 140.54 seconds
Started Sep 11 05:00:11 AM UTC 24
Finished Sep 11 05:02:33 AM UTC 24
Peak memory 209956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964109142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_with_pre_cond.1964109142
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.4127134048
Short name T417
Test name
Test status
Simulation time 3929333139 ps
CPU time 3.05 seconds
Started Sep 11 05:00:07 AM UTC 24
Finished Sep 11 05:00:11 AM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127134048 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.4127134048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.4202084545
Short name T196
Test name
Test status
Simulation time 4604217509 ps
CPU time 3.95 seconds
Started Sep 11 05:00:11 AM UTC 24
Finished Sep 11 05:00:15 AM UTC 24
Peak memory 209980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202084545 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.4202084545
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.663943539
Short name T418
Test name
Test status
Simulation time 2632823016 ps
CPU time 3.06 seconds
Started Sep 11 05:00:07 AM UTC 24
Finished Sep 11 05:00:11 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663943539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.663943539
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.105272800
Short name T421
Test name
Test status
Simulation time 2487602757 ps
CPU time 6.15 seconds
Started Sep 11 05:00:06 AM UTC 24
Finished Sep 11 05:00:13 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105272800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.105272800
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.547902647
Short name T223
Test name
Test status
Simulation time 2256854807 ps
CPU time 3.26 seconds
Started Sep 11 05:00:06 AM UTC 24
Finished Sep 11 05:00:10 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547902647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.547902647
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.3499857056
Short name T425
Test name
Test status
Simulation time 2510105610 ps
CPU time 8.59 seconds
Started Sep 11 05:00:07 AM UTC 24
Finished Sep 11 05:00:17 AM UTC 24
Peak memory 210016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499857056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.3499857056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.241775590
Short name T128
Test name
Test status
Simulation time 2118761365 ps
CPU time 3.98 seconds
Started Sep 11 05:00:06 AM UTC 24
Finished Sep 11 05:00:11 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241775590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.241775590
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.4239924925
Short name T112
Test name
Test status
Simulation time 45760859820 ps
CPU time 40.93 seconds
Started Sep 11 05:00:12 AM UTC 24
Finished Sep 11 05:00:54 AM UTC 24
Peak memory 210016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239924925 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.4239924925
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2504952346
Short name T441
Test name
Test status
Simulation time 7097327336 ps
CPU time 12.3 seconds
Started Sep 11 05:00:12 AM UTC 24
Finished Sep 11 05:00:25 AM UTC 24
Peak memory 226676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2504952346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.2504952346
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1524583541
Short name T96
Test name
Test status
Simulation time 5234069416 ps
CPU time 3.18 seconds
Started Sep 11 05:00:08 AM UTC 24
Finished Sep 11 05:00:13 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524583541 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.1524583541
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.728069419
Short name T439
Test name
Test status
Simulation time 2014634603 ps
CPU time 7 seconds
Started Sep 11 05:00:17 AM UTC 24
Finished Sep 11 05:00:25 AM UTC 24
Peak memory 209796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728069419 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.728069419
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3825397800
Short name T434
Test name
Test status
Simulation time 3171763002 ps
CPU time 6.74 seconds
Started Sep 11 05:00:14 AM UTC 24
Finished Sep 11 05:00:22 AM UTC 24
Peak memory 210260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825397800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.3825397800
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.4258582467
Short name T430
Test name
Test status
Simulation time 2772486206 ps
CPU time 4.03 seconds
Started Sep 11 05:00:14 AM UTC 24
Finished Sep 11 05:00:19 AM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258582467 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.4258582467
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1964687804
Short name T213
Test name
Test status
Simulation time 2882925751 ps
CPU time 3.78 seconds
Started Sep 11 05:00:17 AM UTC 24
Finished Sep 11 05:00:21 AM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964687804 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.1964687804
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1244290960
Short name T426
Test name
Test status
Simulation time 2654627487 ps
CPU time 1.81 seconds
Started Sep 11 05:00:14 AM UTC 24
Finished Sep 11 05:00:17 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244290960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.1244290960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1573883918
Short name T424
Test name
Test status
Simulation time 2486886408 ps
CPU time 3.59 seconds
Started Sep 11 05:00:12 AM UTC 24
Finished Sep 11 05:00:17 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573883918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.1573883918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.3813604600
Short name T427
Test name
Test status
Simulation time 2094723427 ps
CPU time 3.9 seconds
Started Sep 11 05:00:13 AM UTC 24
Finished Sep 11 05:00:18 AM UTC 24
Peak memory 209784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813604600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.3813604600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.4102864670
Short name T431
Test name
Test status
Simulation time 2514478268 ps
CPU time 5.57 seconds
Started Sep 11 05:00:13 AM UTC 24
Finished Sep 11 05:00:20 AM UTC 24
Peak memory 210016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102864670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.4102864670
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.1198090196
Short name T422
Test name
Test status
Simulation time 2159435218 ps
CPU time 1.71 seconds
Started Sep 11 05:00:12 AM UTC 24
Finished Sep 11 05:00:15 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198090196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.1198090196
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.868666264
Short name T454
Test name
Test status
Simulation time 8932847278 ps
CPU time 16.79 seconds
Started Sep 11 05:00:17 AM UTC 24
Finished Sep 11 05:00:35 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868666264 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.868666264
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3366744426
Short name T446
Test name
Test status
Simulation time 6846929916 ps
CPU time 10.82 seconds
Started Sep 11 05:00:17 AM UTC 24
Finished Sep 11 05:00:29 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3366744426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.3366744426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3632183663
Short name T139
Test name
Test status
Simulation time 9746580886 ps
CPU time 1.69 seconds
Started Sep 11 05:00:15 AM UTC 24
Finished Sep 11 05:00:18 AM UTC 24
Peak memory 208172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632183663 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.3632183663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.2673391319
Short name T453
Test name
Test status
Simulation time 2008733263 ps
CPU time 10.29 seconds
Started Sep 11 05:00:23 AM UTC 24
Finished Sep 11 05:00:34 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673391319 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.2673391319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.265007583
Short name T442
Test name
Test status
Simulation time 3633401627 ps
CPU time 4.51 seconds
Started Sep 11 05:00:20 AM UTC 24
Finished Sep 11 05:00:26 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265007583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.265007583
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.3381770496
Short name T325
Test name
Test status
Simulation time 125914291822 ps
CPU time 323.69 seconds
Started Sep 11 05:00:20 AM UTC 24
Finished Sep 11 05:05:48 AM UTC 24
Peak memory 210168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381770496 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.3381770496
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2517257490
Short name T234
Test name
Test status
Simulation time 34431129983 ps
CPU time 109.1 seconds
Started Sep 11 05:00:21 AM UTC 24
Finished Sep 11 05:02:13 AM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517257490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_with_pre_cond.2517257490
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.725435694
Short name T749
Test name
Test status
Simulation time 554284787364 ps
CPU time 360.04 seconds
Started Sep 11 05:00:19 AM UTC 24
Finished Sep 11 05:06:24 AM UTC 24
Peak memory 212600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725435694 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.725435694
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2817238908
Short name T180
Test name
Test status
Simulation time 4523209331 ps
CPU time 3.49 seconds
Started Sep 11 05:00:20 AM UTC 24
Finished Sep 11 05:00:25 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817238908 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.2817238908
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.544842534
Short name T437
Test name
Test status
Simulation time 2636098279 ps
CPU time 2.33 seconds
Started Sep 11 05:00:19 AM UTC 24
Finished Sep 11 05:00:23 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544842534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.544842534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.2802635516
Short name T444
Test name
Test status
Simulation time 2456241293 ps
CPU time 8.21 seconds
Started Sep 11 05:00:18 AM UTC 24
Finished Sep 11 05:00:27 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802635516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.2802635516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.4048349130
Short name T433
Test name
Test status
Simulation time 2144615471 ps
CPU time 1.8 seconds
Started Sep 11 05:00:18 AM UTC 24
Finished Sep 11 05:00:21 AM UTC 24
Peak memory 208212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048349130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.4048349130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.3787180042
Short name T449
Test name
Test status
Simulation time 2510525684 ps
CPU time 11.34 seconds
Started Sep 11 05:00:18 AM UTC 24
Finished Sep 11 05:00:30 AM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787180042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.3787180042
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.2883992700
Short name T436
Test name
Test status
Simulation time 2126370268 ps
CPU time 4.87 seconds
Started Sep 11 05:00:17 AM UTC 24
Finished Sep 11 05:00:23 AM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883992700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.2883992700
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3940026059
Short name T182
Test name
Test status
Simulation time 18568398929 ps
CPU time 14.64 seconds
Started Sep 11 05:00:22 AM UTC 24
Finished Sep 11 05:00:37 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940026059 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.3940026059
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.43974344
Short name T272
Test name
Test status
Simulation time 6550369714 ps
CPU time 20.01 seconds
Started Sep 11 05:00:22 AM UTC 24
Finished Sep 11 05:00:43 AM UTC 24
Peak memory 226260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=43974344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.43974344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1902444404
Short name T93
Test name
Test status
Simulation time 3762148911 ps
CPU time 9.19 seconds
Started Sep 11 05:00:20 AM UTC 24
Finished Sep 11 05:00:31 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902444404 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.1902444404
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.302489732
Short name T64
Test name
Test status
Simulation time 2023864286 ps
CPU time 3.19 seconds
Started Sep 11 04:58:23 AM UTC 24
Finished Sep 11 04:58:27 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302489732 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.302489732
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1407639741
Short name T28
Test name
Test status
Simulation time 3994985255 ps
CPU time 3.04 seconds
Started Sep 11 04:58:18 AM UTC 24
Finished Sep 11 04:58:22 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407639741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.1407639741
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1386169016
Short name T54
Test name
Test status
Simulation time 2216820864 ps
CPU time 1.78 seconds
Started Sep 11 04:58:12 AM UTC 24
Finished Sep 11 04:58:15 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386169016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.1386169016
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2082248655
Short name T29
Test name
Test status
Simulation time 2289196874 ps
CPU time 3.93 seconds
Started Sep 11 04:58:12 AM UTC 24
Finished Sep 11 04:58:17 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082248655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2082248655
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2209769274
Short name T87
Test name
Test status
Simulation time 25334175325 ps
CPU time 87.14 seconds
Started Sep 11 04:58:21 AM UTC 24
Finished Sep 11 04:59:50 AM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209769274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_with_pre_cond.2209769274
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3544797356
Short name T172
Test name
Test status
Simulation time 3524125724 ps
CPU time 18.48 seconds
Started Sep 11 04:58:15 AM UTC 24
Finished Sep 11 04:58:35 AM UTC 24
Peak memory 210132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544797356 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.3544797356
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3339148363
Short name T81
Test name
Test status
Simulation time 2612241844 ps
CPU time 8.31 seconds
Started Sep 11 04:58:15 AM UTC 24
Finished Sep 11 04:58:25 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339148363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.3339148363
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.3681005931
Short name T72
Test name
Test status
Simulation time 2496073940 ps
CPU time 2.35 seconds
Started Sep 11 04:58:11 AM UTC 24
Finished Sep 11 04:58:14 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681005931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.3681005931
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.548899728
Short name T135
Test name
Test status
Simulation time 2128559222 ps
CPU time 6.54 seconds
Started Sep 11 04:58:14 AM UTC 24
Finished Sep 11 04:58:22 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548899728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.548899728
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2817482692
Short name T178
Test name
Test status
Simulation time 42172186597 ps
CPU time 27.88 seconds
Started Sep 11 04:58:23 AM UTC 24
Finished Sep 11 04:58:52 AM UTC 24
Peak memory 240276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817482692 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.2817482692
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.2792338179
Short name T197
Test name
Test status
Simulation time 2114961135 ps
CPU time 6.45 seconds
Started Sep 11 04:58:10 AM UTC 24
Finished Sep 11 04:58:17 AM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792338179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.2792338179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.4099812748
Short name T194
Test name
Test status
Simulation time 5560762848 ps
CPU time 18.22 seconds
Started Sep 11 04:58:22 AM UTC 24
Finished Sep 11 04:58:41 AM UTC 24
Peak memory 220540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4099812748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.4099812748
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.208707258
Short name T23
Test name
Test status
Simulation time 9911601976 ps
CPU time 3.89 seconds
Started Sep 11 04:58:18 AM UTC 24
Finished Sep 11 04:58:22 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208707258 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.208707258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.2932952198
Short name T451
Test name
Test status
Simulation time 2059496746 ps
CPU time 2.81 seconds
Started Sep 11 05:00:28 AM UTC 24
Finished Sep 11 05:00:32 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932952198 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.2932952198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.4285328068
Short name T448
Test name
Test status
Simulation time 3416907678 ps
CPU time 4.49 seconds
Started Sep 11 05:00:24 AM UTC 24
Finished Sep 11 05:00:30 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285328068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.4285328068
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.3313681651
Short name T250
Test name
Test status
Simulation time 128892271293 ps
CPU time 183.16 seconds
Started Sep 11 05:00:25 AM UTC 24
Finished Sep 11 05:03:32 AM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313681651 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.3313681651
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1406715928
Short name T445
Test name
Test status
Simulation time 2762858742 ps
CPU time 2 seconds
Started Sep 11 05:00:24 AM UTC 24
Finished Sep 11 05:00:28 AM UTC 24
Peak memory 208172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406715928 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.1406715928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.4075573776
Short name T181
Test name
Test status
Simulation time 4602823152 ps
CPU time 9.44 seconds
Started Sep 11 05:00:25 AM UTC 24
Finished Sep 11 05:00:36 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075573776 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.4075573776
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1122492215
Short name T443
Test name
Test status
Simulation time 2731570771 ps
CPU time 1.53 seconds
Started Sep 11 05:00:24 AM UTC 24
Finished Sep 11 05:00:27 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122492215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.1122492215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.70568170
Short name T450
Test name
Test status
Simulation time 2466509262 ps
CPU time 7.3 seconds
Started Sep 11 05:00:23 AM UTC 24
Finished Sep 11 05:00:31 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70568170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.70568170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.1673663384
Short name T458
Test name
Test status
Simulation time 2216851551 ps
CPU time 12.01 seconds
Started Sep 11 05:00:24 AM UTC 24
Finished Sep 11 05:00:38 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673663384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.1673663384
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.141848115
Short name T447
Test name
Test status
Simulation time 2520464794 ps
CPU time 4.2 seconds
Started Sep 11 05:00:24 AM UTC 24
Finished Sep 11 05:00:30 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141848115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.141848115
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.2454587053
Short name T440
Test name
Test status
Simulation time 2174227159 ps
CPU time 1.25 seconds
Started Sep 11 05:00:23 AM UTC 24
Finished Sep 11 05:00:25 AM UTC 24
Peak memory 208160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454587053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.2454587053
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1571214400
Short name T97
Test name
Test status
Simulation time 7002693527 ps
CPU time 2.34 seconds
Started Sep 11 05:00:25 AM UTC 24
Finished Sep 11 05:00:29 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571214400 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.1571214400
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.1808303039
Short name T460
Test name
Test status
Simulation time 2049601488 ps
CPU time 1.79 seconds
Started Sep 11 05:00:36 AM UTC 24
Finished Sep 11 05:00:39 AM UTC 24
Peak memory 208236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808303039 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.1808303039
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2663908286
Short name T462
Test name
Test status
Simulation time 3970988472 ps
CPU time 8.49 seconds
Started Sep 11 05:00:31 AM UTC 24
Finished Sep 11 05:00:41 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663908286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.2663908286
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.2119360112
Short name T359
Test name
Test status
Simulation time 100139148556 ps
CPU time 272.85 seconds
Started Sep 11 05:00:32 AM UTC 24
Finished Sep 11 05:05:09 AM UTC 24
Peak memory 210168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119360112 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.2119360112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3748991566
Short name T783
Test name
Test status
Simulation time 237711963445 ps
CPU time 617.16 seconds
Started Sep 11 05:00:31 AM UTC 24
Finished Sep 11 05:10:56 AM UTC 24
Peak memory 212528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748991566 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.3748991566
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.1077736748
Short name T467
Test name
Test status
Simulation time 2896738975 ps
CPU time 8.41 seconds
Started Sep 11 05:00:32 AM UTC 24
Finished Sep 11 05:00:42 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077736748 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.1077736748
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.2891146733
Short name T456
Test name
Test status
Simulation time 2620558801 ps
CPU time 3.23 seconds
Started Sep 11 05:00:31 AM UTC 24
Finished Sep 11 05:00:35 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891146733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.2891146733
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.575954859
Short name T455
Test name
Test status
Simulation time 2468701435 ps
CPU time 4.95 seconds
Started Sep 11 05:00:29 AM UTC 24
Finished Sep 11 05:00:35 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575954859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.575954859
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1791291675
Short name T463
Test name
Test status
Simulation time 2235280062 ps
CPU time 9.75 seconds
Started Sep 11 05:00:30 AM UTC 24
Finished Sep 11 05:00:41 AM UTC 24
Peak memory 209948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791291675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.1791291675
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.3540132965
Short name T464
Test name
Test status
Simulation time 2512592195 ps
CPU time 9.92 seconds
Started Sep 11 05:00:30 AM UTC 24
Finished Sep 11 05:00:41 AM UTC 24
Peak memory 210012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540132965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.3540132965
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.561326225
Short name T452
Test name
Test status
Simulation time 2121256787 ps
CPU time 3.31 seconds
Started Sep 11 05:00:28 AM UTC 24
Finished Sep 11 05:00:32 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561326225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.561326225
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.1485091637
Short name T252
Test name
Test status
Simulation time 94772362315 ps
CPU time 314.96 seconds
Started Sep 11 05:00:35 AM UTC 24
Finished Sep 11 05:05:54 AM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485091637 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.1485091637
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2599565136
Short name T306
Test name
Test status
Simulation time 6849397685 ps
CPU time 15.57 seconds
Started Sep 11 05:00:34 AM UTC 24
Finished Sep 11 05:00:50 AM UTC 24
Peak memory 220784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2599565136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.2599565136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1917407871
Short name T457
Test name
Test status
Simulation time 5807651938 ps
CPU time 3.71 seconds
Started Sep 11 05:00:31 AM UTC 24
Finished Sep 11 05:00:36 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917407871 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.1917407871
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1102219817
Short name T470
Test name
Test status
Simulation time 2043657524 ps
CPU time 2.94 seconds
Started Sep 11 05:00:42 AM UTC 24
Finished Sep 11 05:00:46 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102219817 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.1102219817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2167441337
Short name T786
Test name
Test status
Simulation time 283132511645 ps
CPU time 653.38 seconds
Started Sep 11 05:00:38 AM UTC 24
Finished Sep 11 05:11:40 AM UTC 24
Peak memory 212596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167441337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.2167441337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.1862721130
Short name T116
Test name
Test status
Simulation time 64721201992 ps
CPU time 45.02 seconds
Started Sep 11 05:00:39 AM UTC 24
Finished Sep 11 05:01:27 AM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862721130 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.1862721130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1421191743
Short name T469
Test name
Test status
Simulation time 4014798814 ps
CPU time 4.99 seconds
Started Sep 11 05:00:38 AM UTC 24
Finished Sep 11 05:00:45 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421191743 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.1421191743
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.3393270608
Short name T186
Test name
Test status
Simulation time 4467670443 ps
CPU time 16.41 seconds
Started Sep 11 05:00:39 AM UTC 24
Finished Sep 11 05:00:58 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393270608 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.3393270608
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3628876914
Short name T475
Test name
Test status
Simulation time 2610775923 ps
CPU time 11.62 seconds
Started Sep 11 05:00:37 AM UTC 24
Finished Sep 11 05:00:50 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628876914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3628876914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3294383609
Short name T461
Test name
Test status
Simulation time 2491937474 ps
CPU time 2.44 seconds
Started Sep 11 05:00:36 AM UTC 24
Finished Sep 11 05:00:40 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294383609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.3294383609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.2326223268
Short name T465
Test name
Test status
Simulation time 2219707997 ps
CPU time 3.12 seconds
Started Sep 11 05:00:37 AM UTC 24
Finished Sep 11 05:00:41 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326223268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.2326223268
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.847006300
Short name T466
Test name
Test status
Simulation time 2533944591 ps
CPU time 3.54 seconds
Started Sep 11 05:00:37 AM UTC 24
Finished Sep 11 05:00:42 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847006300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.847006300
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.436883067
Short name T468
Test name
Test status
Simulation time 2114041956 ps
CPU time 5.58 seconds
Started Sep 11 05:00:36 AM UTC 24
Finished Sep 11 05:00:43 AM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436883067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.436883067
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2802184527
Short name T492
Test name
Test status
Simulation time 6893728821 ps
CPU time 23.08 seconds
Started Sep 11 05:00:42 AM UTC 24
Finished Sep 11 05:01:06 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802184527 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.2802184527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3563238343
Short name T291
Test name
Test status
Simulation time 6406831476 ps
CPU time 15.02 seconds
Started Sep 11 05:00:42 AM UTC 24
Finished Sep 11 05:00:58 AM UTC 24
Peak memory 226680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3563238343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.3563238343
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2245208612
Short name T105
Test name
Test status
Simulation time 5658318532 ps
CPU time 7.23 seconds
Started Sep 11 05:00:39 AM UTC 24
Finished Sep 11 05:00:48 AM UTC 24
Peak memory 210256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245208612 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.2245208612
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.2300336534
Short name T479
Test name
Test status
Simulation time 2038476710 ps
CPU time 2.16 seconds
Started Sep 11 05:00:50 AM UTC 24
Finished Sep 11 05:00:53 AM UTC 24
Peak memory 209808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300336534 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.2300336534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3619402206
Short name T477
Test name
Test status
Simulation time 3463101553 ps
CPU time 5.31 seconds
Started Sep 11 05:00:45 AM UTC 24
Finished Sep 11 05:00:52 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619402206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.3619402206
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.27124716
Short name T334
Test name
Test status
Simulation time 59027879728 ps
CPU time 159.35 seconds
Started Sep 11 05:00:49 AM UTC 24
Finished Sep 11 05:03:31 AM UTC 24
Peak memory 210564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27124716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_with_pre_cond.27124716
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.342951041
Short name T474
Test name
Test status
Simulation time 2874572017 ps
CPU time 3.93 seconds
Started Sep 11 05:00:44 AM UTC 24
Finished Sep 11 05:00:49 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342951041 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.342951041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1423755602
Short name T173
Test name
Test status
Simulation time 4999949862 ps
CPU time 3.41 seconds
Started Sep 11 05:00:48 AM UTC 24
Finished Sep 11 05:00:52 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423755602 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.1423755602
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.62990159
Short name T473
Test name
Test status
Simulation time 2626576180 ps
CPU time 4.49 seconds
Started Sep 11 05:00:43 AM UTC 24
Finished Sep 11 05:00:49 AM UTC 24
Peak memory 210260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62990159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.62990159
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.4229936436
Short name T476
Test name
Test status
Simulation time 2477648976 ps
CPU time 7.4 seconds
Started Sep 11 05:00:42 AM UTC 24
Finished Sep 11 05:00:51 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229936436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.4229936436
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.1274730385
Short name T471
Test name
Test status
Simulation time 2239115975 ps
CPU time 3.11 seconds
Started Sep 11 05:00:43 AM UTC 24
Finished Sep 11 05:00:47 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274730385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1274730385
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.522696816
Short name T472
Test name
Test status
Simulation time 2521165697 ps
CPU time 3.54 seconds
Started Sep 11 05:00:43 AM UTC 24
Finished Sep 11 05:00:48 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522696816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.522696816
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.305427545
Short name T459
Test name
Test status
Simulation time 2117036124 ps
CPU time 3.93 seconds
Started Sep 11 05:00:42 AM UTC 24
Finished Sep 11 05:00:47 AM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305427545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.305427545
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.566377548
Short name T487
Test name
Test status
Simulation time 7290555285 ps
CPU time 9.11 seconds
Started Sep 11 05:00:50 AM UTC 24
Finished Sep 11 05:01:00 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566377548 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.566377548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.614386938
Short name T484
Test name
Test status
Simulation time 9674930096 ps
CPU time 6.46 seconds
Started Sep 11 05:00:49 AM UTC 24
Finished Sep 11 05:00:56 AM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=614386938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.614386938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2622246297
Short name T478
Test name
Test status
Simulation time 11750124374 ps
CPU time 5.44 seconds
Started Sep 11 05:00:45 AM UTC 24
Finished Sep 11 05:00:52 AM UTC 24
Peak memory 210260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622246297 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.2622246297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.3046639222
Short name T490
Test name
Test status
Simulation time 2033967917 ps
CPU time 3.23 seconds
Started Sep 11 05:00:57 AM UTC 24
Finished Sep 11 05:01:01 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046639222 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.3046639222
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3572960784
Short name T771
Test name
Test status
Simulation time 281004488360 ps
CPU time 385.36 seconds
Started Sep 11 05:00:52 AM UTC 24
Finished Sep 11 05:07:23 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572960784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.3572960784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1390177997
Short name T331
Test name
Test status
Simulation time 63042837445 ps
CPU time 175.77 seconds
Started Sep 11 05:00:53 AM UTC 24
Finished Sep 11 05:03:52 AM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390177997 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.1390177997
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1642585305
Short name T101
Test name
Test status
Simulation time 67368606624 ps
CPU time 53.18 seconds
Started Sep 11 05:00:55 AM UTC 24
Finished Sep 11 05:01:49 AM UTC 24
Peak memory 210560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642585305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_with_pre_cond.1642585305
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.683405359
Short name T789
Test name
Test status
Simulation time 1060171633066 ps
CPU time 2937.18 seconds
Started Sep 11 05:00:52 AM UTC 24
Finished Sep 11 05:50:19 AM UTC 24
Peak memory 212528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683405359 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.683405359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3556108864
Short name T183
Test name
Test status
Simulation time 4978560524 ps
CPU time 3.79 seconds
Started Sep 11 05:00:55 AM UTC 24
Finished Sep 11 05:00:59 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556108864 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.3556108864
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3212739468
Short name T483
Test name
Test status
Simulation time 2633988911 ps
CPU time 3.99 seconds
Started Sep 11 05:00:51 AM UTC 24
Finished Sep 11 05:00:56 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212739468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.3212739468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.1315133490
Short name T480
Test name
Test status
Simulation time 2451238746 ps
CPU time 2.96 seconds
Started Sep 11 05:00:51 AM UTC 24
Finished Sep 11 05:00:55 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315133490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.1315133490
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.1252236773
Short name T485
Test name
Test status
Simulation time 2125352397 ps
CPU time 6.61 seconds
Started Sep 11 05:00:51 AM UTC 24
Finished Sep 11 05:00:59 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252236773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.1252236773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.1073566197
Short name T481
Test name
Test status
Simulation time 2531493114 ps
CPU time 3.06 seconds
Started Sep 11 05:00:51 AM UTC 24
Finished Sep 11 05:00:55 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073566197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.1073566197
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.1106279117
Short name T486
Test name
Test status
Simulation time 2108942187 ps
CPU time 8.41 seconds
Started Sep 11 05:00:50 AM UTC 24
Finished Sep 11 05:01:00 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106279117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.1106279117
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2256779405
Short name T526
Test name
Test status
Simulation time 14492747428 ps
CPU time 47.9 seconds
Started Sep 11 05:00:56 AM UTC 24
Finished Sep 11 05:01:45 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256779405 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.2256779405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1008945153
Short name T505
Test name
Test status
Simulation time 10767759316 ps
CPU time 25.32 seconds
Started Sep 11 05:00:56 AM UTC 24
Finished Sep 11 05:01:22 AM UTC 24
Peak memory 222576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1008945153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1008945153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2673781878
Short name T482
Test name
Test status
Simulation time 2789506920 ps
CPU time 2.43 seconds
Started Sep 11 05:00:52 AM UTC 24
Finished Sep 11 05:00:56 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673781878 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.2673781878
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.4107032865
Short name T495
Test name
Test status
Simulation time 2026507345 ps
CPU time 4.2 seconds
Started Sep 11 05:01:07 AM UTC 24
Finished Sep 11 05:01:12 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107032865 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.4107032865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1853238780
Short name T494
Test name
Test status
Simulation time 3273578464 ps
CPU time 7.44 seconds
Started Sep 11 05:01:00 AM UTC 24
Finished Sep 11 05:01:09 AM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853238780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.1853238780
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.611310890
Short name T235
Test name
Test status
Simulation time 24614774312 ps
CPU time 24.41 seconds
Started Sep 11 05:01:02 AM UTC 24
Finished Sep 11 05:01:27 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611310890 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.611310890
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3960994621
Short name T502
Test name
Test status
Simulation time 4475561619 ps
CPU time 19.51 seconds
Started Sep 11 05:01:00 AM UTC 24
Finished Sep 11 05:01:21 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960994621 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.3960994621
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.1616765597
Short name T496
Test name
Test status
Simulation time 3346034368 ps
CPU time 10.44 seconds
Started Sep 11 05:01:02 AM UTC 24
Finished Sep 11 05:01:13 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616765597 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.1616765597
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.432607939
Short name T493
Test name
Test status
Simulation time 2609111339 ps
CPU time 6.94 seconds
Started Sep 11 05:00:59 AM UTC 24
Finished Sep 11 05:01:07 AM UTC 24
Peak memory 210272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432607939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.432607939
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.2645949719
Short name T491
Test name
Test status
Simulation time 2451066130 ps
CPU time 6.49 seconds
Started Sep 11 05:00:57 AM UTC 24
Finished Sep 11 05:01:05 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645949719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.2645949719
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.3220340615
Short name T489
Test name
Test status
Simulation time 2202227723 ps
CPU time 2.03 seconds
Started Sep 11 05:00:58 AM UTC 24
Finished Sep 11 05:01:01 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220340615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.3220340615
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.2475833521
Short name T497
Test name
Test status
Simulation time 2512435343 ps
CPU time 13.34 seconds
Started Sep 11 05:00:59 AM UTC 24
Finished Sep 11 05:01:14 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475833521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.2475833521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1980746453
Short name T488
Test name
Test status
Simulation time 2128312990 ps
CPU time 2.33 seconds
Started Sep 11 05:00:57 AM UTC 24
Finished Sep 11 05:01:00 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980746453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.1980746453
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.3992480799
Short name T738
Test name
Test status
Simulation time 102210993104 ps
CPU time 234.36 seconds
Started Sep 11 05:01:06 AM UTC 24
Finished Sep 11 05:05:04 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992480799 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.3992480799
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.96378315
Short name T499
Test name
Test status
Simulation time 2069826477 ps
CPU time 11.36 seconds
Started Sep 11 05:01:02 AM UTC 24
Finished Sep 11 05:01:14 AM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=96378315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.96378315
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2392768168
Short name T149
Test name
Test status
Simulation time 4244975255 ps
CPU time 14.87 seconds
Started Sep 11 05:01:02 AM UTC 24
Finished Sep 11 05:01:18 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392768168 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.2392768168
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.3636179049
Short name T510
Test name
Test status
Simulation time 2017815157 ps
CPU time 4.88 seconds
Started Sep 11 05:01:22 AM UTC 24
Finished Sep 11 05:01:28 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636179049 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.3636179049
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2104919300
Short name T511
Test name
Test status
Simulation time 3439210876 ps
CPU time 14.16 seconds
Started Sep 11 05:01:14 AM UTC 24
Finished Sep 11 05:01:30 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104919300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2104919300
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3671606862
Short name T356
Test name
Test status
Simulation time 149087377183 ps
CPU time 96.27 seconds
Started Sep 11 05:01:16 AM UTC 24
Finished Sep 11 05:02:54 AM UTC 24
Peak memory 210168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671606862 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.3671606862
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3128794909
Short name T249
Test name
Test status
Simulation time 26090726859 ps
CPU time 42.93 seconds
Started Sep 11 05:01:17 AM UTC 24
Finished Sep 11 05:02:01 AM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128794909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_with_pre_cond.3128794909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2008236792
Short name T507
Test name
Test status
Simulation time 5451267909 ps
CPU time 10.43 seconds
Started Sep 11 05:01:14 AM UTC 24
Finished Sep 11 05:01:26 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008236792 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.2008236792
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2793577244
Short name T509
Test name
Test status
Simulation time 3272882743 ps
CPU time 9.13 seconds
Started Sep 11 05:01:17 AM UTC 24
Finished Sep 11 05:01:27 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793577244 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.2793577244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3281010859
Short name T501
Test name
Test status
Simulation time 2617672739 ps
CPU time 6.53 seconds
Started Sep 11 05:01:13 AM UTC 24
Finished Sep 11 05:01:21 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281010859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3281010859
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.4154458937
Short name T504
Test name
Test status
Simulation time 2459079835 ps
CPU time 12.28 seconds
Started Sep 11 05:01:08 AM UTC 24
Finished Sep 11 05:01:21 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154458937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.4154458937
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.2975083763
Short name T503
Test name
Test status
Simulation time 2074536276 ps
CPU time 10.12 seconds
Started Sep 11 05:01:10 AM UTC 24
Finished Sep 11 05:01:21 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975083763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.2975083763
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.3341297577
Short name T500
Test name
Test status
Simulation time 2525881490 ps
CPU time 3.87 seconds
Started Sep 11 05:01:11 AM UTC 24
Finished Sep 11 05:01:16 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341297577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3341297577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.291552054
Short name T498
Test name
Test status
Simulation time 2113317334 ps
CPU time 5.71 seconds
Started Sep 11 05:01:07 AM UTC 24
Finished Sep 11 05:01:14 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291552054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.291552054
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.2774952666
Short name T513
Test name
Test status
Simulation time 11223520519 ps
CPU time 10.41 seconds
Started Sep 11 05:01:19 AM UTC 24
Finished Sep 11 05:01:30 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774952666 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.2774952666
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3785034847
Short name T508
Test name
Test status
Simulation time 4040119600 ps
CPU time 6.71 seconds
Started Sep 11 05:01:19 AM UTC 24
Finished Sep 11 05:01:27 AM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3785034847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.3785034847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1294108817
Short name T98
Test name
Test status
Simulation time 3285383566 ps
CPU time 2.07 seconds
Started Sep 11 05:01:15 AM UTC 24
Finished Sep 11 05:01:18 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294108817 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.1294108817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.2244068124
Short name T524
Test name
Test status
Simulation time 2014136306 ps
CPU time 10.12 seconds
Started Sep 11 05:01:31 AM UTC 24
Finished Sep 11 05:01:43 AM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244068124 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.2244068124
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2883020227
Short name T515
Test name
Test status
Simulation time 3671240477 ps
CPU time 4.36 seconds
Started Sep 11 05:01:27 AM UTC 24
Finished Sep 11 05:01:32 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883020227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2883020227
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.678508560
Short name T512
Test name
Test status
Simulation time 2598704529 ps
CPU time 3.46 seconds
Started Sep 11 05:01:25 AM UTC 24
Finished Sep 11 05:01:30 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678508560 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.678508560
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.3712708386
Short name T187
Test name
Test status
Simulation time 3266051392 ps
CPU time 8.69 seconds
Started Sep 11 05:01:28 AM UTC 24
Finished Sep 11 05:01:38 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712708386 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.3712708386
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2777999879
Short name T519
Test name
Test status
Simulation time 2609819851 ps
CPU time 11.98 seconds
Started Sep 11 05:01:25 AM UTC 24
Finished Sep 11 05:01:38 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777999879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.2777999879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.688436751
Short name T514
Test name
Test status
Simulation time 2444769416 ps
CPU time 7.32 seconds
Started Sep 11 05:01:22 AM UTC 24
Finished Sep 11 05:01:30 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688436751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.688436751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.658780288
Short name T506
Test name
Test status
Simulation time 2175607089 ps
CPU time 1.61 seconds
Started Sep 11 05:01:22 AM UTC 24
Finished Sep 11 05:01:25 AM UTC 24
Peak memory 208236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658780288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.658780288
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.765465957
Short name T517
Test name
Test status
Simulation time 2514648033 ps
CPU time 11.9 seconds
Started Sep 11 05:01:23 AM UTC 24
Finished Sep 11 05:01:36 AM UTC 24
Peak memory 210260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765465957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.765465957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.3927805808
Short name T516
Test name
Test status
Simulation time 2112503303 ps
CPU time 8.89 seconds
Started Sep 11 05:01:22 AM UTC 24
Finished Sep 11 05:01:32 AM UTC 24
Peak memory 209804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927805808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.3927805808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.941966073
Short name T788
Test name
Test status
Simulation time 423677070503 ps
CPU time 1123.44 seconds
Started Sep 11 05:01:31 AM UTC 24
Finished Sep 11 05:20:26 AM UTC 24
Peak memory 212672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941966073 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.941966073
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2274585653
Short name T528
Test name
Test status
Simulation time 16432920846 ps
CPU time 15.73 seconds
Started Sep 11 05:01:29 AM UTC 24
Finished Sep 11 05:01:46 AM UTC 24
Peak memory 220472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2274585653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.2274585653
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3052994540
Short name T518
Test name
Test status
Simulation time 3728862166 ps
CPU time 7.91 seconds
Started Sep 11 05:01:28 AM UTC 24
Finished Sep 11 05:01:37 AM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052994540 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.3052994540
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.400855918
Short name T533
Test name
Test status
Simulation time 2016718484 ps
CPU time 6.68 seconds
Started Sep 11 05:01:41 AM UTC 24
Finished Sep 11 05:01:49 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400855918 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.400855918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2184702798
Short name T530
Test name
Test status
Simulation time 3790868953 ps
CPU time 8.86 seconds
Started Sep 11 05:01:37 AM UTC 24
Finished Sep 11 05:01:47 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184702798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.2184702798
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.250021870
Short name T787
Test name
Test status
Simulation time 180262169223 ps
CPU time 597.68 seconds
Started Sep 11 05:01:38 AM UTC 24
Finished Sep 11 05:11:43 AM UTC 24
Peak memory 212820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250021870 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.250021870
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.523428496
Short name T522
Test name
Test status
Simulation time 2831106758 ps
CPU time 3.11 seconds
Started Sep 11 05:01:37 AM UTC 24
Finished Sep 11 05:01:41 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523428496 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.523428496
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.2274674606
Short name T199
Test name
Test status
Simulation time 4662763829 ps
CPU time 2.23 seconds
Started Sep 11 05:01:39 AM UTC 24
Finished Sep 11 05:01:42 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274674606 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.2274674606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2660106414
Short name T521
Test name
Test status
Simulation time 2620676988 ps
CPU time 5.87 seconds
Started Sep 11 05:01:33 AM UTC 24
Finished Sep 11 05:01:40 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660106414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.2660106414
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.2465891566
Short name T525
Test name
Test status
Simulation time 2453765136 ps
CPU time 10.2 seconds
Started Sep 11 05:01:31 AM UTC 24
Finished Sep 11 05:01:43 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465891566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.2465891566
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2488689711
Short name T520
Test name
Test status
Simulation time 2018067522 ps
CPU time 5.59 seconds
Started Sep 11 05:01:32 AM UTC 24
Finished Sep 11 05:01:39 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488689711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2488689711
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.3477562580
Short name T527
Test name
Test status
Simulation time 2510693936 ps
CPU time 12.11 seconds
Started Sep 11 05:01:32 AM UTC 24
Finished Sep 11 05:01:46 AM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477562580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.3477562580
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3710610505
Short name T523
Test name
Test status
Simulation time 2114246079 ps
CPU time 9.7 seconds
Started Sep 11 05:01:31 AM UTC 24
Finished Sep 11 05:01:42 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710610505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.3710610505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.3958564144
Short name T554
Test name
Test status
Simulation time 9131044377 ps
CPU time 28.66 seconds
Started Sep 11 05:01:41 AM UTC 24
Finished Sep 11 05:02:11 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958564144 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.3958564144
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2364182996
Short name T301
Test name
Test status
Simulation time 2644992222 ps
CPU time 10.5 seconds
Started Sep 11 05:01:40 AM UTC 24
Finished Sep 11 05:01:52 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2364182996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.2364182996
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2286664338
Short name T531
Test name
Test status
Simulation time 12093320482 ps
CPU time 8.64 seconds
Started Sep 11 05:01:38 AM UTC 24
Finished Sep 11 05:01:47 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286664338 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.2286664338
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.3241050891
Short name T539
Test name
Test status
Simulation time 2023017855 ps
CPU time 5.11 seconds
Started Sep 11 05:01:49 AM UTC 24
Finished Sep 11 05:01:55 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241050891 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.3241050891
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3876639968
Short name T544
Test name
Test status
Simulation time 3844046947 ps
CPU time 14.99 seconds
Started Sep 11 05:01:46 AM UTC 24
Finished Sep 11 05:02:02 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876639968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.3876639968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.3823829165
Short name T118
Test name
Test status
Simulation time 40812300320 ps
CPU time 30.82 seconds
Started Sep 11 05:01:47 AM UTC 24
Finished Sep 11 05:02:19 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823829165 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.3823829165
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.821282800
Short name T591
Test name
Test status
Simulation time 26334266305 ps
CPU time 50.96 seconds
Started Sep 11 05:01:47 AM UTC 24
Finished Sep 11 05:02:40 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821282800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_with_pre_cond.821282800
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.918831389
Short name T543
Test name
Test status
Simulation time 4641923806 ps
CPU time 15.08 seconds
Started Sep 11 05:01:45 AM UTC 24
Finished Sep 11 05:02:01 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918831389 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.918831389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.3658764129
Short name T184
Test name
Test status
Simulation time 6069110120 ps
CPU time 8.71 seconds
Started Sep 11 05:01:47 AM UTC 24
Finished Sep 11 05:01:57 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658764129 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.3658764129
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.450007320
Short name T536
Test name
Test status
Simulation time 2614724600 ps
CPU time 9.09 seconds
Started Sep 11 05:01:44 AM UTC 24
Finished Sep 11 05:01:54 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450007320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.450007320
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.3530853521
Short name T535
Test name
Test status
Simulation time 2439612072 ps
CPU time 7 seconds
Started Sep 11 05:01:43 AM UTC 24
Finished Sep 11 05:01:51 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530853521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.3530853521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1503693501
Short name T532
Test name
Test status
Simulation time 2214027121 ps
CPU time 3.45 seconds
Started Sep 11 05:01:43 AM UTC 24
Finished Sep 11 05:01:48 AM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503693501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.1503693501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.3260418529
Short name T534
Test name
Test status
Simulation time 2516271356 ps
CPU time 6 seconds
Started Sep 11 05:01:43 AM UTC 24
Finished Sep 11 05:01:50 AM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260418529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3260418529
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.1820988262
Short name T529
Test name
Test status
Simulation time 2139787809 ps
CPU time 2.9 seconds
Started Sep 11 05:01:42 AM UTC 24
Finished Sep 11 05:01:46 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820988262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.1820988262
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.1951108866
Short name T562
Test name
Test status
Simulation time 16438005992 ps
CPU time 25.94 seconds
Started Sep 11 05:01:48 AM UTC 24
Finished Sep 11 05:02:15 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951108866 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.1951108866
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3311026847
Short name T273
Test name
Test status
Simulation time 5168389009 ps
CPU time 17.65 seconds
Started Sep 11 05:01:48 AM UTC 24
Finished Sep 11 05:02:07 AM UTC 24
Peak memory 220444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3311026847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.3311026847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3663325521
Short name T160
Test name
Test status
Simulation time 5482409052 ps
CPU time 4.17 seconds
Started Sep 11 05:01:47 AM UTC 24
Finished Sep 11 05:01:52 AM UTC 24
Peak memory 209960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663325521 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.3663325521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.970558994
Short name T189
Test name
Test status
Simulation time 2039981771 ps
CPU time 3.67 seconds
Started Sep 11 04:58:34 AM UTC 24
Finished Sep 11 04:58:39 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970558994 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.970558994
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1725549330
Short name T56
Test name
Test status
Simulation time 3375884993 ps
CPU time 3.76 seconds
Started Sep 11 04:58:29 AM UTC 24
Finished Sep 11 04:58:33 AM UTC 24
Peak memory 210324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725549330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.1725549330
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1033399229
Short name T57
Test name
Test status
Simulation time 2232950526 ps
CPU time 10.51 seconds
Started Sep 11 04:58:23 AM UTC 24
Finished Sep 11 04:58:35 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033399229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.1033399229
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.928753084
Short name T55
Test name
Test status
Simulation time 2308221521 ps
CPU time 3.96 seconds
Started Sep 11 04:58:25 AM UTC 24
Finished Sep 11 04:58:30 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928753084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.928753084
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.873029256
Short name T232
Test name
Test status
Simulation time 66618169232 ps
CPU time 224.71 seconds
Started Sep 11 04:58:32 AM UTC 24
Finished Sep 11 05:02:20 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873029256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_with_pre_cond.873029256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.4265995772
Short name T193
Test name
Test status
Simulation time 2521946999 ps
CPU time 9.37 seconds
Started Sep 11 04:58:29 AM UTC 24
Finished Sep 11 04:58:39 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265995772 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.4265995772
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2870902177
Short name T82
Test name
Test status
Simulation time 2654053940 ps
CPU time 1.77 seconds
Started Sep 11 04:58:27 AM UTC 24
Finished Sep 11 04:58:30 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870902177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2870902177
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.993375983
Short name T73
Test name
Test status
Simulation time 2472472290 ps
CPU time 7.53 seconds
Started Sep 11 04:58:23 AM UTC 24
Finished Sep 11 04:58:32 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993375983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.993375983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.584827729
Short name T90
Test name
Test status
Simulation time 2077979941 ps
CPU time 6.22 seconds
Started Sep 11 04:58:25 AM UTC 24
Finished Sep 11 04:58:33 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584827729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.584827729
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1654407794
Short name T83
Test name
Test status
Simulation time 2510111680 ps
CPU time 13.37 seconds
Started Sep 11 04:58:26 AM UTC 24
Finished Sep 11 04:58:41 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654407794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.1654407794
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.253277506
Short name T226
Test name
Test status
Simulation time 22009388779 ps
CPU time 68.75 seconds
Started Sep 11 04:58:33 AM UTC 24
Finished Sep 11 04:59:43 AM UTC 24
Peak memory 240264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253277506 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.253277506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.2747374425
Short name T65
Test name
Test status
Simulation time 2126049187 ps
CPU time 3.05 seconds
Started Sep 11 04:58:23 AM UTC 24
Finished Sep 11 04:58:27 AM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747374425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2747374425
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1748709473
Short name T75
Test name
Test status
Simulation time 9627869534 ps
CPU time 12.85 seconds
Started Sep 11 04:58:33 AM UTC 24
Finished Sep 11 04:58:47 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748709473 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.1748709473
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.3614223186
Short name T18
Test name
Test status
Simulation time 5024644960 ps
CPU time 6.74 seconds
Started Sep 11 04:58:30 AM UTC 24
Finished Sep 11 04:58:38 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614223186 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.3614223186
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.580844599
Short name T551
Test name
Test status
Simulation time 2013194680 ps
CPU time 6.92 seconds
Started Sep 11 05:02:00 AM UTC 24
Finished Sep 11 05:02:08 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580844599 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.580844599
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.454319866
Short name T540
Test name
Test status
Simulation time 3011169628 ps
CPU time 2.7 seconds
Started Sep 11 05:01:55 AM UTC 24
Finished Sep 11 05:01:59 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454319866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.454319866
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.2208449148
Short name T119
Test name
Test status
Simulation time 63208537847 ps
CPU time 39.4 seconds
Started Sep 11 05:01:56 AM UTC 24
Finished Sep 11 05:02:37 AM UTC 24
Peak memory 210236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208449148 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.2208449148
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2380004898
Short name T256
Test name
Test status
Simulation time 59759138413 ps
CPU time 30.31 seconds
Started Sep 11 05:01:56 AM UTC 24
Finished Sep 11 05:02:28 AM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380004898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_with_pre_cond.2380004898
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3296357845
Short name T541
Test name
Test status
Simulation time 3624985423 ps
CPU time 4.23 seconds
Started Sep 11 05:01:54 AM UTC 24
Finished Sep 11 05:01:59 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296357845 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.3296357845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.514341323
Short name T542
Test name
Test status
Simulation time 2556363381 ps
CPU time 3.32 seconds
Started Sep 11 05:01:56 AM UTC 24
Finished Sep 11 05:02:00 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514341323 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.514341323
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1323575302
Short name T549
Test name
Test status
Simulation time 2610943214 ps
CPU time 12.37 seconds
Started Sep 11 05:01:53 AM UTC 24
Finished Sep 11 05:02:06 AM UTC 24
Peak memory 209472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323575302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1323575302
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.710145392
Short name T537
Test name
Test status
Simulation time 2488880770 ps
CPU time 2.38 seconds
Started Sep 11 05:01:50 AM UTC 24
Finished Sep 11 05:01:54 AM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710145392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.710145392
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.3689134466
Short name T545
Test name
Test status
Simulation time 2260170722 ps
CPU time 10.75 seconds
Started Sep 11 05:01:51 AM UTC 24
Finished Sep 11 05:02:04 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689134466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3689134466
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.3427424113
Short name T546
Test name
Test status
Simulation time 2513340976 ps
CPU time 10.39 seconds
Started Sep 11 05:01:53 AM UTC 24
Finished Sep 11 05:02:04 AM UTC 24
Peak memory 209524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427424113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3427424113
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.3418319796
Short name T538
Test name
Test status
Simulation time 2130760594 ps
CPU time 3.32 seconds
Started Sep 11 05:01:50 AM UTC 24
Finished Sep 11 05:01:55 AM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418319796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.3418319796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2476164549
Short name T552
Test name
Test status
Simulation time 6083597492 ps
CPU time 9.81 seconds
Started Sep 11 05:01:58 AM UTC 24
Finished Sep 11 05:02:09 AM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2476164549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.2476164549
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3827083808
Short name T558
Test name
Test status
Simulation time 2062109905 ps
CPU time 2.21 seconds
Started Sep 11 05:02:10 AM UTC 24
Finished Sep 11 05:02:14 AM UTC 24
Peak memory 209576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827083808 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.3827083808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3135726136
Short name T556
Test name
Test status
Simulation time 3422604890 ps
CPU time 4.98 seconds
Started Sep 11 05:02:06 AM UTC 24
Finished Sep 11 05:02:12 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135726136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3135726136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.801328351
Short name T758
Test name
Test status
Simulation time 398180155548 ps
CPU time 286.4 seconds
Started Sep 11 05:02:05 AM UTC 24
Finished Sep 11 05:06:55 AM UTC 24
Peak memory 210256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801328351 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.801328351
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.919415914
Short name T569
Test name
Test status
Simulation time 2703205567 ps
CPU time 13.19 seconds
Started Sep 11 05:02:07 AM UTC 24
Finished Sep 11 05:02:21 AM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919415914 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.919415914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3968788679
Short name T553
Test name
Test status
Simulation time 2621365701 ps
CPU time 4.78 seconds
Started Sep 11 05:02:04 AM UTC 24
Finished Sep 11 05:02:10 AM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968788679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.3968788679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1243031268
Short name T550
Test name
Test status
Simulation time 2461312069 ps
CPU time 4.48 seconds
Started Sep 11 05:02:01 AM UTC 24
Finished Sep 11 05:02:07 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243031268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1243031268
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.1467192795
Short name T547
Test name
Test status
Simulation time 2280536663 ps
CPU time 1.59 seconds
Started Sep 11 05:02:03 AM UTC 24
Finished Sep 11 05:02:05 AM UTC 24
Peak memory 208236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467192795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.1467192795
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.935945600
Short name T557
Test name
Test status
Simulation time 2512602905 ps
CPU time 9.17 seconds
Started Sep 11 05:02:03 AM UTC 24
Finished Sep 11 05:02:13 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935945600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.935945600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.745538420
Short name T548
Test name
Test status
Simulation time 2131134667 ps
CPU time 3.35 seconds
Started Sep 11 05:02:01 AM UTC 24
Finished Sep 11 05:02:06 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745538420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.745538420
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2782128650
Short name T559
Test name
Test status
Simulation time 13829837540 ps
CPU time 3.48 seconds
Started Sep 11 05:02:09 AM UTC 24
Finished Sep 11 05:02:14 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782128650 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.2782128650
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1793554892
Short name T588
Test name
Test status
Simulation time 13311505956 ps
CPU time 28.37 seconds
Started Sep 11 05:02:08 AM UTC 24
Finished Sep 11 05:02:38 AM UTC 24
Peak memory 220472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1793554892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.1793554892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2497925274
Short name T561
Test name
Test status
Simulation time 4492549536 ps
CPU time 7.7 seconds
Started Sep 11 05:02:06 AM UTC 24
Finished Sep 11 05:02:15 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497925274 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.2497925274
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1099922595
Short name T572
Test name
Test status
Simulation time 2012673721 ps
CPU time 5.75 seconds
Started Sep 11 05:02:19 AM UTC 24
Finished Sep 11 05:02:26 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099922595 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.1099922595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2760443998
Short name T565
Test name
Test status
Simulation time 3089120404 ps
CPU time 3.28 seconds
Started Sep 11 05:02:15 AM UTC 24
Finished Sep 11 05:02:19 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760443998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.2760443998
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.546812295
Short name T332
Test name
Test status
Simulation time 124272758249 ps
CPU time 84.4 seconds
Started Sep 11 05:02:15 AM UTC 24
Finished Sep 11 05:03:41 AM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546812295 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.546812295
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.4017740074
Short name T577
Test name
Test status
Simulation time 3538962283 ps
CPU time 13.74 seconds
Started Sep 11 05:02:14 AM UTC 24
Finished Sep 11 05:02:28 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017740074 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.4017740074
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.3910071145
Short name T371
Test name
Test status
Simulation time 75597815729 ps
CPU time 23.51 seconds
Started Sep 11 05:02:16 AM UTC 24
Finished Sep 11 05:02:41 AM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910071145 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.3910071145
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1871888412
Short name T564
Test name
Test status
Simulation time 2625635429 ps
CPU time 3.93 seconds
Started Sep 11 05:02:14 AM UTC 24
Finished Sep 11 05:02:18 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871888412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.1871888412
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.2890186098
Short name T560
Test name
Test status
Simulation time 2471575227 ps
CPU time 2.79 seconds
Started Sep 11 05:02:10 AM UTC 24
Finished Sep 11 05:02:14 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890186098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.2890186098
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.1373276469
Short name T567
Test name
Test status
Simulation time 2130092174 ps
CPU time 7.9 seconds
Started Sep 11 05:02:11 AM UTC 24
Finished Sep 11 05:02:20 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373276469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.1373276469
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.3155219819
Short name T563
Test name
Test status
Simulation time 2518529466 ps
CPU time 4.51 seconds
Started Sep 11 05:02:12 AM UTC 24
Finished Sep 11 05:02:18 AM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155219819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.3155219819
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.628806278
Short name T566
Test name
Test status
Simulation time 2111276334 ps
CPU time 7.53 seconds
Started Sep 11 05:02:10 AM UTC 24
Finished Sep 11 05:02:19 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628806278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.628806278
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.193073035
Short name T582
Test name
Test status
Simulation time 6148687594 ps
CPU time 14.8 seconds
Started Sep 11 05:02:17 AM UTC 24
Finished Sep 11 05:02:33 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193073035 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.193073035
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.73239297
Short name T574
Test name
Test status
Simulation time 10055756275 ps
CPU time 10.5 seconds
Started Sep 11 05:02:16 AM UTC 24
Finished Sep 11 05:02:28 AM UTC 24
Peak memory 220408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=73239297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.73239297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2519762039
Short name T568
Test name
Test status
Simulation time 3624828538 ps
CPU time 5.08 seconds
Started Sep 11 05:02:15 AM UTC 24
Finished Sep 11 05:02:21 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519762039 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.2519762039
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.3594129181
Short name T555
Test name
Test status
Simulation time 2055913621 ps
CPU time 2.51 seconds
Started Sep 11 05:02:27 AM UTC 24
Finished Sep 11 05:02:31 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594129181 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.3594129181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.617237994
Short name T571
Test name
Test status
Simulation time 3422379845 ps
CPU time 2.52 seconds
Started Sep 11 05:02:22 AM UTC 24
Finished Sep 11 05:02:25 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617237994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.617237994
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.3704772392
Short name T750
Test name
Test status
Simulation time 162805317589 ps
CPU time 240.51 seconds
Started Sep 11 05:02:23 AM UTC 24
Finished Sep 11 05:06:27 AM UTC 24
Peak memory 210236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704772392 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.3704772392
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3702282672
Short name T751
Test name
Test status
Simulation time 70552730506 ps
CPU time 238.49 seconds
Started Sep 11 05:02:26 AM UTC 24
Finished Sep 11 05:06:28 AM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702282672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_with_pre_cond.3702282672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1717696338
Short name T589
Test name
Test status
Simulation time 4461354120 ps
CPU time 14.99 seconds
Started Sep 11 05:02:22 AM UTC 24
Finished Sep 11 05:02:38 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717696338 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.1717696338
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.2666512079
Short name T586
Test name
Test status
Simulation time 2466909977 ps
CPU time 9.91 seconds
Started Sep 11 05:02:25 AM UTC 24
Finished Sep 11 05:02:36 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666512079 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.2666512079
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3843096321
Short name T579
Test name
Test status
Simulation time 2609682197 ps
CPU time 8.62 seconds
Started Sep 11 05:02:21 AM UTC 24
Finished Sep 11 05:02:30 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843096321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3843096321
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.564818078
Short name T570
Test name
Test status
Simulation time 2493527848 ps
CPU time 3.58 seconds
Started Sep 11 05:02:20 AM UTC 24
Finished Sep 11 05:02:25 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564818078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.564818078
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.608651968
Short name T573
Test name
Test status
Simulation time 2210133397 ps
CPU time 6.04 seconds
Started Sep 11 05:02:20 AM UTC 24
Finished Sep 11 05:02:28 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608651968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.608651968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.1450533813
Short name T576
Test name
Test status
Simulation time 2515120546 ps
CPU time 6.7 seconds
Started Sep 11 05:02:20 AM UTC 24
Finished Sep 11 05:02:28 AM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450533813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.1450533813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.105383700
Short name T575
Test name
Test status
Simulation time 2108189921 ps
CPU time 7.98 seconds
Started Sep 11 05:02:19 AM UTC 24
Finished Sep 11 05:02:28 AM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105383700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.105383700
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1738252977
Short name T614
Test name
Test status
Simulation time 14197558905 ps
CPU time 32.85 seconds
Started Sep 11 05:02:26 AM UTC 24
Finished Sep 11 05:03:00 AM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738252977 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.1738252977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3469861920
Short name T284
Test name
Test status
Simulation time 2774707552 ps
CPU time 8.25 seconds
Started Sep 11 05:02:26 AM UTC 24
Finished Sep 11 05:02:35 AM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3469861920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.3469861920
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.4063124139
Short name T578
Test name
Test status
Simulation time 3370863165 ps
CPU time 5.27 seconds
Started Sep 11 05:02:23 AM UTC 24
Finished Sep 11 05:02:29 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063124139 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.4063124139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.807309014
Short name T594
Test name
Test status
Simulation time 2014693751 ps
CPU time 6.51 seconds
Started Sep 11 05:02:33 AM UTC 24
Finished Sep 11 05:02:41 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807309014 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.807309014
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2315576886
Short name T584
Test name
Test status
Simulation time 3603664668 ps
CPU time 4.31 seconds
Started Sep 11 05:02:30 AM UTC 24
Finished Sep 11 05:02:35 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315576886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.2315576886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.1434794747
Short name T323
Test name
Test status
Simulation time 207109540408 ps
CPU time 61.96 seconds
Started Sep 11 05:02:31 AM UTC 24
Finished Sep 11 05:03:34 AM UTC 24
Peak memory 210168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434794747 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.1434794747
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2263399291
Short name T344
Test name
Test status
Simulation time 44118576984 ps
CPU time 107.99 seconds
Started Sep 11 05:02:33 AM UTC 24
Finished Sep 11 05:04:23 AM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263399291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_with_pre_cond.2263399291
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.4012995774
Short name T592
Test name
Test status
Simulation time 4979471426 ps
CPU time 8.92 seconds
Started Sep 11 05:02:30 AM UTC 24
Finished Sep 11 05:02:40 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012995774 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.4012995774
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.2756075941
Short name T585
Test name
Test status
Simulation time 2839106858 ps
CPU time 2.14 seconds
Started Sep 11 05:02:32 AM UTC 24
Finished Sep 11 05:02:35 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756075941 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.2756075941
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1866928021
Short name T596
Test name
Test status
Simulation time 2608946818 ps
CPU time 11.26 seconds
Started Sep 11 05:02:30 AM UTC 24
Finished Sep 11 05:02:42 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866928021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1866928021
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.121718904
Short name T581
Test name
Test status
Simulation time 2484840827 ps
CPU time 2.95 seconds
Started Sep 11 05:02:28 AM UTC 24
Finished Sep 11 05:02:32 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121718904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.121718904
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.2720042147
Short name T580
Test name
Test status
Simulation time 2236588984 ps
CPU time 2.48 seconds
Started Sep 11 05:02:28 AM UTC 24
Finished Sep 11 05:02:32 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720042147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.2720042147
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.4145735213
Short name T583
Test name
Test status
Simulation time 2542980820 ps
CPU time 2.61 seconds
Started Sep 11 05:02:30 AM UTC 24
Finished Sep 11 05:02:33 AM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145735213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.4145735213
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.2758489166
Short name T587
Test name
Test status
Simulation time 2113274332 ps
CPU time 8.02 seconds
Started Sep 11 05:02:28 AM UTC 24
Finished Sep 11 05:02:37 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758489166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.2758489166
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.883236482
Short name T643
Test name
Test status
Simulation time 58550832501 ps
CPU time 52.4 seconds
Started Sep 11 05:02:33 AM UTC 24
Finished Sep 11 05:03:27 AM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883236482 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.883236482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1998471592
Short name T605
Test name
Test status
Simulation time 3816173520 ps
CPU time 15.86 seconds
Started Sep 11 05:02:33 AM UTC 24
Finished Sep 11 05:02:50 AM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1998471592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.1998471592
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.563583824
Short name T161
Test name
Test status
Simulation time 5142692173 ps
CPU time 11.6 seconds
Started Sep 11 05:02:30 AM UTC 24
Finished Sep 11 05:02:43 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563583824 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.563583824
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.3160491010
Short name T604
Test name
Test status
Simulation time 2011121529 ps
CPU time 8.48 seconds
Started Sep 11 05:02:40 AM UTC 24
Finished Sep 11 05:02:50 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160491010 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.3160491010
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2110708600
Short name T779
Test name
Test status
Simulation time 169197433423 ps
CPU time 452.64 seconds
Started Sep 11 05:02:37 AM UTC 24
Finished Sep 11 05:10:15 AM UTC 24
Peak memory 209948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110708600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.2110708600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2285319640
Short name T330
Test name
Test status
Simulation time 71721255457 ps
CPU time 198.54 seconds
Started Sep 11 05:02:38 AM UTC 24
Finished Sep 11 05:05:59 AM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285319640 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.2285319640
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1722900479
Short name T210
Test name
Test status
Simulation time 102428968993 ps
CPU time 134.23 seconds
Started Sep 11 05:02:39 AM UTC 24
Finished Sep 11 05:04:56 AM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722900479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_with_pre_cond.1722900479
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.4019864517
Short name T612
Test name
Test status
Simulation time 4689325150 ps
CPU time 22.06 seconds
Started Sep 11 05:02:37 AM UTC 24
Finished Sep 11 05:03:00 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019864517 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.4019864517
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2708154115
Short name T593
Test name
Test status
Simulation time 2633484302 ps
CPU time 3.93 seconds
Started Sep 11 05:02:36 AM UTC 24
Finished Sep 11 05:02:40 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708154115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2708154115
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.225554697
Short name T595
Test name
Test status
Simulation time 2458759892 ps
CPU time 5.94 seconds
Started Sep 11 05:02:34 AM UTC 24
Finished Sep 11 05:02:41 AM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225554697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.225554697
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.1249135337
Short name T590
Test name
Test status
Simulation time 2029889662 ps
CPU time 3.2 seconds
Started Sep 11 05:02:34 AM UTC 24
Finished Sep 11 05:02:39 AM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249135337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1249135337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.2833551777
Short name T598
Test name
Test status
Simulation time 2508557441 ps
CPU time 9.59 seconds
Started Sep 11 05:02:36 AM UTC 24
Finished Sep 11 05:02:46 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833551777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.2833551777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.2461833348
Short name T599
Test name
Test status
Simulation time 2112575888 ps
CPU time 11.26 seconds
Started Sep 11 05:02:34 AM UTC 24
Finished Sep 11 05:02:47 AM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461833348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.2461833348
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.3789842909
Short name T374
Test name
Test status
Simulation time 12149596305 ps
CPU time 18.47 seconds
Started Sep 11 05:02:40 AM UTC 24
Finished Sep 11 05:03:00 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789842909 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.3789842909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3853278047
Short name T611
Test name
Test status
Simulation time 8787232456 ps
CPU time 16.65 seconds
Started Sep 11 05:02:39 AM UTC 24
Finished Sep 11 05:02:57 AM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3853278047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.3853278047
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3476452893
Short name T150
Test name
Test status
Simulation time 6479895622 ps
CPU time 3.03 seconds
Started Sep 11 05:02:38 AM UTC 24
Finished Sep 11 05:02:42 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476452893 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.3476452893
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.4009652468
Short name T609
Test name
Test status
Simulation time 2019656937 ps
CPU time 5.35 seconds
Started Sep 11 05:02:49 AM UTC 24
Finished Sep 11 05:02:56 AM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009652468 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.4009652468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3601871610
Short name T746
Test name
Test status
Simulation time 253189165619 ps
CPU time 194.34 seconds
Started Sep 11 05:02:44 AM UTC 24
Finished Sep 11 05:06:01 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601871610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3601871610
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.3815372128
Short name T120
Test name
Test status
Simulation time 96685953402 ps
CPU time 33.22 seconds
Started Sep 11 05:02:47 AM UTC 24
Finished Sep 11 05:03:21 AM UTC 24
Peak memory 210168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815372128 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.3815372128
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1609562055
Short name T606
Test name
Test status
Simulation time 3666510343 ps
CPU time 9.21 seconds
Started Sep 11 05:02:43 AM UTC 24
Finished Sep 11 05:02:53 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609562055 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.1609562055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.3884523751
Short name T190
Test name
Test status
Simulation time 3793395516 ps
CPU time 9.25 seconds
Started Sep 11 05:02:48 AM UTC 24
Finished Sep 11 05:02:58 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884523751 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.3884523751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2702431244
Short name T602
Test name
Test status
Simulation time 2614541809 ps
CPU time 4.89 seconds
Started Sep 11 05:02:43 AM UTC 24
Finished Sep 11 05:02:49 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702431244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.2702431244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.345460158
Short name T603
Test name
Test status
Simulation time 2467514218 ps
CPU time 6.69 seconds
Started Sep 11 05:02:41 AM UTC 24
Finished Sep 11 05:02:49 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345460158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.345460158
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.4013384767
Short name T601
Test name
Test status
Simulation time 2144245201 ps
CPU time 5.93 seconds
Started Sep 11 05:02:41 AM UTC 24
Finished Sep 11 05:02:48 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013384767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.4013384767
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.2919299705
Short name T600
Test name
Test status
Simulation time 2532418657 ps
CPU time 3.61 seconds
Started Sep 11 05:02:43 AM UTC 24
Finished Sep 11 05:02:47 AM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919299705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.2919299705
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.2527305865
Short name T597
Test name
Test status
Simulation time 2134646463 ps
CPU time 2.9 seconds
Started Sep 11 05:02:41 AM UTC 24
Finished Sep 11 05:02:45 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527305865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.2527305865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2508813692
Short name T297
Test name
Test status
Simulation time 12650919824 ps
CPU time 22.85 seconds
Started Sep 11 05:02:48 AM UTC 24
Finished Sep 11 05:03:12 AM UTC 24
Peak memory 220728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2508813692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2508813692
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2897609692
Short name T607
Test name
Test status
Simulation time 3612448280 ps
CPU time 6.67 seconds
Started Sep 11 05:02:46 AM UTC 24
Finished Sep 11 05:02:54 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897609692 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.2897609692
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.2687525891
Short name T624
Test name
Test status
Simulation time 2013313434 ps
CPU time 9.98 seconds
Started Sep 11 05:03:00 AM UTC 24
Finished Sep 11 05:03:12 AM UTC 24
Peak memory 209808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687525891 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.2687525891
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3154637485
Short name T619
Test name
Test status
Simulation time 3403671490 ps
CPU time 10.68 seconds
Started Sep 11 05:02:55 AM UTC 24
Finished Sep 11 05:03:07 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154637485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.3154637485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1532561715
Short name T770
Test name
Test status
Simulation time 76403417991 ps
CPU time 254.42 seconds
Started Sep 11 05:02:58 AM UTC 24
Finished Sep 11 05:07:16 AM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532561715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_with_pre_cond.1532561715
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3917286747
Short name T621
Test name
Test status
Simulation time 2603945417 ps
CPU time 12.84 seconds
Started Sep 11 05:02:55 AM UTC 24
Finished Sep 11 05:03:09 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917286747 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.3917286747
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.4030107858
Short name T211
Test name
Test status
Simulation time 4569056125 ps
CPU time 16.03 seconds
Started Sep 11 05:02:57 AM UTC 24
Finished Sep 11 05:03:14 AM UTC 24
Peak memory 210256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030107858 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.4030107858
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3648491197
Short name T620
Test name
Test status
Simulation time 2609483063 ps
CPU time 12.89 seconds
Started Sep 11 05:02:54 AM UTC 24
Finished Sep 11 05:03:08 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648491197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3648491197
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.4070390794
Short name T615
Test name
Test status
Simulation time 2456505273 ps
CPU time 8.82 seconds
Started Sep 11 05:02:50 AM UTC 24
Finished Sep 11 05:03:00 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070390794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.4070390794
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.1213260559
Short name T610
Test name
Test status
Simulation time 2117704165 ps
CPU time 3.37 seconds
Started Sep 11 05:02:52 AM UTC 24
Finished Sep 11 05:02:56 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213260559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.1213260559
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.1910918381
Short name T613
Test name
Test status
Simulation time 2515064343 ps
CPU time 7.33 seconds
Started Sep 11 05:02:52 AM UTC 24
Finished Sep 11 05:03:00 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910918381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.1910918381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.1840024984
Short name T608
Test name
Test status
Simulation time 2130295028 ps
CPU time 3.24 seconds
Started Sep 11 05:02:50 AM UTC 24
Finished Sep 11 05:02:55 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840024984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1840024984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.573114343
Short name T790
Test name
Test status
Simulation time 1682633229428 ps
CPU time 5068.02 seconds
Started Sep 11 05:02:59 AM UTC 24
Finished Sep 11 06:28:27 AM UTC 24
Peak memory 212928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573114343 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.573114343
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2557294505
Short name T630
Test name
Test status
Simulation time 12477878260 ps
CPU time 16.88 seconds
Started Sep 11 05:02:58 AM UTC 24
Finished Sep 11 05:03:16 AM UTC 24
Peak memory 226928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2557294505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.2557294505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1040065115
Short name T616
Test name
Test status
Simulation time 6486455367 ps
CPU time 4.43 seconds
Started Sep 11 05:02:56 AM UTC 24
Finished Sep 11 05:03:01 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040065115 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.1040065115
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3053962600
Short name T634
Test name
Test status
Simulation time 2009851891 ps
CPU time 5.92 seconds
Started Sep 11 05:03:10 AM UTC 24
Finished Sep 11 05:03:17 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053962600 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.3053962600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3105832121
Short name T622
Test name
Test status
Simulation time 3725327912 ps
CPU time 4.67 seconds
Started Sep 11 05:03:04 AM UTC 24
Finished Sep 11 05:03:10 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105832121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.3105832121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.1345817023
Short name T742
Test name
Test status
Simulation time 110563269464 ps
CPU time 150.68 seconds
Started Sep 11 05:03:07 AM UTC 24
Finished Sep 11 05:05:40 AM UTC 24
Peak memory 210224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345817023 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.1345817023
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2330947642
Short name T685
Test name
Test status
Simulation time 36077487511 ps
CPU time 57.46 seconds
Started Sep 11 05:03:08 AM UTC 24
Finished Sep 11 05:04:07 AM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330947642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_with_pre_cond.2330947642
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3092063731
Short name T629
Test name
Test status
Simulation time 3086281278 ps
CPU time 11.54 seconds
Started Sep 11 05:03:03 AM UTC 24
Finished Sep 11 05:03:15 AM UTC 24
Peak memory 210260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092063731 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.3092063731
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.4174013251
Short name T191
Test name
Test status
Simulation time 5788365537 ps
CPU time 3.19 seconds
Started Sep 11 05:03:08 AM UTC 24
Finished Sep 11 05:03:13 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174013251 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.4174013251
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2560598295
Short name T627
Test name
Test status
Simulation time 2611378901 ps
CPU time 12.33 seconds
Started Sep 11 05:03:02 AM UTC 24
Finished Sep 11 05:03:15 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560598295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.2560598295
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.3709639229
Short name T623
Test name
Test status
Simulation time 2456779191 ps
CPU time 8.08 seconds
Started Sep 11 05:03:01 AM UTC 24
Finished Sep 11 05:03:10 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709639229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.3709639229
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.2324763079
Short name T618
Test name
Test status
Simulation time 2180695558 ps
CPU time 2.08 seconds
Started Sep 11 05:03:02 AM UTC 24
Finished Sep 11 05:03:05 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324763079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.2324763079
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.2558275261
Short name T626
Test name
Test status
Simulation time 2514081840 ps
CPU time 9.64 seconds
Started Sep 11 05:03:02 AM UTC 24
Finished Sep 11 05:03:12 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558275261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.2558275261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2781669539
Short name T617
Test name
Test status
Simulation time 2155915349 ps
CPU time 1.82 seconds
Started Sep 11 05:03:01 AM UTC 24
Finished Sep 11 05:03:03 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781669539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.2781669539
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.2979650095
Short name T778
Test name
Test status
Simulation time 143307166547 ps
CPU time 407.73 seconds
Started Sep 11 05:03:10 AM UTC 24
Finished Sep 11 05:10:03 AM UTC 24
Peak memory 210104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979650095 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.2979650095
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.4236471633
Short name T639
Test name
Test status
Simulation time 4260876634 ps
CPU time 13.36 seconds
Started Sep 11 05:03:09 AM UTC 24
Finished Sep 11 05:03:24 AM UTC 24
Peak memory 220796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4236471633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.4236471633
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1440852555
Short name T625
Test name
Test status
Simulation time 11799558509 ps
CPU time 5.24 seconds
Started Sep 11 05:03:06 AM UTC 24
Finished Sep 11 05:03:12 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440852555 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.1440852555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.3315862380
Short name T641
Test name
Test status
Simulation time 2015209214 ps
CPU time 5.32 seconds
Started Sep 11 05:03:19 AM UTC 24
Finished Sep 11 05:03:25 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315862380 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.3315862380
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1751318800
Short name T647
Test name
Test status
Simulation time 3405810436 ps
CPU time 14.67 seconds
Started Sep 11 05:03:15 AM UTC 24
Finished Sep 11 05:03:32 AM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751318800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1751318800
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2694324099
Short name T785
Test name
Test status
Simulation time 153054372830 ps
CPU time 491.2 seconds
Started Sep 11 05:03:16 AM UTC 24
Finished Sep 11 05:11:33 AM UTC 24
Peak memory 210100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694324099 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.2694324099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3112313359
Short name T347
Test name
Test status
Simulation time 34638908993 ps
CPU time 26.76 seconds
Started Sep 11 05:03:17 AM UTC 24
Finished Sep 11 05:03:45 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112313359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_with_pre_cond.3112313359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1072128858
Short name T637
Test name
Test status
Simulation time 3053980818 ps
CPU time 8.04 seconds
Started Sep 11 05:03:14 AM UTC 24
Finished Sep 11 05:03:24 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072128858 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.1072128858
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.1264132430
Short name T217
Test name
Test status
Simulation time 3656413147 ps
CPU time 8.34 seconds
Started Sep 11 05:03:16 AM UTC 24
Finished Sep 11 05:03:26 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264132430 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.1264132430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1009334019
Short name T635
Test name
Test status
Simulation time 2624652121 ps
CPU time 3.13 seconds
Started Sep 11 05:03:14 AM UTC 24
Finished Sep 11 05:03:19 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009334019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.1009334019
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.74060204
Short name T632
Test name
Test status
Simulation time 2512264275 ps
CPU time 2.68 seconds
Started Sep 11 05:03:13 AM UTC 24
Finished Sep 11 05:03:17 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74060204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.74060204
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2842829249
Short name T628
Test name
Test status
Simulation time 2300213003 ps
CPU time 1.6 seconds
Started Sep 11 05:03:13 AM UTC 24
Finished Sep 11 05:03:15 AM UTC 24
Peak memory 208236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842829249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2842829249
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.3324932135
Short name T638
Test name
Test status
Simulation time 2511943102 ps
CPU time 10.2 seconds
Started Sep 11 05:03:13 AM UTC 24
Finished Sep 11 05:03:24 AM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324932135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.3324932135
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.4237943212
Short name T631
Test name
Test status
Simulation time 2131636296 ps
CPU time 3.69 seconds
Started Sep 11 05:03:12 AM UTC 24
Finished Sep 11 05:03:16 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237943212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.4237943212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2028984325
Short name T185
Test name
Test status
Simulation time 24345760705 ps
CPU time 15.12 seconds
Started Sep 11 05:03:17 AM UTC 24
Finished Sep 11 05:03:34 AM UTC 24
Peak memory 220792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2028984325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.2028984325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.433376261
Short name T151
Test name
Test status
Simulation time 10820767052 ps
CPU time 3.75 seconds
Started Sep 11 05:03:16 AM UTC 24
Finished Sep 11 05:03:21 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433376261 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.433376261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.819867519
Short name T177
Test name
Test status
Simulation time 2024891993 ps
CPU time 3.25 seconds
Started Sep 11 04:58:47 AM UTC 24
Finished Sep 11 04:58:52 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819867519 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.819867519
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1007536932
Short name T59
Test name
Test status
Simulation time 3900279347 ps
CPU time 10.91 seconds
Started Sep 11 04:58:42 AM UTC 24
Finished Sep 11 04:58:54 AM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007536932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.1007536932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3840222452
Short name T121
Test name
Test status
Simulation time 160785628400 ps
CPU time 70.13 seconds
Started Sep 11 04:58:43 AM UTC 24
Finished Sep 11 04:59:55 AM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840222452 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.3840222452
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.189274903
Short name T130
Test name
Test status
Simulation time 2412253920 ps
CPU time 12.04 seconds
Started Sep 11 04:58:38 AM UTC 24
Finished Sep 11 04:58:52 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189274903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.189274903
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2066495979
Short name T84
Test name
Test status
Simulation time 2533940113 ps
CPU time 2.64 seconds
Started Sep 11 04:58:38 AM UTC 24
Finished Sep 11 04:58:42 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066495979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2066495979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3930372468
Short name T52
Test name
Test status
Simulation time 86003627659 ps
CPU time 49.64 seconds
Started Sep 11 04:58:44 AM UTC 24
Finished Sep 11 04:59:35 AM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930372468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_with_pre_cond.3930372468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3957443313
Short name T175
Test name
Test status
Simulation time 3332754641 ps
CPU time 6.01 seconds
Started Sep 11 04:58:42 AM UTC 24
Finished Sep 11 04:58:49 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957443313 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.3957443313
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.811366104
Short name T50
Test name
Test status
Simulation time 3271122580 ps
CPU time 13.1 seconds
Started Sep 11 04:58:44 AM UTC 24
Finished Sep 11 04:58:58 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811366104 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.811366104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2002957508
Short name T195
Test name
Test status
Simulation time 2646304312 ps
CPU time 2.75 seconds
Started Sep 11 04:58:40 AM UTC 24
Finished Sep 11 04:58:43 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002957508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.2002957508
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.4227572867
Short name T74
Test name
Test status
Simulation time 2467289615 ps
CPU time 6.57 seconds
Started Sep 11 04:58:36 AM UTC 24
Finished Sep 11 04:58:44 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227572867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.4227572867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.3357006016
Short name T299
Test name
Test status
Simulation time 2067981702 ps
CPU time 3.45 seconds
Started Sep 11 04:58:40 AM UTC 24
Finished Sep 11 04:58:44 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357006016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.3357006016
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2758553102
Short name T79
Test name
Test status
Simulation time 2516810035 ps
CPU time 6.97 seconds
Started Sep 11 04:58:40 AM UTC 24
Finished Sep 11 04:58:48 AM UTC 24
Peak memory 210016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758553102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.2758553102
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.3080056741
Short name T263
Test name
Test status
Simulation time 42126481780 ps
CPU time 40.86 seconds
Started Sep 11 04:58:45 AM UTC 24
Finished Sep 11 04:59:28 AM UTC 24
Peak memory 238228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080056741 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.3080056741
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.1374738718
Short name T174
Test name
Test status
Simulation time 2114195458 ps
CPU time 11.39 seconds
Started Sep 11 04:58:35 AM UTC 24
Finished Sep 11 04:58:48 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374738718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.1374738718
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.3201454014
Short name T76
Test name
Test status
Simulation time 9210986754 ps
CPU time 13.94 seconds
Started Sep 11 04:58:45 AM UTC 24
Finished Sep 11 04:59:00 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201454014 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.3201454014
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.4138496104
Short name T216
Test name
Test status
Simulation time 8824138163 ps
CPU time 7.04 seconds
Started Sep 11 04:58:45 AM UTC 24
Finished Sep 11 04:58:53 AM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4138496104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.4138496104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.3569809685
Short name T646
Test name
Test status
Simulation time 2028714802 ps
CPU time 2.7 seconds
Started Sep 11 05:03:28 AM UTC 24
Finished Sep 11 05:03:32 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569809685 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.3569809685
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1866432806
Short name T653
Test name
Test status
Simulation time 3721694884 ps
CPU time 12.24 seconds
Started Sep 11 05:03:24 AM UTC 24
Finished Sep 11 05:03:37 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866432806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.1866432806
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.3040906710
Short name T254
Test name
Test status
Simulation time 178748143230 ps
CPU time 431.43 seconds
Started Sep 11 05:03:25 AM UTC 24
Finished Sep 11 05:10:42 AM UTC 24
Peak memory 210544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040906710 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.3040906710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1287984445
Short name T350
Test name
Test status
Simulation time 42739334469 ps
CPU time 10.47 seconds
Started Sep 11 05:03:26 AM UTC 24
Finished Sep 11 05:03:38 AM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287984445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_with_pre_cond.1287984445
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4245647991
Short name T656
Test name
Test status
Simulation time 3328897050 ps
CPU time 16.13 seconds
Started Sep 11 05:03:23 AM UTC 24
Finished Sep 11 05:03:40 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245647991 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.4245647991
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.665891615
Short name T212
Test name
Test status
Simulation time 4171914198 ps
CPU time 2.8 seconds
Started Sep 11 05:03:25 AM UTC 24
Finished Sep 11 05:03:29 AM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665891615 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.665891615
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3399346317
Short name T640
Test name
Test status
Simulation time 2671335512 ps
CPU time 1.86 seconds
Started Sep 11 05:03:22 AM UTC 24
Finished Sep 11 05:03:25 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399346317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3399346317
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.1408305084
Short name T636
Test name
Test status
Simulation time 2559800709 ps
CPU time 1.7 seconds
Started Sep 11 05:03:19 AM UTC 24
Finished Sep 11 05:03:21 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408305084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.1408305084
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.2579888037
Short name T645
Test name
Test status
Simulation time 2086891157 ps
CPU time 8.06 seconds
Started Sep 11 05:03:20 AM UTC 24
Finished Sep 11 05:03:29 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579888037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.2579888037
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2553411374
Short name T644
Test name
Test status
Simulation time 2515992674 ps
CPU time 5.2 seconds
Started Sep 11 05:03:22 AM UTC 24
Finished Sep 11 05:03:28 AM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553411374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.2553411374
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.1475780926
Short name T642
Test name
Test status
Simulation time 2115518388 ps
CPU time 5.89 seconds
Started Sep 11 05:03:19 AM UTC 24
Finished Sep 11 05:03:26 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475780926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.1475780926
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3260956573
Short name T298
Test name
Test status
Simulation time 8692219758 ps
CPU time 11.05 seconds
Started Sep 11 05:03:26 AM UTC 24
Finished Sep 11 05:03:39 AM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3260956573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.3260956573
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3131350016
Short name T651
Test name
Test status
Simulation time 5398714328 ps
CPU time 7.15 seconds
Started Sep 11 05:03:25 AM UTC 24
Finished Sep 11 05:03:33 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131350016 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.3131350016
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.2842176533
Short name T665
Test name
Test status
Simulation time 2010024130 ps
CPU time 7.77 seconds
Started Sep 11 05:03:37 AM UTC 24
Finished Sep 11 05:03:46 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842176533 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.2842176533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3118938463
Short name T664
Test name
Test status
Simulation time 3492045638 ps
CPU time 10.43 seconds
Started Sep 11 05:03:33 AM UTC 24
Finished Sep 11 05:03:45 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118938463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.3118938463
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.28422248
Short name T772
Test name
Test status
Simulation time 106396939281 ps
CPU time 243.14 seconds
Started Sep 11 05:03:34 AM UTC 24
Finished Sep 11 05:07:42 AM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28422248 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.28422248
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.426852907
Short name T204
Test name
Test status
Simulation time 68201543064 ps
CPU time 73.98 seconds
Started Sep 11 05:03:34 AM UTC 24
Finished Sep 11 05:04:51 AM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426852907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_with_pre_cond.426852907
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2996614773
Short name T658
Test name
Test status
Simulation time 2874403401 ps
CPU time 7.49 seconds
Started Sep 11 05:03:33 AM UTC 24
Finished Sep 11 05:03:42 AM UTC 24
Peak memory 210260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996614773 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.2996614773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.2448559328
Short name T218
Test name
Test status
Simulation time 3398155005 ps
CPU time 10.75 seconds
Started Sep 11 05:03:34 AM UTC 24
Finished Sep 11 05:03:47 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448559328 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.2448559328
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1483304385
Short name T661
Test name
Test status
Simulation time 2608821704 ps
CPU time 10.09 seconds
Started Sep 11 05:03:32 AM UTC 24
Finished Sep 11 05:03:44 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483304385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.1483304385
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2334199784
Short name T649
Test name
Test status
Simulation time 2490326675 ps
CPU time 2.14 seconds
Started Sep 11 05:03:30 AM UTC 24
Finished Sep 11 05:03:33 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334199784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.2334199784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1212554411
Short name T650
Test name
Test status
Simulation time 2289840728 ps
CPU time 2.38 seconds
Started Sep 11 05:03:30 AM UTC 24
Finished Sep 11 05:03:33 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212554411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1212554411
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.1492098030
Short name T652
Test name
Test status
Simulation time 2578873580 ps
CPU time 2.11 seconds
Started Sep 11 05:03:32 AM UTC 24
Finished Sep 11 05:03:36 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492098030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.1492098030
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.2029463169
Short name T648
Test name
Test status
Simulation time 2127733339 ps
CPU time 3.14 seconds
Started Sep 11 05:03:29 AM UTC 24
Finished Sep 11 05:03:33 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029463169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.2029463169
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.2569435209
Short name T251
Test name
Test status
Simulation time 61784317824 ps
CPU time 98.75 seconds
Started Sep 11 05:03:36 AM UTC 24
Finished Sep 11 05:05:16 AM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569435209 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.2569435209
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3118320995
Short name T654
Test name
Test status
Simulation time 14821562596 ps
CPU time 3.23 seconds
Started Sep 11 05:03:34 AM UTC 24
Finished Sep 11 05:03:39 AM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3118320995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.3118320995
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.884206414
Short name T655
Test name
Test status
Simulation time 6367739068 ps
CPU time 3.71 seconds
Started Sep 11 05:03:34 AM UTC 24
Finished Sep 11 05:03:40 AM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884206414 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.884206414
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.3957870820
Short name T676
Test name
Test status
Simulation time 2014142058 ps
CPU time 10.13 seconds
Started Sep 11 05:03:45 AM UTC 24
Finished Sep 11 05:03:56 AM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957870820 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.3957870820
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1051530906
Short name T663
Test name
Test status
Simulation time 3252670527 ps
CPU time 2.75 seconds
Started Sep 11 05:03:40 AM UTC 24
Finished Sep 11 05:03:44 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051530906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.1051530906
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.904633488
Short name T765
Test name
Test status
Simulation time 153222098039 ps
CPU time 201.21 seconds
Started Sep 11 05:03:42 AM UTC 24
Finished Sep 11 05:07:06 AM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904633488 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.904633488
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3548812393
Short name T668
Test name
Test status
Simulation time 4710472367 ps
CPU time 6.7 seconds
Started Sep 11 05:03:40 AM UTC 24
Finished Sep 11 05:03:48 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548812393 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.3548812393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.1436464463
Short name T666
Test name
Test status
Simulation time 2615138355 ps
CPU time 3.02 seconds
Started Sep 11 05:03:42 AM UTC 24
Finished Sep 11 05:03:46 AM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436464463 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.1436464463
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2598984050
Short name T660
Test name
Test status
Simulation time 2628048756 ps
CPU time 3.65 seconds
Started Sep 11 05:03:39 AM UTC 24
Finished Sep 11 05:03:44 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598984050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.2598984050
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1156366257
Short name T657
Test name
Test status
Simulation time 2480318734 ps
CPU time 2.69 seconds
Started Sep 11 05:03:38 AM UTC 24
Finished Sep 11 05:03:41 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156366257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.1156366257
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1321349634
Short name T659
Test name
Test status
Simulation time 2099476526 ps
CPU time 3.04 seconds
Started Sep 11 05:03:39 AM UTC 24
Finished Sep 11 05:03:43 AM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321349634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1321349634
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.2635701152
Short name T662
Test name
Test status
Simulation time 2537560029 ps
CPU time 3.71 seconds
Started Sep 11 05:03:39 AM UTC 24
Finished Sep 11 05:03:44 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635701152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.2635701152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.1628815656
Short name T667
Test name
Test status
Simulation time 2111954516 ps
CPU time 8.74 seconds
Started Sep 11 05:03:38 AM UTC 24
Finished Sep 11 05:03:48 AM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628815656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.1628815656
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.1587096960
Short name T714
Test name
Test status
Simulation time 12145916650 ps
CPU time 48.15 seconds
Started Sep 11 05:03:44 AM UTC 24
Finished Sep 11 05:04:33 AM UTC 24
Peak memory 209928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587096960 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.1587096960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1788520495
Short name T684
Test name
Test status
Simulation time 4772141776 ps
CPU time 21.42 seconds
Started Sep 11 05:03:44 AM UTC 24
Finished Sep 11 05:04:06 AM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1788520495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.1788520495
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1266894356
Short name T674
Test name
Test status
Simulation time 3824883009 ps
CPU time 11.05 seconds
Started Sep 11 05:03:41 AM UTC 24
Finished Sep 11 05:03:53 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266894356 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.1266894356
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.4208954832
Short name T681
Test name
Test status
Simulation time 2013314796 ps
CPU time 9.87 seconds
Started Sep 11 05:03:50 AM UTC 24
Finished Sep 11 05:04:00 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208954832 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.4208954832
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1907027802
Short name T672
Test name
Test status
Simulation time 3435992768 ps
CPU time 3.59 seconds
Started Sep 11 05:03:47 AM UTC 24
Finished Sep 11 05:03:52 AM UTC 24
Peak memory 209928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907027802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.1907027802
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.94679374
Short name T782
Test name
Test status
Simulation time 133790045475 ps
CPU time 412.93 seconds
Started Sep 11 05:03:47 AM UTC 24
Finished Sep 11 05:10:45 AM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94679374 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.94679374
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2301164395
Short name T351
Test name
Test status
Simulation time 75841204165 ps
CPU time 38.37 seconds
Started Sep 11 05:03:48 AM UTC 24
Finished Sep 11 05:04:28 AM UTC 24
Peak memory 210556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301164395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_with_pre_cond.2301164395
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.592192774
Short name T777
Test name
Test status
Simulation time 96680679348 ps
CPU time 301.43 seconds
Started Sep 11 05:03:46 AM UTC 24
Finished Sep 11 05:08:52 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592192774 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.592192774
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.3572758998
Short name T680
Test name
Test status
Simulation time 2752433341 ps
CPU time 10.63 seconds
Started Sep 11 05:03:48 AM UTC 24
Finished Sep 11 05:04:00 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572758998 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.3572758998
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2274330381
Short name T677
Test name
Test status
Simulation time 2608117355 ps
CPU time 9.31 seconds
Started Sep 11 05:03:46 AM UTC 24
Finished Sep 11 05:03:57 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274330381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2274330381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.1213483750
Short name T673
Test name
Test status
Simulation time 2458537577 ps
CPU time 5.97 seconds
Started Sep 11 05:03:45 AM UTC 24
Finished Sep 11 05:03:52 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213483750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.1213483750
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.4222702824
Short name T669
Test name
Test status
Simulation time 2269638647 ps
CPU time 2.11 seconds
Started Sep 11 05:03:45 AM UTC 24
Finished Sep 11 05:03:48 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222702824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.4222702824
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.1832569311
Short name T671
Test name
Test status
Simulation time 2529061444 ps
CPU time 2.44 seconds
Started Sep 11 05:03:46 AM UTC 24
Finished Sep 11 05:03:50 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832569311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.1832569311
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2071616851
Short name T670
Test name
Test status
Simulation time 2124678088 ps
CPU time 3.09 seconds
Started Sep 11 05:03:45 AM UTC 24
Finished Sep 11 05:03:49 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071616851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2071616851
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.3333732060
Short name T696
Test name
Test status
Simulation time 11364542397 ps
CPU time 23.24 seconds
Started Sep 11 05:03:50 AM UTC 24
Finished Sep 11 05:04:14 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333732060 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.3333732060
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1186821194
Short name T282
Test name
Test status
Simulation time 9843418627 ps
CPU time 11.77 seconds
Started Sep 11 05:03:48 AM UTC 24
Finished Sep 11 05:04:01 AM UTC 24
Peak memory 226612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1186821194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.1186821194
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1415913762
Short name T140
Test name
Test status
Simulation time 5414205037 ps
CPU time 4.89 seconds
Started Sep 11 05:03:47 AM UTC 24
Finished Sep 11 05:03:53 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415913762 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.1415913762
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1553624661
Short name T687
Test name
Test status
Simulation time 2022112745 ps
CPU time 5.69 seconds
Started Sep 11 05:04:02 AM UTC 24
Finished Sep 11 05:04:09 AM UTC 24
Peak memory 209808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553624661 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.1553624661
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.489959527
Short name T694
Test name
Test status
Simulation time 3096347880 ps
CPU time 16.2 seconds
Started Sep 11 05:03:56 AM UTC 24
Finished Sep 11 05:04:14 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489959527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.489959527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.2247277844
Short name T333
Test name
Test status
Simulation time 121853237212 ps
CPU time 305.71 seconds
Started Sep 11 05:03:57 AM UTC 24
Finished Sep 11 05:09:07 AM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247277844 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.2247277844
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2453387782
Short name T633
Test name
Test status
Simulation time 2622685795 ps
CPU time 3.99 seconds
Started Sep 11 05:03:54 AM UTC 24
Finished Sep 11 05:03:59 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453387782 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.2453387782
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.509181729
Short name T200
Test name
Test status
Simulation time 6229289695 ps
CPU time 13.47 seconds
Started Sep 11 05:03:58 AM UTC 24
Finished Sep 11 05:04:13 AM UTC 24
Peak memory 209856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509181729 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.509181729
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1588935860
Short name T682
Test name
Test status
Simulation time 2611884796 ps
CPU time 7.85 seconds
Started Sep 11 05:03:54 AM UTC 24
Finished Sep 11 05:04:03 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588935860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.1588935860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.4257089818
Short name T679
Test name
Test status
Simulation time 2478379453 ps
CPU time 3.43 seconds
Started Sep 11 05:03:53 AM UTC 24
Finished Sep 11 05:03:57 AM UTC 24
Peak memory 209820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257089818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.4257089818
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.3966524584
Short name T678
Test name
Test status
Simulation time 2089714385 ps
CPU time 3.15 seconds
Started Sep 11 05:03:53 AM UTC 24
Finished Sep 11 05:03:57 AM UTC 24
Peak memory 209788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966524584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.3966524584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3629633611
Short name T683
Test name
Test status
Simulation time 2509531308 ps
CPU time 10.79 seconds
Started Sep 11 05:03:53 AM UTC 24
Finished Sep 11 05:04:05 AM UTC 24
Peak memory 209652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629633611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.3629633611
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.343275759
Short name T675
Test name
Test status
Simulation time 2128114485 ps
CPU time 3.28 seconds
Started Sep 11 05:03:51 AM UTC 24
Finished Sep 11 05:03:55 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343275759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.343275759
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.3556439563
Short name T689
Test name
Test status
Simulation time 9170938890 ps
CPU time 7.56 seconds
Started Sep 11 05:04:01 AM UTC 24
Finished Sep 11 05:04:09 AM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556439563 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.3556439563
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2968609064
Short name T688
Test name
Test status
Simulation time 3623805295 ps
CPU time 10.26 seconds
Started Sep 11 05:03:57 AM UTC 24
Finished Sep 11 05:04:09 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968609064 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.2968609064
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.1904925899
Short name T697
Test name
Test status
Simulation time 2036264516 ps
CPU time 2.63 seconds
Started Sep 11 05:04:13 AM UTC 24
Finished Sep 11 05:04:16 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904925899 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.1904925899
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.960578149
Short name T699
Test name
Test status
Simulation time 3552349769 ps
CPU time 8.65 seconds
Started Sep 11 05:04:08 AM UTC 24
Finished Sep 11 05:04:18 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960578149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.960578149
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.4229070813
Short name T329
Test name
Test status
Simulation time 202635858384 ps
CPU time 166.51 seconds
Started Sep 11 05:04:09 AM UTC 24
Finished Sep 11 05:06:58 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229070813 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.4229070813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2202870078
Short name T723
Test name
Test status
Simulation time 25608487930 ps
CPU time 28.17 seconds
Started Sep 11 05:04:11 AM UTC 24
Finished Sep 11 05:04:40 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202870078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_with_pre_cond.2202870078
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3550384039
Short name T700
Test name
Test status
Simulation time 4108801022 ps
CPU time 9.71 seconds
Started Sep 11 05:04:08 AM UTC 24
Finished Sep 11 05:04:19 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550384039 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.3550384039
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.1227656781
Short name T701
Test name
Test status
Simulation time 2713546679 ps
CPU time 7.55 seconds
Started Sep 11 05:04:11 AM UTC 24
Finished Sep 11 05:04:19 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227656781 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.1227656781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2018062999
Short name T690
Test name
Test status
Simulation time 2792109633 ps
CPU time 1.62 seconds
Started Sep 11 05:04:07 AM UTC 24
Finished Sep 11 05:04:10 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018062999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.2018062999
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.1171923242
Short name T692
Test name
Test status
Simulation time 2470880046 ps
CPU time 6.85 seconds
Started Sep 11 05:04:04 AM UTC 24
Finished Sep 11 05:04:12 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171923242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.1171923242
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.1091296433
Short name T695
Test name
Test status
Simulation time 2231466965 ps
CPU time 8.96 seconds
Started Sep 11 05:04:04 AM UTC 24
Finished Sep 11 05:04:14 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091296433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.1091296433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.2270780984
Short name T691
Test name
Test status
Simulation time 2514486606 ps
CPU time 4.03 seconds
Started Sep 11 05:04:06 AM UTC 24
Finished Sep 11 05:04:11 AM UTC 24
Peak memory 209888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270780984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.2270780984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.520399291
Short name T686
Test name
Test status
Simulation time 2110695286 ps
CPU time 4.87 seconds
Started Sep 11 05:04:02 AM UTC 24
Finished Sep 11 05:04:08 AM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520399291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.520399291
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.1888000973
Short name T253
Test name
Test status
Simulation time 45281879964 ps
CPU time 142.36 seconds
Started Sep 11 05:04:13 AM UTC 24
Finished Sep 11 05:06:37 AM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888000973 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.1888000973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2008491293
Short name T162
Test name
Test status
Simulation time 14039319684 ps
CPU time 12.93 seconds
Started Sep 11 05:04:12 AM UTC 24
Finished Sep 11 05:04:26 AM UTC 24
Peak memory 226448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2008491293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.2008491293
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.147057541
Short name T693
Test name
Test status
Simulation time 5195026742 ps
CPU time 2.4 seconds
Started Sep 11 05:04:09 AM UTC 24
Finished Sep 11 05:04:13 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147057541 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.147057541
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3621906041
Short name T707
Test name
Test status
Simulation time 2031857424 ps
CPU time 3.1 seconds
Started Sep 11 05:04:22 AM UTC 24
Finished Sep 11 05:04:26 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621906041 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.3621906041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3259352287
Short name T704
Test name
Test status
Simulation time 3607268066 ps
CPU time 4.97 seconds
Started Sep 11 05:04:18 AM UTC 24
Finished Sep 11 05:04:24 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259352287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.3259352287
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.2114271223
Short name T357
Test name
Test status
Simulation time 46679077865 ps
CPU time 77.61 seconds
Started Sep 11 05:04:19 AM UTC 24
Finished Sep 11 05:05:39 AM UTC 24
Peak memory 210236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114271223 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.2114271223
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.344302600
Short name T343
Test name
Test status
Simulation time 52617572899 ps
CPU time 36.42 seconds
Started Sep 11 05:04:21 AM UTC 24
Finished Sep 11 05:04:58 AM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344302600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_with_pre_cond.344302600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3399552591
Short name T715
Test name
Test status
Simulation time 3425478616 ps
CPU time 15.6 seconds
Started Sep 11 05:04:17 AM UTC 24
Finished Sep 11 05:04:34 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399552591 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.3399552591
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.511465277
Short name T709
Test name
Test status
Simulation time 2495303948 ps
CPU time 6.75 seconds
Started Sep 11 05:04:21 AM UTC 24
Finished Sep 11 05:04:28 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511465277 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.511465277
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1679150102
Short name T705
Test name
Test status
Simulation time 2613030709 ps
CPU time 9 seconds
Started Sep 11 05:04:15 AM UTC 24
Finished Sep 11 05:04:25 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679150102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.1679150102
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.2741148063
Short name T698
Test name
Test status
Simulation time 2470361597 ps
CPU time 2.52 seconds
Started Sep 11 05:04:14 AM UTC 24
Finished Sep 11 05:04:17 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741148063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.2741148063
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.339680564
Short name T703
Test name
Test status
Simulation time 2105898706 ps
CPU time 4.16 seconds
Started Sep 11 05:04:15 AM UTC 24
Finished Sep 11 05:04:20 AM UTC 24
Peak memory 209808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339680564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.339680564
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.586107991
Short name T702
Test name
Test status
Simulation time 2536899673 ps
CPU time 3.78 seconds
Started Sep 11 05:04:15 AM UTC 24
Finished Sep 11 05:04:20 AM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586107991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.586107991
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.1592531960
Short name T706
Test name
Test status
Simulation time 2110564961 ps
CPU time 10.65 seconds
Started Sep 11 05:04:14 AM UTC 24
Finished Sep 11 05:04:26 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592531960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.1592531960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.299122904
Short name T713
Test name
Test status
Simulation time 9386875570 ps
CPU time 11.25 seconds
Started Sep 11 05:04:21 AM UTC 24
Finished Sep 11 05:04:33 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299122904 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.299122904
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2007237255
Short name T203
Test name
Test status
Simulation time 5691053253 ps
CPU time 28.12 seconds
Started Sep 11 05:04:21 AM UTC 24
Finished Sep 11 05:04:50 AM UTC 24
Peak memory 226556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2007237255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.2007237255
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.778772468
Short name T372
Test name
Test status
Simulation time 1837865843830 ps
CPU time 247.27 seconds
Started Sep 11 05:04:18 AM UTC 24
Finished Sep 11 05:08:29 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778772468 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.778772468
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.1963232441
Short name T718
Test name
Test status
Simulation time 2030183208 ps
CPU time 3.02 seconds
Started Sep 11 05:04:34 AM UTC 24
Finished Sep 11 05:04:38 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963232441 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.1963232441
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1872431459
Short name T716
Test name
Test status
Simulation time 2841703510 ps
CPU time 3.82 seconds
Started Sep 11 05:04:29 AM UTC 24
Finished Sep 11 05:04:34 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872431459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.1872431459
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.284382180
Short name T238
Test name
Test status
Simulation time 149477995908 ps
CPU time 54.64 seconds
Started Sep 11 05:04:30 AM UTC 24
Finished Sep 11 05:05:26 AM UTC 24
Peak memory 210224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284382180 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.284382180
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.4201154552
Short name T720
Test name
Test status
Simulation time 2899730241 ps
CPU time 9.94 seconds
Started Sep 11 05:04:27 AM UTC 24
Finished Sep 11 05:04:38 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201154552 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.4201154552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.2339563943
Short name T219
Test name
Test status
Simulation time 4433479261 ps
CPU time 4.65 seconds
Started Sep 11 05:04:31 AM UTC 24
Finished Sep 11 05:04:36 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339563943 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.2339563943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1164731149
Short name T712
Test name
Test status
Simulation time 2647857978 ps
CPU time 2.79 seconds
Started Sep 11 05:04:26 AM UTC 24
Finished Sep 11 05:04:30 AM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164731149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.1164731149
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.3752521250
Short name T708
Test name
Test status
Simulation time 2505307142 ps
CPU time 2.15 seconds
Started Sep 11 05:04:25 AM UTC 24
Finished Sep 11 05:04:28 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752521250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.3752521250
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.3369830279
Short name T710
Test name
Test status
Simulation time 2040482460 ps
CPU time 2.57 seconds
Started Sep 11 05:04:26 AM UTC 24
Finished Sep 11 05:04:30 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369830279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.3369830279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.2059359722
Short name T721
Test name
Test status
Simulation time 2510502658 ps
CPU time 11.41 seconds
Started Sep 11 05:04:26 AM UTC 24
Finished Sep 11 05:04:39 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059359722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.2059359722
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.2905232848
Short name T711
Test name
Test status
Simulation time 2122626086 ps
CPU time 4.93 seconds
Started Sep 11 05:04:24 AM UTC 24
Finished Sep 11 05:04:30 AM UTC 24
Peak memory 210136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905232848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.2905232848
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1470077983
Short name T776
Test name
Test status
Simulation time 499952989321 ps
CPU time 235.35 seconds
Started Sep 11 05:04:34 AM UTC 24
Finished Sep 11 05:08:33 AM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470077983 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.1470077983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2592224107
Short name T209
Test name
Test status
Simulation time 16203899558 ps
CPU time 20.29 seconds
Started Sep 11 05:04:31 AM UTC 24
Finished Sep 11 05:04:52 AM UTC 24
Peak memory 222504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2592224107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.2592224107
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1073364110
Short name T719
Test name
Test status
Simulation time 7333652707 ps
CPU time 7.44 seconds
Started Sep 11 05:04:30 AM UTC 24
Finished Sep 11 05:04:38 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073364110 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.1073364110
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.2854851684
Short name T729
Test name
Test status
Simulation time 2013743058 ps
CPU time 8.53 seconds
Started Sep 11 05:04:46 AM UTC 24
Finished Sep 11 05:04:56 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854851684 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.2854851684
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3206426955
Short name T206
Test name
Test status
Simulation time 3237201911 ps
CPU time 9.65 seconds
Started Sep 11 05:04:40 AM UTC 24
Finished Sep 11 05:04:51 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206426955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.3206426955
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.3488458889
Short name T774
Test name
Test status
Simulation time 124381363816 ps
CPU time 183.66 seconds
Started Sep 11 05:04:40 AM UTC 24
Finished Sep 11 05:07:47 AM UTC 24
Peak memory 210104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488458889 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.3488458889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.822190440
Short name T734
Test name
Test status
Simulation time 21351477338 ps
CPU time 16.9 seconds
Started Sep 11 05:04:41 AM UTC 24
Finished Sep 11 05:04:59 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822190440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_with_pre_cond.822190440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3597781385
Short name T202
Test name
Test status
Simulation time 3157858221 ps
CPU time 8.45 seconds
Started Sep 11 05:04:39 AM UTC 24
Finished Sep 11 05:04:49 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597781385 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.3597781385
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2787922836
Short name T725
Test name
Test status
Simulation time 2625103435 ps
CPU time 3.72 seconds
Started Sep 11 05:04:39 AM UTC 24
Finished Sep 11 05:04:45 AM UTC 24
Peak memory 210008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787922836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.2787922836
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.2559220665
Short name T722
Test name
Test status
Simulation time 2509159503 ps
CPU time 2.45 seconds
Started Sep 11 05:04:35 AM UTC 24
Finished Sep 11 05:04:39 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559220665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.2559220665
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.934652660
Short name T724
Test name
Test status
Simulation time 2186774361 ps
CPU time 2.11 seconds
Started Sep 11 05:04:37 AM UTC 24
Finished Sep 11 05:04:40 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934652660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.934652660
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3216401178
Short name T207
Test name
Test status
Simulation time 2509439718 ps
CPU time 11.56 seconds
Started Sep 11 05:04:38 AM UTC 24
Finished Sep 11 05:04:51 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216401178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.3216401178
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.2414221592
Short name T717
Test name
Test status
Simulation time 2254024204 ps
CPU time 1.31 seconds
Started Sep 11 05:04:35 AM UTC 24
Finished Sep 11 05:04:38 AM UTC 24
Peak memory 208176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414221592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.2414221592
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.924494698
Short name T739
Test name
Test status
Simulation time 10545022786 ps
CPU time 19.85 seconds
Started Sep 11 05:04:45 AM UTC 24
Finished Sep 11 05:05:06 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924494698 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.924494698
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1898666726
Short name T727
Test name
Test status
Simulation time 2892499056 ps
CPU time 13.23 seconds
Started Sep 11 05:04:41 AM UTC 24
Finished Sep 11 05:04:56 AM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1898666726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.1898666726
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.161950736
Short name T726
Test name
Test status
Simulation time 4033092065 ps
CPU time 3.76 seconds
Started Sep 11 05:04:40 AM UTC 24
Finished Sep 11 05:04:45 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161950736 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.161950736
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.29415539
Short name T736
Test name
Test status
Simulation time 2028524980 ps
CPU time 3.16 seconds
Started Sep 11 05:04:57 AM UTC 24
Finished Sep 11 05:05:01 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29415539 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.29415539
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4012225097
Short name T737
Test name
Test status
Simulation time 3486102675 ps
CPU time 8.62 seconds
Started Sep 11 05:04:53 AM UTC 24
Finished Sep 11 05:05:03 AM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012225097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.4012225097
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.3775140932
Short name T262
Test name
Test status
Simulation time 172665025122 ps
CPU time 474.94 seconds
Started Sep 11 05:04:54 AM UTC 24
Finished Sep 11 05:12:54 AM UTC 24
Peak memory 213088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775140932 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.3775140932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3229929094
Short name T743
Test name
Test status
Simulation time 20836264794 ps
CPU time 43.27 seconds
Started Sep 11 05:04:57 AM UTC 24
Finished Sep 11 05:05:42 AM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229929094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_with_pre_cond.3229929094
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3274678693
Short name T732
Test name
Test status
Simulation time 3647497183 ps
CPU time 4.26 seconds
Started Sep 11 05:04:51 AM UTC 24
Finished Sep 11 05:04:57 AM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274678693 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.3274678693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.2190799994
Short name T201
Test name
Test status
Simulation time 4413973929 ps
CPU time 3.86 seconds
Started Sep 11 05:04:57 AM UTC 24
Finished Sep 11 05:05:02 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190799994 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.2190799994
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2094261435
Short name T731
Test name
Test status
Simulation time 2627017081 ps
CPU time 3.85 seconds
Started Sep 11 05:04:51 AM UTC 24
Finished Sep 11 05:04:56 AM UTC 24
Peak memory 210264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094261435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.2094261435
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.1621331708
Short name T733
Test name
Test status
Simulation time 2452668074 ps
CPU time 6.54 seconds
Started Sep 11 05:04:50 AM UTC 24
Finished Sep 11 05:04:58 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621331708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.1621331708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.211548124
Short name T728
Test name
Test status
Simulation time 2042365945 ps
CPU time 3.21 seconds
Started Sep 11 05:04:51 AM UTC 24
Finished Sep 11 05:04:56 AM UTC 24
Peak memory 209804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211548124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.211548124
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.4077649028
Short name T730
Test name
Test status
Simulation time 2525029244 ps
CPU time 3.67 seconds
Started Sep 11 05:04:51 AM UTC 24
Finished Sep 11 05:04:56 AM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077649028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.4077649028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.602795580
Short name T205
Test name
Test status
Simulation time 2157962026 ps
CPU time 1.62 seconds
Started Sep 11 05:04:48 AM UTC 24
Finished Sep 11 05:04:51 AM UTC 24
Peak memory 208232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602795580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.602795580
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.2340168964
Short name T780
Test name
Test status
Simulation time 114138605565 ps
CPU time 317.8 seconds
Started Sep 11 05:04:57 AM UTC 24
Finished Sep 11 05:10:19 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340168964 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.2340168964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.894685456
Short name T283
Test name
Test status
Simulation time 10455177328 ps
CPU time 13.31 seconds
Started Sep 11 05:04:57 AM UTC 24
Finished Sep 11 05:05:12 AM UTC 24
Peak memory 210228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=894685456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.894685456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.401099075
Short name T382
Test name
Test status
Simulation time 2019160380 ps
CPU time 3.53 seconds
Started Sep 11 04:58:54 AM UTC 24
Finished Sep 11 04:58:59 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401099075 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.401099075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.266458762
Short name T380
Test name
Test status
Simulation time 4317162413 ps
CPU time 4.23 seconds
Started Sep 11 04:58:51 AM UTC 24
Finished Sep 11 04:58:56 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266458762 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.266458762
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3545484527
Short name T45
Test name
Test status
Simulation time 3973378298 ps
CPU time 2.74 seconds
Started Sep 11 04:58:52 AM UTC 24
Finished Sep 11 04:58:56 AM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545484527 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.3545484527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.500471686
Short name T214
Test name
Test status
Simulation time 2725083380 ps
CPU time 1.86 seconds
Started Sep 11 04:58:50 AM UTC 24
Finished Sep 11 04:58:53 AM UTC 24
Peak memory 208172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500471686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.500471686
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.2347445287
Short name T378
Test name
Test status
Simulation time 2459336189 ps
CPU time 11.75 seconds
Started Sep 11 04:58:48 AM UTC 24
Finished Sep 11 04:59:01 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347445287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.2347445287
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.3919663782
Short name T381
Test name
Test status
Simulation time 2140349812 ps
CPU time 8.9 seconds
Started Sep 11 04:58:49 AM UTC 24
Finished Sep 11 04:58:58 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919663782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.3919663782
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.2877664306
Short name T215
Test name
Test status
Simulation time 2119709554 ps
CPU time 3.45 seconds
Started Sep 11 04:58:48 AM UTC 24
Finished Sep 11 04:58:53 AM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877664306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.2877664306
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1821116993
Short name T287
Test name
Test status
Simulation time 8071416195 ps
CPU time 18.28 seconds
Started Sep 11 04:58:53 AM UTC 24
Finished Sep 11 04:59:13 AM UTC 24
Peak memory 222448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1821116993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.1821116993
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3778519387
Short name T66
Test name
Test status
Simulation time 2971370163 ps
CPU time 2.66 seconds
Started Sep 11 04:58:51 AM UTC 24
Finished Sep 11 04:58:54 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778519387 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.3778519387
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3015338502
Short name T741
Test name
Test status
Simulation time 24091702080 ps
CPU time 32.08 seconds
Started Sep 11 05:04:57 AM UTC 24
Finished Sep 11 05:05:31 AM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015338502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_with_pre_cond.3015338502
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3631321017
Short name T775
Test name
Test status
Simulation time 58924258860 ps
CPU time 176.93 seconds
Started Sep 11 05:04:58 AM UTC 24
Finished Sep 11 05:07:58 AM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631321017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_with_pre_cond.3631321017
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.899174618
Short name T756
Test name
Test status
Simulation time 28333870252 ps
CPU time 104.88 seconds
Started Sep 11 05:04:59 AM UTC 24
Finished Sep 11 05:06:46 AM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899174618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_with_pre_cond.899174618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.629825859
Short name T103
Test name
Test status
Simulation time 116269592837 ps
CPU time 115.58 seconds
Started Sep 11 05:04:59 AM UTC 24
Finished Sep 11 05:06:57 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629825859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_with_pre_cond.629825859
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.4233493569
Short name T766
Test name
Test status
Simulation time 44934281240 ps
CPU time 126.25 seconds
Started Sep 11 05:05:00 AM UTC 24
Finished Sep 11 05:07:09 AM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233493569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_with_pre_cond.4233493569
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1107994128
Short name T748
Test name
Test status
Simulation time 26082898844 ps
CPU time 78.53 seconds
Started Sep 11 05:05:01 AM UTC 24
Finished Sep 11 05:06:22 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107994128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_with_pre_cond.1107994128
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1964670569
Short name T761
Test name
Test status
Simulation time 27331107639 ps
CPU time 115.38 seconds
Started Sep 11 05:05:03 AM UTC 24
Finished Sep 11 05:07:00 AM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964670569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_with_pre_cond.1964670569
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3555367105
Short name T99
Test name
Test status
Simulation time 50353728159 ps
CPU time 48.98 seconds
Started Sep 11 05:05:03 AM UTC 24
Finished Sep 11 05:05:53 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555367105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_with_pre_cond.3555367105
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3208931788
Short name T757
Test name
Test status
Simulation time 30333304288 ps
CPU time 107.98 seconds
Started Sep 11 05:05:04 AM UTC 24
Finished Sep 11 05:06:54 AM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208931788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_with_pre_cond.3208931788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.3264375964
Short name T385
Test name
Test status
Simulation time 2024639265 ps
CPU time 2.88 seconds
Started Sep 11 04:59:01 AM UTC 24
Finished Sep 11 04:59:05 AM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264375964 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.3264375964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.654449979
Short name T60
Test name
Test status
Simulation time 3445306625 ps
CPU time 5.05 seconds
Started Sep 11 04:58:57 AM UTC 24
Finished Sep 11 04:59:03 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654449979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.654449979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2725030904
Short name T86
Test name
Test status
Simulation time 56232106547 ps
CPU time 42.59 seconds
Started Sep 11 04:59:00 AM UTC 24
Finished Sep 11 04:59:44 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725030904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_with_pre_cond.2725030904
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1413341272
Short name T388
Test name
Test status
Simulation time 2851443195 ps
CPU time 9.04 seconds
Started Sep 11 04:58:57 AM UTC 24
Finished Sep 11 04:59:07 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413341272 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.1413341272
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2781964861
Short name T49
Test name
Test status
Simulation time 3665282492 ps
CPU time 11.63 seconds
Started Sep 11 04:59:00 AM UTC 24
Finished Sep 11 04:59:13 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781964861 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.2781964861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1215902938
Short name T390
Test name
Test status
Simulation time 2611405271 ps
CPU time 12.21 seconds
Started Sep 11 04:58:56 AM UTC 24
Finished Sep 11 04:59:09 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215902938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.1215902938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.2947277089
Short name T293
Test name
Test status
Simulation time 2481246720 ps
CPU time 3.8 seconds
Started Sep 11 04:58:55 AM UTC 24
Finished Sep 11 04:59:00 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947277089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.2947277089
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.428983039
Short name T383
Test name
Test status
Simulation time 2100652863 ps
CPU time 3.51 seconds
Started Sep 11 04:58:56 AM UTC 24
Finished Sep 11 04:59:00 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428983039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.428983039
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.837016979
Short name T375
Test name
Test status
Simulation time 2512283086 ps
CPU time 9.64 seconds
Started Sep 11 04:58:56 AM UTC 24
Finished Sep 11 04:59:06 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837016979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.837016979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.2588685932
Short name T384
Test name
Test status
Simulation time 2110738954 ps
CPU time 7.67 seconds
Started Sep 11 04:58:54 AM UTC 24
Finished Sep 11 04:59:03 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588685932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.2588685932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.3017669286
Short name T264
Test name
Test status
Simulation time 8740369650 ps
CPU time 17.02 seconds
Started Sep 11 04:59:01 AM UTC 24
Finished Sep 11 04:59:20 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017669286 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.3017669286
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1804583289
Short name T271
Test name
Test status
Simulation time 6364986362 ps
CPU time 18.94 seconds
Started Sep 11 04:59:01 AM UTC 24
Finished Sep 11 04:59:21 AM UTC 24
Peak memory 220796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1804583289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.1804583289
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.275139326
Short name T67
Test name
Test status
Simulation time 9246818451 ps
CPU time 3.48 seconds
Started Sep 11 04:58:59 AM UTC 24
Finished Sep 11 04:59:04 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275139326 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.275139326
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3690630066
Short name T740
Test name
Test status
Simulation time 37923675033 ps
CPU time 22.33 seconds
Started Sep 11 05:05:07 AM UTC 24
Finished Sep 11 05:05:30 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690630066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_with_pre_cond.3690630066
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1347379666
Short name T744
Test name
Test status
Simulation time 52902427044 ps
CPU time 35.26 seconds
Started Sep 11 05:05:10 AM UTC 24
Finished Sep 11 05:05:47 AM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347379666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_with_pre_cond.1347379666
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1708617718
Short name T773
Test name
Test status
Simulation time 88134947074 ps
CPU time 150.98 seconds
Started Sep 11 05:05:10 AM UTC 24
Finished Sep 11 05:07:43 AM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708617718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_with_pre_cond.1708617718
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3706482898
Short name T767
Test name
Test status
Simulation time 25578101854 ps
CPU time 114.86 seconds
Started Sep 11 05:05:12 AM UTC 24
Finished Sep 11 05:07:09 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706482898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_with_pre_cond.3706482898
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2676443556
Short name T349
Test name
Test status
Simulation time 207250811617 ps
CPU time 165.58 seconds
Started Sep 11 05:05:12 AM UTC 24
Finished Sep 11 05:08:00 AM UTC 24
Peak memory 210176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676443556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_with_pre_cond.2676443556
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3764453833
Short name T745
Test name
Test status
Simulation time 47214404396 ps
CPU time 40.47 seconds
Started Sep 11 05:05:17 AM UTC 24
Finished Sep 11 05:05:59 AM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764453833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_with_pre_cond.3764453833
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3137116493
Short name T762
Test name
Test status
Simulation time 26582289882 ps
CPU time 94.32 seconds
Started Sep 11 05:05:27 AM UTC 24
Finished Sep 11 05:07:03 AM UTC 24
Peak memory 210176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137116493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_with_pre_cond.3137116493
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1992395451
Short name T768
Test name
Test status
Simulation time 68665985863 ps
CPU time 98.43 seconds
Started Sep 11 05:05:32 AM UTC 24
Finished Sep 11 05:07:12 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992395451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_with_pre_cond.1992395451
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2411100420
Short name T341
Test name
Test status
Simulation time 71177402570 ps
CPU time 88.88 seconds
Started Sep 11 05:05:32 AM UTC 24
Finished Sep 11 05:07:02 AM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411100420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_with_pre_cond.2411100420
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.1731348796
Short name T302
Test name
Test status
Simulation time 2024386920 ps
CPU time 3.48 seconds
Started Sep 11 04:59:09 AM UTC 24
Finished Sep 11 04:59:14 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731348796 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.1731348796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.4031553480
Short name T109
Test name
Test status
Simulation time 3442900045 ps
CPU time 17.17 seconds
Started Sep 11 04:59:07 AM UTC 24
Finished Sep 11 04:59:25 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031553480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.4031553480
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.710730215
Short name T42
Test name
Test status
Simulation time 51868306212 ps
CPU time 71.15 seconds
Started Sep 11 04:59:08 AM UTC 24
Finished Sep 11 05:00:21 AM UTC 24
Peak memory 210104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710730215 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.710730215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3261518331
Short name T89
Test name
Test status
Simulation time 24829596187 ps
CPU time 63.88 seconds
Started Sep 11 04:59:08 AM UTC 24
Finished Sep 11 05:00:14 AM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261518331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_with_pre_cond.3261518331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2370405985
Short name T303
Test name
Test status
Simulation time 2720107170 ps
CPU time 7.87 seconds
Started Sep 11 04:59:06 AM UTC 24
Finished Sep 11 04:59:15 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370405985 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.2370405985
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.2616979739
Short name T51
Test name
Test status
Simulation time 3553009748 ps
CPU time 4.53 seconds
Started Sep 11 04:59:08 AM UTC 24
Finished Sep 11 04:59:14 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616979739 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.2616979739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2953460087
Short name T391
Test name
Test status
Simulation time 2633326096 ps
CPU time 3.66 seconds
Started Sep 11 04:59:05 AM UTC 24
Finished Sep 11 04:59:09 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953460087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.2953460087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.1565764169
Short name T386
Test name
Test status
Simulation time 2498721520 ps
CPU time 2.5 seconds
Started Sep 11 04:59:02 AM UTC 24
Finished Sep 11 04:59:06 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565764169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.1565764169
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.3144033868
Short name T389
Test name
Test status
Simulation time 2044804700 ps
CPU time 3.65 seconds
Started Sep 11 04:59:03 AM UTC 24
Finished Sep 11 04:59:08 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144033868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.3144033868
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.737837365
Short name T295
Test name
Test status
Simulation time 2509973314 ps
CPU time 7.94 seconds
Started Sep 11 04:59:05 AM UTC 24
Finished Sep 11 04:59:14 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737837365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.737837365
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.3089756227
Short name T387
Test name
Test status
Simulation time 2134811882 ps
CPU time 3.15 seconds
Started Sep 11 04:59:02 AM UTC 24
Finished Sep 11 04:59:07 AM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089756227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.3089756227
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.976586834
Short name T321
Test name
Test status
Simulation time 12999187388 ps
CPU time 9.88 seconds
Started Sep 11 04:59:09 AM UTC 24
Finished Sep 11 04:59:20 AM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976586834 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.976586834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.613261101
Short name T70
Test name
Test status
Simulation time 3827056900 ps
CPU time 9.45 seconds
Started Sep 11 04:59:07 AM UTC 24
Finished Sep 11 04:59:17 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613261101 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.613261101
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.223837851
Short name T335
Test name
Test status
Simulation time 65280591258 ps
CPU time 180.72 seconds
Started Sep 11 05:05:40 AM UTC 24
Finished Sep 11 05:08:43 AM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223837851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_with_pre_cond.223837851
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.133615334
Short name T360
Test name
Test status
Simulation time 59774098131 ps
CPU time 42.78 seconds
Started Sep 11 05:05:43 AM UTC 24
Finished Sep 11 05:06:27 AM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133615334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_with_pre_cond.133615334
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3248160954
Short name T754
Test name
Test status
Simulation time 24840382192 ps
CPU time 56.3 seconds
Started Sep 11 05:05:47 AM UTC 24
Finished Sep 11 05:06:45 AM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248160954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_with_pre_cond.3248160954
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2604138133
Short name T747
Test name
Test status
Simulation time 27301013973 ps
CPU time 11.2 seconds
Started Sep 11 05:05:49 AM UTC 24
Finished Sep 11 05:06:01 AM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604138133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_with_pre_cond.2604138133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4038167181
Short name T781
Test name
Test status
Simulation time 93211299639 ps
CPU time 265.76 seconds
Started Sep 11 05:05:54 AM UTC 24
Finished Sep 11 05:10:24 AM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038167181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_with_pre_cond.4038167181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4031700876
Short name T752
Test name
Test status
Simulation time 68211469118 ps
CPU time 39.12 seconds
Started Sep 11 05:05:59 AM UTC 24
Finished Sep 11 05:06:40 AM UTC 24
Peak memory 210304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031700876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_with_pre_cond.4031700876
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1302943490
Short name T755
Test name
Test status
Simulation time 40614860288 ps
CPU time 43.01 seconds
Started Sep 11 05:06:01 AM UTC 24
Finished Sep 11 05:06:45 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302943490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_with_pre_cond.1302943490
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.1329810970
Short name T243
Test name
Test status
Simulation time 2017188824 ps
CPU time 4.73 seconds
Started Sep 11 04:59:18 AM UTC 24
Finished Sep 11 04:59:24 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329810970 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.1329810970
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.696120601
Short name T132
Test name
Test status
Simulation time 3211878098 ps
CPU time 11.38 seconds
Started Sep 11 04:59:15 AM UTC 24
Finished Sep 11 04:59:28 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696120601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.696120601
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.3424852798
Short name T40
Test name
Test status
Simulation time 59142984454 ps
CPU time 14.78 seconds
Started Sep 11 04:59:15 AM UTC 24
Finished Sep 11 04:59:31 AM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424852798 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.3424852798
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1253144916
Short name T85
Test name
Test status
Simulation time 26033358815 ps
CPU time 6.82 seconds
Started Sep 11 04:59:16 AM UTC 24
Finished Sep 11 04:59:24 AM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253144916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_with_pre_cond.1253144916
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3904820090
Short name T244
Test name
Test status
Simulation time 4352160799 ps
CPU time 8.35 seconds
Started Sep 11 04:59:15 AM UTC 24
Finished Sep 11 04:59:24 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904820090 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.3904820090
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.2060763598
Short name T192
Test name
Test status
Simulation time 2981552716 ps
CPU time 1.7 seconds
Started Sep 11 04:59:16 AM UTC 24
Finished Sep 11 04:59:19 AM UTC 24
Peak memory 208112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060763598 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.2060763598
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2589168960
Short name T248
Test name
Test status
Simulation time 2614379151 ps
CPU time 11.39 seconds
Started Sep 11 04:59:14 AM UTC 24
Finished Sep 11 04:59:26 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589168960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.2589168960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.840716523
Short name T304
Test name
Test status
Simulation time 2474077596 ps
CPU time 3.41 seconds
Started Sep 11 04:59:10 AM UTC 24
Finished Sep 11 04:59:15 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840716523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.840716523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.2912966786
Short name T392
Test name
Test status
Simulation time 2254740769 ps
CPU time 4.52 seconds
Started Sep 11 04:59:13 AM UTC 24
Finished Sep 11 04:59:19 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912966786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.2912966786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1652015642
Short name T376
Test name
Test status
Simulation time 2522816010 ps
CPU time 4.15 seconds
Started Sep 11 04:59:14 AM UTC 24
Finished Sep 11 04:59:19 AM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652015642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1652015642
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.3222390861
Short name T305
Test name
Test status
Simulation time 2123407513 ps
CPU time 3.73 seconds
Started Sep 11 04:59:10 AM UTC 24
Finished Sep 11 04:59:15 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222390861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.3222390861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.2004618363
Short name T143
Test name
Test status
Simulation time 6736178639 ps
CPU time 9.95 seconds
Started Sep 11 04:59:18 AM UTC 24
Finished Sep 11 04:59:29 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004618363 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.2004618363
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1920112212
Short name T144
Test name
Test status
Simulation time 3900831437 ps
CPU time 12.21 seconds
Started Sep 11 04:59:16 AM UTC 24
Finished Sep 11 04:59:29 AM UTC 24
Peak memory 220512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1920112212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.1920112212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3304213402
Short name T393
Test name
Test status
Simulation time 8127840824 ps
CPU time 6.41 seconds
Started Sep 11 04:59:15 AM UTC 24
Finished Sep 11 04:59:23 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304213402 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.3304213402
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2581909379
Short name T763
Test name
Test status
Simulation time 26342103447 ps
CPU time 61.15 seconds
Started Sep 11 05:06:02 AM UTC 24
Finished Sep 11 05:07:05 AM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581909379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_with_pre_cond.2581909379
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1351224023
Short name T753
Test name
Test status
Simulation time 29385233963 ps
CPU time 36.06 seconds
Started Sep 11 05:06:03 AM UTC 24
Finished Sep 11 05:06:40 AM UTC 24
Peak memory 210172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351224023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_with_pre_cond.1351224023
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2855654949
Short name T346
Test name
Test status
Simulation time 66128370936 ps
CPU time 19.27 seconds
Started Sep 11 05:06:23 AM UTC 24
Finished Sep 11 05:06:43 AM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855654949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_with_pre_cond.2855654949
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.112045304
Short name T769
Test name
Test status
Simulation time 45718000612 ps
CPU time 69.32 seconds
Started Sep 11 05:06:28 AM UTC 24
Finished Sep 11 05:07:39 AM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112045304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_with_pre_cond.112045304
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3841171
Short name T100
Test name
Test status
Simulation time 84997217718 ps
CPU time 123.46 seconds
Started Sep 11 05:06:29 AM UTC 24
Finished Sep 11 05:08:35 AM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_
TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_with_pre_cond.3841171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.954472165
Short name T764
Test name
Test status
Simulation time 29098060093 ps
CPU time 25.28 seconds
Started Sep 11 05:06:38 AM UTC 24
Finished Sep 11 05:07:05 AM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954472165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_with_pre_cond.954472165
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.814742550
Short name T784
Test name
Test status
Simulation time 88530781015 ps
CPU time 284.72 seconds
Started Sep 11 05:06:39 AM UTC 24
Finished Sep 11 05:11:28 AM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814742550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_with_pre_cond.814742550
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.446232062
Short name T147
Test name
Test status
Simulation time 2019401401 ps
CPU time 5.33 seconds
Started Sep 11 04:59:25 AM UTC 24
Finished Sep 11 04:59:32 AM UTC 24
Peak memory 209848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446232062 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.446232062
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3340077970
Short name T107
Test name
Test status
Simulation time 3215211402 ps
CPU time 12.94 seconds
Started Sep 11 04:59:22 AM UTC 24
Finished Sep 11 04:59:36 AM UTC 24
Peak memory 210324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340077970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.3340077970
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.2565050267
Short name T117
Test name
Test status
Simulation time 191230929934 ps
CPU time 140.44 seconds
Started Sep 11 04:59:23 AM UTC 24
Finished Sep 11 05:01:46 AM UTC 24
Peak memory 210428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565050267 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.2565050267
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1375038448
Short name T394
Test name
Test status
Simulation time 4340755389 ps
CPU time 5.45 seconds
Started Sep 11 04:59:22 AM UTC 24
Finished Sep 11 04:59:28 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375038448 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.1375038448
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.3866020834
Short name T171
Test name
Test status
Simulation time 4931287651 ps
CPU time 3.23 seconds
Started Sep 11 04:59:24 AM UTC 24
Finished Sep 11 04:59:28 AM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866020834 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.3866020834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.754199177
Short name T247
Test name
Test status
Simulation time 2639501089 ps
CPU time 3.73 seconds
Started Sep 11 04:59:21 AM UTC 24
Finished Sep 11 04:59:25 AM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754199177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.754199177
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.2372500254
Short name T246
Test name
Test status
Simulation time 2462172067 ps
CPU time 4.87 seconds
Started Sep 11 04:59:19 AM UTC 24
Finished Sep 11 04:59:25 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372500254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.2372500254
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.683765747
Short name T245
Test name
Test status
Simulation time 2057131993 ps
CPU time 4.32 seconds
Started Sep 11 04:59:19 AM UTC 24
Finished Sep 11 04:59:25 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683765747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.683765747
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.975895569
Short name T145
Test name
Test status
Simulation time 2515136329 ps
CPU time 9.47 seconds
Started Sep 11 04:59:21 AM UTC 24
Finished Sep 11 04:59:31 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975895569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.975895569
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.2557636698
Short name T242
Test name
Test status
Simulation time 2133565411 ps
CPU time 3.95 seconds
Started Sep 11 04:59:18 AM UTC 24
Finished Sep 11 04:59:23 AM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557636698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.2557636698
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.2281758766
Short name T146
Test name
Test status
Simulation time 12518535766 ps
CPU time 5.22 seconds
Started Sep 11 04:59:25 AM UTC 24
Finished Sep 11 04:59:32 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281758766 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.2281758766
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1959760302
Short name T288
Test name
Test status
Simulation time 4118980527 ps
CPU time 13.27 seconds
Started Sep 11 04:59:25 AM UTC 24
Finished Sep 11 04:59:40 AM UTC 24
Peak memory 210300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1959760302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.1959760302
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.197404527
Short name T68
Test name
Test status
Simulation time 5543023870 ps
CPU time 5.55 seconds
Started Sep 11 04:59:22 AM UTC 24
Finished Sep 11 04:59:28 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197404527 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.197404527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2302243005
Short name T353
Test name
Test status
Simulation time 91279088007 ps
CPU time 243.31 seconds
Started Sep 11 05:06:41 AM UTC 24
Finished Sep 11 05:10:47 AM UTC 24
Peak memory 210304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302243005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_with_pre_cond.2302243005
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1104440133
Short name T352
Test name
Test status
Simulation time 198602589838 ps
CPU time 127.15 seconds
Started Sep 11 05:06:45 AM UTC 24
Finished Sep 11 05:08:54 AM UTC 24
Peak memory 210248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104440133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_with_pre_cond.1104440133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.682213523
Short name T759
Test name
Test status
Simulation time 21178898991 ps
CPU time 10.28 seconds
Started Sep 11 05:06:47 AM UTC 24
Finished Sep 11 05:06:58 AM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682213523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_with_pre_cond.682213523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.6002397
Short name T760
Test name
Test status
Simulation time 26082610515 ps
CPU time 42.4 seconds
Started Sep 11 05:06:49 AM UTC 24
Finished Sep 11 05:07:33 AM UTC 24
Peak memory 210176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6002397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_
TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_with_pre_cond.6002397
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.397358745
Short name T345
Test name
Test status
Simulation time 83174804096 ps
CPU time 54.47 seconds
Started Sep 11 05:06:58 AM UTC 24
Finished Sep 11 05:07:54 AM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397358745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_with_pre_cond.397358745
Directory /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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