| T191 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.4174013251 |
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Sep 11 05:03:08 AM UTC 24 |
Sep 11 05:03:13 AM UTC 24 |
5788365537 ps |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.4030107858 |
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Sep 11 05:02:57 AM UTC 24 |
Sep 11 05:03:14 AM UTC 24 |
4569056125 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2560598295 |
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Sep 11 05:03:02 AM UTC 24 |
Sep 11 05:03:15 AM UTC 24 |
2611378901 ps |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2842829249 |
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Sep 11 05:03:13 AM UTC 24 |
Sep 11 05:03:15 AM UTC 24 |
2300213003 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3092063731 |
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Sep 11 05:03:03 AM UTC 24 |
Sep 11 05:03:15 AM UTC 24 |
3086281278 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2557294505 |
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Sep 11 05:02:58 AM UTC 24 |
Sep 11 05:03:16 AM UTC 24 |
12477878260 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.4237943212 |
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Sep 11 05:03:12 AM UTC 24 |
Sep 11 05:03:16 AM UTC 24 |
2131636296 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.74060204 |
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Sep 11 05:03:13 AM UTC 24 |
Sep 11 05:03:17 AM UTC 24 |
2512264275 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2453387782 |
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Sep 11 05:03:54 AM UTC 24 |
Sep 11 05:03:59 AM UTC 24 |
2622685795 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3053962600 |
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Sep 11 05:03:10 AM UTC 24 |
Sep 11 05:03:17 AM UTC 24 |
2009851891 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.279388407 |
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Sep 11 05:02:07 AM UTC 24 |
Sep 11 05:03:18 AM UTC 24 |
151539179929 ps |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.3343957744 |
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Sep 11 05:00:08 AM UTC 24 |
Sep 11 05:03:18 AM UTC 24 |
63709727959 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1009334019 |
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Sep 11 05:03:14 AM UTC 24 |
Sep 11 05:03:19 AM UTC 24 |
2624652121 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.433376261 |
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Sep 11 05:03:16 AM UTC 24 |
Sep 11 05:03:21 AM UTC 24 |
10820767052 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.1408305084 |
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Sep 11 05:03:19 AM UTC 24 |
Sep 11 05:03:21 AM UTC 24 |
2559800709 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.3815372128 |
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Sep 11 05:02:47 AM UTC 24 |
Sep 11 05:03:21 AM UTC 24 |
96685953402 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1072128858 |
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Sep 11 05:03:14 AM UTC 24 |
Sep 11 05:03:24 AM UTC 24 |
3053980818 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.3324932135 |
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Sep 11 05:03:13 AM UTC 24 |
Sep 11 05:03:24 AM UTC 24 |
2511943102 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.4236471633 |
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Sep 11 05:03:09 AM UTC 24 |
Sep 11 05:03:24 AM UTC 24 |
4260876634 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3399346317 |
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Sep 11 05:03:22 AM UTC 24 |
Sep 11 05:03:25 AM UTC 24 |
2671335512 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.3315862380 |
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Sep 11 05:03:19 AM UTC 24 |
Sep 11 05:03:25 AM UTC 24 |
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| T642 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.1475780926 |
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Sep 11 05:03:19 AM UTC 24 |
Sep 11 05:03:26 AM UTC 24 |
2115518388 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.1264132430 |
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Sep 11 05:03:16 AM UTC 24 |
Sep 11 05:03:26 AM UTC 24 |
3656413147 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.883236482 |
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Sep 11 05:02:33 AM UTC 24 |
Sep 11 05:03:27 AM UTC 24 |
58550832501 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2553411374 |
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Sep 11 05:03:22 AM UTC 24 |
Sep 11 05:03:28 AM UTC 24 |
2515992674 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.2579888037 |
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Sep 11 05:03:20 AM UTC 24 |
Sep 11 05:03:29 AM UTC 24 |
2086891157 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.665891615 |
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Sep 11 05:03:25 AM UTC 24 |
Sep 11 05:03:29 AM UTC 24 |
4171914198 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.27124716 |
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Sep 11 05:00:49 AM UTC 24 |
Sep 11 05:03:31 AM UTC 24 |
59027879728 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.3569809685 |
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Sep 11 05:03:28 AM UTC 24 |
Sep 11 05:03:32 AM UTC 24 |
2028714802 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1751318800 |
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Sep 11 05:03:15 AM UTC 24 |
Sep 11 05:03:32 AM UTC 24 |
3405810436 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.3313681651 |
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Sep 11 05:00:25 AM UTC 24 |
Sep 11 05:03:32 AM UTC 24 |
128892271293 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.2029463169 |
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Sep 11 05:03:29 AM UTC 24 |
Sep 11 05:03:33 AM UTC 24 |
2127733339 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2334199784 |
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Sep 11 05:03:30 AM UTC 24 |
Sep 11 05:03:33 AM UTC 24 |
2490326675 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1212554411 |
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Sep 11 05:03:30 AM UTC 24 |
Sep 11 05:03:33 AM UTC 24 |
2289840728 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3131350016 |
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Sep 11 05:03:25 AM UTC 24 |
Sep 11 05:03:33 AM UTC 24 |
5398714328 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2028984325 |
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Sep 11 05:03:17 AM UTC 24 |
Sep 11 05:03:34 AM UTC 24 |
24345760705 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.1434794747 |
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Sep 11 05:02:31 AM UTC 24 |
Sep 11 05:03:34 AM UTC 24 |
207109540408 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.1492098030 |
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Sep 11 05:03:32 AM UTC 24 |
Sep 11 05:03:36 AM UTC 24 |
2578873580 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.252441735 |
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Sep 11 04:59:51 AM UTC 24 |
Sep 11 05:03:37 AM UTC 24 |
70785682314 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1866432806 |
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Sep 11 05:03:24 AM UTC 24 |
Sep 11 05:03:37 AM UTC 24 |
3721694884 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.4124322654 |
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Sep 11 05:02:16 AM UTC 24 |
Sep 11 05:03:38 AM UTC 24 |
120505705194 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1287984445 |
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Sep 11 05:03:26 AM UTC 24 |
Sep 11 05:03:38 AM UTC 24 |
42739334469 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3260956573 |
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Sep 11 05:03:26 AM UTC 24 |
Sep 11 05:03:39 AM UTC 24 |
8692219758 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3118320995 |
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Sep 11 05:03:34 AM UTC 24 |
Sep 11 05:03:39 AM UTC 24 |
14821562596 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.884206414 |
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Sep 11 05:03:34 AM UTC 24 |
Sep 11 05:03:40 AM UTC 24 |
6367739068 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4245647991 |
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Sep 11 05:03:23 AM UTC 24 |
Sep 11 05:03:40 AM UTC 24 |
3328897050 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.546812295 |
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Sep 11 05:02:15 AM UTC 24 |
Sep 11 05:03:41 AM UTC 24 |
124272758249 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1156366257 |
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Sep 11 05:03:38 AM UTC 24 |
Sep 11 05:03:41 AM UTC 24 |
2480318734 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2996614773 |
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Sep 11 05:03:33 AM UTC 24 |
Sep 11 05:03:42 AM UTC 24 |
2874403401 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.1826127800 |
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Sep 11 05:03:26 AM UTC 24 |
Sep 11 05:03:43 AM UTC 24 |
15880044627 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1321349634 |
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Sep 11 05:03:39 AM UTC 24 |
Sep 11 05:03:43 AM UTC 24 |
2099476526 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2598984050 |
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Sep 11 05:03:39 AM UTC 24 |
Sep 11 05:03:44 AM UTC 24 |
2628048756 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1483304385 |
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Sep 11 05:03:32 AM UTC 24 |
Sep 11 05:03:44 AM UTC 24 |
2608821704 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.2635701152 |
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Sep 11 05:03:39 AM UTC 24 |
Sep 11 05:03:44 AM UTC 24 |
2537560029 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1051530906 |
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Sep 11 05:03:40 AM UTC 24 |
Sep 11 05:03:44 AM UTC 24 |
3252670527 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3118938463 |
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Sep 11 05:03:33 AM UTC 24 |
Sep 11 05:03:45 AM UTC 24 |
3492045638 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3112313359 |
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Sep 11 05:03:17 AM UTC 24 |
Sep 11 05:03:45 AM UTC 24 |
34638908993 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.2842176533 |
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Sep 11 05:03:37 AM UTC 24 |
Sep 11 05:03:46 AM UTC 24 |
2010024130 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2554622516 |
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Sep 11 04:59:46 AM UTC 24 |
Sep 11 05:03:46 AM UTC 24 |
180599352301 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.1436464463 |
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Sep 11 05:03:42 AM UTC 24 |
Sep 11 05:03:46 AM UTC 24 |
2615138355 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.2448559328 |
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Sep 11 05:03:34 AM UTC 24 |
Sep 11 05:03:47 AM UTC 24 |
3398155005 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.1628815656 |
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Sep 11 05:03:38 AM UTC 24 |
Sep 11 05:03:48 AM UTC 24 |
2111954516 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3548812393 |
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Sep 11 05:03:40 AM UTC 24 |
Sep 11 05:03:48 AM UTC 24 |
4710472367 ps |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.4222702824 |
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Sep 11 05:03:45 AM UTC 24 |
Sep 11 05:03:48 AM UTC 24 |
2269638647 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2071616851 |
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Sep 11 05:03:45 AM UTC 24 |
Sep 11 05:03:49 AM UTC 24 |
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| T671 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.1832569311 |
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Sep 11 05:03:46 AM UTC 24 |
Sep 11 05:03:50 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1907027802 |
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Sep 11 05:03:47 AM UTC 24 |
Sep 11 05:03:52 AM UTC 24 |
3435992768 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.1213483750 |
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Sep 11 05:03:45 AM UTC 24 |
Sep 11 05:03:52 AM UTC 24 |
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| T331 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1390177997 |
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Sep 11 05:00:53 AM UTC 24 |
Sep 11 05:03:52 AM UTC 24 |
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| T140 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1415913762 |
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Sep 11 05:03:47 AM UTC 24 |
Sep 11 05:03:53 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1266894356 |
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Sep 11 05:03:41 AM UTC 24 |
Sep 11 05:03:53 AM UTC 24 |
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| T675 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.343275759 |
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Sep 11 05:03:51 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.3957870820 |
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Sep 11 05:03:45 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2274330381 |
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Sep 11 05:03:46 AM UTC 24 |
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2608117355 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.3966524584 |
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Sep 11 05:03:53 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.4257089818 |
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Sep 11 05:03:53 AM UTC 24 |
Sep 11 05:03:57 AM UTC 24 |
2478379453 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.3572758998 |
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Sep 11 05:03:48 AM UTC 24 |
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2752433341 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.4208954832 |
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Sep 11 05:03:50 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1186821194 |
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Sep 11 05:03:48 AM UTC 24 |
Sep 11 05:04:01 AM UTC 24 |
9843418627 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1588935860 |
|
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Sep 11 05:03:54 AM UTC 24 |
Sep 11 05:04:03 AM UTC 24 |
2611884796 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3629633611 |
|
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Sep 11 05:03:53 AM UTC 24 |
Sep 11 05:04:05 AM UTC 24 |
2509531308 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1788520495 |
|
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Sep 11 05:03:44 AM UTC 24 |
Sep 11 05:04:06 AM UTC 24 |
4772141776 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2330947642 |
|
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Sep 11 05:03:08 AM UTC 24 |
Sep 11 05:04:07 AM UTC 24 |
36077487511 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.520399291 |
|
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Sep 11 05:04:02 AM UTC 24 |
Sep 11 05:04:08 AM UTC 24 |
2110695286 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1553624661 |
|
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Sep 11 05:04:02 AM UTC 24 |
Sep 11 05:04:09 AM UTC 24 |
2022112745 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2968609064 |
|
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Sep 11 05:03:57 AM UTC 24 |
Sep 11 05:04:09 AM UTC 24 |
3623805295 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.3556439563 |
|
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Sep 11 05:04:01 AM UTC 24 |
Sep 11 05:04:09 AM UTC 24 |
9170938890 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2018062999 |
|
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Sep 11 05:04:07 AM UTC 24 |
Sep 11 05:04:10 AM UTC 24 |
2792109633 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.2270780984 |
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Sep 11 05:04:06 AM UTC 24 |
Sep 11 05:04:11 AM UTC 24 |
2514486606 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.937670876 |
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Sep 11 05:00:06 AM UTC 24 |
Sep 11 05:04:12 AM UTC 24 |
91753392301 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.1171923242 |
|
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Sep 11 05:04:04 AM UTC 24 |
Sep 11 05:04:12 AM UTC 24 |
2470880046 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.147057541 |
|
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Sep 11 05:04:09 AM UTC 24 |
Sep 11 05:04:13 AM UTC 24 |
5195026742 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.509181729 |
|
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Sep 11 05:03:58 AM UTC 24 |
Sep 11 05:04:13 AM UTC 24 |
6229289695 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.489959527 |
|
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Sep 11 05:03:56 AM UTC 24 |
Sep 11 05:04:14 AM UTC 24 |
3096347880 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.1091296433 |
|
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Sep 11 05:04:04 AM UTC 24 |
Sep 11 05:04:14 AM UTC 24 |
2231466965 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.3333732060 |
|
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Sep 11 05:03:50 AM UTC 24 |
Sep 11 05:04:14 AM UTC 24 |
11364542397 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.1904925899 |
|
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Sep 11 05:04:13 AM UTC 24 |
Sep 11 05:04:16 AM UTC 24 |
2036264516 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.2741148063 |
|
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Sep 11 05:04:14 AM UTC 24 |
Sep 11 05:04:17 AM UTC 24 |
2470361597 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.960578149 |
|
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Sep 11 05:04:08 AM UTC 24 |
Sep 11 05:04:18 AM UTC 24 |
3552349769 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3550384039 |
|
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Sep 11 05:04:08 AM UTC 24 |
Sep 11 05:04:19 AM UTC 24 |
4108801022 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.1227656781 |
|
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Sep 11 05:04:11 AM UTC 24 |
Sep 11 05:04:19 AM UTC 24 |
2713546679 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.586107991 |
|
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Sep 11 05:04:15 AM UTC 24 |
Sep 11 05:04:20 AM UTC 24 |
2536899673 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1525678053 |
|
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Sep 11 05:04:00 AM UTC 24 |
Sep 11 05:04:20 AM UTC 24 |
19012812630 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.339680564 |
|
|
Sep 11 05:04:15 AM UTC 24 |
Sep 11 05:04:20 AM UTC 24 |
2105898706 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.308724556 |
|
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Sep 11 05:03:17 AM UTC 24 |
Sep 11 05:04:21 AM UTC 24 |
109334552730 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2263399291 |
|
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Sep 11 05:02:33 AM UTC 24 |
Sep 11 05:04:23 AM UTC 24 |
44118576984 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3259352287 |
|
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Sep 11 05:04:18 AM UTC 24 |
Sep 11 05:04:24 AM UTC 24 |
3607268066 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1679150102 |
|
|
Sep 11 05:04:15 AM UTC 24 |
Sep 11 05:04:25 AM UTC 24 |
2613030709 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.1592531960 |
|
|
Sep 11 05:04:14 AM UTC 24 |
Sep 11 05:04:26 AM UTC 24 |
2110564961 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2008491293 |
|
|
Sep 11 05:04:12 AM UTC 24 |
Sep 11 05:04:26 AM UTC 24 |
14039319684 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3621906041 |
|
|
Sep 11 05:04:22 AM UTC 24 |
Sep 11 05:04:26 AM UTC 24 |
2031857424 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2301164395 |
|
|
Sep 11 05:03:48 AM UTC 24 |
Sep 11 05:04:28 AM UTC 24 |
75841204165 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.3752521250 |
|
|
Sep 11 05:04:25 AM UTC 24 |
Sep 11 05:04:28 AM UTC 24 |
2505307142 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.511465277 |
|
|
Sep 11 05:04:21 AM UTC 24 |
Sep 11 05:04:28 AM UTC 24 |
2495303948 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.3369830279 |
|
|
Sep 11 05:04:26 AM UTC 24 |
Sep 11 05:04:30 AM UTC 24 |
2040482460 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.2905232848 |
|
|
Sep 11 05:04:24 AM UTC 24 |
Sep 11 05:04:30 AM UTC 24 |
2122626086 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1164731149 |
|
|
Sep 11 05:04:26 AM UTC 24 |
Sep 11 05:04:30 AM UTC 24 |
2647857978 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.299122904 |
|
|
Sep 11 05:04:21 AM UTC 24 |
Sep 11 05:04:33 AM UTC 24 |
9386875570 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.1587096960 |
|
|
Sep 11 05:03:44 AM UTC 24 |
Sep 11 05:04:33 AM UTC 24 |
12145916650 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3399552591 |
|
|
Sep 11 05:04:17 AM UTC 24 |
Sep 11 05:04:34 AM UTC 24 |
3425478616 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1872431459 |
|
|
Sep 11 05:04:29 AM UTC 24 |
Sep 11 05:04:34 AM UTC 24 |
2841703510 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.2339563943 |
|
|
Sep 11 05:04:31 AM UTC 24 |
Sep 11 05:04:36 AM UTC 24 |
4433479261 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.2414221592 |
|
|
Sep 11 05:04:35 AM UTC 24 |
Sep 11 05:04:38 AM UTC 24 |
2254024204 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.1963232441 |
|
|
Sep 11 05:04:34 AM UTC 24 |
Sep 11 05:04:38 AM UTC 24 |
2030183208 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1073364110 |
|
|
Sep 11 05:04:30 AM UTC 24 |
Sep 11 05:04:38 AM UTC 24 |
7333652707 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.4201154552 |
|
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Sep 11 05:04:27 AM UTC 24 |
Sep 11 05:04:38 AM UTC 24 |
2899730241 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.2059359722 |
|
|
Sep 11 05:04:26 AM UTC 24 |
Sep 11 05:04:39 AM UTC 24 |
2510502658 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.2559220665 |
|
|
Sep 11 05:04:35 AM UTC 24 |
Sep 11 05:04:39 AM UTC 24 |
2509159503 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.413989170 |
|
|
Sep 11 05:00:46 AM UTC 24 |
Sep 11 05:04:39 AM UTC 24 |
85588410689 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2202870078 |
|
|
Sep 11 05:04:11 AM UTC 24 |
Sep 11 05:04:40 AM UTC 24 |
25608487930 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.934652660 |
|
|
Sep 11 05:04:37 AM UTC 24 |
Sep 11 05:04:40 AM UTC 24 |
2186774361 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2787922836 |
|
|
Sep 11 05:04:39 AM UTC 24 |
Sep 11 05:04:45 AM UTC 24 |
2625103435 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.161950736 |
|
|
Sep 11 05:04:40 AM UTC 24 |
Sep 11 05:04:45 AM UTC 24 |
4033092065 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.803987032 |
|
|
Sep 11 05:04:41 AM UTC 24 |
Sep 11 05:04:47 AM UTC 24 |
4132134262 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3597781385 |
|
|
Sep 11 05:04:39 AM UTC 24 |
Sep 11 05:04:49 AM UTC 24 |
3157858221 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2007237255 |
|
|
Sep 11 05:04:21 AM UTC 24 |
Sep 11 05:04:50 AM UTC 24 |
5691053253 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.426852907 |
|
|
Sep 11 05:03:34 AM UTC 24 |
Sep 11 05:04:51 AM UTC 24 |
68201543064 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.602795580 |
|
|
Sep 11 05:04:48 AM UTC 24 |
Sep 11 05:04:51 AM UTC 24 |
2157962026 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3206426955 |
|
|
Sep 11 05:04:40 AM UTC 24 |
Sep 11 05:04:51 AM UTC 24 |
3237201911 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3216401178 |
|
|
Sep 11 05:04:38 AM UTC 24 |
Sep 11 05:04:51 AM UTC 24 |
2509439718 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.1925148252 |
|
|
Sep 11 05:02:57 AM UTC 24 |
Sep 11 05:04:52 AM UTC 24 |
77859606216 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2592224107 |
|
|
Sep 11 05:04:31 AM UTC 24 |
Sep 11 05:04:52 AM UTC 24 |
16203899558 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1722900479 |
|
|
Sep 11 05:02:39 AM UTC 24 |
Sep 11 05:04:56 AM UTC 24 |
102428968993 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1898666726 |
|
|
Sep 11 05:04:41 AM UTC 24 |
Sep 11 05:04:56 AM UTC 24 |
2892499056 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.211548124 |
|
|
Sep 11 05:04:51 AM UTC 24 |
Sep 11 05:04:56 AM UTC 24 |
2042365945 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.2854851684 |
|
|
Sep 11 05:04:46 AM UTC 24 |
Sep 11 05:04:56 AM UTC 24 |
2013743058 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.4077649028 |
|
|
Sep 11 05:04:51 AM UTC 24 |
Sep 11 05:04:56 AM UTC 24 |
2525029244 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2094261435 |
|
|
Sep 11 05:04:51 AM UTC 24 |
Sep 11 05:04:56 AM UTC 24 |
2627017081 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3274678693 |
|
|
Sep 11 05:04:51 AM UTC 24 |
Sep 11 05:04:57 AM UTC 24 |
3647497183 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.1621331708 |
|
|
Sep 11 05:04:50 AM UTC 24 |
Sep 11 05:04:58 AM UTC 24 |
2452668074 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.344302600 |
|
|
Sep 11 05:04:21 AM UTC 24 |
Sep 11 05:04:58 AM UTC 24 |
52617572899 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.822190440 |
|
|
Sep 11 05:04:41 AM UTC 24 |
Sep 11 05:04:59 AM UTC 24 |
21351477338 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.2988331099 |
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|
Sep 11 04:58:09 AM UTC 24 |
Sep 11 05:05:01 AM UTC 24 |
147909336072 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.29415539 |
|
|
Sep 11 05:04:57 AM UTC 24 |
Sep 11 05:05:01 AM UTC 24 |
2028524980 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.2190799994 |
|
|
Sep 11 05:04:57 AM UTC 24 |
Sep 11 05:05:02 AM UTC 24 |
4413973929 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4012225097 |
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|
Sep 11 05:04:53 AM UTC 24 |
Sep 11 05:05:03 AM UTC 24 |
3486102675 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.3992480799 |
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|
Sep 11 05:01:06 AM UTC 24 |
Sep 11 05:05:04 AM UTC 24 |
102210993104 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.924494698 |
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|
Sep 11 05:04:45 AM UTC 24 |
Sep 11 05:05:06 AM UTC 24 |
10545022786 ps |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.1203296119 |
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Sep 11 04:59:46 AM UTC 24 |
Sep 11 05:05:09 AM UTC 24 |
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Sep 11 05:00:32 AM UTC 24 |
Sep 11 05:05:09 AM UTC 24 |
100139148556 ps |
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Sep 11 04:59:24 AM UTC 24 |
Sep 11 05:07:29 AM UTC 24 |
186441918853 ps |
| T283 |
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Sep 11 05:04:57 AM UTC 24 |
Sep 11 05:05:12 AM UTC 24 |
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Sep 11 05:03:36 AM UTC 24 |
Sep 11 05:05:16 AM UTC 24 |
61784317824 ps |
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Sep 11 05:04:30 AM UTC 24 |
Sep 11 05:05:26 AM UTC 24 |
149477995908 ps |
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Sep 11 05:05:07 AM UTC 24 |
Sep 11 05:05:30 AM UTC 24 |
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Sep 11 05:04:57 AM UTC 24 |
Sep 11 05:05:31 AM UTC 24 |
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Sep 11 05:04:19 AM UTC 24 |
Sep 11 05:05:39 AM UTC 24 |
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Sep 11 05:03:07 AM UTC 24 |
Sep 11 05:05:40 AM UTC 24 |
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Sep 11 05:04:53 AM UTC 24 |
Sep 11 05:05:40 AM UTC 24 |
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Sep 11 05:04:57 AM UTC 24 |
Sep 11 05:05:42 AM UTC 24 |
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Sep 11 05:05:10 AM UTC 24 |
Sep 11 05:05:47 AM UTC 24 |
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Sep 11 05:00:20 AM UTC 24 |
Sep 11 05:05:48 AM UTC 24 |
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Sep 11 05:05:03 AM UTC 24 |
Sep 11 05:05:53 AM UTC 24 |
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Sep 11 05:00:35 AM UTC 24 |
Sep 11 05:05:54 AM UTC 24 |
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Sep 11 05:05:17 AM UTC 24 |
Sep 11 05:05:59 AM UTC 24 |
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Sep 11 05:02:38 AM UTC 24 |
Sep 11 05:05:59 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3601871610 |
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Sep 11 05:02:44 AM UTC 24 |
Sep 11 05:06:01 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2604138133 |
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Sep 11 05:05:49 AM UTC 24 |
Sep 11 05:06:01 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1107994128 |
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Sep 11 05:05:01 AM UTC 24 |
Sep 11 05:06:22 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.725435694 |
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Sep 11 05:00:19 AM UTC 24 |
Sep 11 05:06:24 AM UTC 24 |
554284787364 ps |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.3704772392 |
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Sep 11 05:02:23 AM UTC 24 |
Sep 11 05:06:27 AM UTC 24 |
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Sep 11 05:05:43 AM UTC 24 |
Sep 11 05:06:27 AM UTC 24 |
59774098131 ps |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3702282672 |
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Sep 11 05:02:26 AM UTC 24 |
Sep 11 05:06:28 AM UTC 24 |
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Sep 11 05:04:13 AM UTC 24 |
Sep 11 05:06:37 AM UTC 24 |
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Sep 11 05:05:25 AM UTC 24 |
Sep 11 05:06:39 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4031700876 |
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Sep 11 05:05:59 AM UTC 24 |
Sep 11 05:06:40 AM UTC 24 |
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Sep 11 05:06:03 AM UTC 24 |
Sep 11 05:06:40 AM UTC 24 |
29385233963 ps |
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Sep 11 05:06:23 AM UTC 24 |
Sep 11 05:06:43 AM UTC 24 |
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Sep 11 05:05:47 AM UTC 24 |
Sep 11 05:06:45 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1302943490 |
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Sep 11 05:06:01 AM UTC 24 |
Sep 11 05:06:45 AM UTC 24 |
40614860288 ps |
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Sep 11 05:04:59 AM UTC 24 |
Sep 11 05:06:46 AM UTC 24 |
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Sep 11 05:05:04 AM UTC 24 |
Sep 11 05:06:54 AM UTC 24 |
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Sep 11 05:02:05 AM UTC 24 |
Sep 11 05:06:55 AM UTC 24 |
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Sep 11 05:04:59 AM UTC 24 |
Sep 11 05:06:57 AM UTC 24 |
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Sep 11 05:06:47 AM UTC 24 |
Sep 11 05:06:58 AM UTC 24 |
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Sep 11 05:04:09 AM UTC 24 |
Sep 11 05:06:58 AM UTC 24 |
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Sep 11 05:06:49 AM UTC 24 |
Sep 11 05:07:33 AM UTC 24 |
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Sep 11 05:05:03 AM UTC 24 |
Sep 11 05:07:00 AM UTC 24 |
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Sep 11 05:05:32 AM UTC 24 |
Sep 11 05:07:02 AM UTC 24 |
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Sep 11 05:05:27 AM UTC 24 |
Sep 11 05:07:03 AM UTC 24 |
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Sep 11 05:06:02 AM UTC 24 |
Sep 11 05:07:05 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.954472165 |
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Sep 11 05:06:38 AM UTC 24 |
Sep 11 05:07:05 AM UTC 24 |
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Sep 11 05:03:42 AM UTC 24 |
Sep 11 05:07:06 AM UTC 24 |
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Sep 11 05:05:00 AM UTC 24 |
Sep 11 05:07:09 AM UTC 24 |
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Sep 11 05:05:12 AM UTC 24 |
Sep 11 05:07:09 AM UTC 24 |
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Sep 11 05:05:32 AM UTC 24 |
Sep 11 05:07:12 AM UTC 24 |
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Sep 11 05:06:28 AM UTC 24 |
Sep 11 05:07:39 AM UTC 24 |
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Sep 11 05:02:58 AM UTC 24 |
Sep 11 05:07:16 AM UTC 24 |
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Sep 11 05:06:08 AM UTC 24 |
Sep 11 05:07:16 AM UTC 24 |
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Sep 11 05:01:39 AM UTC 24 |
Sep 11 05:07:16 AM UTC 24 |
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Sep 11 05:05:54 AM UTC 24 |
Sep 11 05:07:21 AM UTC 24 |
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Sep 11 05:06:56 AM UTC 24 |
Sep 11 05:07:22 AM UTC 24 |
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Sep 11 05:06:28 AM UTC 24 |
Sep 11 05:07:23 AM UTC 24 |
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Sep 11 05:00:52 AM UTC 24 |
Sep 11 05:07:23 AM UTC 24 |
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Sep 11 05:06:54 AM UTC 24 |
Sep 11 05:07:42 AM UTC 24 |
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Sep 11 05:03:34 AM UTC 24 |
Sep 11 05:07:42 AM UTC 24 |
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Sep 11 05:05:10 AM UTC 24 |
Sep 11 05:07:43 AM UTC 24 |
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Sep 11 05:04:40 AM UTC 24 |
Sep 11 05:07:47 AM UTC 24 |
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Sep 11 05:06:58 AM UTC 24 |
Sep 11 05:07:54 AM UTC 24 |
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Sep 11 05:04:58 AM UTC 24 |
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Sep 11 05:05:12 AM UTC 24 |
Sep 11 05:08:00 AM UTC 24 |
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Sep 11 05:02:08 AM UTC 24 |
Sep 11 05:08:20 AM UTC 24 |
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Sep 11 05:04:18 AM UTC 24 |
Sep 11 05:08:29 AM UTC 24 |
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Sep 11 05:04:34 AM UTC 24 |
Sep 11 05:08:33 AM UTC 24 |
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Sep 11 05:06:29 AM UTC 24 |
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Sep 11 05:05:40 AM UTC 24 |
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Sep 11 05:03:46 AM UTC 24 |
Sep 11 05:08:52 AM UTC 24 |
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Sep 11 05:06:45 AM UTC 24 |
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Sep 11 05:03:57 AM UTC 24 |
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Sep 11 05:05:41 AM UTC 24 |
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Sep 11 05:03:10 AM UTC 24 |
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Sep 11 05:02:37 AM UTC 24 |
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Sep 11 05:04:57 AM UTC 24 |
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Sep 11 05:06:46 AM UTC 24 |
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Sep 11 05:05:54 AM UTC 24 |
Sep 11 05:10:24 AM UTC 24 |
93211299639 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.3040906710 |
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|
Sep 11 05:03:25 AM UTC 24 |
Sep 11 05:10:42 AM UTC 24 |
178748143230 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.94679374 |
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Sep 11 05:03:47 AM UTC 24 |
Sep 11 05:10:45 AM UTC 24 |
133790045475 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2302243005 |
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Sep 11 05:06:41 AM UTC 24 |
Sep 11 05:10:47 AM UTC 24 |
91279088007 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3748991566 |
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Sep 11 05:00:31 AM UTC 24 |
Sep 11 05:10:56 AM UTC 24 |
237711963445 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.814742550 |
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Sep 11 05:06:39 AM UTC 24 |
Sep 11 05:11:28 AM UTC 24 |
88530781015 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2694324099 |
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|
Sep 11 05:03:16 AM UTC 24 |
Sep 11 05:11:33 AM UTC 24 |
153054372830 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2167441337 |
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Sep 11 05:00:38 AM UTC 24 |
Sep 11 05:11:40 AM UTC 24 |
283132511645 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.250021870 |
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|
Sep 11 05:01:38 AM UTC 24 |
Sep 11 05:11:43 AM UTC 24 |
180262169223 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.3775140932 |
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|
Sep 11 05:04:54 AM UTC 24 |
Sep 11 05:12:54 AM UTC 24 |
172665025122 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.941966073 |
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Sep 11 05:01:31 AM UTC 24 |
Sep 11 05:20:26 AM UTC 24 |
423677070503 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.683405359 |
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Sep 11 05:00:52 AM UTC 24 |
Sep 11 05:50:19 AM UTC 24 |
1060171633066 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.573114343 |
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Sep 11 05:02:59 AM UTC 24 |
Sep 11 06:28:27 AM UTC 24 |
1682633229428 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3223311735 |
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Sep 11 05:07:01 AM UTC 24 |
Sep 11 05:07:04 AM UTC 24 |
2030998289 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.785125044 |
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Sep 11 05:06:59 AM UTC 24 |
Sep 11 05:07:07 AM UTC 24 |
2075819592 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1772544586 |
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Sep 11 05:07:04 AM UTC 24 |
Sep 11 05:07:08 AM UTC 24 |
2528795073 ps |