Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1028010
Category 01028010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1028010
Severity 01028010

Summary for Assertions
NUMBERPERCENT
Total Number1028100.00
Uncovered50.49
Success102399.51
Failure00.00
Incomplete10.10
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0091091000
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001401202356206595500
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 001401201797566100
tb.dut.tlul_assert_device.gen_device.contigMask_M 0014012023561507557200
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00140120235616390900
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 001401201797584600
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0014012023561650959500
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00140120235647611800
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0014012023561650959500
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00140120235647611800
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00140120235647611800
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00140120235647611800
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 001401201797370200
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 001401201797369500
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0091091000
tb.dut.u_reg.en2addrHit 00140120179723800300
tb.dut.u_reg.reAfterRv 00140120179723800300
tb.dut.u_reg.rePulse 00140120179712572900
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A 001401201797114270200
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A 001401201797114300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797114300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830114300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830106100
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797115100
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A 001401201797104531200
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A 001401201797102500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797102500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830102500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 001001383094100
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797103500
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0091091000
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A 001401201797164573700
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A 001401201797174900
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797174900
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830174900
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830166400
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797175900
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A 001401201797159764400
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A 001401201797172900
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797172900
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830172900
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830165100
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797173800
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A 001401201797162957400
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A 001401201797175400
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797175400
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830175400
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830167500
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797176100
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A 001401201797157605900
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A 001401201797171300
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797171300
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830171300
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830163000
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797172300
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A 001401201797162719400
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A 001401201797175300
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797175300
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830175300
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830166700
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797176300
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A 001401201797159528800
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A 001401201797173000
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797173000
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830173000
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830165000
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797174100
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A 001401201797158321800
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A 001401201797171100
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797171100
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830171100
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830162900
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797172000
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A 001401201797153662900
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A 001401201797169600
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797169600
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830169600
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830161000
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797170500
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A 001401201797112707600
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A 001401201797116600
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797116600
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830116600
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830108200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797117200
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A 001401201797113518100
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A 001401201797118000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797118000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830118000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830109600
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797118900
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A 001401201797110682900
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A 001401201797117000
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797117000
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830117000
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830108500
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797117700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A 001401201797114034500
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A 001401201797118200
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797118200
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830118200
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830110300
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797119300
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A 001401201797632191200
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A 001401201797693400
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797693400
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830693400
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830684700
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797694100
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A 001401201797635107200
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A 001401201797698100
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797698100
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830698100
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830689500
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797699200
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A 001401201797615596900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A 001401201797690900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797690900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830690900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830682900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797691800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A 001401201797607104600
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A 001401201797692700
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797692700
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830692700
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830683900
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797693400
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A 001401201797689946000
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A 001401201797750800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797750800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830750800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830742400
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797751700
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A 001401201797687371600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A 001401201797750600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797750600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830750600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830741800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797751500
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A 001401201797665443600
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A 001401201797744100
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797744100
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830744100
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830735700
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797745100
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A 001401201797656604600
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A 001401201797745900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797745900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830745900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830737600
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797747200
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A 001401201797160043700
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A 001401201797177000
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001401201797177000
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 0010013830177000
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 0010013830168500
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001401201797177800
tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A 00140120179793262900
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A 0010013830939116100
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcAckBusyChk_A 00140120179793000
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A 001401201797140077935800
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 00140120179793000
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