| T247 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.783928926 |
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Oct 02 10:43:36 PM UTC 24 |
Oct 02 10:43:41 PM UTC 24 |
2062767342 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.565297999 |
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Oct 02 10:43:12 PM UTC 24 |
Oct 02 10:43:42 PM UTC 24 |
12269498510 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3794247877 |
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Oct 02 10:43:31 PM UTC 24 |
Oct 02 10:43:42 PM UTC 24 |
3108951446 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.558776850 |
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Oct 02 10:43:33 PM UTC 24 |
Oct 02 10:43:42 PM UTC 24 |
7140547673 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.857028279 |
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Oct 02 10:43:31 PM UTC 24 |
Oct 02 10:43:43 PM UTC 24 |
2613366698 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1636259740 |
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Oct 02 10:43:10 PM UTC 24 |
Oct 02 10:43:44 PM UTC 24 |
42194411846 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1291235752 |
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Oct 02 10:43:27 PM UTC 24 |
Oct 02 10:43:44 PM UTC 24 |
13866212277 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.3740575341 |
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Oct 02 10:44:02 PM UTC 24 |
Oct 02 10:44:06 PM UTC 24 |
2534921289 ps |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2417821221 |
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Oct 02 10:43:40 PM UTC 24 |
Oct 02 10:43:44 PM UTC 24 |
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| T497 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.528091276 |
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Oct 02 10:43:34 PM UTC 24 |
Oct 02 10:43:44 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.3314604623 |
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Oct 02 10:43:41 PM UTC 24 |
Oct 02 10:43:45 PM UTC 24 |
2491710681 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.2415440932 |
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Oct 02 10:43:34 PM UTC 24 |
Oct 02 10:43:46 PM UTC 24 |
2113907669 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2140839902 |
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Oct 02 10:43:46 PM UTC 24 |
Oct 02 10:44:05 PM UTC 24 |
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| T338 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3899950008 |
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Oct 02 10:43:51 PM UTC 24 |
Oct 02 10:44:07 PM UTC 24 |
8209113616 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.1852496393 |
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Oct 02 10:43:43 PM UTC 24 |
Oct 02 10:43:46 PM UTC 24 |
2100252370 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2905570168 |
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Oct 02 10:43:39 PM UTC 24 |
Oct 02 10:43:47 PM UTC 24 |
2612524826 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.2251502979 |
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Oct 02 10:43:36 PM UTC 24 |
Oct 02 10:43:48 PM UTC 24 |
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| T502 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.3002504507 |
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Oct 02 10:43:45 PM UTC 24 |
Oct 02 10:43:49 PM UTC 24 |
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| T503 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.353640768 |
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Oct 02 10:43:45 PM UTC 24 |
Oct 02 10:43:52 PM UTC 24 |
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| T41 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2434152683 |
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Oct 02 10:42:27 PM UTC 24 |
Oct 02 10:43:52 PM UTC 24 |
115641140369 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1069721935 |
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Oct 02 10:43:40 PM UTC 24 |
Oct 02 10:43:54 PM UTC 24 |
4226427121 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1373719937 |
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Oct 02 10:43:45 PM UTC 24 |
Oct 02 10:43:54 PM UTC 24 |
2241188578 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.621299320 |
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Oct 02 10:43:46 PM UTC 24 |
Oct 02 10:43:54 PM UTC 24 |
2613742884 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3168284751 |
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Oct 02 10:43:40 PM UTC 24 |
Oct 02 10:43:55 PM UTC 24 |
3376595946 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2945917166 |
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Oct 02 10:43:47 PM UTC 24 |
Oct 02 10:43:55 PM UTC 24 |
3209768663 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1593000889 |
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Oct 02 10:43:49 PM UTC 24 |
Oct 02 10:43:55 PM UTC 24 |
3692803648 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2320648343 |
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Oct 02 10:43:53 PM UTC 24 |
Oct 02 10:43:56 PM UTC 24 |
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| T223 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.4143853519 |
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Oct 02 10:43:48 PM UTC 24 |
Oct 02 10:43:57 PM UTC 24 |
2847157882 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.2890745897 |
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Oct 02 10:43:45 PM UTC 24 |
Oct 02 10:43:57 PM UTC 24 |
2509311024 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.2295225961 |
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Oct 02 10:43:54 PM UTC 24 |
Oct 02 10:43:59 PM UTC 24 |
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| T43 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.806744259 |
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Oct 02 10:42:06 PM UTC 24 |
Oct 02 10:44:00 PM UTC 24 |
176616134244 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3920059044 |
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Oct 02 10:43:42 PM UTC 24 |
Oct 02 10:44:00 PM UTC 24 |
4355371323 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.3242046311 |
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Oct 02 10:43:53 PM UTC 24 |
Oct 02 10:44:01 PM UTC 24 |
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| T221 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2223199828 |
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Oct 02 10:43:43 PM UTC 24 |
Oct 02 10:44:01 PM UTC 24 |
14204206482 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.2412402242 |
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Oct 02 10:43:34 PM UTC 24 |
Oct 02 10:44:02 PM UTC 24 |
12929575198 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.1705821603 |
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Oct 02 10:43:56 PM UTC 24 |
Oct 02 10:44:02 PM UTC 24 |
15410135284 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2500543949 |
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Oct 02 10:43:55 PM UTC 24 |
Oct 02 10:44:02 PM UTC 24 |
2616990482 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.930649995 |
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Oct 02 10:43:55 PM UTC 24 |
Oct 02 10:44:02 PM UTC 24 |
2078218612 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2951320103 |
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Oct 02 10:43:56 PM UTC 24 |
Oct 02 10:44:04 PM UTC 24 |
3519889292 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.3893685139 |
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Oct 02 10:42:32 PM UTC 24 |
Oct 02 10:44:05 PM UTC 24 |
177569560336 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.1242612173 |
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Oct 02 10:43:55 PM UTC 24 |
Oct 02 10:44:07 PM UTC 24 |
2512596999 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.4408477 |
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Oct 02 10:44:02 PM UTC 24 |
Oct 02 10:44:07 PM UTC 24 |
2620385412 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.543094225 |
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Oct 02 10:44:02 PM UTC 24 |
Oct 02 10:44:10 PM UTC 24 |
2185396642 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3096697675 |
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Oct 02 10:41:28 PM UTC 24 |
Oct 02 10:44:10 PM UTC 24 |
95080953167 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2317260327 |
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Oct 02 10:44:01 PM UTC 24 |
Oct 02 10:44:11 PM UTC 24 |
2113766882 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.2779048745 |
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Oct 02 10:40:54 PM UTC 24 |
Oct 02 10:44:12 PM UTC 24 |
67564280938 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2614057529 |
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Oct 02 10:43:33 PM UTC 24 |
Oct 02 10:44:13 PM UTC 24 |
37289336344 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3781811497 |
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Oct 02 10:44:04 PM UTC 24 |
Oct 02 10:44:14 PM UTC 24 |
3645235525 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1269375566 |
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Oct 02 10:44:12 PM UTC 24 |
Oct 02 10:44:15 PM UTC 24 |
3578197382 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.2277006790 |
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Oct 02 10:44:01 PM UTC 24 |
Oct 02 10:44:15 PM UTC 24 |
2453676096 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.3810019875 |
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Oct 02 10:44:08 PM UTC 24 |
Oct 02 10:44:16 PM UTC 24 |
2114707109 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.656453522 |
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Oct 02 10:44:11 PM UTC 24 |
Oct 02 10:44:16 PM UTC 24 |
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| T203 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1188970634 |
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Oct 02 10:44:06 PM UTC 24 |
Oct 02 10:44:16 PM UTC 24 |
3964524348 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.387642719 |
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Oct 02 10:44:08 PM UTC 24 |
Oct 02 10:44:18 PM UTC 24 |
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| T344 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.3912431687 |
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Oct 02 10:44:06 PM UTC 24 |
Oct 02 10:44:19 PM UTC 24 |
16125499812 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.204994360 |
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Oct 02 10:44:11 PM UTC 24 |
Oct 02 10:44:19 PM UTC 24 |
2206521314 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2435195679 |
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Oct 02 10:44:13 PM UTC 24 |
Oct 02 10:44:19 PM UTC 24 |
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| T184 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2720797434 |
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Oct 02 10:44:14 PM UTC 24 |
Oct 02 10:44:20 PM UTC 24 |
2579810406 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.2427603961 |
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Oct 02 10:44:08 PM UTC 24 |
Oct 02 10:44:22 PM UTC 24 |
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| T521 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.3365717101 |
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Oct 02 10:44:11 PM UTC 24 |
Oct 02 10:44:22 PM UTC 24 |
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| T44 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.776838534 |
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Oct 02 10:43:41 PM UTC 24 |
Oct 02 10:44:23 PM UTC 24 |
55938677178 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1823890590 |
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Oct 02 10:43:58 PM UTC 24 |
Oct 02 10:44:24 PM UTC 24 |
4881996158 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2551643718 |
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Oct 02 10:44:13 PM UTC 24 |
Oct 02 10:44:24 PM UTC 24 |
3296360154 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.3990400508 |
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Oct 02 10:44:16 PM UTC 24 |
Oct 02 10:44:25 PM UTC 24 |
7748886720 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1786444715 |
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Oct 02 10:44:18 PM UTC 24 |
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2111261057 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1910121815 |
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Oct 02 10:44:16 PM UTC 24 |
Oct 02 10:44:25 PM UTC 24 |
14364884560 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.2975824631 |
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Oct 02 10:44:20 PM UTC 24 |
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| T213 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.979094736 |
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Oct 02 10:44:23 PM UTC 24 |
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| T526 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.3581509586 |
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Oct 02 10:43:59 PM UTC 24 |
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7219693491 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.1550041580 |
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Oct 02 10:44:20 PM UTC 24 |
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| T528 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.1585942953 |
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Oct 02 10:44:18 PM UTC 24 |
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| T529 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.584377739 |
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Oct 02 10:44:20 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2130985852 |
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Oct 02 10:42:54 PM UTC 24 |
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| T530 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.4205345545 |
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Oct 02 10:44:21 PM UTC 24 |
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| T435 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.630192737 |
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Oct 02 10:43:47 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1452441023 |
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Oct 02 10:44:27 PM UTC 24 |
Oct 02 10:44:32 PM UTC 24 |
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| T532 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.3476034496 |
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Oct 02 10:44:26 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.446866426 |
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Oct 02 10:44:31 PM UTC 24 |
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| T533 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1812717896 |
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Oct 02 10:44:21 PM UTC 24 |
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2610057417 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.3604107457 |
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Oct 02 10:44:27 PM UTC 24 |
Oct 02 10:44:34 PM UTC 24 |
2200972347 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.803162282 |
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Oct 02 10:44:28 PM UTC 24 |
Oct 02 10:44:35 PM UTC 24 |
3703459349 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3701170299 |
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Oct 02 10:44:28 PM UTC 24 |
Oct 02 10:44:35 PM UTC 24 |
2616843711 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.58282912 |
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Oct 02 10:44:26 PM UTC 24 |
Oct 02 10:44:38 PM UTC 24 |
2111684061 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.799736351 |
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Oct 02 10:44:28 PM UTC 24 |
Oct 02 10:44:38 PM UTC 24 |
3034992408 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.1063270924 |
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Oct 02 10:44:36 PM UTC 24 |
Oct 02 10:44:39 PM UTC 24 |
2114107857 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.340614073 |
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Oct 02 10:44:31 PM UTC 24 |
Oct 02 10:44:39 PM UTC 24 |
5351068272 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.1650773241 |
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Oct 02 10:44:28 PM UTC 24 |
Oct 02 10:44:40 PM UTC 24 |
2514193686 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.419775050 |
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Oct 02 10:44:36 PM UTC 24 |
Oct 02 10:44:41 PM UTC 24 |
2479621199 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2163550016 |
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Oct 02 10:44:34 PM UTC 24 |
Oct 02 10:44:43 PM UTC 24 |
10286518745 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.1462823565 |
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Oct 02 10:44:36 PM UTC 24 |
Oct 02 10:44:43 PM UTC 24 |
2041732992 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.38231979 |
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Oct 02 10:44:42 PM UTC 24 |
Oct 02 10:44:48 PM UTC 24 |
8113947806 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.2553169391 |
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Oct 02 10:44:36 PM UTC 24 |
Oct 02 10:44:48 PM UTC 24 |
2109540271 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3033411261 |
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Oct 02 10:44:42 PM UTC 24 |
Oct 02 10:44:48 PM UTC 24 |
3529132380 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.532216451 |
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Oct 02 10:44:43 PM UTC 24 |
Oct 02 10:44:49 PM UTC 24 |
3210455078 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2153041388 |
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Oct 02 10:43:18 PM UTC 24 |
Oct 02 10:44:49 PM UTC 24 |
108575782755 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3067896253 |
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Oct 02 10:44:24 PM UTC 24 |
Oct 02 10:44:50 PM UTC 24 |
8482094134 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1802624837 |
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Oct 02 10:43:26 PM UTC 24 |
Oct 02 10:44:51 PM UTC 24 |
54855504989 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.348639011 |
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Oct 02 10:44:40 PM UTC 24 |
Oct 02 10:44:54 PM UTC 24 |
2513593618 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.478268546 |
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Oct 02 10:44:49 PM UTC 24 |
Oct 02 10:44:54 PM UTC 24 |
2031765275 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.3826103480 |
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Oct 02 10:44:51 PM UTC 24 |
Oct 02 10:44:55 PM UTC 24 |
2247052564 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.879101660 |
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Oct 02 10:44:40 PM UTC 24 |
Oct 02 10:44:55 PM UTC 24 |
2613433108 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.777653345 |
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Oct 02 10:44:49 PM UTC 24 |
Oct 02 10:44:56 PM UTC 24 |
2116602500 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.4150343776 |
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Oct 02 10:44:52 PM UTC 24 |
Oct 02 10:44:57 PM UTC 24 |
2623528254 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3068924988 |
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Oct 02 10:44:55 PM UTC 24 |
Oct 02 10:45:00 PM UTC 24 |
3147970683 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2161685289 |
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Oct 02 10:44:55 PM UTC 24 |
Oct 02 10:45:02 PM UTC 24 |
4190106606 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.361862488 |
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Oct 02 10:41:59 PM UTC 24 |
Oct 02 10:45:03 PM UTC 24 |
85923299504 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.2511088625 |
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Oct 02 10:41:24 PM UTC 24 |
Oct 02 10:45:03 PM UTC 24 |
232296487183 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.625413556 |
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Oct 02 10:44:49 PM UTC 24 |
Oct 02 10:45:04 PM UTC 24 |
2462733739 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.4076707545 |
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Oct 02 10:44:51 PM UTC 24 |
Oct 02 10:45:04 PM UTC 24 |
2510181633 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.3937729834 |
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Oct 02 10:43:03 PM UTC 24 |
Oct 02 10:45:05 PM UTC 24 |
79355986275 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2428860363 |
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Oct 02 10:44:44 PM UTC 24 |
Oct 02 10:45:05 PM UTC 24 |
7258663596 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3027469736 |
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Oct 02 10:44:57 PM UTC 24 |
Oct 02 10:45:06 PM UTC 24 |
3815979199 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3219498435 |
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Oct 02 10:42:18 PM UTC 24 |
Oct 02 10:45:07 PM UTC 24 |
59853270409 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2060623028 |
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Oct 02 10:45:04 PM UTC 24 |
Oct 02 10:45:08 PM UTC 24 |
2023800088 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.543357903 |
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Oct 02 10:45:05 PM UTC 24 |
Oct 02 10:45:10 PM UTC 24 |
2483838147 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3986731725 |
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Oct 02 10:42:46 PM UTC 24 |
Oct 02 10:45:10 PM UTC 24 |
47734956150 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.2778277760 |
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Oct 02 10:45:06 PM UTC 24 |
Oct 02 10:45:11 PM UTC 24 |
2530472017 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1439173598 |
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Oct 02 10:45:06 PM UTC 24 |
Oct 02 10:45:14 PM UTC 24 |
2098527091 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2555904109 |
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Oct 02 10:41:40 PM UTC 24 |
Oct 02 10:45:15 PM UTC 24 |
75071162616 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.1312383206 |
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Oct 02 10:45:05 PM UTC 24 |
Oct 02 10:45:17 PM UTC 24 |
2111839440 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.354172637 |
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Oct 02 10:43:58 PM UTC 24 |
Oct 02 10:45:20 PM UTC 24 |
87925362538 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2591877408 |
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Oct 02 10:45:06 PM UTC 24 |
Oct 02 10:45:22 PM UTC 24 |
2611026670 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.2726517283 |
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Oct 02 10:45:18 PM UTC 24 |
Oct 02 10:45:22 PM UTC 24 |
2026189215 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1712577370 |
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Oct 02 10:45:01 PM UTC 24 |
Oct 02 10:45:24 PM UTC 24 |
9928294808 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.428268398 |
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Oct 02 10:45:11 PM UTC 24 |
Oct 02 10:45:24 PM UTC 24 |
4127634073 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2789835166 |
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Oct 02 10:45:09 PM UTC 24 |
Oct 02 10:45:24 PM UTC 24 |
4128557550 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.985117880 |
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Oct 02 10:45:23 PM UTC 24 |
Oct 02 10:45:26 PM UTC 24 |
2260293381 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1152370856 |
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Oct 02 10:45:08 PM UTC 24 |
Oct 02 10:45:26 PM UTC 24 |
3457846733 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.2216522327 |
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Oct 02 10:45:16 PM UTC 24 |
Oct 02 10:45:28 PM UTC 24 |
6653210796 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3034618942 |
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Oct 02 10:43:48 PM UTC 24 |
Oct 02 10:45:29 PM UTC 24 |
32605697659 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.3140826484 |
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Oct 02 10:45:21 PM UTC 24 |
Oct 02 10:45:30 PM UTC 24 |
2116596605 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.4062336108 |
|
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Oct 02 10:44:16 PM UTC 24 |
Oct 02 10:45:31 PM UTC 24 |
63274506668 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.3978907343 |
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Oct 02 10:45:07 PM UTC 24 |
Oct 02 10:45:31 PM UTC 24 |
4577921073 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3781645362 |
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Oct 02 10:45:24 PM UTC 24 |
Oct 02 10:45:32 PM UTC 24 |
4863914197 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.944154579 |
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Oct 02 10:45:24 PM UTC 24 |
Oct 02 10:45:32 PM UTC 24 |
2516302459 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1568378844 |
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Oct 02 10:45:26 PM UTC 24 |
Oct 02 10:45:32 PM UTC 24 |
3801004994 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.1757911374 |
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Oct 02 10:45:30 PM UTC 24 |
Oct 02 10:45:34 PM UTC 24 |
2537122973 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.4272141525 |
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Oct 02 10:44:23 PM UTC 24 |
Oct 02 10:45:35 PM UTC 24 |
780887418701 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.35405453 |
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Oct 02 10:45:23 PM UTC 24 |
Oct 02 10:45:35 PM UTC 24 |
2492679042 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.3375512727 |
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Oct 02 10:44:05 PM UTC 24 |
Oct 02 10:45:35 PM UTC 24 |
93518174984 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1061356195 |
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Oct 02 10:45:15 PM UTC 24 |
Oct 02 10:45:36 PM UTC 24 |
6601451988 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.661307306 |
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Oct 02 10:45:24 PM UTC 24 |
Oct 02 10:45:38 PM UTC 24 |
2607622978 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.3742704214 |
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Oct 02 10:45:33 PM UTC 24 |
Oct 02 10:45:38 PM UTC 24 |
2506179774 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.263150602 |
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Oct 02 10:46:17 PM UTC 24 |
Oct 02 10:46:23 PM UTC 24 |
3090646961 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3371245374 |
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Oct 02 10:45:37 PM UTC 24 |
Oct 02 10:45:39 PM UTC 24 |
3527525102 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.3161526793 |
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Oct 02 10:45:32 PM UTC 24 |
Oct 02 10:45:40 PM UTC 24 |
2011636591 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.942801826 |
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Oct 02 10:45:35 PM UTC 24 |
Oct 02 10:45:42 PM UTC 24 |
2081692797 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2125356740 |
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Oct 02 10:45:37 PM UTC 24 |
Oct 02 10:45:42 PM UTC 24 |
2621411880 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.4180874738 |
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Oct 02 10:43:19 PM UTC 24 |
Oct 02 10:45:44 PM UTC 24 |
124766027600 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.4173688661 |
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Oct 02 10:45:33 PM UTC 24 |
Oct 02 10:45:45 PM UTC 24 |
2108997248 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1177075888 |
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Oct 02 10:45:32 PM UTC 24 |
Oct 02 10:45:46 PM UTC 24 |
6439401564 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.556971290 |
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Oct 02 10:44:24 PM UTC 24 |
Oct 02 10:45:46 PM UTC 24 |
28828844636 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.1953753824 |
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Oct 02 10:45:36 PM UTC 24 |
Oct 02 10:45:47 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.4105490722 |
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Oct 02 10:45:44 PM UTC 24 |
Oct 02 10:45:48 PM UTC 24 |
2132920717 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.1614950024 |
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Oct 02 10:45:43 PM UTC 24 |
Oct 02 10:45:49 PM UTC 24 |
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| T581 |
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Oct 02 10:45:37 PM UTC 24 |
Oct 02 10:45:50 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.4192326003 |
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Oct 02 10:46:10 PM UTC 24 |
Oct 02 10:46:17 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.2994926920 |
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Oct 02 10:45:40 PM UTC 24 |
Oct 02 10:45:51 PM UTC 24 |
3629068086 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.3338572669 |
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Oct 02 10:45:46 PM UTC 24 |
Oct 02 10:45:51 PM UTC 24 |
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| T584 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.3145693337 |
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Oct 02 10:45:48 PM UTC 24 |
Oct 02 10:45:52 PM UTC 24 |
2241200940 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.3438191407 |
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Oct 02 10:42:39 PM UTC 24 |
Oct 02 10:45:53 PM UTC 24 |
72754288790 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.3456355800 |
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Oct 02 10:45:51 PM UTC 24 |
Oct 02 10:45:57 PM UTC 24 |
3238238480 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.2169656164 |
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Oct 02 10:45:55 PM UTC 24 |
Oct 02 10:45:58 PM UTC 24 |
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| T586 |
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Oct 02 10:45:51 PM UTC 24 |
Oct 02 10:45:59 PM UTC 24 |
9315501986 ps |
| T252 |
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Oct 02 10:45:12 PM UTC 24 |
Oct 02 10:46:00 PM UTC 24 |
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| T587 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2507277305 |
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Oct 02 10:45:43 PM UTC 24 |
Oct 02 10:46:01 PM UTC 24 |
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| T588 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1708555299 |
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Oct 02 10:45:49 PM UTC 24 |
Oct 02 10:46:02 PM UTC 24 |
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| T589 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.2144915546 |
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Oct 02 10:45:58 PM UTC 24 |
Oct 02 10:46:02 PM UTC 24 |
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| T590 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.812609797 |
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Oct 02 10:45:48 PM UTC 24 |
Oct 02 10:46:02 PM UTC 24 |
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| T591 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.506753496 |
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Oct 02 10:45:48 PM UTC 24 |
Oct 02 10:46:03 PM UTC 24 |
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| T592 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2440268590 |
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Oct 02 10:46:00 PM UTC 24 |
Oct 02 10:46:04 PM UTC 24 |
2241480085 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.239518263 |
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Oct 02 10:44:07 PM UTC 24 |
Oct 02 10:46:05 PM UTC 24 |
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| T593 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.3401610780 |
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Oct 02 10:46:01 PM UTC 24 |
Oct 02 10:46:06 PM UTC 24 |
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| T253 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1040293175 |
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Oct 02 10:41:18 PM UTC 24 |
Oct 02 10:46:06 PM UTC 24 |
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| T594 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.1951092418 |
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Oct 02 10:45:59 PM UTC 24 |
Oct 02 10:46:06 PM UTC 24 |
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| T595 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3519209550 |
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Oct 02 10:45:50 PM UTC 24 |
Oct 02 10:46:08 PM UTC 24 |
3932134222 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3069621543 |
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Oct 02 10:45:53 PM UTC 24 |
Oct 02 10:46:09 PM UTC 24 |
5294220233 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.4197066492 |
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Oct 02 10:46:05 PM UTC 24 |
Oct 02 10:46:10 PM UTC 24 |
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| T596 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3185546187 |
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Oct 02 10:46:02 PM UTC 24 |
Oct 02 10:46:11 PM UTC 24 |
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| T597 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.3350860040 |
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Oct 02 10:46:08 PM UTC 24 |
Oct 02 10:46:11 PM UTC 24 |
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| T598 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.3472371533 |
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Oct 02 10:46:09 PM UTC 24 |
Oct 02 10:46:14 PM UTC 24 |
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| T599 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.2923578902 |
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Oct 02 10:46:11 PM UTC 24 |
Oct 02 10:46:15 PM UTC 24 |
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| T600 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.736866331 |
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Oct 02 10:46:09 PM UTC 24 |
Oct 02 10:46:15 PM UTC 24 |
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| T601 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.2299411445 |
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Oct 02 10:46:11 PM UTC 24 |
Oct 02 10:46:16 PM UTC 24 |
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| T602 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1600118602 |
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Oct 02 10:46:03 PM UTC 24 |
Oct 02 10:46:16 PM UTC 24 |
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| T603 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3864624488 |
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Oct 02 10:46:07 PM UTC 24 |
Oct 02 10:46:17 PM UTC 24 |
3132028393 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.3691906237 |
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Oct 02 10:42:52 PM UTC 24 |
Oct 02 10:46:19 PM UTC 24 |
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| T604 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2233316220 |
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Oct 02 10:46:14 PM UTC 24 |
Oct 02 10:46:20 PM UTC 24 |
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| T605 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3321930571 |
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Oct 02 10:46:15 PM UTC 24 |
Oct 02 10:46:21 PM UTC 24 |
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| T606 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3208263524 |
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Oct 02 10:46:17 PM UTC 24 |
Oct 02 10:46:22 PM UTC 24 |
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| T401 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3346403623 |
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Oct 02 10:44:57 PM UTC 24 |
Oct 02 10:46:22 PM UTC 24 |
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| T109 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2874242451 |
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Oct 02 10:45:27 PM UTC 24 |
Oct 02 10:46:24 PM UTC 24 |
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| T607 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.657611228 |
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Oct 02 10:46:21 PM UTC 24 |
Oct 02 10:46:25 PM UTC 24 |
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| T608 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.2153694390 |
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Oct 02 10:46:23 PM UTC 24 |
Oct 02 10:46:26 PM UTC 24 |
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| T609 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.4110888825 |
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Oct 02 10:46:23 PM UTC 24 |
Oct 02 10:46:26 PM UTC 24 |
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| T224 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.829984966 |
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Oct 02 10:45:53 PM UTC 24 |
Oct 02 10:46:29 PM UTC 24 |
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| T610 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.51736715 |
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Oct 02 10:46:22 PM UTC 24 |
Oct 02 10:46:29 PM UTC 24 |
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| T611 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2362221243 |
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Oct 02 10:46:26 PM UTC 24 |
Oct 02 10:46:30 PM UTC 24 |
2650717968 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.283326891 |
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Oct 02 10:46:26 PM UTC 24 |
Oct 02 10:46:31 PM UTC 24 |
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| T155 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.3958129368 |
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Oct 02 10:46:20 PM UTC 24 |
Oct 02 10:46:32 PM UTC 24 |
10165563648 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.4041362937 |
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Oct 02 10:46:03 PM UTC 24 |
Oct 02 10:46:35 PM UTC 24 |
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| T373 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1066063168 |
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Oct 02 10:42:26 PM UTC 24 |
Oct 02 10:46:37 PM UTC 24 |
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| T375 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1682261129 |
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Oct 02 10:44:34 PM UTC 24 |
Oct 02 10:46:38 PM UTC 24 |
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| T330 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1647724150 |
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Oct 02 10:46:18 PM UTC 24 |
Oct 02 10:46:38 PM UTC 24 |
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| T613 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.3177094971 |
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Oct 02 10:46:33 PM UTC 24 |
Oct 02 10:46:38 PM UTC 24 |
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| T614 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3539981024 |
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Oct 02 10:46:27 PM UTC 24 |
Oct 02 10:46:39 PM UTC 24 |
3283632082 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.1502421218 |
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Oct 02 10:46:23 PM UTC 24 |
Oct 02 10:46:39 PM UTC 24 |
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| T616 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.663360597 |
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Oct 02 10:46:37 PM UTC 24 |
Oct 02 10:46:41 PM UTC 24 |
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| T617 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.1875832786 |
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Oct 02 10:46:39 PM UTC 24 |
Oct 02 10:46:41 PM UTC 24 |
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| T618 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.4144943205 |
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Oct 02 10:46:41 PM UTC 24 |
Oct 02 10:46:44 PM UTC 24 |
3293450645 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.2378052305 |
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Oct 02 10:46:39 PM UTC 24 |
Oct 02 10:46:44 PM UTC 24 |
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| T285 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.3063250555 |
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Oct 02 10:45:29 PM UTC 24 |
Oct 02 10:46:45 PM UTC 24 |
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| T620 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.3117859657 |
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Oct 02 10:46:40 PM UTC 24 |
Oct 02 10:46:45 PM UTC 24 |
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| T376 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1907547499 |
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Oct 02 10:44:42 PM UTC 24 |
Oct 02 10:46:46 PM UTC 24 |
157525251919 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.2717995615 |
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Oct 02 10:46:36 PM UTC 24 |
Oct 02 10:46:46 PM UTC 24 |
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| T622 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3352552345 |
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Oct 02 10:46:07 PM UTC 24 |
Oct 02 10:46:48 PM UTC 24 |
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| T196 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2983480734 |
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Oct 02 10:46:30 PM UTC 24 |
Oct 02 10:46:51 PM UTC 24 |
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| T623 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.4008369401 |
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Oct 02 10:46:49 PM UTC 24 |
Oct 02 10:46:52 PM UTC 24 |
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| T331 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3970989452 |
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Oct 02 10:46:31 PM UTC 24 |
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| T624 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.3957289877 |
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Oct 02 10:46:48 PM UTC 24 |
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| T625 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3413328002 |
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Oct 02 10:46:42 PM UTC 24 |
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| T626 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.843241392 |
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Oct 02 10:46:39 PM UTC 24 |
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Oct 02 10:46:46 PM UTC 24 |
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| T193 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2115748852 |
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Oct 02 10:46:46 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3565908923 |
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Oct 02 10:46:53 PM UTC 24 |
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| T433 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3934206275 |
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Oct 02 10:43:01 PM UTC 24 |
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| T629 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.2735720352 |
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Oct 02 10:46:52 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3218147814 |
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Oct 02 10:46:53 PM UTC 24 |
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Oct 02 10:46:04 PM UTC 24 |
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| T631 |
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Oct 02 10:46:53 PM UTC 24 |
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Oct 02 10:46:58 PM UTC 24 |
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Oct 02 10:45:52 PM UTC 24 |
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Oct 02 10:47:01 PM UTC 24 |
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Oct 02 10:46:45 PM UTC 24 |
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Oct 02 10:46:55 PM UTC 24 |
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Oct 02 10:44:56 PM UTC 24 |
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Oct 02 10:47:02 PM UTC 24 |
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2476948151 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.575025670 |
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Oct 02 10:43:40 PM UTC 24 |
Oct 02 10:47:07 PM UTC 24 |
224988504950 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1230250734 |
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Oct 02 10:46:54 PM UTC 24 |
Oct 02 10:47:08 PM UTC 24 |
2724824726 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.795122045 |
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Oct 02 10:47:04 PM UTC 24 |
Oct 02 10:47:09 PM UTC 24 |
2536014035 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3894179008 |
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Oct 02 10:47:04 PM UTC 24 |
Oct 02 10:47:09 PM UTC 24 |
2626466714 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3963265079 |
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Oct 02 10:47:07 PM UTC 24 |
Oct 02 10:47:10 PM UTC 24 |
3899209320 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3829210294 |
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Oct 02 10:46:54 PM UTC 24 |
Oct 02 10:47:11 PM UTC 24 |
3103438370 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1299244555 |
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Oct 02 10:47:07 PM UTC 24 |
Oct 02 10:47:11 PM UTC 24 |
6438558965 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.2164059458 |
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Oct 02 10:47:04 PM UTC 24 |
Oct 02 10:47:12 PM UTC 24 |
2129388138 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.3528788337 |
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Oct 02 10:47:02 PM UTC 24 |
Oct 02 10:47:13 PM UTC 24 |
2107924271 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1190093903 |
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Oct 02 10:47:00 PM UTC 24 |
Oct 02 10:47:13 PM UTC 24 |
8168412677 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.923504978 |
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Oct 02 10:43:47 PM UTC 24 |
Oct 02 10:47:13 PM UTC 24 |
120752897109 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.1715470083 |
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Oct 02 10:45:40 PM UTC 24 |
Oct 02 10:47:15 PM UTC 24 |
27083182965 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.2856662930 |
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Oct 02 10:47:11 PM UTC 24 |
Oct 02 10:47:16 PM UTC 24 |
2025734266 ps |