| T639 |
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Oct 02 10:47:11 PM UTC 24 |
Oct 02 10:47:16 PM UTC 24 |
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Oct 02 10:46:31 PM UTC 24 |
Oct 02 10:47:17 PM UTC 24 |
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Oct 02 10:47:12 PM UTC 24 |
Oct 02 10:47:18 PM UTC 24 |
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Oct 02 10:47:10 PM UTC 24 |
Oct 02 10:47:19 PM UTC 24 |
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Oct 02 10:46:18 PM UTC 24 |
Oct 02 10:47:20 PM UTC 24 |
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Oct 02 10:47:17 PM UTC 24 |
Oct 02 10:47:21 PM UTC 24 |
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Oct 02 10:47:14 PM UTC 24 |
Oct 02 10:47:22 PM UTC 24 |
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Oct 02 10:47:12 PM UTC 24 |
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Oct 02 10:47:08 PM UTC 24 |
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Oct 02 10:47:21 PM UTC 24 |
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Oct 02 10:47:13 PM UTC 24 |
Oct 02 10:47:26 PM UTC 24 |
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Oct 02 10:47:20 PM UTC 24 |
Oct 02 10:47:30 PM UTC 24 |
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Oct 02 10:47:21 PM UTC 24 |
Oct 02 10:47:31 PM UTC 24 |
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Oct 02 10:47:24 PM UTC 24 |
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Oct 02 10:46:44 PM UTC 24 |
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Oct 02 10:47:23 PM UTC 24 |
Oct 02 10:47:33 PM UTC 24 |
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Oct 02 10:47:25 PM UTC 24 |
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Oct 02 10:47:30 PM UTC 24 |
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Oct 02 10:47:31 PM UTC 24 |
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Oct 02 10:47:19 PM UTC 24 |
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Oct 02 10:47:27 PM UTC 24 |
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Oct 02 10:47:25 PM UTC 24 |
Oct 02 10:47:40 PM UTC 24 |
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Oct 02 10:47:37 PM UTC 24 |
Oct 02 10:47:41 PM UTC 24 |
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Oct 02 10:47:32 PM UTC 24 |
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Oct 02 10:43:09 PM UTC 24 |
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Oct 02 10:47:42 PM UTC 24 |
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Oct 02 10:47:38 PM UTC 24 |
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Oct 02 10:47:45 PM UTC 24 |
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Oct 02 10:47:37 PM UTC 24 |
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Oct 02 10:47:41 PM UTC 24 |
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Oct 02 10:49:15 PM UTC 24 |
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Oct 02 10:45:31 PM UTC 24 |
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Oct 02 10:47:35 PM UTC 24 |
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Oct 02 10:46:30 PM UTC 24 |
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Oct 02 10:47:48 PM UTC 24 |
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Oct 02 10:47:36 PM UTC 24 |
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Oct 02 10:47:49 PM UTC 24 |
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Oct 02 10:47:48 PM UTC 24 |
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Oct 02 10:45:51 PM UTC 24 |
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Oct 02 10:47:32 PM UTC 24 |
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Oct 02 10:47:43 PM UTC 24 |
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Oct 02 10:47:15 PM UTC 24 |
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Oct 02 10:47:54 PM UTC 24 |
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Oct 02 10:47:56 PM UTC 24 |
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Oct 02 10:47:53 PM UTC 24 |
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Oct 02 10:42:10 PM UTC 24 |
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Oct 02 10:41:39 PM UTC 24 |
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Oct 02 10:48:03 PM UTC 24 |
Oct 02 10:48:30 PM UTC 24 |
6853556137 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3780031595 |
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Oct 02 10:48:17 PM UTC 24 |
Oct 02 10:48:30 PM UTC 24 |
2513054350 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.459521197 |
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Oct 02 10:48:09 PM UTC 24 |
Oct 02 10:48:30 PM UTC 24 |
3714495505 ps |
| T697 |
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Oct 02 10:48:25 PM UTC 24 |
Oct 02 10:48:31 PM UTC 24 |
2018434080 ps |
| T698 |
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Oct 02 10:48:27 PM UTC 24 |
Oct 02 10:48:32 PM UTC 24 |
2124934943 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.3432402476 |
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Oct 02 10:47:07 PM UTC 24 |
Oct 02 10:48:32 PM UTC 24 |
93857130816 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.2087454594 |
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Oct 02 10:48:29 PM UTC 24 |
Oct 02 10:48:34 PM UTC 24 |
2035858703 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1463388165 |
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Oct 02 10:48:30 PM UTC 24 |
Oct 02 10:48:34 PM UTC 24 |
3733519328 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.292354332 |
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Oct 02 10:48:29 PM UTC 24 |
Oct 02 10:48:34 PM UTC 24 |
2604584002 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.466035233 |
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Oct 02 10:48:19 PM UTC 24 |
Oct 02 10:48:35 PM UTC 24 |
3527363368 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.4021107855 |
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Oct 02 10:48:29 PM UTC 24 |
Oct 02 10:48:35 PM UTC 24 |
2516925483 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.3062409847 |
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Oct 02 10:48:32 PM UTC 24 |
Oct 02 10:48:37 PM UTC 24 |
4830555925 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.1742299275 |
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Oct 02 10:48:25 PM UTC 24 |
Oct 02 10:48:40 PM UTC 24 |
14833137186 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2867351873 |
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Oct 02 10:48:34 PM UTC 24 |
Oct 02 10:48:41 PM UTC 24 |
2015688466 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.2613047106 |
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Oct 02 10:48:37 PM UTC 24 |
Oct 02 10:48:41 PM UTC 24 |
2049230337 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.1117164240 |
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Oct 02 10:48:36 PM UTC 24 |
Oct 02 10:48:42 PM UTC 24 |
2123338081 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.2337253244 |
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Oct 02 10:48:38 PM UTC 24 |
Oct 02 10:48:43 PM UTC 24 |
2528616638 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.67237487 |
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Oct 02 10:48:24 PM UTC 24 |
Oct 02 10:48:43 PM UTC 24 |
4785747912 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.1937399471 |
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Oct 02 10:48:27 PM UTC 24 |
Oct 02 10:48:44 PM UTC 24 |
2472215774 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2517596538 |
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Oct 02 10:46:27 PM UTC 24 |
Oct 02 10:48:44 PM UTC 24 |
1723220530235 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.3390970132 |
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Oct 02 10:44:36 PM UTC 24 |
Oct 02 10:48:44 PM UTC 24 |
139044617365 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3054976029 |
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Oct 02 10:48:29 PM UTC 24 |
Oct 02 10:48:44 PM UTC 24 |
2613342626 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.660903013 |
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Oct 02 10:48:41 PM UTC 24 |
Oct 02 10:48:46 PM UTC 24 |
2632383135 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.4130806098 |
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Oct 02 10:48:42 PM UTC 24 |
Oct 02 10:48:48 PM UTC 24 |
2800529173 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3983078341 |
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Oct 02 10:47:18 PM UTC 24 |
Oct 02 10:48:49 PM UTC 24 |
58389365966 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2681827072 |
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Oct 02 10:44:23 PM UTC 24 |
Oct 02 10:48:49 PM UTC 24 |
182859937758 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.222893189 |
|
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Oct 02 10:48:37 PM UTC 24 |
Oct 02 10:48:50 PM UTC 24 |
2463699803 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1362257179 |
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Oct 02 10:48:43 PM UTC 24 |
Oct 02 10:48:50 PM UTC 24 |
3809284538 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.373580074 |
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Oct 02 10:48:49 PM UTC 24 |
Oct 02 10:48:52 PM UTC 24 |
2489245140 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.2246515192 |
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Oct 02 10:48:50 PM UTC 24 |
Oct 02 10:48:53 PM UTC 24 |
2081052200 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.999214303 |
|
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Oct 02 10:48:46 PM UTC 24 |
Oct 02 10:48:54 PM UTC 24 |
2014539613 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3714902425 |
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Oct 02 10:48:51 PM UTC 24 |
Oct 02 10:48:54 PM UTC 24 |
2717155758 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1189222214 |
|
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Oct 02 10:48:33 PM UTC 24 |
Oct 02 10:48:55 PM UTC 24 |
4473064199 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.1070787165 |
|
|
Oct 02 10:48:13 PM UTC 24 |
Oct 02 10:48:56 PM UTC 24 |
28573434641 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.947605909 |
|
|
Oct 02 10:45:32 PM UTC 24 |
Oct 02 10:48:57 PM UTC 24 |
277582933411 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3569076661 |
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Oct 02 10:46:45 PM UTC 24 |
Oct 02 10:48:57 PM UTC 24 |
34919264828 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1310608077 |
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|
Oct 02 10:48:42 PM UTC 24 |
Oct 02 10:48:58 PM UTC 24 |
3025218263 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.1137135947 |
|
|
Oct 02 10:48:50 PM UTC 24 |
Oct 02 10:48:58 PM UTC 24 |
2519405867 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.176556040 |
|
|
Oct 02 10:48:44 PM UTC 24 |
Oct 02 10:48:58 PM UTC 24 |
3293743228 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.3559058861 |
|
|
Oct 02 10:48:47 PM UTC 24 |
Oct 02 10:48:59 PM UTC 24 |
2109416071 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.967980996 |
|
|
Oct 02 10:48:54 PM UTC 24 |
Oct 02 10:48:59 PM UTC 24 |
2945996055 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3433400328 |
|
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Oct 02 10:48:23 PM UTC 24 |
Oct 02 10:49:01 PM UTC 24 |
26590051919 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.430840977 |
|
|
Oct 02 10:48:46 PM UTC 24 |
Oct 02 10:49:02 PM UTC 24 |
3929810620 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.4201893321 |
|
|
Oct 02 10:48:59 PM UTC 24 |
Oct 02 10:49:04 PM UTC 24 |
2259618171 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.2489619645 |
|
|
Oct 02 10:48:59 PM UTC 24 |
Oct 02 10:49:04 PM UTC 24 |
2129905248 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3148581509 |
|
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Oct 02 10:49:00 PM UTC 24 |
Oct 02 10:49:04 PM UTC 24 |
2641834461 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.2256541393 |
|
|
Oct 02 10:48:58 PM UTC 24 |
Oct 02 10:49:05 PM UTC 24 |
2010510897 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1936223833 |
|
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Oct 02 10:46:42 PM UTC 24 |
Oct 02 10:49:05 PM UTC 24 |
1802642782627 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3589850225 |
|
|
Oct 02 10:48:57 PM UTC 24 |
Oct 02 10:49:06 PM UTC 24 |
2450735071 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.1072599718 |
|
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Oct 02 10:48:59 PM UTC 24 |
Oct 02 10:49:06 PM UTC 24 |
2460773930 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3239276515 |
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|
Oct 02 10:48:51 PM UTC 24 |
Oct 02 10:49:08 PM UTC 24 |
4842134632 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.2589405707 |
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Oct 02 10:48:46 PM UTC 24 |
Oct 02 10:49:08 PM UTC 24 |
15277460392 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2037272900 |
|
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Oct 02 10:49:05 PM UTC 24 |
Oct 02 10:49:09 PM UTC 24 |
4661479488 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.3651641713 |
|
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Oct 02 10:49:05 PM UTC 24 |
Oct 02 10:49:10 PM UTC 24 |
5207912916 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.378706005 |
|
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Oct 02 10:47:01 PM UTC 24 |
Oct 02 10:49:12 PM UTC 24 |
235328445100 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.413379124 |
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Oct 02 10:48:58 PM UTC 24 |
Oct 02 10:49:13 PM UTC 24 |
13252094734 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.3549615410 |
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Oct 02 10:49:09 PM UTC 24 |
Oct 02 10:49:13 PM UTC 24 |
2477891925 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3275296505 |
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Oct 02 10:48:59 PM UTC 24 |
Oct 02 10:49:14 PM UTC 24 |
2514123789 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3576423853 |
|
|
Oct 02 10:48:02 PM UTC 24 |
Oct 02 10:49:15 PM UTC 24 |
51311946161 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.3400297342 |
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|
Oct 02 10:49:07 PM UTC 24 |
Oct 02 10:49:16 PM UTC 24 |
2007207267 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.3161231667 |
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Oct 02 10:49:11 PM UTC 24 |
Oct 02 10:49:16 PM UTC 24 |
2538001377 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.3869584155 |
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Oct 02 10:49:10 PM UTC 24 |
Oct 02 10:49:16 PM UTC 24 |
2169327968 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.3885939628 |
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Oct 02 10:49:07 PM UTC 24 |
Oct 02 10:49:16 PM UTC 24 |
9129471249 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1205809171 |
|
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Oct 02 10:49:02 PM UTC 24 |
Oct 02 10:49:16 PM UTC 24 |
3629869852 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.374293527 |
|
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Oct 02 10:49:08 PM UTC 24 |
Oct 02 10:49:17 PM UTC 24 |
2108781386 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2473505292 |
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|
Oct 02 10:49:06 PM UTC 24 |
Oct 02 10:49:17 PM UTC 24 |
15802980130 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.986035799 |
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Oct 02 10:48:54 PM UTC 24 |
Oct 02 10:49:19 PM UTC 24 |
5481699070 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.1832046746 |
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Oct 02 10:49:17 PM UTC 24 |
Oct 02 10:49:23 PM UTC 24 |
2018813362 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3698767125 |
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Oct 02 10:49:14 PM UTC 24 |
Oct 02 10:49:19 PM UTC 24 |
2954839327 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.532118139 |
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Oct 02 10:46:59 PM UTC 24 |
Oct 02 10:49:20 PM UTC 24 |
42339318277 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.1349599346 |
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Oct 02 10:48:34 PM UTC 24 |
Oct 02 10:49:20 PM UTC 24 |
9292909915 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2771236788 |
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Oct 02 10:49:14 PM UTC 24 |
Oct 02 10:49:21 PM UTC 24 |
2616776602 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.2062798301 |
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Oct 02 10:47:49 PM UTC 24 |
Oct 02 10:49:22 PM UTC 24 |
74737665333 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.653678290 |
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Oct 02 10:49:14 PM UTC 24 |
Oct 02 10:49:26 PM UTC 24 |
3784654975 ps |
| T406 |
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Oct 02 10:48:45 PM UTC 24 |
Oct 02 10:49:26 PM UTC 24 |
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Oct 02 10:45:02 PM UTC 24 |
Oct 02 10:49:27 PM UTC 24 |
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Oct 02 10:47:59 PM UTC 24 |
Oct 02 10:49:27 PM UTC 24 |
107897349130 ps |
| T215 |
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Oct 02 10:44:26 PM UTC 24 |
Oct 02 10:49:29 PM UTC 24 |
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| T408 |
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Oct 02 10:48:56 PM UTC 24 |
Oct 02 10:49:29 PM UTC 24 |
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Oct 02 10:47:17 PM UTC 24 |
Oct 02 10:49:29 PM UTC 24 |
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Oct 02 10:49:17 PM UTC 24 |
Oct 02 10:49:30 PM UTC 24 |
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Oct 02 10:46:17 PM UTC 24 |
Oct 02 10:49:33 PM UTC 24 |
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Oct 02 10:42:05 PM UTC 24 |
Oct 02 10:49:36 PM UTC 24 |
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Oct 02 10:49:17 PM UTC 24 |
Oct 02 10:49:37 PM UTC 24 |
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Oct 02 10:47:52 PM UTC 24 |
Oct 02 10:49:39 PM UTC 24 |
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Oct 02 10:49:24 PM UTC 24 |
Oct 02 10:49:44 PM UTC 24 |
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Oct 02 10:49:24 PM UTC 24 |
Oct 02 10:49:45 PM UTC 24 |
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Oct 02 10:47:34 PM UTC 24 |
Oct 02 10:49:49 PM UTC 24 |
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Oct 02 10:41:58 PM UTC 24 |
Oct 02 10:49:55 PM UTC 24 |
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Oct 02 10:49:17 PM UTC 24 |
Oct 02 10:49:56 PM UTC 24 |
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Oct 02 10:44:14 PM UTC 24 |
Oct 02 10:49:58 PM UTC 24 |
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Oct 02 10:48:54 PM UTC 24 |
Oct 02 10:49:59 PM UTC 24 |
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Oct 02 10:49:20 PM UTC 24 |
Oct 02 10:50:05 PM UTC 24 |
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Oct 02 10:48:33 PM UTC 24 |
Oct 02 10:50:11 PM UTC 24 |
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Oct 02 10:48:52 PM UTC 24 |
Oct 02 10:50:14 PM UTC 24 |
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Oct 02 10:50:00 PM UTC 24 |
Oct 02 10:50:16 PM UTC 24 |
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Oct 02 10:49:19 PM UTC 24 |
Oct 02 10:50:18 PM UTC 24 |
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Oct 02 10:50:42 PM UTC 24 |
Oct 02 10:52:41 PM UTC 24 |
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| T758 |
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Oct 02 10:49:17 PM UTC 24 |
Oct 02 10:50:20 PM UTC 24 |
90621995615 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1586837651 |
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Oct 02 10:49:22 PM UTC 24 |
Oct 02 10:50:23 PM UTC 24 |
65765204368 ps |
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Oct 02 10:49:40 PM UTC 24 |
Oct 02 10:50:30 PM UTC 24 |
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| T380 |
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Oct 02 10:49:27 PM UTC 24 |
Oct 02 10:50:30 PM UTC 24 |
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Oct 02 10:50:14 PM UTC 24 |
Oct 02 10:52:45 PM UTC 24 |
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Oct 02 10:49:46 PM UTC 24 |
Oct 02 10:50:31 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.846963445 |
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Oct 02 10:49:23 PM UTC 24 |
Oct 02 10:50:34 PM UTC 24 |
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Oct 02 10:48:14 PM UTC 24 |
Oct 02 10:50:35 PM UTC 24 |
93913624301 ps |
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3553162153 |
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Oct 02 10:49:56 PM UTC 24 |
Oct 02 10:50:40 PM UTC 24 |
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Oct 02 10:48:31 PM UTC 24 |
Oct 02 10:50:41 PM UTC 24 |
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Oct 02 10:49:06 PM UTC 24 |
Oct 02 10:50:43 PM UTC 24 |
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Oct 02 10:49:30 PM UTC 24 |
Oct 02 10:50:44 PM UTC 24 |
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Oct 02 10:49:27 PM UTC 24 |
Oct 02 10:50:49 PM UTC 24 |
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Oct 02 10:43:01 PM UTC 24 |
Oct 02 10:50:51 PM UTC 24 |
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Oct 02 10:50:17 PM UTC 24 |
Oct 02 10:51:00 PM UTC 24 |
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Oct 02 10:47:16 PM UTC 24 |
Oct 02 10:51:01 PM UTC 24 |
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Oct 02 10:49:27 PM UTC 24 |
Oct 02 10:51:04 PM UTC 24 |
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Oct 02 10:42:13 PM UTC 24 |
Oct 02 10:51:05 PM UTC 24 |
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Oct 02 10:50:12 PM UTC 24 |
Oct 02 10:51:06 PM UTC 24 |
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Oct 02 10:49:49 PM UTC 24 |
Oct 02 10:51:13 PM UTC 24 |
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Oct 02 10:49:37 PM UTC 24 |
Oct 02 10:51:14 PM UTC 24 |
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Oct 02 10:49:16 PM UTC 24 |
Oct 02 10:51:15 PM UTC 24 |
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Oct 02 10:49:34 PM UTC 24 |
Oct 02 10:51:16 PM UTC 24 |
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Oct 02 10:44:04 PM UTC 24 |
Oct 02 10:51:19 PM UTC 24 |
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Oct 02 10:49:59 PM UTC 24 |
Oct 02 10:51:23 PM UTC 24 |
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Oct 02 10:50:19 PM UTC 24 |
Oct 02 10:51:24 PM UTC 24 |
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Oct 02 10:50:31 PM UTC 24 |
Oct 02 10:51:28 PM UTC 24 |
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Oct 02 10:50:36 PM UTC 24 |
Oct 02 10:51:41 PM UTC 24 |
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Oct 02 10:46:03 PM UTC 24 |
Oct 02 10:51:49 PM UTC 24 |
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Oct 02 10:50:35 PM UTC 24 |
Oct 02 10:52:05 PM UTC 24 |
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Oct 02 10:49:57 PM UTC 24 |
Oct 02 10:52:07 PM UTC 24 |
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Oct 02 10:48:21 PM UTC 24 |
Oct 02 10:52:08 PM UTC 24 |
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Oct 02 10:43:32 PM UTC 24 |
Oct 02 10:52:14 PM UTC 24 |
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Oct 02 10:49:31 PM UTC 24 |
Oct 02 10:52:15 PM UTC 24 |
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Oct 02 10:50:31 PM UTC 24 |
Oct 02 10:52:17 PM UTC 24 |
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Oct 02 10:49:21 PM UTC 24 |
Oct 02 10:52:24 PM UTC 24 |
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Oct 02 10:50:32 PM UTC 24 |
Oct 02 10:52:35 PM UTC 24 |
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Oct 02 10:44:44 PM UTC 24 |
Oct 02 10:52:38 PM UTC 24 |
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Oct 02 10:50:00 PM UTC 24 |
Oct 02 10:52:38 PM UTC 24 |
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Oct 02 10:49:18 PM UTC 24 |
Oct 02 10:52:39 PM UTC 24 |
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Oct 02 10:49:27 PM UTC 24 |
Oct 02 10:52:47 PM UTC 24 |
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Oct 02 10:49:26 PM UTC 24 |
Oct 02 10:52:48 PM UTC 24 |
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Oct 02 10:50:24 PM UTC 24 |
Oct 02 10:52:56 PM UTC 24 |
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Oct 02 10:50:13 PM UTC 24 |
Oct 02 10:53:07 PM UTC 24 |
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Oct 02 10:49:23 PM UTC 24 |
Oct 02 10:53:10 PM UTC 24 |
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Oct 02 10:50:32 PM UTC 24 |
Oct 02 10:53:40 PM UTC 24 |
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Oct 02 10:48:10 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
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Oct 02 10:48:44 PM UTC 24 |
Oct 02 10:53:48 PM UTC 24 |
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Oct 02 10:44:56 PM UTC 24 |
Oct 02 10:53:48 PM UTC 24 |
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Oct 02 10:49:30 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
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Oct 02 10:49:17 PM UTC 24 |
Oct 02 10:54:08 PM UTC 24 |
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Oct 02 10:46:06 PM UTC 24 |
Oct 02 10:54:21 PM UTC 24 |
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Oct 02 10:46:55 PM UTC 24 |
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Oct 02 10:50:22 PM UTC 24 |
Oct 02 10:54:41 PM UTC 24 |
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Oct 02 10:49:30 PM UTC 24 |
Oct 02 10:54:44 PM UTC 24 |
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Oct 02 10:44:04 PM UTC 24 |
Oct 02 10:54:48 PM UTC 24 |
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Oct 02 10:45:39 PM UTC 24 |
Oct 02 10:54:55 PM UTC 24 |
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Oct 02 10:50:42 PM UTC 24 |
Oct 02 10:54:55 PM UTC 24 |
132370792616 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.25489499 |
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Oct 02 10:47:58 PM UTC 24 |
Oct 02 10:55:31 PM UTC 24 |
143404988734 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.91390225 |
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Oct 02 10:48:31 PM UTC 24 |
Oct 02 10:56:32 PM UTC 24 |
6543149112667 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2054144721 |
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Oct 02 10:44:22 PM UTC 24 |
Oct 02 10:56:45 PM UTC 24 |
244569403725 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.306181440 |
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Oct 02 10:49:05 PM UTC 24 |
Oct 02 10:57:17 PM UTC 24 |
193101563280 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1114077081 |
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Oct 02 10:42:45 PM UTC 24 |
Oct 02 10:57:18 PM UTC 24 |
259048009274 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.420811338 |
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Oct 02 10:47:15 PM UTC 24 |
Oct 02 11:05:44 PM UTC 24 |
392142642732 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3197092974 |
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Oct 02 10:44:40 PM UTC 24 |
Oct 02 11:14:18 PM UTC 24 |
1247897445809 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.3813543103 |
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Oct 02 10:42:40 PM UTC 24 |
Oct 02 11:18:48 PM UTC 24 |
1169737289899 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.664094636 |
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Oct 02 10:41:37 PM UTC 24 |
Oct 02 11:33:49 PM UTC 24 |
1251080757411 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3880099218 |
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Oct 02 10:49:01 PM UTC 24 |
Oct 02 11:35:08 PM UTC 24 |
899431163269 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.62535371 |
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Oct 02 10:50:45 PM UTC 24 |
Oct 02 10:50:49 PM UTC 24 |
2249607659 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2517933130 |
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Oct 02 10:50:49 PM UTC 24 |
Oct 02 10:50:54 PM UTC 24 |
2032040618 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3518873508 |
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Oct 02 10:50:50 PM UTC 24 |
Oct 02 10:50:57 PM UTC 24 |
4045965150 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.322969165 |
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Oct 02 10:50:52 PM UTC 24 |
Oct 02 10:50:57 PM UTC 24 |
2073189614 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3094559945 |
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Oct 02 10:50:57 PM UTC 24 |
Oct 02 10:51:04 PM UTC 24 |
2662465865 ps |