| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.03 | 99.29 | 97.93 | 100.00 | 96.79 | 99.52 | 99.52 | 86.18 |
| T316 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3291853484 | Oct 02 10:51:02 PM UTC 24 | Oct 02 10:51:06 PM UTC 24 | 2188186280 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.453154191 | Oct 02 10:51:02 PM UTC 24 | Oct 02 10:51:07 PM UTC 24 | 2430462987 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1580625262 | Oct 02 10:51:07 PM UTC 24 | Oct 02 10:51:11 PM UTC 24 | 2111093941 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2707874411 | Oct 02 10:51:07 PM UTC 24 | Oct 02 10:51:16 PM UTC 24 | 2510377390 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.291076725 | Oct 02 10:51:11 PM UTC 24 | Oct 02 10:51:16 PM UTC 24 | 4694705946 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3444807001 | Oct 02 10:51:13 PM UTC 24 | Oct 02 10:51:17 PM UTC 24 | 2558426399 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4096574645 | Oct 02 10:51:05 PM UTC 24 | Oct 02 10:51:17 PM UTC 24 | 2011532920 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.81620357 | Oct 02 10:50:54 PM UTC 24 | Oct 02 10:51:18 PM UTC 24 | 40574462507 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2156702204 | Oct 02 10:51:17 PM UTC 24 | Oct 02 10:51:19 PM UTC 24 | 2135459370 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2135893902 | Oct 02 10:51:06 PM UTC 24 | Oct 02 10:51:24 PM UTC 24 | 4018250220 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3674309717 | Oct 02 10:51:17 PM UTC 24 | Oct 02 10:51:24 PM UTC 24 | 4045056817 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.4195279609 | Oct 02 10:51:19 PM UTC 24 | Oct 02 10:51:24 PM UTC 24 | 2102972175 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.279690386 | Oct 02 10:51:18 PM UTC 24 | Oct 02 10:51:27 PM UTC 24 | 2554922054 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1396324814 | Oct 02 10:51:20 PM UTC 24 | Oct 02 10:51:28 PM UTC 24 | 2027355104 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3407235259 | Oct 02 10:51:14 PM UTC 24 | Oct 02 10:51:28 PM UTC 24 | 2087295733 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2693500645 | Oct 02 10:51:25 PM UTC 24 | Oct 02 10:51:29 PM UTC 24 | 2052553147 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2561232017 | Oct 02 10:51:18 PM UTC 24 | Oct 02 10:51:29 PM UTC 24 | 4415031283 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3185616400 | Oct 02 10:51:25 PM UTC 24 | Oct 02 10:51:29 PM UTC 24 | 4056212261 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3275698799 | Oct 02 10:51:17 PM UTC 24 | Oct 02 10:51:30 PM UTC 24 | 2048495904 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2495251798 | Oct 02 10:51:19 PM UTC 24 | Oct 02 10:51:32 PM UTC 24 | 5084184857 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3559551542 | Oct 02 10:51:30 PM UTC 24 | Oct 02 10:51:34 PM UTC 24 | 2051881309 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1050247701 | Oct 02 10:51:31 PM UTC 24 | Oct 02 10:51:35 PM UTC 24 | 2069677947 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3902893022 | Oct 02 10:51:24 PM UTC 24 | Oct 02 10:51:35 PM UTC 24 | 2013671527 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3316285651 | Oct 02 10:51:29 PM UTC 24 | Oct 02 10:51:36 PM UTC 24 | 2047582187 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2461694785 | Oct 02 10:51:30 PM UTC 24 | Oct 02 10:51:38 PM UTC 24 | 6035957120 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1337868447 | Oct 02 10:51:36 PM UTC 24 | Oct 02 10:51:40 PM UTC 24 | 2117207382 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.4284684203 | Oct 02 10:51:29 PM UTC 24 | Oct 02 10:51:41 PM UTC 24 | 2039385174 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2255770165 | Oct 02 10:51:33 PM UTC 24 | Oct 02 10:51:42 PM UTC 24 | 4469806100 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2914223745 | Oct 02 10:51:36 PM UTC 24 | Oct 02 10:51:43 PM UTC 24 | 4687906819 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1689474172 | Oct 02 10:51:28 PM UTC 24 | Oct 02 10:51:43 PM UTC 24 | 2507082217 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.481057332 | Oct 02 10:51:35 PM UTC 24 | Oct 02 10:51:45 PM UTC 24 | 2329353260 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3082098908 | Oct 02 10:51:41 PM UTC 24 | Oct 02 10:51:46 PM UTC 24 | 2035781249 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.4177596329 | Oct 02 10:51:37 PM UTC 24 | Oct 02 10:51:47 PM UTC 24 | 2056894531 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3572359866 | Oct 02 10:51:46 PM UTC 24 | Oct 02 10:51:50 PM UTC 24 | 2111701932 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3613494494 | Oct 02 10:51:44 PM UTC 24 | Oct 02 10:51:50 PM UTC 24 | 4061882475 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3019900130 | Oct 02 10:51:43 PM UTC 24 | Oct 02 10:51:51 PM UTC 24 | 2045620892 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2885358265 | Oct 02 10:50:58 PM UTC 24 | Oct 02 10:51:52 PM UTC 24 | 10279798822 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3537278266 | Oct 02 10:51:47 PM UTC 24 | Oct 02 10:51:54 PM UTC 24 | 2045550640 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2185477111 | Oct 02 10:51:50 PM UTC 24 | Oct 02 10:51:55 PM UTC 24 | 2112825230 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.4143848630 | Oct 02 10:51:42 PM UTC 24 | Oct 02 10:51:56 PM UTC 24 | 2033491237 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.676638264 | Oct 02 10:51:48 PM UTC 24 | Oct 02 10:51:58 PM UTC 24 | 7331916100 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.622937313 | Oct 02 10:51:53 PM UTC 24 | Oct 02 10:51:59 PM UTC 24 | 2052397390 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3495931606 | Oct 02 10:51:29 PM UTC 24 | Oct 02 10:52:01 PM UTC 24 | 8947278910 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1264184720 | Oct 02 10:52:21 PM UTC 24 | Oct 02 10:52:28 PM UTC 24 | 2042365972 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2710347619 | Oct 02 10:51:52 PM UTC 24 | Oct 02 10:52:01 PM UTC 24 | 2017671423 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2860753727 | Oct 02 10:51:55 PM UTC 24 | Oct 02 10:52:02 PM UTC 24 | 2057379993 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.12382898 | Oct 02 10:51:51 PM UTC 24 | Oct 02 10:52:03 PM UTC 24 | 2029057511 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2083878859 | Oct 02 10:52:00 PM UTC 24 | Oct 02 10:52:05 PM UTC 24 | 2070598336 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2695119854 | Oct 02 10:51:59 PM UTC 24 | Oct 02 10:52:05 PM UTC 24 | 2022510639 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1449595394 | Oct 02 10:52:03 PM UTC 24 | Oct 02 10:52:07 PM UTC 24 | 2382186028 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3169773029 | Oct 02 10:51:56 PM UTC 24 | Oct 02 10:52:08 PM UTC 24 | 2082801723 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2999267544 | Oct 02 10:52:06 PM UTC 24 | Oct 02 10:52:10 PM UTC 24 | 2096960923 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2189041522 | Oct 02 10:51:24 PM UTC 24 | Oct 02 10:52:12 PM UTC 24 | 22362191112 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.383816470 | Oct 02 10:51:42 PM UTC 24 | Oct 02 10:52:13 PM UTC 24 | 4725192045 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1694941477 | Oct 02 10:52:09 PM UTC 24 | Oct 02 10:52:14 PM UTC 24 | 2023909477 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2472382276 | Oct 02 10:52:08 PM UTC 24 | Oct 02 10:52:14 PM UTC 24 | 2499702955 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3807053269 | Oct 02 10:52:02 PM UTC 24 | Oct 02 10:52:15 PM UTC 24 | 2076490825 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.4193954352 | Oct 02 10:52:06 PM UTC 24 | Oct 02 10:52:17 PM UTC 24 | 2014120459 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3009225127 | Oct 02 10:52:07 PM UTC 24 | Oct 02 10:52:19 PM UTC 24 | 2045643614 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3915761406 | Oct 02 10:52:14 PM UTC 24 | Oct 02 10:52:19 PM UTC 24 | 2084016076 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.4235570406 | Oct 02 10:52:15 PM UTC 24 | Oct 02 10:52:19 PM UTC 24 | 2029052201 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.224589770 | Oct 02 10:51:55 PM UTC 24 | Oct 02 10:52:20 PM UTC 24 | 4515540618 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2768398450 | Oct 02 10:52:16 PM UTC 24 | Oct 02 10:52:21 PM UTC 24 | 2062168639 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1742485893 | Oct 02 10:52:17 PM UTC 24 | Oct 02 10:52:23 PM UTC 24 | 2077597109 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1206488932 | Oct 02 10:52:11 PM UTC 24 | Oct 02 10:52:23 PM UTC 24 | 2042763326 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.12266777 | Oct 02 10:52:20 PM UTC 24 | Oct 02 10:52:26 PM UTC 24 | 2022974280 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.724289613 | Oct 02 10:52:15 PM UTC 24 | Oct 02 10:52:26 PM UTC 24 | 2123082831 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.812713874 | Oct 02 10:52:16 PM UTC 24 | Oct 02 10:52:26 PM UTC 24 | 7221979648 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1440408954 | Oct 02 10:52:17 PM UTC 24 | Oct 02 10:52:27 PM UTC 24 | 2084815058 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3072415775 | Oct 02 10:52:22 PM UTC 24 | Oct 02 10:52:27 PM UTC 24 | 2082828541 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2957552218 | Oct 02 10:51:07 PM UTC 24 | Oct 02 10:52:29 PM UTC 24 | 76302028231 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3240519025 | Oct 02 10:52:15 PM UTC 24 | Oct 02 10:52:30 PM UTC 24 | 43108987480 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2224427309 | Oct 02 10:52:26 PM UTC 24 | Oct 02 10:52:30 PM UTC 24 | 2093996633 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1945397368 | Oct 02 10:52:25 PM UTC 24 | Oct 02 10:52:30 PM UTC 24 | 2021833571 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3378467122 | Oct 02 10:52:27 PM UTC 24 | Oct 02 10:52:31 PM UTC 24 | 2171784977 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2699436426 | Oct 02 10:52:06 PM UTC 24 | Oct 02 10:52:31 PM UTC 24 | 4565377712 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.364172208 | Oct 02 10:52:02 PM UTC 24 | Oct 02 10:52:32 PM UTC 24 | 5360963178 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1027021274 | Oct 02 10:52:24 PM UTC 24 | Oct 02 10:52:33 PM UTC 24 | 2080036246 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3436956537 | Oct 02 10:52:09 PM UTC 24 | Oct 02 10:52:33 PM UTC 24 | 22474221058 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1129019662 | Oct 02 10:52:27 PM UTC 24 | Oct 02 10:52:33 PM UTC 24 | 2098637052 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1625824957 | Oct 02 10:51:05 PM UTC 24 | Oct 02 10:52:34 PM UTC 24 | 22203126328 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3442385623 | Oct 02 10:52:30 PM UTC 24 | Oct 02 10:52:34 PM UTC 24 | 2082292262 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1376540853 | Oct 02 10:51:57 PM UTC 24 | Oct 02 10:52:35 PM UTC 24 | 22397498395 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3577454110 | Oct 02 10:52:32 PM UTC 24 | Oct 02 10:52:36 PM UTC 24 | 2027956034 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3067683382 | Oct 02 10:52:04 PM UTC 24 | Oct 02 10:52:36 PM UTC 24 | 22289727420 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.134179388 | Oct 02 10:52:33 PM UTC 24 | Oct 02 10:52:37 PM UTC 24 | 5771907650 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2147130163 | Oct 02 10:52:29 PM UTC 24 | Oct 02 10:52:37 PM UTC 24 | 2017819378 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2002490898 | Oct 02 10:52:31 PM UTC 24 | Oct 02 10:52:38 PM UTC 24 | 2077218954 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.920199083 | Oct 02 10:52:37 PM UTC 24 | Oct 02 10:52:40 PM UTC 24 | 2301715322 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3960162332 | Oct 02 10:52:33 PM UTC 24 | Oct 02 10:52:40 PM UTC 24 | 2051004647 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.317771151 | Oct 02 10:52:34 PM UTC 24 | Oct 02 10:52:41 PM UTC 24 | 2164572914 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3522815251 | Oct 02 10:52:36 PM UTC 24 | Oct 02 10:52:41 PM UTC 24 | 5001459962 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3042141943 | Oct 02 10:52:21 PM UTC 24 | Oct 02 10:52:42 PM UTC 24 | 5048279336 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1813580569 | Oct 02 10:52:56 PM UTC 24 | Oct 02 10:53:06 PM UTC 24 | 2017318106 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3035695244 | Oct 02 10:52:36 PM UTC 24 | Oct 02 10:52:42 PM UTC 24 | 2024358014 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3283918781 | Oct 02 10:52:31 PM UTC 24 | Oct 02 10:52:42 PM UTC 24 | 2092032107 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1030627162 | Oct 02 10:52:39 PM UTC 24 | Oct 02 10:52:43 PM UTC 24 | 2733485236 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.92637123 | Oct 02 10:52:39 PM UTC 24 | Oct 02 10:52:44 PM UTC 24 | 2073848830 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1069350732 | Oct 02 10:52:34 PM UTC 24 | Oct 02 10:52:44 PM UTC 24 | 2065188552 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2590422738 | Oct 02 10:52:36 PM UTC 24 | Oct 02 10:52:44 PM UTC 24 | 2033129007 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1726169974 | Oct 02 10:52:39 PM UTC 24 | Oct 02 10:52:44 PM UTC 24 | 2059446232 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.26677808 | Oct 02 10:51:44 PM UTC 24 | Oct 02 10:53:08 PM UTC 24 | 22212056703 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2006006303 | Oct 02 10:52:37 PM UTC 24 | Oct 02 10:52:44 PM UTC 24 | 2093045600 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3990404985 | Oct 02 10:52:42 PM UTC 24 | Oct 02 10:52:45 PM UTC 24 | 2088059061 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3444011903 | Oct 02 10:52:42 PM UTC 24 | Oct 02 10:52:46 PM UTC 24 | 2164588770 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1068513824 | Oct 02 10:52:45 PM UTC 24 | Oct 02 10:52:48 PM UTC 24 | 2062981757 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1185963278 | Oct 02 10:52:44 PM UTC 24 | Oct 02 10:52:49 PM UTC 24 | 2076774912 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2722139689 | Oct 02 10:52:42 PM UTC 24 | Oct 02 10:52:49 PM UTC 24 | 2023016385 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1982592502 | Oct 02 10:52:43 PM UTC 24 | Oct 02 10:52:49 PM UTC 24 | 2217436374 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.702647447 | Oct 02 10:52:45 PM UTC 24 | Oct 02 10:52:50 PM UTC 24 | 2075721975 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1890284538 | Oct 02 10:52:38 PM UTC 24 | Oct 02 10:52:50 PM UTC 24 | 2009380767 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2167312860 | Oct 02 10:52:39 PM UTC 24 | Oct 02 10:52:51 PM UTC 24 | 7428600997 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2088146192 | Oct 02 10:52:47 PM UTC 24 | Oct 02 10:52:51 PM UTC 24 | 2038486458 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2450133273 | Oct 02 10:52:42 PM UTC 24 | Oct 02 10:52:51 PM UTC 24 | 9821913247 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2213271522 | Oct 02 10:52:47 PM UTC 24 | Oct 02 10:52:52 PM UTC 24 | 2043516702 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1153185760 | Oct 02 10:52:46 PM UTC 24 | Oct 02 10:52:52 PM UTC 24 | 2021004461 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3903004005 | Oct 02 10:52:43 PM UTC 24 | Oct 02 10:52:53 PM UTC 24 | 2015043143 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.271607153 | Oct 02 10:52:50 PM UTC 24 | Oct 02 10:52:54 PM UTC 24 | 2051074217 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.4270850862 | Oct 02 10:52:49 PM UTC 24 | Oct 02 10:52:54 PM UTC 24 | 2020696187 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2110026684 | Oct 02 10:52:52 PM UTC 24 | Oct 02 10:52:54 PM UTC 24 | 2069462733 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1730861130 | Oct 02 10:52:49 PM UTC 24 | Oct 02 10:52:55 PM UTC 24 | 2021012117 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.4257314123 | Oct 02 10:52:48 PM UTC 24 | Oct 02 10:52:55 PM UTC 24 | 2029720071 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.824852229 | Oct 02 10:52:31 PM UTC 24 | Oct 02 10:52:55 PM UTC 24 | 9579292787 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2218649515 | Oct 02 10:52:51 PM UTC 24 | Oct 02 10:52:55 PM UTC 24 | 2028101322 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1600871984 | Oct 02 10:52:36 PM UTC 24 | Oct 02 10:52:56 PM UTC 24 | 43899672701 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1136861576 | Oct 02 10:52:53 PM UTC 24 | Oct 02 10:52:56 PM UTC 24 | 2037193088 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.4210781243 | Oct 02 10:52:45 PM UTC 24 | Oct 02 10:52:57 PM UTC 24 | 2012145364 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3556966228 | Oct 02 10:52:50 PM UTC 24 | Oct 02 10:52:57 PM UTC 24 | 2013927442 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1051205689 | Oct 02 10:52:54 PM UTC 24 | Oct 02 10:52:57 PM UTC 24 | 2034988475 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2152261495 | Oct 02 10:52:45 PM UTC 24 | Oct 02 10:52:57 PM UTC 24 | 2012924452 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1337518521 | Oct 02 10:52:50 PM UTC 24 | Oct 02 10:52:58 PM UTC 24 | 2016643589 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1368245877 | Oct 02 10:52:54 PM UTC 24 | Oct 02 10:52:58 PM UTC 24 | 2048184966 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3173818447 | Oct 02 10:52:52 PM UTC 24 | Oct 02 10:52:58 PM UTC 24 | 2009775995 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2029495001 | Oct 02 10:52:53 PM UTC 24 | Oct 02 10:52:59 PM UTC 24 | 2015512671 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3414014740 | Oct 02 10:52:51 PM UTC 24 | Oct 02 10:52:59 PM UTC 24 | 2013550891 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1089224222 | Oct 02 10:51:51 PM UTC 24 | Oct 02 10:53:00 PM UTC 24 | 42634991906 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2890339596 | Oct 02 10:52:56 PM UTC 24 | Oct 02 10:53:00 PM UTC 24 | 2031206187 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3983835228 | Oct 02 10:52:55 PM UTC 24 | Oct 02 10:53:00 PM UTC 24 | 2030635918 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3002968027 | Oct 02 10:52:56 PM UTC 24 | Oct 02 10:53:00 PM UTC 24 | 2040181161 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.758962877 | Oct 02 10:52:58 PM UTC 24 | Oct 02 10:53:01 PM UTC 24 | 2094915215 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2183275174 | Oct 02 10:52:58 PM UTC 24 | Oct 02 10:53:01 PM UTC 24 | 2026117335 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1897211478 | Oct 02 10:52:53 PM UTC 24 | Oct 02 10:53:01 PM UTC 24 | 2009315670 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2841045856 | Oct 02 10:52:55 PM UTC 24 | Oct 02 10:53:02 PM UTC 24 | 2023624346 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.438279628 | Oct 02 10:52:44 PM UTC 24 | Oct 02 10:53:02 PM UTC 24 | 8256890172 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1068319520 | Oct 02 10:52:58 PM UTC 24 | Oct 02 10:53:02 PM UTC 24 | 2019940245 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2930214028 | Oct 02 10:52:40 PM UTC 24 | Oct 02 10:53:03 PM UTC 24 | 22384374221 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.96672252 | Oct 02 10:52:56 PM UTC 24 | Oct 02 10:53:04 PM UTC 24 | 2012408473 ps | ||
| T901 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2357719798 | Oct 02 10:52:13 PM UTC 24 | Oct 02 10:53:07 PM UTC 24 | 9864416313 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2796325781 | Oct 02 10:52:38 PM UTC 24 | Oct 02 10:53:14 PM UTC 24 | 22206689929 ps | ||
| T902 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2221138871 | Oct 02 10:52:26 PM UTC 24 | Oct 02 10:53:16 PM UTC 24 | 10804723924 ps | ||
| T903 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.157888623 | Oct 02 10:51:16 PM UTC 24 | Oct 02 10:53:23 PM UTC 24 | 42470374622 ps | ||
| T904 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.658759612 | Oct 02 10:52:27 PM UTC 24 | Oct 02 10:53:25 PM UTC 24 | 22229370849 ps | ||
| T905 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.173925179 | Oct 02 10:52:20 PM UTC 24 | Oct 02 10:53:28 PM UTC 24 | 22191114629 ps | ||
| T906 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3147149579 | Oct 02 10:52:24 PM UTC 24 | Oct 02 10:53:31 PM UTC 24 | 22201177395 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.920395959 | Oct 02 10:50:47 PM UTC 24 | Oct 02 10:53:31 PM UTC 24 | 42456232715 ps | ||
| T907 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1683636278 | Oct 02 10:52:32 PM UTC 24 | Oct 02 10:53:37 PM UTC 24 | 22216088752 ps | ||
| T908 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.222425490 | Oct 02 10:51:30 PM UTC 24 | Oct 02 10:53:41 PM UTC 24 | 42422261239 ps | ||
| T909 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.959033532 | Oct 02 10:51:39 PM UTC 24 | Oct 02 10:53:42 PM UTC 24 | 42389329835 ps | ||
| T910 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3793820817 | Oct 02 10:51:25 PM UTC 24 | Oct 02 10:54:31 PM UTC 24 | 75766613265 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2811638481 | Oct 02 10:52:43 PM UTC 24 | Oct 02 10:54:35 PM UTC 24 | 42343095558 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.3457922544 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3224197367 ps |
| CPU time | 3.87 seconds |
| Started | Oct 02 10:40:53 PM UTC 24 |
| Finished | Oct 02 10:40:58 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457922544 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.3457922544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.4208471918 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 40623619228 ps |
| CPU time | 33.06 seconds |
| Started | Oct 02 10:40:54 PM UTC 24 |
| Finished | Oct 02 10:41:28 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208471918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.4208471918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.3531090340 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 2528167600 ps |
| CPU time | 4.08 seconds |
| Started | Oct 02 10:41:13 PM UTC 24 |
| Finished | Oct 02 10:41:18 PM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531090340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.3531090340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.308214370 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2454419112 ps |
| CPU time | 5.3 seconds |
| Started | Oct 02 10:40:48 PM UTC 24 |
| Finished | Oct 02 10:40:54 PM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308214370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.308214370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.135799531 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 78958157738 ps |
| CPU time | 64.7 seconds |
| Started | Oct 02 10:41:02 PM UTC 24 |
| Finished | Oct 02 10:42:09 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135799531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_with_pre_cond.135799531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3298070997 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 48074118413 ps |
| CPU time | 16.3 seconds |
| Started | Oct 02 10:41:51 PM UTC 24 |
| Finished | Oct 02 10:42:08 PM UTC 24 |
| Peak memory | 224220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3298070997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.3298070997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2852730987 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2242544750514 ps |
| CPU time | 75.9 seconds |
| Started | Oct 02 10:41:00 PM UTC 24 |
| Finished | Oct 02 10:42:18 PM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852730987 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.2852730987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.806744259 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 176616134244 ps |
| CPU time | 111.57 seconds |
| Started | Oct 02 10:42:06 PM UTC 24 |
| Finished | Oct 02 10:44:00 PM UTC 24 |
| Peak memory | 211860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806744259 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.806744259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.4016537398 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 34226972970 ps |
| CPU time | 110.26 seconds |
| Started | Oct 02 10:41:02 PM UTC 24 |
| Finished | Oct 02 10:42:55 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016537398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.4016537398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_feature_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1124296466 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 31694203111 ps |
| CPU time | 15.26 seconds |
| Started | Oct 02 10:47:52 PM UTC 24 |
| Finished | Oct 02 10:48:08 PM UTC 24 |
| Peak memory | 228348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1124296466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.1124296466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3240519025 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 43108987480 ps |
| CPU time | 13.69 seconds |
| Started | Oct 02 10:52:15 PM UTC 24 |
| Finished | Oct 02 10:52:30 PM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240519025 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.3240519025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1297445127 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 5467793781 ps |
| CPU time | 6.15 seconds |
| Started | Oct 02 10:41:04 PM UTC 24 |
| Finished | Oct 02 10:41:12 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1297445127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.1297445127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.900224155 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2222999670 ps |
| CPU time | 3.44 seconds |
| Started | Oct 02 10:40:49 PM UTC 24 |
| Finished | Oct 02 10:40:53 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900224155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.900224155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.3078406016 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4241777086 ps |
| CPU time | 3.14 seconds |
| Started | Oct 02 10:41:02 PM UTC 24 |
| Finished | Oct 02 10:41:07 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078406016 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.3078406016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3444807001 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2558426399 ps |
| CPU time | 2.26 seconds |
| Started | Oct 02 10:51:13 PM UTC 24 |
| Finished | Oct 02 10:51:17 PM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3444807001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .sysrst_ctrl_csr_mem_rw_with_rand_reset.3444807001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2153041388 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 108575782755 ps |
| CPU time | 89.85 seconds |
| Started | Oct 02 10:43:18 PM UTC 24 |
| Finished | Oct 02 10:44:49 PM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153041388 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.2153041388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.2779048745 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 67564280938 ps |
| CPU time | 194.61 seconds |
| Started | Oct 02 10:40:54 PM UTC 24 |
| Finished | Oct 02 10:44:12 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779048745 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.2779048745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.960040165 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 17802583475 ps |
| CPU time | 75.93 seconds |
| Started | Oct 02 10:42:00 PM UTC 24 |
| Finished | Oct 02 10:43:18 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960040165 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.960040165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.3480781875 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 42034314554 ps |
| CPU time | 61.19 seconds |
| Started | Oct 02 10:40:54 PM UTC 24 |
| Finished | Oct 02 10:41:57 PM UTC 24 |
| Peak memory | 243628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480781875 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3480781875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.4272141525 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 780887418701 ps |
| CPU time | 69.79 seconds |
| Started | Oct 02 10:44:23 PM UTC 24 |
| Finished | Oct 02 10:45:35 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272141525 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.4272141525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1682261129 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 62807460272 ps |
| CPU time | 121.67 seconds |
| Started | Oct 02 10:44:34 PM UTC 24 |
| Finished | Oct 02 10:46:38 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682261129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_with_pre_cond.1682261129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2915164987 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 195900561523 ps |
| CPU time | 271.94 seconds |
| Started | Oct 02 10:43:09 PM UTC 24 |
| Finished | Oct 02 10:47:44 PM UTC 24 |
| Peak memory | 211732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915164987 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.2915164987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3532319574 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 320082946992 ps |
| CPU time | 34.36 seconds |
| Started | Oct 02 10:42:40 PM UTC 24 |
| Finished | Oct 02 10:43:16 PM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3532319574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3532319574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1823890590 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4881996158 ps |
| CPU time | 24.51 seconds |
| Started | Oct 02 10:43:58 PM UTC 24 |
| Finished | Oct 02 10:44:24 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823890590 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.1823890590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3275698799 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2048495904 ps |
| CPU time | 12.37 seconds |
| Started | Oct 02 10:51:17 PM UTC 24 |
| Finished | Oct 02 10:51:30 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275698799 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.3275698799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.4181813498 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3286492425 ps |
| CPU time | 2.08 seconds |
| Started | Oct 02 10:40:51 PM UTC 24 |
| Finished | Oct 02 10:40:55 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181813498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.4181813498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.1387724034 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 16639153015 ps |
| CPU time | 42.85 seconds |
| Started | Oct 02 10:41:41 PM UTC 24 |
| Finished | Oct 02 10:42:25 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387724034 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.1387724034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.386096636 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 13720201739 ps |
| CPU time | 11.59 seconds |
| Started | Oct 02 10:43:21 PM UTC 24 |
| Finished | Oct 02 10:43:34 PM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=386096636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.386096636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2434152683 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 115641140369 ps |
| CPU time | 83.47 seconds |
| Started | Oct 02 10:42:27 PM UTC 24 |
| Finished | Oct 02 10:43:52 PM UTC 24 |
| Peak memory | 211848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434152683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_with_pre_cond.2434152683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3407235259 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2087295733 ps |
| CPU time | 12.61 seconds |
| Started | Oct 02 10:51:14 PM UTC 24 |
| Finished | Oct 02 10:51:28 PM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407235259 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.3407235259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.3128670127 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 4820735323 ps |
| CPU time | 18.7 seconds |
| Started | Oct 02 10:46:45 PM UTC 24 |
| Finished | Oct 02 10:47:05 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128670127 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.3128670127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.2846700950 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2518323174 ps |
| CPU time | 8.27 seconds |
| Started | Oct 02 10:41:23 PM UTC 24 |
| Finished | Oct 02 10:41:32 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846700950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.2846700950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.354172637 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 87925362538 ps |
| CPU time | 80.23 seconds |
| Started | Oct 02 10:43:58 PM UTC 24 |
| Finished | Oct 02 10:45:20 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354172637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_with_pre_cond.354172637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.923504978 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 120752897109 ps |
| CPU time | 203.09 seconds |
| Started | Oct 02 10:43:47 PM UTC 24 |
| Finished | Oct 02 10:47:13 PM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923504978 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.923504978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.574096639 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2533479075 ps |
| CPU time | 4.39 seconds |
| Started | Oct 02 10:42:36 PM UTC 24 |
| Finished | Oct 02 10:42:42 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574096639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.574096639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.476937624 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 70351493431 ps |
| CPU time | 95.78 seconds |
| Started | Oct 02 10:48:33 PM UTC 24 |
| Finished | Oct 02 10:50:11 PM UTC 24 |
| Peak memory | 211808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476937624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_with_pre_cond.476937624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.3308658215 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 85432463634 ps |
| CPU time | 65.04 seconds |
| Started | Oct 02 10:40:53 PM UTC 24 |
| Finished | Oct 02 10:41:59 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308658215 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.3308658215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2045173758 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5237669234 ps |
| CPU time | 3.69 seconds |
| Started | Oct 02 10:41:58 PM UTC 24 |
| Finished | Oct 02 10:42:02 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045173758 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.2045173758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.2968560403 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2013979235 ps |
| CPU time | 7.82 seconds |
| Started | Oct 02 10:40:55 PM UTC 24 |
| Finished | Oct 02 10:41:04 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968560403 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.2968560403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.81620357 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 40574462507 ps |
| CPU time | 22.07 seconds |
| Started | Oct 02 10:50:54 PM UTC 24 |
| Finished | Oct 02 10:51:18 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81620357 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.81620357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1299848390 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 103683767095 ps |
| CPU time | 61.15 seconds |
| Started | Oct 02 10:49:27 PM UTC 24 |
| Finished | Oct 02 10:50:30 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299848390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_with_pre_cond.1299848390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.4180874738 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 124766027600 ps |
| CPU time | 142.75 seconds |
| Started | Oct 02 10:43:19 PM UTC 24 |
| Finished | Oct 02 10:45:44 PM UTC 24 |
| Peak memory | 211732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180874738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_with_pre_cond.4180874738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.62535371 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2249607659 ps |
| CPU time | 3.65 seconds |
| Started | Oct 02 10:50:45 PM UTC 24 |
| Finished | Oct 02 10:50:49 PM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62535371 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.62535371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.920395959 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 42456232715 ps |
| CPU time | 161.85 seconds |
| Started | Oct 02 10:50:47 PM UTC 24 |
| Finished | Oct 02 10:53:31 PM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920395959 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.920395959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3986731725 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 47734956150 ps |
| CPU time | 141.38 seconds |
| Started | Oct 02 10:42:46 PM UTC 24 |
| Finished | Oct 02 10:45:10 PM UTC 24 |
| Peak memory | 211804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986731725 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.3986731725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.1067163055 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2514889030 ps |
| CPU time | 5.13 seconds |
| Started | Oct 02 10:42:51 PM UTC 24 |
| Finished | Oct 02 10:42:57 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067163055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.1067163055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.239518263 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 41309890469 ps |
| CPU time | 115.65 seconds |
| Started | Oct 02 10:44:07 PM UTC 24 |
| Finished | Oct 02 10:46:05 PM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239518263 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.239518263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1907547499 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 157525251919 ps |
| CPU time | 121.34 seconds |
| Started | Oct 02 10:44:42 PM UTC 24 |
| Finished | Oct 02 10:46:46 PM UTC 24 |
| Peak memory | 211672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907547499 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.1907547499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.532118139 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 42339318277 ps |
| CPU time | 138.55 seconds |
| Started | Oct 02 10:46:59 PM UTC 24 |
| Finished | Oct 02 10:49:20 PM UTC 24 |
| Peak memory | 211832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532118139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_with_pre_cond.532118139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.317561770 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 104000714935 ps |
| CPU time | 48.43 seconds |
| Started | Oct 02 10:49:40 PM UTC 24 |
| Finished | Oct 02 10:50:30 PM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317561770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_with_pre_cond.317561770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/72.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2431784739 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 89898887971 ps |
| CPU time | 81.54 seconds |
| Started | Oct 02 10:49:49 PM UTC 24 |
| Finished | Oct 02 10:51:13 PM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431784739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_with_pre_cond.2431784739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.254047799 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 107406887399 ps |
| CPU time | 117.07 seconds |
| Started | Oct 02 10:50:42 PM UTC 24 |
| Finished | Oct 02 10:52:41 PM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254047799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_with_pre_cond.254047799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1050247701 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2069677947 ps |
| CPU time | 2.32 seconds |
| Started | Oct 02 10:51:31 PM UTC 24 |
| Finished | Oct 02 10:51:35 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050247701 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.1050247701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1489742765 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3446257111 ps |
| CPU time | 12.62 seconds |
| Started | Oct 02 10:41:00 PM UTC 24 |
| Finished | Oct 02 10:41:14 PM UTC 24 |
| Peak memory | 211780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489742765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.1489742765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.3354250940 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 136026244297 ps |
| CPU time | 103.5 seconds |
| Started | Oct 02 10:41:18 PM UTC 24 |
| Finished | Oct 02 10:43:03 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354250940 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.3354250940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.2022926769 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 92846820452 ps |
| CPU time | 299.13 seconds |
| Started | Oct 02 10:44:26 PM UTC 24 |
| Finished | Oct 02 10:49:29 PM UTC 24 |
| Peak memory | 211804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022926769 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.2022926769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2120861752 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 113103582225 ps |
| CPU time | 161.83 seconds |
| Started | Oct 02 10:49:31 PM UTC 24 |
| Finished | Oct 02 10:52:15 PM UTC 24 |
| Peak memory | 211796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120861752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_with_pre_cond.2120861752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/68.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2874242451 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 332078308453 ps |
| CPU time | 56.21 seconds |
| Started | Oct 02 10:45:27 PM UTC 24 |
| Finished | Oct 02 10:46:24 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874242451 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.2874242451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2720797434 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2579810406 ps |
| CPU time | 4.06 seconds |
| Started | Oct 02 10:44:14 PM UTC 24 |
| Finished | Oct 02 10:44:20 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720797434 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.2720797434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3039440560 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2508419880 ps |
| CPU time | 8.78 seconds |
| Started | Oct 02 10:40:49 PM UTC 24 |
| Finished | Oct 02 10:40:59 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039440560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3039440560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3983078341 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 58389365966 ps |
| CPU time | 89.03 seconds |
| Started | Oct 02 10:47:18 PM UTC 24 |
| Finished | Oct 02 10:48:49 PM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983078341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_with_pre_cond.3983078341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.551476056 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 5323458709 ps |
| CPU time | 4.9 seconds |
| Started | Oct 02 10:42:46 PM UTC 24 |
| Finished | Oct 02 10:42:52 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551476056 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.551476056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2783107924 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 107811021181 ps |
| CPU time | 128.79 seconds |
| Started | Oct 02 10:41:29 PM UTC 24 |
| Finished | Oct 02 10:43:40 PM UTC 24 |
| Peak memory | 211868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783107924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_with_pre_cond.2783107924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1076167634 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 52690590365 ps |
| CPU time | 40.48 seconds |
| Started | Oct 02 10:40:53 PM UTC 24 |
| Finished | Oct 02 10:41:35 PM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076167634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_with_pre_cond.1076167634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1662745975 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 175613755211 ps |
| CPU time | 468.09 seconds |
| Started | Oct 02 10:44:44 PM UTC 24 |
| Finished | Oct 02 10:52:38 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662745975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_with_pre_cond.1662745975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2433679502 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 117538129270 ps |
| CPU time | 69.25 seconds |
| Started | Oct 02 10:45:52 PM UTC 24 |
| Finished | Oct 02 10:47:03 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433679502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_with_pre_cond.2433679502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2555904109 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 75071162616 ps |
| CPU time | 212.21 seconds |
| Started | Oct 02 10:41:40 PM UTC 24 |
| Finished | Oct 02 10:45:15 PM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555904109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_with_pre_cond.2555904109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.1716082532 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 56655651606 ps |
| CPU time | 54.41 seconds |
| Started | Oct 02 10:47:32 PM UTC 24 |
| Finished | Oct 02 10:48:28 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716082532 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.1716082532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2151487735 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 93913624301 ps |
| CPU time | 139.27 seconds |
| Started | Oct 02 10:48:14 PM UTC 24 |
| Finished | Oct 02 10:50:35 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151487735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_with_pre_cond.2151487735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.1900525558 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 119198030423 ps |
| CPU time | 224.51 seconds |
| Started | Oct 02 10:48:21 PM UTC 24 |
| Finished | Oct 02 10:52:08 PM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900525558 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.1900525558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.4131654170 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 60384903333 ps |
| CPU time | 197.52 seconds |
| Started | Oct 02 10:49:18 PM UTC 24 |
| Finished | Oct 02 10:52:39 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131654170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_with_pre_cond.4131654170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.249571109 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 63038621644 ps |
| CPU time | 197.13 seconds |
| Started | Oct 02 10:49:27 PM UTC 24 |
| Finished | Oct 02 10:52:47 PM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249571109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_with_pre_cond.249571109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3693510708 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 148738805420 ps |
| CPU time | 255.19 seconds |
| Started | Oct 02 10:49:30 PM UTC 24 |
| Finished | Oct 02 10:53:49 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693510708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_with_pre_cond.3693510708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1274415899 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 74504688861 ps |
| CPU time | 63.16 seconds |
| Started | Oct 02 10:50:36 PM UTC 24 |
| Finished | Oct 02 10:51:41 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274415899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_with_pre_cond.1274415899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.577244644 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4687682679 ps |
| CPU time | 5.56 seconds |
| Started | Oct 02 10:42:33 PM UTC 24 |
| Finished | Oct 02 10:42:39 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577244644 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.577244644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.1024565255 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 4193098176 ps |
| CPU time | 4.35 seconds |
| Started | Oct 02 10:46:58 PM UTC 24 |
| Finished | Oct 02 10:47:03 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024565255 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.1024565255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2885358265 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 10279798822 ps |
| CPU time | 52.9 seconds |
| Started | Oct 02 10:50:58 PM UTC 24 |
| Finished | Oct 02 10:51:52 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885358265 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.2885358265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.453154191 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2430462987 ps |
| CPU time | 3.89 seconds |
| Started | Oct 02 10:51:02 PM UTC 24 |
| Finished | Oct 02 10:51:07 PM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453154191 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.453154191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3094559945 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2662465865 ps |
| CPU time | 5.88 seconds |
| Started | Oct 02 10:50:57 PM UTC 24 |
| Finished | Oct 02 10:51:04 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094559945 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.3094559945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3518873508 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4045965150 ps |
| CPU time | 5.58 seconds |
| Started | Oct 02 10:50:50 PM UTC 24 |
| Finished | Oct 02 10:50:57 PM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518873508 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.3518873508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3291853484 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2188186280 ps |
| CPU time | 3.38 seconds |
| Started | Oct 02 10:51:02 PM UTC 24 |
| Finished | Oct 02 10:51:06 PM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3291853484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .sysrst_ctrl_csr_mem_rw_with_rand_reset.3291853484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.322969165 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2073189614 ps |
| CPU time | 3.62 seconds |
| Started | Oct 02 10:50:52 PM UTC 24 |
| Finished | Oct 02 10:50:57 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322969165 -assert nopostproc +UVM_TESTNAME=s ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.322969165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2517933130 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2032040618 ps |
| CPU time | 3.56 seconds |
| Started | Oct 02 10:50:49 PM UTC 24 |
| Finished | Oct 02 10:50:54 PM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517933130 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.2517933130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2707874411 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2510377390 ps |
| CPU time | 7.53 seconds |
| Started | Oct 02 10:51:07 PM UTC 24 |
| Finished | Oct 02 10:51:16 PM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707874411 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.2707874411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2957552218 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 76302028231 ps |
| CPU time | 80.35 seconds |
| Started | Oct 02 10:51:07 PM UTC 24 |
| Finished | Oct 02 10:52:29 PM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957552218 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.2957552218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2135893902 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4018250220 ps |
| CPU time | 16.8 seconds |
| Started | Oct 02 10:51:06 PM UTC 24 |
| Finished | Oct 02 10:51:24 PM UTC 24 |
| Peak memory | 211004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135893902 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.2135893902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1580625262 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2111093941 ps |
| CPU time | 2.46 seconds |
| Started | Oct 02 10:51:07 PM UTC 24 |
| Finished | Oct 02 10:51:11 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580625262 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.1580625262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4096574645 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 2011532920 ps |
| CPU time | 10.96 seconds |
| Started | Oct 02 10:51:05 PM UTC 24 |
| Finished | Oct 02 10:51:17 PM UTC 24 |
| Peak memory | 210672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096574645 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.4096574645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.291076725 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4694705946 ps |
| CPU time | 3.89 seconds |
| Started | Oct 02 10:51:11 PM UTC 24 |
| Finished | Oct 02 10:51:16 PM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291076725 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.291076725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1625824957 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 22203126328 ps |
| CPU time | 87.3 seconds |
| Started | Oct 02 10:51:05 PM UTC 24 |
| Finished | Oct 02 10:52:34 PM UTC 24 |
| Peak memory | 210944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625824957 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.1625824957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3915761406 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 2084016076 ps |
| CPU time | 4.1 seconds |
| Started | Oct 02 10:52:14 PM UTC 24 |
| Finished | Oct 02 10:52:19 PM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3915761406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3915761406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1206488932 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 2042763326 ps |
| CPU time | 10.98 seconds |
| Started | Oct 02 10:52:11 PM UTC 24 |
| Finished | Oct 02 10:52:23 PM UTC 24 |
| Peak memory | 211016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206488932 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.1206488932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1694941477 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2023909477 ps |
| CPU time | 3.4 seconds |
| Started | Oct 02 10:52:09 PM UTC 24 |
| Finished | Oct 02 10:52:14 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694941477 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.1694941477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2357719798 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 9864416313 ps |
| CPU time | 52.65 seconds |
| Started | Oct 02 10:52:13 PM UTC 24 |
| Finished | Oct 02 10:53:07 PM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357719798 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.2357719798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2472382276 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2499702955 ps |
| CPU time | 5.02 seconds |
| Started | Oct 02 10:52:08 PM UTC 24 |
| Finished | Oct 02 10:52:14 PM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472382276 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.2472382276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3436956537 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 22474221058 ps |
| CPU time | 22.29 seconds |
| Started | Oct 02 10:52:09 PM UTC 24 |
| Finished | Oct 02 10:52:33 PM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436956537 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.3436956537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1742485893 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 2077597109 ps |
| CPU time | 4.36 seconds |
| Started | Oct 02 10:52:17 PM UTC 24 |
| Finished | Oct 02 10:52:23 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1742485893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1742485893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2768398450 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2062168639 ps |
| CPU time | 3.98 seconds |
| Started | Oct 02 10:52:16 PM UTC 24 |
| Finished | Oct 02 10:52:21 PM UTC 24 |
| Peak memory | 211016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768398450 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.2768398450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.4235570406 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2029052201 ps |
| CPU time | 3.49 seconds |
| Started | Oct 02 10:52:15 PM UTC 24 |
| Finished | Oct 02 10:52:19 PM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235570406 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.4235570406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.812713874 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 7221979648 ps |
| CPU time | 8.67 seconds |
| Started | Oct 02 10:52:16 PM UTC 24 |
| Finished | Oct 02 10:52:26 PM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812713874 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.812713874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.724289613 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 2123082831 ps |
| CPU time | 9.88 seconds |
| Started | Oct 02 10:52:15 PM UTC 24 |
| Finished | Oct 02 10:52:26 PM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724289613 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.724289613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3072415775 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 2082828541 ps |
| CPU time | 3.94 seconds |
| Started | Oct 02 10:52:22 PM UTC 24 |
| Finished | Oct 02 10:52:27 PM UTC 24 |
| Peak memory | 211000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3072415775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3072415775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1264184720 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 2042365972 ps |
| CPU time | 6.45 seconds |
| Started | Oct 02 10:52:21 PM UTC 24 |
| Finished | Oct 02 10:52:28 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264184720 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.1264184720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.12266777 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2022974280 ps |
| CPU time | 4.95 seconds |
| Started | Oct 02 10:52:20 PM UTC 24 |
| Finished | Oct 02 10:52:26 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12266777 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.12266777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3042141943 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 5048279336 ps |
| CPU time | 20.1 seconds |
| Started | Oct 02 10:52:21 PM UTC 24 |
| Finished | Oct 02 10:52:42 PM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042141943 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.3042141943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1440408954 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 2084815058 ps |
| CPU time | 8.07 seconds |
| Started | Oct 02 10:52:17 PM UTC 24 |
| Finished | Oct 02 10:52:27 PM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440408954 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.1440408954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.173925179 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 22191114629 ps |
| CPU time | 66.56 seconds |
| Started | Oct 02 10:52:20 PM UTC 24 |
| Finished | Oct 02 10:53:28 PM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173925179 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.173925179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3378467122 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2171784977 ps |
| CPU time | 2.71 seconds |
| Started | Oct 02 10:52:27 PM UTC 24 |
| Finished | Oct 02 10:52:31 PM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3378467122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3378467122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2224427309 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2093996633 ps |
| CPU time | 2.65 seconds |
| Started | Oct 02 10:52:26 PM UTC 24 |
| Finished | Oct 02 10:52:30 PM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224427309 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.2224427309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1945397368 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2021833571 ps |
| CPU time | 4.1 seconds |
| Started | Oct 02 10:52:25 PM UTC 24 |
| Finished | Oct 02 10:52:30 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945397368 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.1945397368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2221138871 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 10804723924 ps |
| CPU time | 48.39 seconds |
| Started | Oct 02 10:52:26 PM UTC 24 |
| Finished | Oct 02 10:53:16 PM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221138871 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.2221138871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1027021274 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 2080036246 ps |
| CPU time | 7.43 seconds |
| Started | Oct 02 10:52:24 PM UTC 24 |
| Finished | Oct 02 10:52:33 PM UTC 24 |
| Peak memory | 210532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027021274 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.1027021274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3147149579 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 22201177395 ps |
| CPU time | 65.2 seconds |
| Started | Oct 02 10:52:24 PM UTC 24 |
| Finished | Oct 02 10:53:31 PM UTC 24 |
| Peak memory | 210564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147149579 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.3147149579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3283918781 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 2092032107 ps |
| CPU time | 10.11 seconds |
| Started | Oct 02 10:52:31 PM UTC 24 |
| Finished | Oct 02 10:52:42 PM UTC 24 |
| Peak memory | 211000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3283918781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3283918781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3442385623 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2082292262 ps |
| CPU time | 3.57 seconds |
| Started | Oct 02 10:52:30 PM UTC 24 |
| Finished | Oct 02 10:52:34 PM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442385623 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.3442385623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2147130163 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 2017819378 ps |
| CPU time | 7.18 seconds |
| Started | Oct 02 10:52:29 PM UTC 24 |
| Finished | Oct 02 10:52:37 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147130163 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.2147130163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.824852229 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 9579292787 ps |
| CPU time | 22.87 seconds |
| Started | Oct 02 10:52:31 PM UTC 24 |
| Finished | Oct 02 10:52:55 PM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824852229 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.824852229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1129019662 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 2098637052 ps |
| CPU time | 4.59 seconds |
| Started | Oct 02 10:52:27 PM UTC 24 |
| Finished | Oct 02 10:52:33 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129019662 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.1129019662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.658759612 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 22229370849 ps |
| CPU time | 55.48 seconds |
| Started | Oct 02 10:52:27 PM UTC 24 |
| Finished | Oct 02 10:53:25 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658759612 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.658759612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1069350732 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2065188552 ps |
| CPU time | 8.44 seconds |
| Started | Oct 02 10:52:34 PM UTC 24 |
| Finished | Oct 02 10:52:44 PM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1069350732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1069350732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3960162332 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 2051004647 ps |
| CPU time | 6.04 seconds |
| Started | Oct 02 10:52:33 PM UTC 24 |
| Finished | Oct 02 10:52:40 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960162332 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.3960162332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3577454110 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2027956034 ps |
| CPU time | 2.96 seconds |
| Started | Oct 02 10:52:32 PM UTC 24 |
| Finished | Oct 02 10:52:36 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577454110 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.3577454110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.134179388 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 5771907650 ps |
| CPU time | 2.55 seconds |
| Started | Oct 02 10:52:33 PM UTC 24 |
| Finished | Oct 02 10:52:37 PM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134179388 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.134179388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2002490898 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2077218954 ps |
| CPU time | 6.11 seconds |
| Started | Oct 02 10:52:31 PM UTC 24 |
| Finished | Oct 02 10:52:38 PM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002490898 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.2002490898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1683636278 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 22216088752 ps |
| CPU time | 63.25 seconds |
| Started | Oct 02 10:52:32 PM UTC 24 |
| Finished | Oct 02 10:53:37 PM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683636278 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.1683636278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.920199083 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2301715322 ps |
| CPU time | 2.19 seconds |
| Started | Oct 02 10:52:37 PM UTC 24 |
| Finished | Oct 02 10:52:40 PM UTC 24 |
| Peak memory | 221412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=920199083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .sysrst_ctrl_csr_mem_rw_with_rand_reset.920199083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2590422738 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 2033129007 ps |
| CPU time | 7.7 seconds |
| Started | Oct 02 10:52:36 PM UTC 24 |
| Finished | Oct 02 10:52:44 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590422738 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.2590422738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3035695244 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2024358014 ps |
| CPU time | 5.63 seconds |
| Started | Oct 02 10:52:36 PM UTC 24 |
| Finished | Oct 02 10:52:42 PM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035695244 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.3035695244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3522815251 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 5001459962 ps |
| CPU time | 4.44 seconds |
| Started | Oct 02 10:52:36 PM UTC 24 |
| Finished | Oct 02 10:52:41 PM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522815251 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.3522815251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.317771151 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2164572914 ps |
| CPU time | 5.36 seconds |
| Started | Oct 02 10:52:34 PM UTC 24 |
| Finished | Oct 02 10:52:41 PM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317771151 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.317771151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1600871984 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 43899672701 ps |
| CPU time | 19.38 seconds |
| Started | Oct 02 10:52:36 PM UTC 24 |
| Finished | Oct 02 10:52:56 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600871984 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.1600871984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1726169974 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 2059446232 ps |
| CPU time | 4.17 seconds |
| Started | Oct 02 10:52:39 PM UTC 24 |
| Finished | Oct 02 10:52:44 PM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1726169974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1726169974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.92637123 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2073848830 ps |
| CPU time | 3.68 seconds |
| Started | Oct 02 10:52:39 PM UTC 24 |
| Finished | Oct 02 10:52:44 PM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92637123 -assert nopostproc +UVM_TESTNAME=sy srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.92637123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1890284538 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 2009380767 ps |
| CPU time | 11.36 seconds |
| Started | Oct 02 10:52:38 PM UTC 24 |
| Finished | Oct 02 10:52:50 PM UTC 24 |
| Peak memory | 210548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890284538 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.1890284538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2167312860 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 7428600997 ps |
| CPU time | 10.58 seconds |
| Started | Oct 02 10:52:39 PM UTC 24 |
| Finished | Oct 02 10:52:51 PM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167312860 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.2167312860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2006006303 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 2093045600 ps |
| CPU time | 6.67 seconds |
| Started | Oct 02 10:52:37 PM UTC 24 |
| Finished | Oct 02 10:52:44 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006006303 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.2006006303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2796325781 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 22206689929 ps |
| CPU time | 34.36 seconds |
| Started | Oct 02 10:52:38 PM UTC 24 |
| Finished | Oct 02 10:53:14 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796325781 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.2796325781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3444011903 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2164588770 ps |
| CPU time | 2.81 seconds |
| Started | Oct 02 10:52:42 PM UTC 24 |
| Finished | Oct 02 10:52:46 PM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3444011903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3444011903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3990404985 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 2088059061 ps |
| CPU time | 2.22 seconds |
| Started | Oct 02 10:52:42 PM UTC 24 |
| Finished | Oct 02 10:52:45 PM UTC 24 |
| Peak memory | 211016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990404985 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.3990404985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2722139689 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 2023016385 ps |
| CPU time | 6.47 seconds |
| Started | Oct 02 10:52:42 PM UTC 24 |
| Finished | Oct 02 10:52:49 PM UTC 24 |
| Peak memory | 210604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722139689 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.2722139689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2450133273 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 9821913247 ps |
| CPU time | 8.43 seconds |
| Started | Oct 02 10:52:42 PM UTC 24 |
| Finished | Oct 02 10:52:51 PM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450133273 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.2450133273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1030627162 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 2733485236 ps |
| CPU time | 2.98 seconds |
| Started | Oct 02 10:52:39 PM UTC 24 |
| Finished | Oct 02 10:52:43 PM UTC 24 |
| Peak memory | 221456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030627162 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.1030627162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2930214028 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 22384374221 ps |
| CPU time | 21.37 seconds |
| Started | Oct 02 10:52:40 PM UTC 24 |
| Finished | Oct 02 10:53:03 PM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930214028 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.2930214028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.702647447 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2075721975 ps |
| CPU time | 3.98 seconds |
| Started | Oct 02 10:52:45 PM UTC 24 |
| Finished | Oct 02 10:52:50 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=702647447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .sysrst_ctrl_csr_mem_rw_with_rand_reset.702647447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1185963278 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 2076774912 ps |
| CPU time | 3.45 seconds |
| Started | Oct 02 10:52:44 PM UTC 24 |
| Finished | Oct 02 10:52:49 PM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185963278 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.1185963278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3903004005 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 2015043143 ps |
| CPU time | 9.28 seconds |
| Started | Oct 02 10:52:43 PM UTC 24 |
| Finished | Oct 02 10:52:53 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903004005 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.3903004005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.438279628 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 8256890172 ps |
| CPU time | 16.71 seconds |
| Started | Oct 02 10:52:44 PM UTC 24 |
| Finished | Oct 02 10:53:02 PM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438279628 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.438279628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1982592502 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2217436374 ps |
| CPU time | 5.52 seconds |
| Started | Oct 02 10:52:43 PM UTC 24 |
| Finished | Oct 02 10:52:49 PM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982592502 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.1982592502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2811638481 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 42343095558 ps |
| CPU time | 110.54 seconds |
| Started | Oct 02 10:52:43 PM UTC 24 |
| Finished | Oct 02 10:54:35 PM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811638481 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.2811638481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.279690386 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2554922054 ps |
| CPU time | 7.65 seconds |
| Started | Oct 02 10:51:18 PM UTC 24 |
| Finished | Oct 02 10:51:27 PM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279690386 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.279690386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2561232017 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4415031283 ps |
| CPU time | 10.29 seconds |
| Started | Oct 02 10:51:18 PM UTC 24 |
| Finished | Oct 02 10:51:29 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561232017 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.2561232017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3674309717 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4045056817 ps |
| CPU time | 6.11 seconds |
| Started | Oct 02 10:51:17 PM UTC 24 |
| Finished | Oct 02 10:51:24 PM UTC 24 |
| Peak memory | 210672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674309717 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.3674309717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.4195279609 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2102972175 ps |
| CPU time | 3.98 seconds |
| Started | Oct 02 10:51:19 PM UTC 24 |
| Finished | Oct 02 10:51:24 PM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4195279609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2 .sysrst_ctrl_csr_mem_rw_with_rand_reset.4195279609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2156702204 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2135459370 ps |
| CPU time | 1.45 seconds |
| Started | Oct 02 10:51:17 PM UTC 24 |
| Finished | Oct 02 10:51:19 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156702204 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.2156702204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2495251798 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5084184857 ps |
| CPU time | 12.1 seconds |
| Started | Oct 02 10:51:19 PM UTC 24 |
| Finished | Oct 02 10:51:32 PM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495251798 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.2495251798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.157888623 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 42470374622 ps |
| CPU time | 125.47 seconds |
| Started | Oct 02 10:51:16 PM UTC 24 |
| Finished | Oct 02 10:53:23 PM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157888623 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.157888623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.4210781243 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2012145364 ps |
| CPU time | 10.22 seconds |
| Started | Oct 02 10:52:45 PM UTC 24 |
| Finished | Oct 02 10:52:57 PM UTC 24 |
| Peak memory | 210540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210781243 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.4210781243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1068513824 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2062981757 ps |
| CPU time | 1.98 seconds |
| Started | Oct 02 10:52:45 PM UTC 24 |
| Finished | Oct 02 10:52:48 PM UTC 24 |
| Peak memory | 209612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068513824 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.1068513824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2152261495 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 2012924452 ps |
| CPU time | 10.89 seconds |
| Started | Oct 02 10:52:45 PM UTC 24 |
| Finished | Oct 02 10:52:57 PM UTC 24 |
| Peak memory | 210868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152261495 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.2152261495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1153185760 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2021004461 ps |
| CPU time | 5.41 seconds |
| Started | Oct 02 10:52:46 PM UTC 24 |
| Finished | Oct 02 10:52:52 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153185760 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.1153185760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2213271522 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2043516702 ps |
| CPU time | 3.87 seconds |
| Started | Oct 02 10:52:47 PM UTC 24 |
| Finished | Oct 02 10:52:52 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213271522 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.2213271522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2088146192 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2038486458 ps |
| CPU time | 3.31 seconds |
| Started | Oct 02 10:52:47 PM UTC 24 |
| Finished | Oct 02 10:52:51 PM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088146192 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.2088146192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.4257314123 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2029720071 ps |
| CPU time | 5.99 seconds |
| Started | Oct 02 10:52:48 PM UTC 24 |
| Finished | Oct 02 10:52:55 PM UTC 24 |
| Peak memory | 210604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257314123 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.4257314123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.4270850862 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2020696187 ps |
| CPU time | 3.63 seconds |
| Started | Oct 02 10:52:49 PM UTC 24 |
| Finished | Oct 02 10:52:54 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270850862 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.4270850862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1730861130 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2021012117 ps |
| CPU time | 4.83 seconds |
| Started | Oct 02 10:52:49 PM UTC 24 |
| Finished | Oct 02 10:52:55 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730861130 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.1730861130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1337518521 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2016643589 ps |
| CPU time | 7.04 seconds |
| Started | Oct 02 10:52:50 PM UTC 24 |
| Finished | Oct 02 10:52:58 PM UTC 24 |
| Peak memory | 210744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337518521 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.1337518521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1689474172 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 2507082217 ps |
| CPU time | 14.31 seconds |
| Started | Oct 02 10:51:28 PM UTC 24 |
| Finished | Oct 02 10:51:43 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689474172 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.1689474172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3793820817 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 75766613265 ps |
| CPU time | 183.39 seconds |
| Started | Oct 02 10:51:25 PM UTC 24 |
| Finished | Oct 02 10:54:31 PM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793820817 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.3793820817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3185616400 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4056212261 ps |
| CPU time | 3.92 seconds |
| Started | Oct 02 10:51:25 PM UTC 24 |
| Finished | Oct 02 10:51:29 PM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185616400 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.3185616400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3316285651 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2047582187 ps |
| CPU time | 5.91 seconds |
| Started | Oct 02 10:51:29 PM UTC 24 |
| Finished | Oct 02 10:51:36 PM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3316285651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3 .sysrst_ctrl_csr_mem_rw_with_rand_reset.3316285651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2693500645 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2052553147 ps |
| CPU time | 3.6 seconds |
| Started | Oct 02 10:51:25 PM UTC 24 |
| Finished | Oct 02 10:51:29 PM UTC 24 |
| Peak memory | 211072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693500645 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.2693500645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3902893022 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 2013671527 ps |
| CPU time | 9.72 seconds |
| Started | Oct 02 10:51:24 PM UTC 24 |
| Finished | Oct 02 10:51:35 PM UTC 24 |
| Peak memory | 210536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902893022 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.3902893022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3495931606 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 8947278910 ps |
| CPU time | 30.48 seconds |
| Started | Oct 02 10:51:29 PM UTC 24 |
| Finished | Oct 02 10:52:01 PM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495931606 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.3495931606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1396324814 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2027355104 ps |
| CPU time | 6.84 seconds |
| Started | Oct 02 10:51:20 PM UTC 24 |
| Finished | Oct 02 10:51:28 PM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396324814 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.1396324814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2189041522 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 22362191112 ps |
| CPU time | 46.14 seconds |
| Started | Oct 02 10:51:24 PM UTC 24 |
| Finished | Oct 02 10:52:12 PM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189041522 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.2189041522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3556966228 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2013927442 ps |
| CPU time | 5.66 seconds |
| Started | Oct 02 10:52:50 PM UTC 24 |
| Finished | Oct 02 10:52:57 PM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556966228 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.3556966228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.271607153 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2051074217 ps |
| CPU time | 2.4 seconds |
| Started | Oct 02 10:52:50 PM UTC 24 |
| Finished | Oct 02 10:52:54 PM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271607153 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.271607153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2218649515 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2028101322 ps |
| CPU time | 2.52 seconds |
| Started | Oct 02 10:52:51 PM UTC 24 |
| Finished | Oct 02 10:52:55 PM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218649515 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.2218649515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3414014740 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2013550891 ps |
| CPU time | 6.62 seconds |
| Started | Oct 02 10:52:51 PM UTC 24 |
| Finished | Oct 02 10:52:59 PM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414014740 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.3414014740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3173818447 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2009775995 ps |
| CPU time | 5.87 seconds |
| Started | Oct 02 10:52:52 PM UTC 24 |
| Finished | Oct 02 10:52:58 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173818447 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.3173818447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2110026684 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 2069462733 ps |
| CPU time | 1.84 seconds |
| Started | Oct 02 10:52:52 PM UTC 24 |
| Finished | Oct 02 10:52:54 PM UTC 24 |
| Peak memory | 210004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110026684 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.2110026684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1136861576 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2037193088 ps |
| CPU time | 2.5 seconds |
| Started | Oct 02 10:52:53 PM UTC 24 |
| Finished | Oct 02 10:52:56 PM UTC 24 |
| Peak memory | 210952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136861576 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.1136861576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1897211478 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2009315670 ps |
| CPU time | 7.38 seconds |
| Started | Oct 02 10:52:53 PM UTC 24 |
| Finished | Oct 02 10:53:01 PM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897211478 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.1897211478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2029495001 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2015512671 ps |
| CPU time | 5.24 seconds |
| Started | Oct 02 10:52:53 PM UTC 24 |
| Finished | Oct 02 10:52:59 PM UTC 24 |
| Peak memory | 210852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029495001 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.2029495001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1368245877 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2048184966 ps |
| CPU time | 3.43 seconds |
| Started | Oct 02 10:52:54 PM UTC 24 |
| Finished | Oct 02 10:52:58 PM UTC 24 |
| Peak memory | 210828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368245877 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.1368245877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.481057332 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2329353260 ps |
| CPU time | 9.57 seconds |
| Started | Oct 02 10:51:35 PM UTC 24 |
| Finished | Oct 02 10:51:45 PM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481057332 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.481057332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2255770165 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 4469806100 ps |
| CPU time | 7.32 seconds |
| Started | Oct 02 10:51:33 PM UTC 24 |
| Finished | Oct 02 10:51:42 PM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255770165 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.2255770165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2461694785 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 6035957120 ps |
| CPU time | 6.53 seconds |
| Started | Oct 02 10:51:30 PM UTC 24 |
| Finished | Oct 02 10:51:38 PM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461694785 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.2461694785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1337868447 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2117207382 ps |
| CPU time | 3.54 seconds |
| Started | Oct 02 10:51:36 PM UTC 24 |
| Finished | Oct 02 10:51:40 PM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1337868447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4 .sysrst_ctrl_csr_mem_rw_with_rand_reset.1337868447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3559551542 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 2051881309 ps |
| CPU time | 2.34 seconds |
| Started | Oct 02 10:51:30 PM UTC 24 |
| Finished | Oct 02 10:51:34 PM UTC 24 |
| Peak memory | 210596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559551542 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.3559551542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2914223745 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4687906819 ps |
| CPU time | 6.48 seconds |
| Started | Oct 02 10:51:36 PM UTC 24 |
| Finished | Oct 02 10:51:43 PM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914223745 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.2914223745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.4284684203 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2039385174 ps |
| CPU time | 10.75 seconds |
| Started | Oct 02 10:51:29 PM UTC 24 |
| Finished | Oct 02 10:51:41 PM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284684203 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.4284684203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.222425490 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 42422261239 ps |
| CPU time | 128.4 seconds |
| Started | Oct 02 10:51:30 PM UTC 24 |
| Finished | Oct 02 10:53:41 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222425490 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.222425490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1051205689 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2034988475 ps |
| CPU time | 2.46 seconds |
| Started | Oct 02 10:52:54 PM UTC 24 |
| Finished | Oct 02 10:52:57 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051205689 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.1051205689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3983835228 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2030635918 ps |
| CPU time | 4.1 seconds |
| Started | Oct 02 10:52:55 PM UTC 24 |
| Finished | Oct 02 10:53:00 PM UTC 24 |
| Peak memory | 210948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983835228 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.3983835228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2841045856 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2023624346 ps |
| CPU time | 5.74 seconds |
| Started | Oct 02 10:52:55 PM UTC 24 |
| Finished | Oct 02 10:53:02 PM UTC 24 |
| Peak memory | 210604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841045856 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.2841045856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.96672252 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2012408473 ps |
| CPU time | 6.93 seconds |
| Started | Oct 02 10:52:56 PM UTC 24 |
| Finished | Oct 02 10:53:04 PM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96672252 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.96672252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3002968027 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2040181161 ps |
| CPU time | 2.85 seconds |
| Started | Oct 02 10:52:56 PM UTC 24 |
| Finished | Oct 02 10:53:00 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002968027 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.3002968027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1813580569 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2017318106 ps |
| CPU time | 8.37 seconds |
| Started | Oct 02 10:52:56 PM UTC 24 |
| Finished | Oct 02 10:53:06 PM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813580569 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.1813580569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2890339596 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2031206187 ps |
| CPU time | 2.64 seconds |
| Started | Oct 02 10:52:56 PM UTC 24 |
| Finished | Oct 02 10:53:00 PM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890339596 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.2890339596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1068319520 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 2019940245 ps |
| CPU time | 3.69 seconds |
| Started | Oct 02 10:52:58 PM UTC 24 |
| Finished | Oct 02 10:53:02 PM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068319520 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.1068319520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2183275174 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2026117335 ps |
| CPU time | 2.54 seconds |
| Started | Oct 02 10:52:58 PM UTC 24 |
| Finished | Oct 02 10:53:01 PM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183275174 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.2183275174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.758962877 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2094915215 ps |
| CPU time | 2.22 seconds |
| Started | Oct 02 10:52:58 PM UTC 24 |
| Finished | Oct 02 10:53:01 PM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758962877 -assert nopostproc +UVM_TESTNAME=sysr st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.758962877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3019900130 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 2045620892 ps |
| CPU time | 6.11 seconds |
| Started | Oct 02 10:51:43 PM UTC 24 |
| Finished | Oct 02 10:51:51 PM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3019900130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5 .sysrst_ctrl_csr_mem_rw_with_rand_reset.3019900130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.4143848630 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2033491237 ps |
| CPU time | 12.68 seconds |
| Started | Oct 02 10:51:42 PM UTC 24 |
| Finished | Oct 02 10:51:56 PM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143848630 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.4143848630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3082098908 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2035781249 ps |
| CPU time | 3.68 seconds |
| Started | Oct 02 10:51:41 PM UTC 24 |
| Finished | Oct 02 10:51:46 PM UTC 24 |
| Peak memory | 210596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082098908 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.3082098908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.383816470 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 4725192045 ps |
| CPU time | 29.8 seconds |
| Started | Oct 02 10:51:42 PM UTC 24 |
| Finished | Oct 02 10:52:13 PM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383816470 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.383816470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.4177596329 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2056894531 ps |
| CPU time | 8.98 seconds |
| Started | Oct 02 10:51:37 PM UTC 24 |
| Finished | Oct 02 10:51:47 PM UTC 24 |
| Peak memory | 211256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177596329 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.4177596329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.959033532 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 42389329835 ps |
| CPU time | 120.18 seconds |
| Started | Oct 02 10:51:39 PM UTC 24 |
| Finished | Oct 02 10:53:42 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959033532 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.959033532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2185477111 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 2112825230 ps |
| CPU time | 4.38 seconds |
| Started | Oct 02 10:51:50 PM UTC 24 |
| Finished | Oct 02 10:51:55 PM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2185477111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6 .sysrst_ctrl_csr_mem_rw_with_rand_reset.2185477111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3537278266 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2045550640 ps |
| CPU time | 5.98 seconds |
| Started | Oct 02 10:51:47 PM UTC 24 |
| Finished | Oct 02 10:51:54 PM UTC 24 |
| Peak memory | 211072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537278266 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.3537278266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3572359866 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2111701932 ps |
| CPU time | 2.04 seconds |
| Started | Oct 02 10:51:46 PM UTC 24 |
| Finished | Oct 02 10:51:50 PM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572359866 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.3572359866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.676638264 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 7331916100 ps |
| CPU time | 9.35 seconds |
| Started | Oct 02 10:51:48 PM UTC 24 |
| Finished | Oct 02 10:51:58 PM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676638264 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.676638264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3613494494 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4061882475 ps |
| CPU time | 4.22 seconds |
| Started | Oct 02 10:51:44 PM UTC 24 |
| Finished | Oct 02 10:51:50 PM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613494494 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.3613494494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.26677808 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 22212056703 ps |
| CPU time | 81.45 seconds |
| Started | Oct 02 10:51:44 PM UTC 24 |
| Finished | Oct 02 10:53:08 PM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26677808 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.26677808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2860753727 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 2057379993 ps |
| CPU time | 6.06 seconds |
| Started | Oct 02 10:51:55 PM UTC 24 |
| Finished | Oct 02 10:52:02 PM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2860753727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7 .sysrst_ctrl_csr_mem_rw_with_rand_reset.2860753727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.622937313 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2052397390 ps |
| CPU time | 4.91 seconds |
| Started | Oct 02 10:51:53 PM UTC 24 |
| Finished | Oct 02 10:51:59 PM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622937313 -assert nopostproc +UVM_TESTNAME=s ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.622937313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2710347619 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 2017671423 ps |
| CPU time | 8.39 seconds |
| Started | Oct 02 10:51:52 PM UTC 24 |
| Finished | Oct 02 10:52:01 PM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710347619 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.2710347619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.224589770 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 4515540618 ps |
| CPU time | 23.68 seconds |
| Started | Oct 02 10:51:55 PM UTC 24 |
| Finished | Oct 02 10:52:20 PM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224589770 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.224589770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.12382898 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 2029057511 ps |
| CPU time | 10.74 seconds |
| Started | Oct 02 10:51:51 PM UTC 24 |
| Finished | Oct 02 10:52:03 PM UTC 24 |
| Peak memory | 221436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12382898 -assert nopostproc +UVM_TESTNAME=sysrs t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.12382898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1089224222 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 42634991906 ps |
| CPU time | 67.29 seconds |
| Started | Oct 02 10:51:51 PM UTC 24 |
| Finished | Oct 02 10:53:00 PM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089224222 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.1089224222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3807053269 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2076490825 ps |
| CPU time | 11.81 seconds |
| Started | Oct 02 10:52:02 PM UTC 24 |
| Finished | Oct 02 10:52:15 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3807053269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8 .sysrst_ctrl_csr_mem_rw_with_rand_reset.3807053269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2083878859 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2070598336 ps |
| CPU time | 4.23 seconds |
| Started | Oct 02 10:52:00 PM UTC 24 |
| Finished | Oct 02 10:52:05 PM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083878859 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.2083878859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2695119854 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 2022510639 ps |
| CPU time | 4.33 seconds |
| Started | Oct 02 10:51:59 PM UTC 24 |
| Finished | Oct 02 10:52:05 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695119854 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.2695119854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.364172208 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 5360963178 ps |
| CPU time | 28.54 seconds |
| Started | Oct 02 10:52:02 PM UTC 24 |
| Finished | Oct 02 10:52:32 PM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364172208 -assert nopostpr oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.364172208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3169773029 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 2082801723 ps |
| CPU time | 10.71 seconds |
| Started | Oct 02 10:51:56 PM UTC 24 |
| Finished | Oct 02 10:52:08 PM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169773029 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.3169773029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1376540853 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 22397498395 ps |
| CPU time | 35.86 seconds |
| Started | Oct 02 10:51:57 PM UTC 24 |
| Finished | Oct 02 10:52:35 PM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376540853 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.1376540853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3009225127 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2045643614 ps |
| CPU time | 10.15 seconds |
| Started | Oct 02 10:52:07 PM UTC 24 |
| Finished | Oct 02 10:52:19 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3009225127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9 .sysrst_ctrl_csr_mem_rw_with_rand_reset.3009225127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2999267544 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2096960923 ps |
| CPU time | 3.03 seconds |
| Started | Oct 02 10:52:06 PM UTC 24 |
| Finished | Oct 02 10:52:10 PM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999267544 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.2999267544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.4193954352 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 2014120459 ps |
| CPU time | 9.77 seconds |
| Started | Oct 02 10:52:06 PM UTC 24 |
| Finished | Oct 02 10:52:17 PM UTC 24 |
| Peak memory | 210672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193954352 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.4193954352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2699436426 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 4565377712 ps |
| CPU time | 23.88 seconds |
| Started | Oct 02 10:52:06 PM UTC 24 |
| Finished | Oct 02 10:52:31 PM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699436426 -assert nopostp roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.2699436426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1449595394 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 2382186028 ps |
| CPU time | 3.42 seconds |
| Started | Oct 02 10:52:03 PM UTC 24 |
| Finished | Oct 02 10:52:07 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449595394 -assert nopostproc +UVM_TESTNAME=sys rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.1449595394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3067683382 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 22289727420 ps |
| CPU time | 30.85 seconds |
| Started | Oct 02 10:52:04 PM UTC 24 |
| Finished | Oct 02 10:52:36 PM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067683382 -assert nopostproc +UVM_ TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.3067683382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1452602096 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2350123048 ps |
| CPU time | 2.47 seconds |
| Started | Oct 02 10:40:49 PM UTC 24 |
| Finished | Oct 02 10:40:52 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452602096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1452602096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4168502988 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4346424195 ps |
| CPU time | 24.08 seconds |
| Started | Oct 02 10:40:51 PM UTC 24 |
| Finished | Oct 02 10:41:17 PM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168502988 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.4168502988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2066480846 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2611107088 ps |
| CPU time | 6.12 seconds |
| Started | Oct 02 10:40:50 PM UTC 24 |
| Finished | Oct 02 10:40:57 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066480846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.2066480846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.1321750487 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2138633364 ps |
| CPU time | 3.32 seconds |
| Started | Oct 02 10:40:49 PM UTC 24 |
| Finished | Oct 02 10:40:53 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321750487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1321750487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.2408311817 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2145737612 ps |
| CPU time | 3.51 seconds |
| Started | Oct 02 10:40:48 PM UTC 24 |
| Finished | Oct 02 10:40:52 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408311817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2408311817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2850497692 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5907562061 ps |
| CPU time | 10.11 seconds |
| Started | Oct 02 10:40:54 PM UTC 24 |
| Finished | Oct 02 10:41:05 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2850497692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.2850497692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3523141831 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5276514208 ps |
| CPU time | 2.95 seconds |
| Started | Oct 02 10:40:53 PM UTC 24 |
| Finished | Oct 02 10:40:57 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523141831 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.3523141831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.4038092682 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2010455022 ps |
| CPU time | 7.67 seconds |
| Started | Oct 02 10:41:08 PM UTC 24 |
| Finished | Oct 02 10:41:17 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038092682 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.4038092682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.3270226020 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 88671488647 ps |
| CPU time | 42.44 seconds |
| Started | Oct 02 10:41:01 PM UTC 24 |
| Finished | Oct 02 10:41:45 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270226020 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.3270226020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2925723875 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2255334568 ps |
| CPU time | 8.88 seconds |
| Started | Oct 02 10:40:57 PM UTC 24 |
| Finished | Oct 02 10:41:07 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925723875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2925723875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3419367703 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2317631798 ps |
| CPU time | 2.88 seconds |
| Started | Oct 02 10:40:58 PM UTC 24 |
| Finished | Oct 02 10:41:01 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419367703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3419367703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3798554021 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2778426710 ps |
| CPU time | 8.78 seconds |
| Started | Oct 02 10:41:00 PM UTC 24 |
| Finished | Oct 02 10:41:10 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798554021 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.3798554021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.461111339 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2635492299 ps |
| CPU time | 3.62 seconds |
| Started | Oct 02 10:40:59 PM UTC 24 |
| Finished | Oct 02 10:41:03 PM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461111339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.461111339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.2163519528 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2461814528 ps |
| CPU time | 11.59 seconds |
| Started | Oct 02 10:40:56 PM UTC 24 |
| Finished | Oct 02 10:41:09 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163519528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2163519528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.216103906 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2144965776 ps |
| CPU time | 12.65 seconds |
| Started | Oct 02 10:40:59 PM UTC 24 |
| Finished | Oct 02 10:41:13 PM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216103906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.216103906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.2773425148 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2510818415 ps |
| CPU time | 7.26 seconds |
| Started | Oct 02 10:40:59 PM UTC 24 |
| Finished | Oct 02 10:41:07 PM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773425148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.2773425148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.2286382027 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 22012903557 ps |
| CPU time | 68.76 seconds |
| Started | Oct 02 10:41:06 PM UTC 24 |
| Finished | Oct 02 10:42:16 PM UTC 24 |
| Peak memory | 243616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286382027 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2286382027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.2580725027 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2122348676 ps |
| CPU time | 4.04 seconds |
| Started | Oct 02 10:40:55 PM UTC 24 |
| Finished | Oct 02 10:41:00 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580725027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.2580725027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.3769305924 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 8911604472 ps |
| CPU time | 11.34 seconds |
| Started | Oct 02 10:41:04 PM UTC 24 |
| Finished | Oct 02 10:41:17 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769305924 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.3769305924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.433403260 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2017013785 ps |
| CPU time | 9.19 seconds |
| Started | Oct 02 10:42:29 PM UTC 24 |
| Finished | Oct 02 10:42:40 PM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433403260 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.433403260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.502057559 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3506946458 ps |
| CPU time | 20.28 seconds |
| Started | Oct 02 10:42:25 PM UTC 24 |
| Finished | Oct 02 10:42:47 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502057559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.502057559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1066063168 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 74582543303 ps |
| CPU time | 247.07 seconds |
| Started | Oct 02 10:42:26 PM UTC 24 |
| Finished | Oct 02 10:46:37 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066063168 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.1066063168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2246949017 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 5636467888 ps |
| CPU time | 24.84 seconds |
| Started | Oct 02 10:42:24 PM UTC 24 |
| Finished | Oct 02 10:42:50 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246949017 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.2246949017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.2391284647 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3286742514 ps |
| CPU time | 5.03 seconds |
| Started | Oct 02 10:42:27 PM UTC 24 |
| Finished | Oct 02 10:42:33 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391284647 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.2391284647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3280691443 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2641884078 ps |
| CPU time | 2.86 seconds |
| Started | Oct 02 10:42:24 PM UTC 24 |
| Finished | Oct 02 10:42:28 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280691443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.3280691443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.1100165448 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2493022387 ps |
| CPU time | 4.44 seconds |
| Started | Oct 02 10:42:24 PM UTC 24 |
| Finished | Oct 02 10:42:29 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100165448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.1100165448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.737900130 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2112612467 ps |
| CPU time | 6.4 seconds |
| Started | Oct 02 10:42:24 PM UTC 24 |
| Finished | Oct 02 10:42:31 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737900130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.737900130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3038338245 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2530485615 ps |
| CPU time | 3.57 seconds |
| Started | Oct 02 10:42:24 PM UTC 24 |
| Finished | Oct 02 10:42:29 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038338245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3038338245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.3309613368 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2112080791 ps |
| CPU time | 8.1 seconds |
| Started | Oct 02 10:42:23 PM UTC 24 |
| Finished | Oct 02 10:42:32 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309613368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.3309613368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.210814938 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 6500051436 ps |
| CPU time | 6.31 seconds |
| Started | Oct 02 10:42:28 PM UTC 24 |
| Finished | Oct 02 10:42:35 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210814938 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.210814938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2704463856 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 4775992477 ps |
| CPU time | 13.04 seconds |
| Started | Oct 02 10:42:28 PM UTC 24 |
| Finished | Oct 02 10:42:42 PM UTC 24 |
| Peak memory | 222220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2704463856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.2704463856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.140178950 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 7813973336 ps |
| CPU time | 1.85 seconds |
| Started | Oct 02 10:42:25 PM UTC 24 |
| Finished | Oct 02 10:42:28 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140178950 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.140178950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1739140057 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2060658646 ps |
| CPU time | 1.8 seconds |
| Started | Oct 02 10:42:35 PM UTC 24 |
| Finished | Oct 02 10:42:38 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739140057 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.1739140057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2842081635 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 3188458556 ps |
| CPU time | 8.68 seconds |
| Started | Oct 02 10:42:30 PM UTC 24 |
| Finished | Oct 02 10:42:40 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842081635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2842081635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.3893685139 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 177569560336 ps |
| CPU time | 90.9 seconds |
| Started | Oct 02 10:42:32 PM UTC 24 |
| Finished | Oct 02 10:44:05 PM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893685139 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.3893685139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.4175393866 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 32374465568 ps |
| CPU time | 54.39 seconds |
| Started | Oct 02 10:42:33 PM UTC 24 |
| Finished | Oct 02 10:43:29 PM UTC 24 |
| Peak memory | 211808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175393866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_with_pre_cond.4175393866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2337327255 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2708221447 ps |
| CPU time | 3.07 seconds |
| Started | Oct 02 10:42:30 PM UTC 24 |
| Finished | Oct 02 10:42:35 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337327255 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.2337327255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.4175638718 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2641253049 ps |
| CPU time | 2.82 seconds |
| Started | Oct 02 10:42:30 PM UTC 24 |
| Finished | Oct 02 10:42:34 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175638718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.4175638718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.906117671 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2473714620 ps |
| CPU time | 4.18 seconds |
| Started | Oct 02 10:42:29 PM UTC 24 |
| Finished | Oct 02 10:42:34 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906117671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.906117671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.873141931 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2220217563 ps |
| CPU time | 7.46 seconds |
| Started | Oct 02 10:42:29 PM UTC 24 |
| Finished | Oct 02 10:42:38 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873141931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.873141931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.1420280927 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2526686598 ps |
| CPU time | 3.79 seconds |
| Started | Oct 02 10:42:30 PM UTC 24 |
| Finished | Oct 02 10:42:35 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420280927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.1420280927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.2856897334 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2112477748 ps |
| CPU time | 7.21 seconds |
| Started | Oct 02 10:42:29 PM UTC 24 |
| Finished | Oct 02 10:42:37 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856897334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2856897334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2952147811 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 6659021612 ps |
| CPU time | 10.17 seconds |
| Started | Oct 02 10:42:34 PM UTC 24 |
| Finished | Oct 02 10:42:45 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952147811 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.2952147811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3428082790 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 8047060684 ps |
| CPU time | 22.83 seconds |
| Started | Oct 02 10:42:33 PM UTC 24 |
| Finished | Oct 02 10:42:57 PM UTC 24 |
| Peak memory | 228136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3428082790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.3428082790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.472524825 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 9635140453 ps |
| CPU time | 12.46 seconds |
| Started | Oct 02 10:42:31 PM UTC 24 |
| Finished | Oct 02 10:42:44 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472524825 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.472524825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.205393412 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2015419716 ps |
| CPU time | 8.22 seconds |
| Started | Oct 02 10:42:41 PM UTC 24 |
| Finished | Oct 02 10:42:51 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205393412 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.205393412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2811423456 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 3900460843 ps |
| CPU time | 14.4 seconds |
| Started | Oct 02 10:42:38 PM UTC 24 |
| Finished | Oct 02 10:42:53 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811423456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.2811423456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.3438191407 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 72754288790 ps |
| CPU time | 191.07 seconds |
| Started | Oct 02 10:42:39 PM UTC 24 |
| Finished | Oct 02 10:45:53 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438191407 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.3438191407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.4171944323 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 28087647397 ps |
| CPU time | 45.5 seconds |
| Started | Oct 02 10:42:40 PM UTC 24 |
| Finished | Oct 02 10:43:28 PM UTC 24 |
| Peak memory | 211848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171944323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_with_pre_cond.4171944323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3513064028 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 4227381274 ps |
| CPU time | 12.73 seconds |
| Started | Oct 02 10:42:37 PM UTC 24 |
| Finished | Oct 02 10:42:50 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513064028 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.3513064028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.3116461040 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3185014511 ps |
| CPU time | 5.09 seconds |
| Started | Oct 02 10:42:39 PM UTC 24 |
| Finished | Oct 02 10:42:45 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116461040 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.3116461040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.880616779 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2621460457 ps |
| CPU time | 4.79 seconds |
| Started | Oct 02 10:42:36 PM UTC 24 |
| Finished | Oct 02 10:42:42 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880616779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.880616779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.162630253 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2445486899 ps |
| CPU time | 5.67 seconds |
| Started | Oct 02 10:42:35 PM UTC 24 |
| Finished | Oct 02 10:42:42 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162630253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.162630253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.2254636766 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 2186855618 ps |
| CPU time | 2.3 seconds |
| Started | Oct 02 10:42:35 PM UTC 24 |
| Finished | Oct 02 10:42:39 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254636766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.2254636766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.2266624238 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2113030660 ps |
| CPU time | 5.62 seconds |
| Started | Oct 02 10:42:35 PM UTC 24 |
| Finished | Oct 02 10:42:42 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266624238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.2266624238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.3813543103 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1169737289899 ps |
| CPU time | 2146.35 seconds |
| Started | Oct 02 10:42:40 PM UTC 24 |
| Finished | Oct 02 11:18:48 PM UTC 24 |
| Peak memory | 213140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813543103 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.3813543103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1943321247 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 6526032098 ps |
| CPU time | 8.36 seconds |
| Started | Oct 02 10:42:39 PM UTC 24 |
| Finished | Oct 02 10:42:48 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943321247 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.1943321247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1381705795 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2119703350 ps |
| CPU time | 1.33 seconds |
| Started | Oct 02 10:42:48 PM UTC 24 |
| Finished | Oct 02 10:42:51 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381705795 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.1381705795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1114077081 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 259048009274 ps |
| CPU time | 863.56 seconds |
| Started | Oct 02 10:42:45 PM UTC 24 |
| Finished | Oct 02 10:57:18 PM UTC 24 |
| Peak memory | 213140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114077081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.1114077081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3691442143 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3524639243 ps |
| CPU time | 5.01 seconds |
| Started | Oct 02 10:42:44 PM UTC 24 |
| Finished | Oct 02 10:42:50 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691442143 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.3691442143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.703151786 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2636252451 ps |
| CPU time | 3.23 seconds |
| Started | Oct 02 10:42:44 PM UTC 24 |
| Finished | Oct 02 10:42:49 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703151786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.703151786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.1099555621 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2469457543 ps |
| CPU time | 4.92 seconds |
| Started | Oct 02 10:42:42 PM UTC 24 |
| Finished | Oct 02 10:42:49 PM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099555621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.1099555621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.3235287254 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2152933873 ps |
| CPU time | 3.49 seconds |
| Started | Oct 02 10:42:42 PM UTC 24 |
| Finished | Oct 02 10:42:48 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235287254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.3235287254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.2469227060 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 2597758566 ps |
| CPU time | 1.94 seconds |
| Started | Oct 02 10:42:44 PM UTC 24 |
| Finished | Oct 02 10:42:47 PM UTC 24 |
| Peak memory | 211788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469227060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.2469227060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.216403844 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2117590338 ps |
| CPU time | 3.61 seconds |
| Started | Oct 02 10:42:42 PM UTC 24 |
| Finished | Oct 02 10:42:47 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216403844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.216403844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.4125565673 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 8847835823 ps |
| CPU time | 25.2 seconds |
| Started | Oct 02 10:42:48 PM UTC 24 |
| Finished | Oct 02 10:43:15 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125565673 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.4125565673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2816317244 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 3999679522 ps |
| CPU time | 17.06 seconds |
| Started | Oct 02 10:42:48 PM UTC 24 |
| Finished | Oct 02 10:43:07 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2816317244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.2816317244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.801171461 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3211298575 ps |
| CPU time | 3.62 seconds |
| Started | Oct 02 10:42:45 PM UTC 24 |
| Finished | Oct 02 10:42:50 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801171461 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.801171461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.26817218 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2017128898 ps |
| CPU time | 3.71 seconds |
| Started | Oct 02 10:42:55 PM UTC 24 |
| Finished | Oct 02 10:42:59 PM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26817218 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.26817218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1050951632 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 3296029257 ps |
| CPU time | 15.16 seconds |
| Started | Oct 02 10:42:51 PM UTC 24 |
| Finished | Oct 02 10:43:07 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050951632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.1050951632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.3691906237 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 142077061283 ps |
| CPU time | 203.78 seconds |
| Started | Oct 02 10:42:52 PM UTC 24 |
| Finished | Oct 02 10:46:19 PM UTC 24 |
| Peak memory | 211860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691906237 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.3691906237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2130985852 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 73660425949 ps |
| CPU time | 91.02 seconds |
| Started | Oct 02 10:42:54 PM UTC 24 |
| Finished | Oct 02 10:44:28 PM UTC 24 |
| Peak memory | 211852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130985852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_with_pre_cond.2130985852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.392659345 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 3215514774 ps |
| CPU time | 4.76 seconds |
| Started | Oct 02 10:42:51 PM UTC 24 |
| Finished | Oct 02 10:42:57 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392659345 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.392659345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.1458208181 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 3084749024 ps |
| CPU time | 7.6 seconds |
| Started | Oct 02 10:42:53 PM UTC 24 |
| Finished | Oct 02 10:43:02 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458208181 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.1458208181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.428438713 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2625087572 ps |
| CPU time | 5.01 seconds |
| Started | Oct 02 10:42:51 PM UTC 24 |
| Finished | Oct 02 10:42:57 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428438713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.428438713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.4029198345 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2470500672 ps |
| CPU time | 3.09 seconds |
| Started | Oct 02 10:42:50 PM UTC 24 |
| Finished | Oct 02 10:42:54 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029198345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.4029198345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.950484854 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2063154432 ps |
| CPU time | 2.74 seconds |
| Started | Oct 02 10:42:50 PM UTC 24 |
| Finished | Oct 02 10:42:53 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950484854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.950484854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.3983633970 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2109621280 ps |
| CPU time | 11.28 seconds |
| Started | Oct 02 10:42:50 PM UTC 24 |
| Finished | Oct 02 10:43:02 PM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983633970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3983633970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.3924195791 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 6721552682 ps |
| CPU time | 33.46 seconds |
| Started | Oct 02 10:42:55 PM UTC 24 |
| Finished | Oct 02 10:43:29 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924195791 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.3924195791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3403367392 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 9058970194 ps |
| CPU time | 14.93 seconds |
| Started | Oct 02 10:42:54 PM UTC 24 |
| Finished | Oct 02 10:43:11 PM UTC 24 |
| Peak memory | 222208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3403367392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.3403367392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2649846966 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 9327769349 ps |
| CPU time | 8.77 seconds |
| Started | Oct 02 10:42:52 PM UTC 24 |
| Finished | Oct 02 10:43:02 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649846966 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.2649846966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1633713351 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2110886670 ps |
| CPU time | 1.75 seconds |
| Started | Oct 02 10:43:04 PM UTC 24 |
| Finished | Oct 02 10:43:07 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633713351 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.1633713351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2628725866 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3911371067 ps |
| CPU time | 2.03 seconds |
| Started | Oct 02 10:43:00 PM UTC 24 |
| Finished | Oct 02 10:43:03 PM UTC 24 |
| Peak memory | 211844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628725866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2628725866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.336398437 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 138064344014 ps |
| CPU time | 463.67 seconds |
| Started | Oct 02 10:43:01 PM UTC 24 |
| Finished | Oct 02 10:50:51 PM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336398437 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.336398437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.3937729834 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 79355986275 ps |
| CPU time | 119.71 seconds |
| Started | Oct 02 10:43:03 PM UTC 24 |
| Finished | Oct 02 10:45:05 PM UTC 24 |
| Peak memory | 211812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937729834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_with_pre_cond.3937729834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2182507289 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2493247576 ps |
| CPU time | 7.28 seconds |
| Started | Oct 02 10:42:59 PM UTC 24 |
| Finished | Oct 02 10:43:08 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182507289 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.2182507289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.2029531301 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 3235355807 ps |
| CPU time | 15.89 seconds |
| Started | Oct 02 10:43:03 PM UTC 24 |
| Finished | Oct 02 10:43:20 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029531301 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.2029531301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.4205384100 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2611956693 ps |
| CPU time | 10.9 seconds |
| Started | Oct 02 10:42:58 PM UTC 24 |
| Finished | Oct 02 10:43:10 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205384100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.4205384100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1576689456 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2446254823 ps |
| CPU time | 8.44 seconds |
| Started | Oct 02 10:42:58 PM UTC 24 |
| Finished | Oct 02 10:43:07 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576689456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1576689456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.355429776 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2060043328 ps |
| CPU time | 9.57 seconds |
| Started | Oct 02 10:42:58 PM UTC 24 |
| Finished | Oct 02 10:43:09 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355429776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.355429776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.4205111868 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2515914790 ps |
| CPU time | 5.79 seconds |
| Started | Oct 02 10:42:58 PM UTC 24 |
| Finished | Oct 02 10:43:05 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205111868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.4205111868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.2223485179 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 2111723369 ps |
| CPU time | 9.9 seconds |
| Started | Oct 02 10:42:56 PM UTC 24 |
| Finished | Oct 02 10:43:07 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223485179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.2223485179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3509094176 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 13564752201 ps |
| CPU time | 11.71 seconds |
| Started | Oct 02 10:43:03 PM UTC 24 |
| Finished | Oct 02 10:43:16 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509094176 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.3509094176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3638318834 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 6422094088 ps |
| CPU time | 13.21 seconds |
| Started | Oct 02 10:43:03 PM UTC 24 |
| Finished | Oct 02 10:43:17 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3638318834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.3638318834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3934206275 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3497395345190 ps |
| CPU time | 233.41 seconds |
| Started | Oct 02 10:43:01 PM UTC 24 |
| Finished | Oct 02 10:46:58 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934206275 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.3934206275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2980679650 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2094598074 ps |
| CPU time | 1.69 seconds |
| Started | Oct 02 10:43:13 PM UTC 24 |
| Finished | Oct 02 10:43:16 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980679650 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.2980679650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1172386154 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 3303001402 ps |
| CPU time | 3.56 seconds |
| Started | Oct 02 10:43:08 PM UTC 24 |
| Finished | Oct 02 10:43:13 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172386154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.1172386154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1636259740 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 42194411846 ps |
| CPU time | 32.49 seconds |
| Started | Oct 02 10:43:10 PM UTC 24 |
| Finished | Oct 02 10:43:44 PM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636259740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_with_pre_cond.1636259740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1816429709 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3050515118 ps |
| CPU time | 8.37 seconds |
| Started | Oct 02 10:43:07 PM UTC 24 |
| Finished | Oct 02 10:43:17 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816429709 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.1816429709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.3839319103 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3088775946 ps |
| CPU time | 10.59 seconds |
| Started | Oct 02 10:43:09 PM UTC 24 |
| Finished | Oct 02 10:43:20 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839319103 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.3839319103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3283156091 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2626981628 ps |
| CPU time | 4 seconds |
| Started | Oct 02 10:43:07 PM UTC 24 |
| Finished | Oct 02 10:43:12 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283156091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3283156091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.3758846950 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2476079212 ps |
| CPU time | 6.75 seconds |
| Started | Oct 02 10:43:04 PM UTC 24 |
| Finished | Oct 02 10:43:12 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758846950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.3758846950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.4118416439 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2173659349 ps |
| CPU time | 10.53 seconds |
| Started | Oct 02 10:43:06 PM UTC 24 |
| Finished | Oct 02 10:43:18 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118416439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.4118416439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2901164868 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2508076248 ps |
| CPU time | 7.26 seconds |
| Started | Oct 02 10:43:07 PM UTC 24 |
| Finished | Oct 02 10:43:16 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901164868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.2901164868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.3812023505 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 2174086090 ps |
| CPU time | 1.67 seconds |
| Started | Oct 02 10:43:04 PM UTC 24 |
| Finished | Oct 02 10:43:07 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812023505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.3812023505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.565297999 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 12269498510 ps |
| CPU time | 28.33 seconds |
| Started | Oct 02 10:43:12 PM UTC 24 |
| Finished | Oct 02 10:43:42 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565297999 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.565297999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.378527983 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 6120460176 ps |
| CPU time | 18.4 seconds |
| Started | Oct 02 10:43:11 PM UTC 24 |
| Finished | Oct 02 10:43:30 PM UTC 24 |
| Peak memory | 222100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=378527983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.378527983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.4175406455 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2004874528996 ps |
| CPU time | 13.83 seconds |
| Started | Oct 02 10:43:09 PM UTC 24 |
| Finished | Oct 02 10:43:23 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175406455 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.4175406455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.3511423187 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2022814366 ps |
| CPU time | 2.81 seconds |
| Started | Oct 02 10:43:21 PM UTC 24 |
| Finished | Oct 02 10:43:25 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511423187 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.3511423187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.3529050889 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3661262179 ps |
| CPU time | 7.2 seconds |
| Started | Oct 02 10:43:18 PM UTC 24 |
| Finished | Oct 02 10:43:26 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529050889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.3529050889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3582973173 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 3548992835 ps |
| CPU time | 5.37 seconds |
| Started | Oct 02 10:43:16 PM UTC 24 |
| Finished | Oct 02 10:43:23 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582973173 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.3582973173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.4036754815 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 3333897035 ps |
| CPU time | 3.14 seconds |
| Started | Oct 02 10:43:19 PM UTC 24 |
| Finished | Oct 02 10:43:23 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036754815 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.4036754815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1644775622 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2614840227 ps |
| CPU time | 9.3 seconds |
| Started | Oct 02 10:43:16 PM UTC 24 |
| Finished | Oct 02 10:43:27 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644775622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.1644775622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.3368998805 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2478601990 ps |
| CPU time | 6.7 seconds |
| Started | Oct 02 10:43:14 PM UTC 24 |
| Finished | Oct 02 10:43:22 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368998805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.3368998805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.1728587691 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2089746326 ps |
| CPU time | 3.61 seconds |
| Started | Oct 02 10:43:15 PM UTC 24 |
| Finished | Oct 02 10:43:20 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728587691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.1728587691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.3653442310 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2532445008 ps |
| CPU time | 4.1 seconds |
| Started | Oct 02 10:43:16 PM UTC 24 |
| Finished | Oct 02 10:43:21 PM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653442310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.3653442310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.942978773 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2108868150 ps |
| CPU time | 7.11 seconds |
| Started | Oct 02 10:43:13 PM UTC 24 |
| Finished | Oct 02 10:43:21 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942978773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.942978773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.701130212 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 6179925856 ps |
| CPU time | 5.06 seconds |
| Started | Oct 02 10:43:21 PM UTC 24 |
| Finished | Oct 02 10:43:27 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701130212 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.701130212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.948899315 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 6341368533 ps |
| CPU time | 3.56 seconds |
| Started | Oct 02 10:43:18 PM UTC 24 |
| Finished | Oct 02 10:43:22 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948899315 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.948899315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.4084475834 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2029452743 ps |
| CPU time | 2.94 seconds |
| Started | Oct 02 10:43:27 PM UTC 24 |
| Finished | Oct 02 10:43:31 PM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084475834 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.4084475834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2056667701 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3579898160 ps |
| CPU time | 3.28 seconds |
| Started | Oct 02 10:43:25 PM UTC 24 |
| Finished | Oct 02 10:43:29 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056667701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.2056667701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.565914348 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 77197715904 ps |
| CPU time | 283.29 seconds |
| Started | Oct 02 10:43:26 PM UTC 24 |
| Finished | Oct 02 10:48:13 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565914348 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.565914348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1802624837 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 54855504989 ps |
| CPU time | 82.92 seconds |
| Started | Oct 02 10:43:26 PM UTC 24 |
| Finished | Oct 02 10:44:51 PM UTC 24 |
| Peak memory | 211868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802624837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_with_pre_cond.1802624837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.3518497879 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3580017743 ps |
| CPU time | 9.22 seconds |
| Started | Oct 02 10:43:24 PM UTC 24 |
| Finished | Oct 02 10:43:34 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518497879 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.3518497879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.2944386738 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 5249360462 ps |
| CPU time | 11.61 seconds |
| Started | Oct 02 10:43:26 PM UTC 24 |
| Finished | Oct 02 10:43:39 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944386738 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.2944386738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.681322076 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2620882691 ps |
| CPU time | 4.84 seconds |
| Started | Oct 02 10:43:23 PM UTC 24 |
| Finished | Oct 02 10:43:30 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681322076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.681322076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1929234343 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2472451022 ps |
| CPU time | 2.6 seconds |
| Started | Oct 02 10:43:22 PM UTC 24 |
| Finished | Oct 02 10:43:26 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929234343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.1929234343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.3356410726 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2265802914 ps |
| CPU time | 1.75 seconds |
| Started | Oct 02 10:43:22 PM UTC 24 |
| Finished | Oct 02 10:43:25 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356410726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.3356410726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.4124062237 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2518726971 ps |
| CPU time | 3.81 seconds |
| Started | Oct 02 10:43:23 PM UTC 24 |
| Finished | Oct 02 10:43:28 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124062237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.4124062237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.2369299475 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2158945839 ps |
| CPU time | 2.16 seconds |
| Started | Oct 02 10:43:22 PM UTC 24 |
| Finished | Oct 02 10:43:25 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369299475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.2369299475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.1901901401 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 16609893301 ps |
| CPU time | 10.7 seconds |
| Started | Oct 02 10:43:27 PM UTC 24 |
| Finished | Oct 02 10:43:39 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901901401 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.1901901401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1291235752 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 13866212277 ps |
| CPU time | 15.33 seconds |
| Started | Oct 02 10:43:27 PM UTC 24 |
| Finished | Oct 02 10:43:44 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1291235752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.1291235752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1330772585 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2751132494 ps |
| CPU time | 3.9 seconds |
| Started | Oct 02 10:43:25 PM UTC 24 |
| Finished | Oct 02 10:43:30 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330772585 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.1330772585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.528091276 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2012692467 ps |
| CPU time | 8.91 seconds |
| Started | Oct 02 10:43:34 PM UTC 24 |
| Finished | Oct 02 10:43:44 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528091276 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.528091276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1614785829 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 3229264181 ps |
| CPU time | 1.95 seconds |
| Started | Oct 02 10:43:31 PM UTC 24 |
| Finished | Oct 02 10:43:34 PM UTC 24 |
| Peak memory | 211780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614785829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1614785829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.478041176 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 187192412593 ps |
| CPU time | 516.79 seconds |
| Started | Oct 02 10:43:32 PM UTC 24 |
| Finished | Oct 02 10:52:14 PM UTC 24 |
| Peak memory | 213380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478041176 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.478041176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2614057529 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 37289336344 ps |
| CPU time | 38.67 seconds |
| Started | Oct 02 10:43:33 PM UTC 24 |
| Finished | Oct 02 10:44:13 PM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614057529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_with_pre_cond.2614057529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3794247877 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 3108951446 ps |
| CPU time | 10.38 seconds |
| Started | Oct 02 10:43:31 PM UTC 24 |
| Finished | Oct 02 10:43:42 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794247877 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.3794247877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.908946817 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3009501663 ps |
| CPU time | 6.09 seconds |
| Started | Oct 02 10:43:32 PM UTC 24 |
| Finished | Oct 02 10:43:39 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908946817 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.908946817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.857028279 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2613366698 ps |
| CPU time | 11.5 seconds |
| Started | Oct 02 10:43:31 PM UTC 24 |
| Finished | Oct 02 10:43:43 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857028279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.857028279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.2329473007 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2489391311 ps |
| CPU time | 2.41 seconds |
| Started | Oct 02 10:43:28 PM UTC 24 |
| Finished | Oct 02 10:43:32 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329473007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.2329473007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.3202647801 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2183297575 ps |
| CPU time | 2.84 seconds |
| Started | Oct 02 10:43:29 PM UTC 24 |
| Finished | Oct 02 10:43:33 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202647801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.3202647801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.1924000161 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2529429569 ps |
| CPU time | 2.79 seconds |
| Started | Oct 02 10:43:30 PM UTC 24 |
| Finished | Oct 02 10:43:33 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924000161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.1924000161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.90493559 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2129091827 ps |
| CPU time | 2.4 seconds |
| Started | Oct 02 10:43:28 PM UTC 24 |
| Finished | Oct 02 10:43:32 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90493559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.90493559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.2412402242 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 12929575198 ps |
| CPU time | 26.13 seconds |
| Started | Oct 02 10:43:34 PM UTC 24 |
| Finished | Oct 02 10:44:02 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412402242 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.2412402242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.558776850 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 7140547673 ps |
| CPU time | 8.04 seconds |
| Started | Oct 02 10:43:33 PM UTC 24 |
| Finished | Oct 02 10:43:42 PM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=558776850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.558776850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2188816661 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 3538938296 ps |
| CPU time | 3.03 seconds |
| Started | Oct 02 10:43:31 PM UTC 24 |
| Finished | Oct 02 10:43:35 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188816661 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.2188816661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.11542730 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2038322299 ps |
| CPU time | 2.08 seconds |
| Started | Oct 02 10:41:19 PM UTC 24 |
| Finished | Oct 02 10:41:22 PM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11542730 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.11542730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3412698255 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3367387113 ps |
| CPU time | 3.29 seconds |
| Started | Oct 02 10:41:15 PM UTC 24 |
| Finished | Oct 02 10:41:20 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412698255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.3412698255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.4254345081 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 157175618283 ps |
| CPU time | 70.51 seconds |
| Started | Oct 02 10:41:17 PM UTC 24 |
| Finished | Oct 02 10:42:29 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254345081 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.4254345081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3780458915 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2261880403 ps |
| CPU time | 7.85 seconds |
| Started | Oct 02 10:41:10 PM UTC 24 |
| Finished | Oct 02 10:41:19 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780458915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.3780458915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4096458162 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2536259267 ps |
| CPU time | 10.05 seconds |
| Started | Oct 02 10:41:11 PM UTC 24 |
| Finished | Oct 02 10:41:22 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096458162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4096458162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1040293175 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 105412806149 ps |
| CPU time | 284.26 seconds |
| Started | Oct 02 10:41:18 PM UTC 24 |
| Finished | Oct 02 10:46:06 PM UTC 24 |
| Peak memory | 213488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040293175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_with_pre_cond.1040293175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3153872528 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2506191035 ps |
| CPU time | 5.47 seconds |
| Started | Oct 02 10:41:14 PM UTC 24 |
| Finished | Oct 02 10:41:21 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153872528 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.3153872528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.3881023597 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2847179970 ps |
| CPU time | 2.91 seconds |
| Started | Oct 02 10:41:17 PM UTC 24 |
| Finished | Oct 02 10:41:21 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881023597 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.3881023597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1995359537 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2612385528 ps |
| CPU time | 14.27 seconds |
| Started | Oct 02 10:41:13 PM UTC 24 |
| Finished | Oct 02 10:41:29 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995359537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1995359537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.3655316006 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2487407485 ps |
| CPU time | 2.59 seconds |
| Started | Oct 02 10:41:09 PM UTC 24 |
| Finished | Oct 02 10:41:13 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655316006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.3655316006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.871355844 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2207609124 ps |
| CPU time | 2.46 seconds |
| Started | Oct 02 10:41:12 PM UTC 24 |
| Finished | Oct 02 10:41:16 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871355844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.871355844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.3252339697 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 22012870518 ps |
| CPU time | 36.4 seconds |
| Started | Oct 02 10:41:19 PM UTC 24 |
| Finished | Oct 02 10:41:57 PM UTC 24 |
| Peak memory | 243588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252339697 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.3252339697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3789297813 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2111245075 ps |
| CPU time | 8.32 seconds |
| Started | Oct 02 10:41:08 PM UTC 24 |
| Finished | Oct 02 10:41:18 PM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789297813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.3789297813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1602176086 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 6708561650 ps |
| CPU time | 16.96 seconds |
| Started | Oct 02 10:41:18 PM UTC 24 |
| Finished | Oct 02 10:41:36 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1602176086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.1602176086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.1852496393 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2100252370 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 10:43:43 PM UTC 24 |
| Finished | Oct 02 10:43:46 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852496393 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.1852496393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3168284751 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3376595946 ps |
| CPU time | 13.75 seconds |
| Started | Oct 02 10:43:40 PM UTC 24 |
| Finished | Oct 02 10:43:55 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168284751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.3168284751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.575025670 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 224988504950 ps |
| CPU time | 203.38 seconds |
| Started | Oct 02 10:43:40 PM UTC 24 |
| Finished | Oct 02 10:47:07 PM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575025670 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.575025670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.776838534 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 55938677178 ps |
| CPU time | 40.11 seconds |
| Started | Oct 02 10:43:41 PM UTC 24 |
| Finished | Oct 02 10:44:23 PM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776838534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_with_pre_cond.776838534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1069721935 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 4226427121 ps |
| CPU time | 12.77 seconds |
| Started | Oct 02 10:43:40 PM UTC 24 |
| Finished | Oct 02 10:43:54 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069721935 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.1069721935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.3314604623 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2491710681 ps |
| CPU time | 3.26 seconds |
| Started | Oct 02 10:43:41 PM UTC 24 |
| Finished | Oct 02 10:43:45 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314604623 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.3314604623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2905570168 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2612524826 ps |
| CPU time | 7.15 seconds |
| Started | Oct 02 10:43:39 PM UTC 24 |
| Finished | Oct 02 10:43:47 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905570168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.2905570168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.90109212 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2472391228 ps |
| CPU time | 3.17 seconds |
| Started | Oct 02 10:43:34 PM UTC 24 |
| Finished | Oct 02 10:43:39 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90109212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.90109212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.783928926 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2062767342 ps |
| CPU time | 4.18 seconds |
| Started | Oct 02 10:43:36 PM UTC 24 |
| Finished | Oct 02 10:43:41 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783928926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.783928926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.2251502979 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2511201520 ps |
| CPU time | 11.67 seconds |
| Started | Oct 02 10:43:36 PM UTC 24 |
| Finished | Oct 02 10:43:48 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251502979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.2251502979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.2415440932 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2113907669 ps |
| CPU time | 10.72 seconds |
| Started | Oct 02 10:43:34 PM UTC 24 |
| Finished | Oct 02 10:43:46 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415440932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.2415440932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2223199828 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 14204206482 ps |
| CPU time | 16.41 seconds |
| Started | Oct 02 10:43:43 PM UTC 24 |
| Finished | Oct 02 10:44:01 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223199828 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.2223199828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3920059044 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4355371323 ps |
| CPU time | 16.74 seconds |
| Started | Oct 02 10:43:42 PM UTC 24 |
| Finished | Oct 02 10:44:00 PM UTC 24 |
| Peak memory | 222052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3920059044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.3920059044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2417821221 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 7037396858 ps |
| CPU time | 3.07 seconds |
| Started | Oct 02 10:43:40 PM UTC 24 |
| Finished | Oct 02 10:43:44 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417821221 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.2417821221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.3242046311 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2015319457 ps |
| CPU time | 6.85 seconds |
| Started | Oct 02 10:43:53 PM UTC 24 |
| Finished | Oct 02 10:44:01 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242046311 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.3242046311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2945917166 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 3209768663 ps |
| CPU time | 7.01 seconds |
| Started | Oct 02 10:43:47 PM UTC 24 |
| Finished | Oct 02 10:43:55 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945917166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.2945917166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3034618942 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 32605697659 ps |
| CPU time | 99.02 seconds |
| Started | Oct 02 10:43:48 PM UTC 24 |
| Finished | Oct 02 10:45:29 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034618942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_with_pre_cond.3034618942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2140839902 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 4701503288 ps |
| CPU time | 18.29 seconds |
| Started | Oct 02 10:43:46 PM UTC 24 |
| Finished | Oct 02 10:44:05 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140839902 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.2140839902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.4143853519 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2847157882 ps |
| CPU time | 7.57 seconds |
| Started | Oct 02 10:43:48 PM UTC 24 |
| Finished | Oct 02 10:43:57 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143853519 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.4143853519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.621299320 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2613742884 ps |
| CPU time | 7.59 seconds |
| Started | Oct 02 10:43:46 PM UTC 24 |
| Finished | Oct 02 10:43:54 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621299320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.621299320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.3002504507 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2501949983 ps |
| CPU time | 3.71 seconds |
| Started | Oct 02 10:43:45 PM UTC 24 |
| Finished | Oct 02 10:43:49 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002504507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.3002504507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1373719937 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 2241188578 ps |
| CPU time | 8.03 seconds |
| Started | Oct 02 10:43:45 PM UTC 24 |
| Finished | Oct 02 10:43:54 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373719937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.1373719937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.2890745897 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2509311024 ps |
| CPU time | 11.25 seconds |
| Started | Oct 02 10:43:45 PM UTC 24 |
| Finished | Oct 02 10:43:57 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890745897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.2890745897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.353640768 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2121091766 ps |
| CPU time | 5.93 seconds |
| Started | Oct 02 10:43:45 PM UTC 24 |
| Finished | Oct 02 10:43:52 PM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353640768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.353640768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3899950008 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 8209113616 ps |
| CPU time | 15.35 seconds |
| Started | Oct 02 10:43:51 PM UTC 24 |
| Finished | Oct 02 10:44:07 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899950008 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.3899950008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1593000889 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 3692803648 ps |
| CPU time | 4.94 seconds |
| Started | Oct 02 10:43:49 PM UTC 24 |
| Finished | Oct 02 10:43:55 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1593000889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.1593000889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.630192737 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 134232828696 ps |
| CPU time | 39.63 seconds |
| Started | Oct 02 10:43:47 PM UTC 24 |
| Finished | Oct 02 10:44:28 PM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630192737 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.630192737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.419148046 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2010212038 ps |
| CPU time | 7.74 seconds |
| Started | Oct 02 10:44:01 PM UTC 24 |
| Finished | Oct 02 10:44:10 PM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419148046 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.419148046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2951320103 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3519889292 ps |
| CPU time | 6.31 seconds |
| Started | Oct 02 10:43:56 PM UTC 24 |
| Finished | Oct 02 10:44:04 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951320103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.2951320103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.1746367237 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 180939127535 ps |
| CPU time | 255.2 seconds |
| Started | Oct 02 10:43:58 PM UTC 24 |
| Finished | Oct 02 10:48:16 PM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746367237 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.1746367237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2500543949 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2616990482 ps |
| CPU time | 5.9 seconds |
| Started | Oct 02 10:43:55 PM UTC 24 |
| Finished | Oct 02 10:44:02 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500543949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.2500543949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.2295225961 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2490576416 ps |
| CPU time | 3.58 seconds |
| Started | Oct 02 10:43:54 PM UTC 24 |
| Finished | Oct 02 10:43:59 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295225961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.2295225961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.930649995 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2078218612 ps |
| CPU time | 6.2 seconds |
| Started | Oct 02 10:43:55 PM UTC 24 |
| Finished | Oct 02 10:44:02 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930649995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.930649995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.1242612173 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2512596999 ps |
| CPU time | 10.77 seconds |
| Started | Oct 02 10:43:55 PM UTC 24 |
| Finished | Oct 02 10:44:07 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242612173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.1242612173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2320648343 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2127650258 ps |
| CPU time | 2.42 seconds |
| Started | Oct 02 10:43:53 PM UTC 24 |
| Finished | Oct 02 10:43:56 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320648343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2320648343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.3581509586 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 7219693491 ps |
| CPU time | 26.33 seconds |
| Started | Oct 02 10:43:59 PM UTC 24 |
| Finished | Oct 02 10:44:27 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581509586 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.3581509586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.1705821603 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 15410135284 ps |
| CPU time | 4.3 seconds |
| Started | Oct 02 10:43:56 PM UTC 24 |
| Finished | Oct 02 10:44:02 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705821603 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.1705821603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.387642719 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2012037096 ps |
| CPU time | 9 seconds |
| Started | Oct 02 10:44:08 PM UTC 24 |
| Finished | Oct 02 10:44:18 PM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387642719 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.387642719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3904981881 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 224652577467 ps |
| CPU time | 637.55 seconds |
| Started | Oct 02 10:44:04 PM UTC 24 |
| Finished | Oct 02 10:54:48 PM UTC 24 |
| Peak memory | 213468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904981881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.3904981881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.3375512727 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 93518174984 ps |
| CPU time | 88.71 seconds |
| Started | Oct 02 10:44:05 PM UTC 24 |
| Finished | Oct 02 10:45:35 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375512727 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.3375512727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3781811497 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 3645235525 ps |
| CPU time | 8.97 seconds |
| Started | Oct 02 10:44:04 PM UTC 24 |
| Finished | Oct 02 10:44:14 PM UTC 24 |
| Peak memory | 211672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781811497 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.3781811497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1188970634 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 3964524348 ps |
| CPU time | 9.06 seconds |
| Started | Oct 02 10:44:06 PM UTC 24 |
| Finished | Oct 02 10:44:16 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188970634 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.1188970634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.4408477 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2620385412 ps |
| CPU time | 3.79 seconds |
| Started | Oct 02 10:44:02 PM UTC 24 |
| Finished | Oct 02 10:44:07 PM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4408477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_ TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.4408477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.2277006790 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2453676096 ps |
| CPU time | 13.07 seconds |
| Started | Oct 02 10:44:01 PM UTC 24 |
| Finished | Oct 02 10:44:15 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277006790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.2277006790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.543094225 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2185396642 ps |
| CPU time | 6.22 seconds |
| Started | Oct 02 10:44:02 PM UTC 24 |
| Finished | Oct 02 10:44:10 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543094225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.543094225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.3740575341 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2534921289 ps |
| CPU time | 2.84 seconds |
| Started | Oct 02 10:44:02 PM UTC 24 |
| Finished | Oct 02 10:44:06 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740575341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.3740575341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2317260327 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2113766882 ps |
| CPU time | 9.15 seconds |
| Started | Oct 02 10:44:01 PM UTC 24 |
| Finished | Oct 02 10:44:11 PM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317260327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.2317260327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.3912431687 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 16125499812 ps |
| CPU time | 11.84 seconds |
| Started | Oct 02 10:44:06 PM UTC 24 |
| Finished | Oct 02 10:44:19 PM UTC 24 |
| Peak memory | 222164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3912431687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.3912431687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2754883571 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1898993093984 ps |
| CPU time | 430.66 seconds |
| Started | Oct 02 10:44:04 PM UTC 24 |
| Finished | Oct 02 10:51:19 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754883571 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.2754883571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.1585942953 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2009690496 ps |
| CPU time | 7.78 seconds |
| Started | Oct 02 10:44:18 PM UTC 24 |
| Finished | Oct 02 10:44:27 PM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585942953 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.1585942953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2551643718 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 3296360154 ps |
| CPU time | 9.55 seconds |
| Started | Oct 02 10:44:13 PM UTC 24 |
| Finished | Oct 02 10:44:24 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551643718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.2551643718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.4208278105 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 105448635335 ps |
| CPU time | 339.1 seconds |
| Started | Oct 02 10:44:14 PM UTC 24 |
| Finished | Oct 02 10:49:58 PM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208278105 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.4208278105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.4062336108 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 63274506668 ps |
| CPU time | 73.31 seconds |
| Started | Oct 02 10:44:16 PM UTC 24 |
| Finished | Oct 02 10:45:31 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062336108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_with_pre_cond.4062336108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1269375566 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 3578197382 ps |
| CPU time | 2.11 seconds |
| Started | Oct 02 10:44:12 PM UTC 24 |
| Finished | Oct 02 10:44:15 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269375566 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.1269375566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.656453522 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2625550455 ps |
| CPU time | 4.3 seconds |
| Started | Oct 02 10:44:11 PM UTC 24 |
| Finished | Oct 02 10:44:16 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656453522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.656453522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.2427603961 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2453913442 ps |
| CPU time | 12.27 seconds |
| Started | Oct 02 10:44:08 PM UTC 24 |
| Finished | Oct 02 10:44:22 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427603961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.2427603961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.204994360 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 2206521314 ps |
| CPU time | 7.5 seconds |
| Started | Oct 02 10:44:11 PM UTC 24 |
| Finished | Oct 02 10:44:19 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204994360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.204994360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.3365717101 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2508667298 ps |
| CPU time | 10.62 seconds |
| Started | Oct 02 10:44:11 PM UTC 24 |
| Finished | Oct 02 10:44:22 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365717101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.3365717101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.3810019875 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2114707109 ps |
| CPU time | 6.47 seconds |
| Started | Oct 02 10:44:08 PM UTC 24 |
| Finished | Oct 02 10:44:16 PM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810019875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.3810019875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.3990400508 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 7748886720 ps |
| CPU time | 7.35 seconds |
| Started | Oct 02 10:44:16 PM UTC 24 |
| Finished | Oct 02 10:44:25 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990400508 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.3990400508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1910121815 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 14364884560 ps |
| CPU time | 7.65 seconds |
| Started | Oct 02 10:44:16 PM UTC 24 |
| Finished | Oct 02 10:44:25 PM UTC 24 |
| Peak memory | 211832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1910121815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1910121815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2435195679 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 4415804438 ps |
| CPU time | 5.38 seconds |
| Started | Oct 02 10:44:13 PM UTC 24 |
| Finished | Oct 02 10:44:19 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435195679 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.2435195679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.3476034496 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2018723266 ps |
| CPU time | 5.41 seconds |
| Started | Oct 02 10:44:26 PM UTC 24 |
| Finished | Oct 02 10:44:32 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476034496 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.3476034496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2054144721 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 244569403725 ps |
| CPU time | 735.2 seconds |
| Started | Oct 02 10:44:22 PM UTC 24 |
| Finished | Oct 02 10:56:45 PM UTC 24 |
| Peak memory | 213136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054144721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.2054144721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2681827072 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 182859937758 ps |
| CPU time | 262.63 seconds |
| Started | Oct 02 10:44:23 PM UTC 24 |
| Finished | Oct 02 10:48:49 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681827072 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.2681827072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.556971290 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 28828844636 ps |
| CPU time | 80.32 seconds |
| Started | Oct 02 10:44:24 PM UTC 24 |
| Finished | Oct 02 10:45:46 PM UTC 24 |
| Peak memory | 211856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556971290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_with_pre_cond.556971290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.4205345545 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2788748344 ps |
| CPU time | 5.47 seconds |
| Started | Oct 02 10:44:21 PM UTC 24 |
| Finished | Oct 02 10:44:28 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205345545 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.4205345545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.979094736 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 2580087940 ps |
| CPU time | 1.5 seconds |
| Started | Oct 02 10:44:23 PM UTC 24 |
| Finished | Oct 02 10:44:26 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979094736 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.979094736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1812717896 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2610057417 ps |
| CPU time | 11.11 seconds |
| Started | Oct 02 10:44:21 PM UTC 24 |
| Finished | Oct 02 10:44:34 PM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812717896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.1812717896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.2975824631 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2497646196 ps |
| CPU time | 4.14 seconds |
| Started | Oct 02 10:44:20 PM UTC 24 |
| Finished | Oct 02 10:44:25 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975824631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.2975824631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.584377739 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2178900878 ps |
| CPU time | 6.21 seconds |
| Started | Oct 02 10:44:20 PM UTC 24 |
| Finished | Oct 02 10:44:27 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584377739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.584377739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.1550041580 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2517136205 ps |
| CPU time | 5.85 seconds |
| Started | Oct 02 10:44:20 PM UTC 24 |
| Finished | Oct 02 10:44:27 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550041580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.1550041580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1786444715 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2111261057 ps |
| CPU time | 5.56 seconds |
| Started | Oct 02 10:44:18 PM UTC 24 |
| Finished | Oct 02 10:44:25 PM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786444715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.1786444715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3067896253 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 8482094134 ps |
| CPU time | 23.97 seconds |
| Started | Oct 02 10:44:24 PM UTC 24 |
| Finished | Oct 02 10:44:50 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3067896253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.3067896253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.1063270924 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2114107857 ps |
| CPU time | 1.51 seconds |
| Started | Oct 02 10:44:36 PM UTC 24 |
| Finished | Oct 02 10:44:39 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063270924 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.1063270924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.803162282 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 3703459349 ps |
| CPU time | 5.45 seconds |
| Started | Oct 02 10:44:28 PM UTC 24 |
| Finished | Oct 02 10:44:35 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803162282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.803162282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.1169101479 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 130591505351 ps |
| CPU time | 220.55 seconds |
| Started | Oct 02 10:44:31 PM UTC 24 |
| Finished | Oct 02 10:48:15 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169101479 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.1169101479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.799736351 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 3034992408 ps |
| CPU time | 9.11 seconds |
| Started | Oct 02 10:44:28 PM UTC 24 |
| Finished | Oct 02 10:44:38 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799736351 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.799736351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.446866426 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4622513478 ps |
| CPU time | 1.82 seconds |
| Started | Oct 02 10:44:31 PM UTC 24 |
| Finished | Oct 02 10:44:34 PM UTC 24 |
| Peak memory | 209304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446866426 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.446866426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3701170299 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 2616843711 ps |
| CPU time | 6.3 seconds |
| Started | Oct 02 10:44:28 PM UTC 24 |
| Finished | Oct 02 10:44:35 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701170299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3701170299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1452441023 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2479208746 ps |
| CPU time | 4.17 seconds |
| Started | Oct 02 10:44:27 PM UTC 24 |
| Finished | Oct 02 10:44:32 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452441023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1452441023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.3604107457 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2200972347 ps |
| CPU time | 6.33 seconds |
| Started | Oct 02 10:44:27 PM UTC 24 |
| Finished | Oct 02 10:44:34 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604107457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.3604107457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.1650773241 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 2514193686 ps |
| CPU time | 10.88 seconds |
| Started | Oct 02 10:44:28 PM UTC 24 |
| Finished | Oct 02 10:44:40 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650773241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.1650773241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.58282912 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2111684061 ps |
| CPU time | 11.03 seconds |
| Started | Oct 02 10:44:26 PM UTC 24 |
| Finished | Oct 02 10:44:38 PM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58282912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.58282912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.3390970132 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 139044617365 ps |
| CPU time | 244.46 seconds |
| Started | Oct 02 10:44:36 PM UTC 24 |
| Finished | Oct 02 10:48:44 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390970132 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.3390970132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2163550016 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 10286518745 ps |
| CPU time | 7.68 seconds |
| Started | Oct 02 10:44:34 PM UTC 24 |
| Finished | Oct 02 10:44:43 PM UTC 24 |
| Peak memory | 228188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2163550016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.2163550016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.340614073 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 5351068272 ps |
| CPU time | 7.54 seconds |
| Started | Oct 02 10:44:31 PM UTC 24 |
| Finished | Oct 02 10:44:39 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340614073 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.340614073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.478268546 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2031765275 ps |
| CPU time | 3.74 seconds |
| Started | Oct 02 10:44:49 PM UTC 24 |
| Finished | Oct 02 10:44:54 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478268546 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.478268546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3033411261 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 3529132380 ps |
| CPU time | 5.19 seconds |
| Started | Oct 02 10:44:42 PM UTC 24 |
| Finished | Oct 02 10:44:48 PM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033411261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.3033411261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3197092974 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1247897445809 ps |
| CPU time | 1760.56 seconds |
| Started | Oct 02 10:44:40 PM UTC 24 |
| Finished | Oct 02 11:14:18 PM UTC 24 |
| Peak memory | 213328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197092974 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.3197092974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.532216451 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3210455078 ps |
| CPU time | 4.69 seconds |
| Started | Oct 02 10:44:43 PM UTC 24 |
| Finished | Oct 02 10:44:49 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532216451 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.532216451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.879101660 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2613433108 ps |
| CPU time | 14.4 seconds |
| Started | Oct 02 10:44:40 PM UTC 24 |
| Finished | Oct 02 10:44:55 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879101660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.879101660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.419775050 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2479621199 ps |
| CPU time | 3.54 seconds |
| Started | Oct 02 10:44:36 PM UTC 24 |
| Finished | Oct 02 10:44:41 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419775050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.419775050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.1462823565 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2041732992 ps |
| CPU time | 5.39 seconds |
| Started | Oct 02 10:44:36 PM UTC 24 |
| Finished | Oct 02 10:44:43 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462823565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.1462823565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.348639011 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2513593618 ps |
| CPU time | 13.06 seconds |
| Started | Oct 02 10:44:40 PM UTC 24 |
| Finished | Oct 02 10:44:54 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348639011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.348639011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.2553169391 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2109540271 ps |
| CPU time | 10.65 seconds |
| Started | Oct 02 10:44:36 PM UTC 24 |
| Finished | Oct 02 10:44:48 PM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553169391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.2553169391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2428860363 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 7258663596 ps |
| CPU time | 19.61 seconds |
| Started | Oct 02 10:44:44 PM UTC 24 |
| Finished | Oct 02 10:45:05 PM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2428860363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.2428860363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.38231979 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 8113947806 ps |
| CPU time | 4.92 seconds |
| Started | Oct 02 10:44:42 PM UTC 24 |
| Finished | Oct 02 10:44:48 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38231979 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.38231979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2060623028 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2023800088 ps |
| CPU time | 3.61 seconds |
| Started | Oct 02 10:45:04 PM UTC 24 |
| Finished | Oct 02 10:45:08 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060623028 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.2060623028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3068924988 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 3147970683 ps |
| CPU time | 4.45 seconds |
| Started | Oct 02 10:44:55 PM UTC 24 |
| Finished | Oct 02 10:45:00 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068924988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.3068924988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.4233794464 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 155766895055 ps |
| CPU time | 127.28 seconds |
| Started | Oct 02 10:44:56 PM UTC 24 |
| Finished | Oct 02 10:47:06 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233794464 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.4233794464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3346403623 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 63889478445 ps |
| CPU time | 83.42 seconds |
| Started | Oct 02 10:44:57 PM UTC 24 |
| Finished | Oct 02 10:46:22 PM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346403623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_with_pre_cond.3346403623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2161685289 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 4190106606 ps |
| CPU time | 5.94 seconds |
| Started | Oct 02 10:44:55 PM UTC 24 |
| Finished | Oct 02 10:45:02 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161685289 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.2161685289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3027469736 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3815979199 ps |
| CPU time | 7.8 seconds |
| Started | Oct 02 10:44:57 PM UTC 24 |
| Finished | Oct 02 10:45:06 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027469736 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.3027469736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.4150343776 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2623528254 ps |
| CPU time | 3.99 seconds |
| Started | Oct 02 10:44:52 PM UTC 24 |
| Finished | Oct 02 10:44:57 PM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150343776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.4150343776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.625413556 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2462733739 ps |
| CPU time | 13.45 seconds |
| Started | Oct 02 10:44:49 PM UTC 24 |
| Finished | Oct 02 10:45:04 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625413556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.625413556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.3826103480 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2247052564 ps |
| CPU time | 3.46 seconds |
| Started | Oct 02 10:44:51 PM UTC 24 |
| Finished | Oct 02 10:44:55 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826103480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.3826103480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.4076707545 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2510181633 ps |
| CPU time | 12.71 seconds |
| Started | Oct 02 10:44:51 PM UTC 24 |
| Finished | Oct 02 10:45:04 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076707545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.4076707545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.777653345 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2116602500 ps |
| CPU time | 5.86 seconds |
| Started | Oct 02 10:44:49 PM UTC 24 |
| Finished | Oct 02 10:44:56 PM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777653345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.777653345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.192108700 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 97616127475 ps |
| CPU time | 260.53 seconds |
| Started | Oct 02 10:45:02 PM UTC 24 |
| Finished | Oct 02 10:49:27 PM UTC 24 |
| Peak memory | 212028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192108700 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.192108700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1712577370 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 9928294808 ps |
| CPU time | 20.91 seconds |
| Started | Oct 02 10:45:01 PM UTC 24 |
| Finished | Oct 02 10:45:24 PM UTC 24 |
| Peak memory | 222412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1712577370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.1712577370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2477596756 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2023554583463 ps |
| CPU time | 526.53 seconds |
| Started | Oct 02 10:44:56 PM UTC 24 |
| Finished | Oct 02 10:53:48 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477596756 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.2477596756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.2726517283 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 2026189215 ps |
| CPU time | 3.3 seconds |
| Started | Oct 02 10:45:18 PM UTC 24 |
| Finished | Oct 02 10:45:22 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726517283 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.2726517283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1152370856 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3457846733 ps |
| CPU time | 16.56 seconds |
| Started | Oct 02 10:45:08 PM UTC 24 |
| Finished | Oct 02 10:45:26 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152370856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.1152370856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.1625224489 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 60856202812 ps |
| CPU time | 178.03 seconds |
| Started | Oct 02 10:45:10 PM UTC 24 |
| Finished | Oct 02 10:48:11 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625224489 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.1625224489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.4109093540 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 33245280334 ps |
| CPU time | 46.93 seconds |
| Started | Oct 02 10:45:12 PM UTC 24 |
| Finished | Oct 02 10:46:00 PM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109093540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_with_pre_cond.4109093540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.3978907343 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 4577921073 ps |
| CPU time | 23.12 seconds |
| Started | Oct 02 10:45:07 PM UTC 24 |
| Finished | Oct 02 10:45:31 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978907343 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.3978907343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.428268398 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4127634073 ps |
| CPU time | 11.17 seconds |
| Started | Oct 02 10:45:11 PM UTC 24 |
| Finished | Oct 02 10:45:24 PM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428268398 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.428268398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2591877408 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2611026670 ps |
| CPU time | 14.74 seconds |
| Started | Oct 02 10:45:06 PM UTC 24 |
| Finished | Oct 02 10:45:22 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591877408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.2591877408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.543357903 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2483838147 ps |
| CPU time | 4.1 seconds |
| Started | Oct 02 10:45:05 PM UTC 24 |
| Finished | Oct 02 10:45:10 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543357903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.543357903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1439173598 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 2098527091 ps |
| CPU time | 7.12 seconds |
| Started | Oct 02 10:45:06 PM UTC 24 |
| Finished | Oct 02 10:45:14 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439173598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.1439173598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.2778277760 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2530472017 ps |
| CPU time | 4.17 seconds |
| Started | Oct 02 10:45:06 PM UTC 24 |
| Finished | Oct 02 10:45:11 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778277760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.2778277760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.1312383206 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2111839440 ps |
| CPU time | 11.02 seconds |
| Started | Oct 02 10:45:05 PM UTC 24 |
| Finished | Oct 02 10:45:17 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312383206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.1312383206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.2216522327 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 6653210796 ps |
| CPU time | 11.47 seconds |
| Started | Oct 02 10:45:16 PM UTC 24 |
| Finished | Oct 02 10:45:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216522327 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.2216522327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1061356195 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 6601451988 ps |
| CPU time | 19.88 seconds |
| Started | Oct 02 10:45:15 PM UTC 24 |
| Finished | Oct 02 10:45:36 PM UTC 24 |
| Peak memory | 222356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1061356195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.1061356195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2789835166 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 4128557550 ps |
| CPU time | 13.43 seconds |
| Started | Oct 02 10:45:09 PM UTC 24 |
| Finished | Oct 02 10:45:24 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789835166 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.2789835166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.2957906683 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2022790325 ps |
| CPU time | 7.41 seconds |
| Started | Oct 02 10:41:30 PM UTC 24 |
| Finished | Oct 02 10:41:39 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957906683 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.2957906683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.2511088625 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 232296487183 ps |
| CPU time | 216.26 seconds |
| Started | Oct 02 10:41:24 PM UTC 24 |
| Finished | Oct 02 10:45:03 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511088625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.2511088625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3096697675 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 95080953167 ps |
| CPU time | 159.2 seconds |
| Started | Oct 02 10:41:28 PM UTC 24 |
| Finished | Oct 02 10:44:10 PM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096697675 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.3096697675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.562734002 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2429356740 ps |
| CPU time | 5.48 seconds |
| Started | Oct 02 10:41:21 PM UTC 24 |
| Finished | Oct 02 10:41:28 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562734002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.562734002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3160440453 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2353274685 ps |
| CPU time | 7.15 seconds |
| Started | Oct 02 10:41:21 PM UTC 24 |
| Finished | Oct 02 10:41:30 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160440453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3160440453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2419297472 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3389588650 ps |
| CPU time | 9.11 seconds |
| Started | Oct 02 10:41:24 PM UTC 24 |
| Finished | Oct 02 10:41:34 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419297472 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.2419297472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2669114773 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3162183171 ps |
| CPU time | 4.44 seconds |
| Started | Oct 02 10:41:28 PM UTC 24 |
| Finished | Oct 02 10:41:34 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669114773 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.2669114773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.715580952 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2661817519 ps |
| CPU time | 3.06 seconds |
| Started | Oct 02 10:41:23 PM UTC 24 |
| Finished | Oct 02 10:41:27 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715580952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.715580952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.2404165031 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2469073498 ps |
| CPU time | 6.75 seconds |
| Started | Oct 02 10:41:20 PM UTC 24 |
| Finished | Oct 02 10:41:28 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404165031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.2404165031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2883057488 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2174024041 ps |
| CPU time | 2.91 seconds |
| Started | Oct 02 10:41:21 PM UTC 24 |
| Finished | Oct 02 10:41:26 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883057488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2883057488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.1552913687 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 22051824035 ps |
| CPU time | 30.02 seconds |
| Started | Oct 02 10:41:29 PM UTC 24 |
| Finished | Oct 02 10:42:01 PM UTC 24 |
| Peak memory | 243560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552913687 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.1552913687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.3323650522 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2115974589 ps |
| CPU time | 6.56 seconds |
| Started | Oct 02 10:41:19 PM UTC 24 |
| Finished | Oct 02 10:41:27 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323650522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.3323650522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.719963926 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 7812453263 ps |
| CPU time | 28.69 seconds |
| Started | Oct 02 10:41:29 PM UTC 24 |
| Finished | Oct 02 10:41:59 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719963926 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.719963926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2443233336 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 5359399424 ps |
| CPU time | 9.42 seconds |
| Started | Oct 02 10:41:29 PM UTC 24 |
| Finished | Oct 02 10:41:40 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2443233336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.2443233336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1183060916 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3914280099 ps |
| CPU time | 3.55 seconds |
| Started | Oct 02 10:41:27 PM UTC 24 |
| Finished | Oct 02 10:41:31 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183060916 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.1183060916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.3161526793 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2011636591 ps |
| CPU time | 6.61 seconds |
| Started | Oct 02 10:45:32 PM UTC 24 |
| Finished | Oct 02 10:45:40 PM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161526793 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.3161526793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1568378844 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3801004994 ps |
| CPU time | 4.65 seconds |
| Started | Oct 02 10:45:26 PM UTC 24 |
| Finished | Oct 02 10:45:32 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568378844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.1568378844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.3063250555 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 52459682340 ps |
| CPU time | 74.47 seconds |
| Started | Oct 02 10:45:29 PM UTC 24 |
| Finished | Oct 02 10:46:45 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063250555 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.3063250555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3562230125 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 40332338044 ps |
| CPU time | 137.75 seconds |
| Started | Oct 02 10:45:31 PM UTC 24 |
| Finished | Oct 02 10:47:51 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562230125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_with_pre_cond.3562230125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3781645362 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 4863914197 ps |
| CPU time | 6.19 seconds |
| Started | Oct 02 10:45:24 PM UTC 24 |
| Finished | Oct 02 10:45:32 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781645362 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.3781645362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.1757911374 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2537122973 ps |
| CPU time | 3.51 seconds |
| Started | Oct 02 10:45:30 PM UTC 24 |
| Finished | Oct 02 10:45:34 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757911374 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.1757911374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.661307306 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 2607622978 ps |
| CPU time | 12.25 seconds |
| Started | Oct 02 10:45:24 PM UTC 24 |
| Finished | Oct 02 10:45:38 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661307306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.661307306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.35405453 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2492679042 ps |
| CPU time | 11.28 seconds |
| Started | Oct 02 10:45:23 PM UTC 24 |
| Finished | Oct 02 10:45:35 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35405453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.35405453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.985117880 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2260293381 ps |
| CPU time | 1.67 seconds |
| Started | Oct 02 10:45:23 PM UTC 24 |
| Finished | Oct 02 10:45:26 PM UTC 24 |
| Peak memory | 211776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985117880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.985117880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.944154579 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2516302459 ps |
| CPU time | 6.81 seconds |
| Started | Oct 02 10:45:24 PM UTC 24 |
| Finished | Oct 02 10:45:32 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944154579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.944154579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.3140826484 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 2116596605 ps |
| CPU time | 8.36 seconds |
| Started | Oct 02 10:45:21 PM UTC 24 |
| Finished | Oct 02 10:45:30 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140826484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.3140826484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.947605909 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 277582933411 ps |
| CPU time | 202.05 seconds |
| Started | Oct 02 10:45:32 PM UTC 24 |
| Finished | Oct 02 10:48:57 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947605909 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.947605909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1177075888 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 6439401564 ps |
| CPU time | 13.15 seconds |
| Started | Oct 02 10:45:32 PM UTC 24 |
| Finished | Oct 02 10:45:46 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1177075888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1177075888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.1614950024 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 2034838002 ps |
| CPU time | 4.07 seconds |
| Started | Oct 02 10:45:43 PM UTC 24 |
| Finished | Oct 02 10:45:49 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614950024 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.1614950024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3371245374 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 3527525102 ps |
| CPU time | 1.94 seconds |
| Started | Oct 02 10:45:37 PM UTC 24 |
| Finished | Oct 02 10:45:39 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371245374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3371245374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.963236097 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 172547733156 ps |
| CPU time | 549.89 seconds |
| Started | Oct 02 10:45:39 PM UTC 24 |
| Finished | Oct 02 10:54:55 PM UTC 24 |
| Peak memory | 211856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963236097 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.963236097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.1715470083 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 27083182965 ps |
| CPU time | 92.88 seconds |
| Started | Oct 02 10:45:40 PM UTC 24 |
| Finished | Oct 02 10:47:15 PM UTC 24 |
| Peak memory | 211924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715470083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_with_pre_cond.1715470083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3847727501 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2799823305 ps |
| CPU time | 12.14 seconds |
| Started | Oct 02 10:45:37 PM UTC 24 |
| Finished | Oct 02 10:45:50 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847727501 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.3847727501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.2994926920 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3629068086 ps |
| CPU time | 9.64 seconds |
| Started | Oct 02 10:45:40 PM UTC 24 |
| Finished | Oct 02 10:45:51 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994926920 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.2994926920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2125356740 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2621411880 ps |
| CPU time | 4.25 seconds |
| Started | Oct 02 10:45:37 PM UTC 24 |
| Finished | Oct 02 10:45:42 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125356740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2125356740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.3742704214 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2506179774 ps |
| CPU time | 3.81 seconds |
| Started | Oct 02 10:45:33 PM UTC 24 |
| Finished | Oct 02 10:45:38 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742704214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.3742704214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.942801826 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2081692797 ps |
| CPU time | 5.16 seconds |
| Started | Oct 02 10:45:35 PM UTC 24 |
| Finished | Oct 02 10:45:42 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942801826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.942801826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.1953753824 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2512948890 ps |
| CPU time | 9.25 seconds |
| Started | Oct 02 10:45:36 PM UTC 24 |
| Finished | Oct 02 10:45:47 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953753824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.1953753824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.4173688661 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 2108997248 ps |
| CPU time | 10.99 seconds |
| Started | Oct 02 10:45:33 PM UTC 24 |
| Finished | Oct 02 10:45:45 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173688661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.4173688661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2507277305 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 17243524961 ps |
| CPU time | 16.77 seconds |
| Started | Oct 02 10:45:43 PM UTC 24 |
| Finished | Oct 02 10:46:01 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507277305 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.2507277305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.2169656164 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2031167690 ps |
| CPU time | 2.52 seconds |
| Started | Oct 02 10:45:55 PM UTC 24 |
| Finished | Oct 02 10:45:58 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169656164 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.2169656164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3519209550 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 3932134222 ps |
| CPU time | 16.91 seconds |
| Started | Oct 02 10:45:50 PM UTC 24 |
| Finished | Oct 02 10:46:08 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519209550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.3519209550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.2924886216 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 172943518981 ps |
| CPU time | 123.88 seconds |
| Started | Oct 02 10:45:51 PM UTC 24 |
| Finished | Oct 02 10:47:57 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924886216 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.2924886216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1708555299 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 4634956516 ps |
| CPU time | 11.62 seconds |
| Started | Oct 02 10:45:49 PM UTC 24 |
| Finished | Oct 02 10:46:02 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708555299 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.1708555299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.3456355800 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3238238480 ps |
| CPU time | 4.58 seconds |
| Started | Oct 02 10:45:51 PM UTC 24 |
| Finished | Oct 02 10:45:57 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456355800 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.3456355800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.812609797 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 2608456540 ps |
| CPU time | 12.69 seconds |
| Started | Oct 02 10:45:48 PM UTC 24 |
| Finished | Oct 02 10:46:02 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812609797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.812609797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.3338572669 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 2514451942 ps |
| CPU time | 2.74 seconds |
| Started | Oct 02 10:45:46 PM UTC 24 |
| Finished | Oct 02 10:45:51 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338572669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3338572669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.3145693337 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2241200940 ps |
| CPU time | 3.19 seconds |
| Started | Oct 02 10:45:48 PM UTC 24 |
| Finished | Oct 02 10:45:52 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145693337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.3145693337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.506753496 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2512546748 ps |
| CPU time | 13.61 seconds |
| Started | Oct 02 10:45:48 PM UTC 24 |
| Finished | Oct 02 10:46:03 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506753496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.506753496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.4105490722 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2132920717 ps |
| CPU time | 2.33 seconds |
| Started | Oct 02 10:45:44 PM UTC 24 |
| Finished | Oct 02 10:45:48 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105490722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.4105490722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.829984966 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 651248425073 ps |
| CPU time | 33.91 seconds |
| Started | Oct 02 10:45:53 PM UTC 24 |
| Finished | Oct 02 10:46:29 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829984966 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.829984966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3069621543 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 5294220233 ps |
| CPU time | 14.09 seconds |
| Started | Oct 02 10:45:53 PM UTC 24 |
| Finished | Oct 02 10:46:09 PM UTC 24 |
| Peak memory | 222372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3069621543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.3069621543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.633637238 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 9315501986 ps |
| CPU time | 6.73 seconds |
| Started | Oct 02 10:45:51 PM UTC 24 |
| Finished | Oct 02 10:45:59 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633637238 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.633637238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.3350860040 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2075041737 ps |
| CPU time | 2.03 seconds |
| Started | Oct 02 10:46:08 PM UTC 24 |
| Finished | Oct 02 10:46:11 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350860040 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.3350860040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3882226126 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 100471351627 ps |
| CPU time | 341.59 seconds |
| Started | Oct 02 10:46:03 PM UTC 24 |
| Finished | Oct 02 10:51:49 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882226126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.3882226126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.3354534522 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 81294561331 ps |
| CPU time | 55.25 seconds |
| Started | Oct 02 10:46:04 PM UTC 24 |
| Finished | Oct 02 10:47:01 PM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354534522 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.3354534522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.822531715 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 171962424823 ps |
| CPU time | 489.76 seconds |
| Started | Oct 02 10:46:06 PM UTC 24 |
| Finished | Oct 02 10:54:21 PM UTC 24 |
| Peak memory | 211928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822531715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_with_pre_cond.822531715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1600118602 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 4921735694 ps |
| CPU time | 11.53 seconds |
| Started | Oct 02 10:46:03 PM UTC 24 |
| Finished | Oct 02 10:46:16 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600118602 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.1600118602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.4197066492 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3720178924 ps |
| CPU time | 2.96 seconds |
| Started | Oct 02 10:46:05 PM UTC 24 |
| Finished | Oct 02 10:46:10 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197066492 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.4197066492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3185546187 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2612269225 ps |
| CPU time | 7.43 seconds |
| Started | Oct 02 10:46:02 PM UTC 24 |
| Finished | Oct 02 10:46:11 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185546187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3185546187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.1951092418 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2485171122 ps |
| CPU time | 6.48 seconds |
| Started | Oct 02 10:45:59 PM UTC 24 |
| Finished | Oct 02 10:46:06 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951092418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.1951092418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2440268590 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 2241480085 ps |
| CPU time | 3.36 seconds |
| Started | Oct 02 10:46:00 PM UTC 24 |
| Finished | Oct 02 10:46:04 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440268590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.2440268590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.3401610780 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2530590525 ps |
| CPU time | 3.49 seconds |
| Started | Oct 02 10:46:01 PM UTC 24 |
| Finished | Oct 02 10:46:06 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401610780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.3401610780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.2144915546 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2132313306 ps |
| CPU time | 3.41 seconds |
| Started | Oct 02 10:45:58 PM UTC 24 |
| Finished | Oct 02 10:46:02 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144915546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.2144915546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3352552345 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 10516222159 ps |
| CPU time | 39.72 seconds |
| Started | Oct 02 10:46:07 PM UTC 24 |
| Finished | Oct 02 10:46:48 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352552345 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.3352552345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3864624488 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 3132028393 ps |
| CPU time | 8.98 seconds |
| Started | Oct 02 10:46:07 PM UTC 24 |
| Finished | Oct 02 10:46:17 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3864624488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.3864624488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.4041362937 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 644626034476 ps |
| CPU time | 30.68 seconds |
| Started | Oct 02 10:46:03 PM UTC 24 |
| Finished | Oct 02 10:46:35 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041362937 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.4041362937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.657611228 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2026825310 ps |
| CPU time | 2.93 seconds |
| Started | Oct 02 10:46:21 PM UTC 24 |
| Finished | Oct 02 10:46:25 PM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657611228 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.657611228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3321930571 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 3133713308 ps |
| CPU time | 4.35 seconds |
| Started | Oct 02 10:46:15 PM UTC 24 |
| Finished | Oct 02 10:46:21 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321930571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.3321930571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.2534748910 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 149099923672 ps |
| CPU time | 194.04 seconds |
| Started | Oct 02 10:46:17 PM UTC 24 |
| Finished | Oct 02 10:49:33 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534748910 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.2534748910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1938142961 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 68527172532 ps |
| CPU time | 60.75 seconds |
| Started | Oct 02 10:46:18 PM UTC 24 |
| Finished | Oct 02 10:47:20 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938142961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_with_pre_cond.1938142961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2233316220 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 5309828816 ps |
| CPU time | 4.68 seconds |
| Started | Oct 02 10:46:14 PM UTC 24 |
| Finished | Oct 02 10:46:20 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233316220 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.2233316220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.263150602 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3090646961 ps |
| CPU time | 4.88 seconds |
| Started | Oct 02 10:46:17 PM UTC 24 |
| Finished | Oct 02 10:46:23 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263150602 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.263150602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.2299411445 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2642541088 ps |
| CPU time | 3.65 seconds |
| Started | Oct 02 10:46:11 PM UTC 24 |
| Finished | Oct 02 10:46:16 PM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299411445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.2299411445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.3472371533 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2474896944 ps |
| CPU time | 3.86 seconds |
| Started | Oct 02 10:46:09 PM UTC 24 |
| Finished | Oct 02 10:46:14 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472371533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.3472371533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.4192326003 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2034770734 ps |
| CPU time | 5.7 seconds |
| Started | Oct 02 10:46:10 PM UTC 24 |
| Finished | Oct 02 10:46:17 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192326003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.4192326003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.2923578902 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2534471686 ps |
| CPU time | 2.88 seconds |
| Started | Oct 02 10:46:11 PM UTC 24 |
| Finished | Oct 02 10:46:15 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923578902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.2923578902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.736866331 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2115191498 ps |
| CPU time | 5.22 seconds |
| Started | Oct 02 10:46:09 PM UTC 24 |
| Finished | Oct 02 10:46:15 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736866331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.736866331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.3958129368 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 10165563648 ps |
| CPU time | 10.8 seconds |
| Started | Oct 02 10:46:20 PM UTC 24 |
| Finished | Oct 02 10:46:32 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958129368 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.3958129368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1647724150 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5456391946 ps |
| CPU time | 19.08 seconds |
| Started | Oct 02 10:46:18 PM UTC 24 |
| Finished | Oct 02 10:46:38 PM UTC 24 |
| Peak memory | 222164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1647724150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.1647724150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3208263524 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 4494596169 ps |
| CPU time | 4.39 seconds |
| Started | Oct 02 10:46:17 PM UTC 24 |
| Finished | Oct 02 10:46:22 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208263524 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.3208263524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.2717995615 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 2015717865 ps |
| CPU time | 8.9 seconds |
| Started | Oct 02 10:46:36 PM UTC 24 |
| Finished | Oct 02 10:46:46 PM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717995615 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.2717995615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3539981024 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 3283632082 ps |
| CPU time | 11.14 seconds |
| Started | Oct 02 10:46:27 PM UTC 24 |
| Finished | Oct 02 10:46:39 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539981024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.3539981024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.3003072135 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 83374849022 ps |
| CPU time | 80.65 seconds |
| Started | Oct 02 10:46:30 PM UTC 24 |
| Finished | Oct 02 10:47:52 PM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003072135 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.3003072135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2963197703 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 26583741892 ps |
| CPU time | 44.32 seconds |
| Started | Oct 02 10:46:31 PM UTC 24 |
| Finished | Oct 02 10:47:17 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963197703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_with_pre_cond.2963197703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.283326891 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 3982604526 ps |
| CPU time | 3.98 seconds |
| Started | Oct 02 10:46:26 PM UTC 24 |
| Finished | Oct 02 10:46:31 PM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283326891 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.283326891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2983480734 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5675508201 ps |
| CPU time | 19.96 seconds |
| Started | Oct 02 10:46:30 PM UTC 24 |
| Finished | Oct 02 10:46:51 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983480734 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.2983480734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2362221243 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2650717968 ps |
| CPU time | 3.21 seconds |
| Started | Oct 02 10:46:26 PM UTC 24 |
| Finished | Oct 02 10:46:30 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362221243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2362221243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.4110888825 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2491141300 ps |
| CPU time | 1.97 seconds |
| Started | Oct 02 10:46:23 PM UTC 24 |
| Finished | Oct 02 10:46:26 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110888825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.4110888825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.2153694390 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 2322638795 ps |
| CPU time | 1.54 seconds |
| Started | Oct 02 10:46:23 PM UTC 24 |
| Finished | Oct 02 10:46:26 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153694390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.2153694390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.1502421218 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 2511058897 ps |
| CPU time | 14.88 seconds |
| Started | Oct 02 10:46:23 PM UTC 24 |
| Finished | Oct 02 10:46:39 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502421218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1502421218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.51736715 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2118452116 ps |
| CPU time | 5.79 seconds |
| Started | Oct 02 10:46:22 PM UTC 24 |
| Finished | Oct 02 10:46:29 PM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51736715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.51736715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.3177094971 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 7734811948 ps |
| CPU time | 3.88 seconds |
| Started | Oct 02 10:46:33 PM UTC 24 |
| Finished | Oct 02 10:46:38 PM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177094971 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.3177094971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3970989452 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 5714680669 ps |
| CPU time | 19.75 seconds |
| Started | Oct 02 10:46:31 PM UTC 24 |
| Finished | Oct 02 10:46:52 PM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3970989452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.3970989452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2517596538 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1723220530235 ps |
| CPU time | 135.34 seconds |
| Started | Oct 02 10:46:27 PM UTC 24 |
| Finished | Oct 02 10:48:44 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517596538 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.2517596538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.3957289877 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2045202104 ps |
| CPU time | 3.66 seconds |
| Started | Oct 02 10:46:48 PM UTC 24 |
| Finished | Oct 02 10:46:52 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957289877 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.3957289877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3413328002 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 3470619352 ps |
| CPU time | 9.85 seconds |
| Started | Oct 02 10:46:42 PM UTC 24 |
| Finished | Oct 02 10:46:53 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413328002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3413328002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.1969156960 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 52159784391 ps |
| CPU time | 45.46 seconds |
| Started | Oct 02 10:46:44 PM UTC 24 |
| Finished | Oct 02 10:47:31 PM UTC 24 |
| Peak memory | 211824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969156960 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.1969156960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3569076661 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 34919264828 ps |
| CPU time | 129.65 seconds |
| Started | Oct 02 10:46:45 PM UTC 24 |
| Finished | Oct 02 10:48:57 PM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569076661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_with_pre_cond.3569076661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.4144943205 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 3293450645 ps |
| CPU time | 1.94 seconds |
| Started | Oct 02 10:46:41 PM UTC 24 |
| Finished | Oct 02 10:46:44 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144943205 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.4144943205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.3117859657 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2617469831 ps |
| CPU time | 4.39 seconds |
| Started | Oct 02 10:46:40 PM UTC 24 |
| Finished | Oct 02 10:46:45 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117859657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.3117859657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.843241392 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2461700246 ps |
| CPU time | 13.39 seconds |
| Started | Oct 02 10:46:39 PM UTC 24 |
| Finished | Oct 02 10:46:53 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843241392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.843241392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.1875832786 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2155604627 ps |
| CPU time | 1.52 seconds |
| Started | Oct 02 10:46:39 PM UTC 24 |
| Finished | Oct 02 10:46:41 PM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875832786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1875832786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.2378052305 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2519248125 ps |
| CPU time | 4.43 seconds |
| Started | Oct 02 10:46:39 PM UTC 24 |
| Finished | Oct 02 10:46:44 PM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378052305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.2378052305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.663360597 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2139363663 ps |
| CPU time | 2.66 seconds |
| Started | Oct 02 10:46:37 PM UTC 24 |
| Finished | Oct 02 10:46:41 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663360597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.663360597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.2929245474 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 8302631677 ps |
| CPU time | 6.25 seconds |
| Started | Oct 02 10:46:46 PM UTC 24 |
| Finished | Oct 02 10:46:54 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929245474 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.2929245474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2115748852 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 10400151490 ps |
| CPU time | 7.27 seconds |
| Started | Oct 02 10:46:46 PM UTC 24 |
| Finished | Oct 02 10:46:55 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2115748852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2115748852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1936223833 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1802642782627 ps |
| CPU time | 141.12 seconds |
| Started | Oct 02 10:46:42 PM UTC 24 |
| Finished | Oct 02 10:49:05 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936223833 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.1936223833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.172190827 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2046864397 ps |
| CPU time | 1.85 seconds |
| Started | Oct 02 10:47:01 PM UTC 24 |
| Finished | Oct 02 10:47:04 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172190827 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.172190827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3829210294 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3103438370 ps |
| CPU time | 15.57 seconds |
| Started | Oct 02 10:46:54 PM UTC 24 |
| Finished | Oct 02 10:47:11 PM UTC 24 |
| Peak memory | 211780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829210294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.3829210294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.986116300 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 163872024211 ps |
| CPU time | 450.8 seconds |
| Started | Oct 02 10:46:55 PM UTC 24 |
| Finished | Oct 02 10:54:32 PM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986116300 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.986116300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1230250734 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2724824726 ps |
| CPU time | 13.04 seconds |
| Started | Oct 02 10:46:54 PM UTC 24 |
| Finished | Oct 02 10:47:08 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230250734 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.1230250734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3218147814 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2619819839 ps |
| CPU time | 6.38 seconds |
| Started | Oct 02 10:46:53 PM UTC 24 |
| Finished | Oct 02 10:47:00 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218147814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3218147814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.2735720352 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 2465579630 ps |
| CPU time | 6.49 seconds |
| Started | Oct 02 10:46:52 PM UTC 24 |
| Finished | Oct 02 10:46:59 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735720352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.2735720352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3565908923 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 2050484335 ps |
| CPU time | 2.92 seconds |
| Started | Oct 02 10:46:53 PM UTC 24 |
| Finished | Oct 02 10:46:57 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565908923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3565908923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.2228113255 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2516732674 ps |
| CPU time | 7.33 seconds |
| Started | Oct 02 10:46:53 PM UTC 24 |
| Finished | Oct 02 10:47:01 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228113255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.2228113255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.4008369401 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2154167170 ps |
| CPU time | 2.2 seconds |
| Started | Oct 02 10:46:49 PM UTC 24 |
| Finished | Oct 02 10:46:52 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008369401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.4008369401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.378706005 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 235328445100 ps |
| CPU time | 129.41 seconds |
| Started | Oct 02 10:47:01 PM UTC 24 |
| Finished | Oct 02 10:49:12 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378706005 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.378706005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1190093903 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 8168412677 ps |
| CPU time | 12.23 seconds |
| Started | Oct 02 10:47:00 PM UTC 24 |
| Finished | Oct 02 10:47:13 PM UTC 24 |
| Peak memory | 227868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1190093903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.1190093903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.4173497617 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 4948504712 ps |
| CPU time | 9 seconds |
| Started | Oct 02 10:46:55 PM UTC 24 |
| Finished | Oct 02 10:47:05 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173497617 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.4173497617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.2856662930 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 2025734266 ps |
| CPU time | 3.18 seconds |
| Started | Oct 02 10:47:11 PM UTC 24 |
| Finished | Oct 02 10:47:16 PM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856662930 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.2856662930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3963265079 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3899209320 ps |
| CPU time | 1.96 seconds |
| Started | Oct 02 10:47:07 PM UTC 24 |
| Finished | Oct 02 10:47:10 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963265079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.3963265079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.3432402476 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 93857130816 ps |
| CPU time | 83.58 seconds |
| Started | Oct 02 10:47:07 PM UTC 24 |
| Finished | Oct 02 10:48:32 PM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432402476 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.3432402476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.1916834520 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3109946613 ps |
| CPU time | 14.6 seconds |
| Started | Oct 02 10:47:08 PM UTC 24 |
| Finished | Oct 02 10:47:23 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916834520 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.1916834520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3894179008 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2626466714 ps |
| CPU time | 3.96 seconds |
| Started | Oct 02 10:47:04 PM UTC 24 |
| Finished | Oct 02 10:47:09 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894179008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.3894179008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.653982119 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 2476948151 ps |
| CPU time | 2.79 seconds |
| Started | Oct 02 10:47:02 PM UTC 24 |
| Finished | Oct 02 10:47:06 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653982119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.653982119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.2164059458 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2129388138 ps |
| CPU time | 6.7 seconds |
| Started | Oct 02 10:47:04 PM UTC 24 |
| Finished | Oct 02 10:47:12 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164059458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.2164059458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.795122045 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2536014035 ps |
| CPU time | 3.38 seconds |
| Started | Oct 02 10:47:04 PM UTC 24 |
| Finished | Oct 02 10:47:09 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795122045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.795122045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.3528788337 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2107924271 ps |
| CPU time | 9.63 seconds |
| Started | Oct 02 10:47:02 PM UTC 24 |
| Finished | Oct 02 10:47:13 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528788337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.3528788337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.4169553137 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 122073270161 ps |
| CPU time | 69.8 seconds |
| Started | Oct 02 10:47:10 PM UTC 24 |
| Finished | Oct 02 10:48:22 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169553137 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.4169553137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2903492769 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 6685851999 ps |
| CPU time | 7.93 seconds |
| Started | Oct 02 10:47:10 PM UTC 24 |
| Finished | Oct 02 10:47:19 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2903492769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.2903492769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1299244555 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 6438558965 ps |
| CPU time | 3.64 seconds |
| Started | Oct 02 10:47:07 PM UTC 24 |
| Finished | Oct 02 10:47:11 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299244555 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.1299244555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.1930208940 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2068572660 ps |
| CPU time | 1.87 seconds |
| Started | Oct 02 10:47:21 PM UTC 24 |
| Finished | Oct 02 10:47:24 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930208940 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.1930208940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.560239851 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 22894419478 ps |
| CPU time | 41.57 seconds |
| Started | Oct 02 10:47:15 PM UTC 24 |
| Finished | Oct 02 10:47:58 PM UTC 24 |
| Peak memory | 211844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560239851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.560239851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.3503445524 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 135067522369 ps |
| CPU time | 129.61 seconds |
| Started | Oct 02 10:47:17 PM UTC 24 |
| Finished | Oct 02 10:49:29 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503445524 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.3503445524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.420811338 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 392142642732 ps |
| CPU time | 1097.52 seconds |
| Started | Oct 02 10:47:15 PM UTC 24 |
| Finished | Oct 02 11:05:44 PM UTC 24 |
| Peak memory | 213140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420811338 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.420811338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.3842557939 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2857168159 ps |
| CPU time | 2.63 seconds |
| Started | Oct 02 10:47:17 PM UTC 24 |
| Finished | Oct 02 10:47:21 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842557939 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.3842557939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3729679111 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2619735887 ps |
| CPU time | 6.68 seconds |
| Started | Oct 02 10:47:14 PM UTC 24 |
| Finished | Oct 02 10:47:22 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729679111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.3729679111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.2711873439 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2470732002 ps |
| CPU time | 4.06 seconds |
| Started | Oct 02 10:47:12 PM UTC 24 |
| Finished | Oct 02 10:47:18 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711873439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.2711873439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2571729552 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2117672609 ps |
| CPU time | 9.39 seconds |
| Started | Oct 02 10:47:12 PM UTC 24 |
| Finished | Oct 02 10:47:23 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571729552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2571729552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.1285890819 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2512881600 ps |
| CPU time | 10.71 seconds |
| Started | Oct 02 10:47:13 PM UTC 24 |
| Finished | Oct 02 10:47:26 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285890819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1285890819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.2438796189 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2114590739 ps |
| CPU time | 3.97 seconds |
| Started | Oct 02 10:47:11 PM UTC 24 |
| Finished | Oct 02 10:47:16 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438796189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.2438796189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.3787557857 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 13676888616 ps |
| CPU time | 8.25 seconds |
| Started | Oct 02 10:47:20 PM UTC 24 |
| Finished | Oct 02 10:47:30 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787557857 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.3787557857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1871608890 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4021910279 ps |
| CPU time | 14.94 seconds |
| Started | Oct 02 10:47:19 PM UTC 24 |
| Finished | Oct 02 10:47:35 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1871608890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.1871608890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2113443074 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 1357670794151 ps |
| CPU time | 221.7 seconds |
| Started | Oct 02 10:47:16 PM UTC 24 |
| Finished | Oct 02 10:51:01 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113443074 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.2113443074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.2920095998 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2038703537 ps |
| CPU time | 2.41 seconds |
| Started | Oct 02 10:41:44 PM UTC 24 |
| Finished | Oct 02 10:41:48 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920095998 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.2920095998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2471579459 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 125738755376 ps |
| CPU time | 392.34 seconds |
| Started | Oct 02 10:41:37 PM UTC 24 |
| Finished | Oct 02 10:48:14 PM UTC 24 |
| Peak memory | 213208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471579459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.2471579459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.4285646795 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 140546508857 ps |
| CPU time | 385.01 seconds |
| Started | Oct 02 10:41:39 PM UTC 24 |
| Finished | Oct 02 10:48:09 PM UTC 24 |
| Peak memory | 213480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285646795 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.4285646795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2945582453 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2396961626 ps |
| CPU time | 9.89 seconds |
| Started | Oct 02 10:41:35 PM UTC 24 |
| Finished | Oct 02 10:41:46 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945582453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2945582453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.890640538 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2331827138 ps |
| CPU time | 3.8 seconds |
| Started | Oct 02 10:41:35 PM UTC 24 |
| Finished | Oct 02 10:41:40 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890640538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.890640538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.664094636 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1251080757411 ps |
| CPU time | 3100.57 seconds |
| Started | Oct 02 10:41:37 PM UTC 24 |
| Finished | Oct 02 11:33:49 PM UTC 24 |
| Peak memory | 213068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664094636 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.664094636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.61983085 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 2685764275 ps |
| CPU time | 9.96 seconds |
| Started | Oct 02 10:41:39 PM UTC 24 |
| Finished | Oct 02 10:41:50 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61983085 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.61983085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2398278519 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2609061851 ps |
| CPU time | 12.83 seconds |
| Started | Oct 02 10:41:36 PM UTC 24 |
| Finished | Oct 02 10:41:50 PM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398278519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.2398278519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.1400722664 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2452646675 ps |
| CPU time | 9.82 seconds |
| Started | Oct 02 10:41:33 PM UTC 24 |
| Finished | Oct 02 10:41:43 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400722664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.1400722664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.3343894200 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2104539158 ps |
| CPU time | 2.64 seconds |
| Started | Oct 02 10:41:35 PM UTC 24 |
| Finished | Oct 02 10:41:38 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343894200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.3343894200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.1527654924 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2519148907 ps |
| CPU time | 6.59 seconds |
| Started | Oct 02 10:41:36 PM UTC 24 |
| Finished | Oct 02 10:41:44 PM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527654924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1527654924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.3184524714 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 22053289738 ps |
| CPU time | 21.43 seconds |
| Started | Oct 02 10:41:43 PM UTC 24 |
| Finished | Oct 02 10:42:05 PM UTC 24 |
| Peak memory | 241496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184524714 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.3184524714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.389099622 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2140347354 ps |
| CPU time | 1.95 seconds |
| Started | Oct 02 10:41:33 PM UTC 24 |
| Finished | Oct 02 10:41:35 PM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389099622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.389099622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1304159301 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10148280248 ps |
| CPU time | 16.73 seconds |
| Started | Oct 02 10:41:41 PM UTC 24 |
| Finished | Oct 02 10:41:59 PM UTC 24 |
| Peak memory | 222108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1304159301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.1304159301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3472524729 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3871911546 ps |
| CPU time | 2.6 seconds |
| Started | Oct 02 10:41:38 PM UTC 24 |
| Finished | Oct 02 10:41:42 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472524729 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.3472524729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.2585416601 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 2012962126 ps |
| CPU time | 11.2 seconds |
| Started | Oct 02 10:47:37 PM UTC 24 |
| Finished | Oct 02 10:47:49 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585416601 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.2585416601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.544912424 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 3453447282 ps |
| CPU time | 3.74 seconds |
| Started | Oct 02 10:47:30 PM UTC 24 |
| Finished | Oct 02 10:47:35 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544912424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.544912424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.291683311 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 42974841987 ps |
| CPU time | 132.08 seconds |
| Started | Oct 02 10:47:34 PM UTC 24 |
| Finished | Oct 02 10:49:49 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291683311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_with_pre_cond.291683311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4070736436 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 3527851628 ps |
| CPU time | 8.29 seconds |
| Started | Oct 02 10:47:27 PM UTC 24 |
| Finished | Oct 02 10:47:37 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070736436 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.4070736436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1669442747 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 3090002588 ps |
| CPU time | 8.46 seconds |
| Started | Oct 02 10:47:32 PM UTC 24 |
| Finished | Oct 02 10:47:42 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669442747 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.1669442747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.122471215 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2609741407 ps |
| CPU time | 14.11 seconds |
| Started | Oct 02 10:47:25 PM UTC 24 |
| Finished | Oct 02 10:47:40 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122471215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.122471215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.1408518350 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2435986888 ps |
| CPU time | 9.72 seconds |
| Started | Oct 02 10:47:23 PM UTC 24 |
| Finished | Oct 02 10:47:33 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408518350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.1408518350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.974530921 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2098558433 ps |
| CPU time | 6.09 seconds |
| Started | Oct 02 10:47:24 PM UTC 24 |
| Finished | Oct 02 10:47:31 PM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974530921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.974530921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.1776639398 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2516367919 ps |
| CPU time | 7.97 seconds |
| Started | Oct 02 10:47:25 PM UTC 24 |
| Finished | Oct 02 10:47:34 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776639398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.1776639398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.4233896863 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2115093306 ps |
| CPU time | 8.04 seconds |
| Started | Oct 02 10:47:21 PM UTC 24 |
| Finished | Oct 02 10:47:31 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233896863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.4233896863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.2232257262 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 174276887061 ps |
| CPU time | 18.18 seconds |
| Started | Oct 02 10:47:36 PM UTC 24 |
| Finished | Oct 02 10:47:55 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232257262 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.2232257262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2235127889 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 3309518982 ps |
| CPU time | 15.31 seconds |
| Started | Oct 02 10:47:35 PM UTC 24 |
| Finished | Oct 02 10:47:52 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2235127889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.2235127889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2414221883 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 5018143355 ps |
| CPU time | 2.84 seconds |
| Started | Oct 02 10:47:31 PM UTC 24 |
| Finished | Oct 02 10:47:35 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414221883 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.2414221883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.2294898523 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 2013889786 ps |
| CPU time | 4.17 seconds |
| Started | Oct 02 10:47:54 PM UTC 24 |
| Finished | Oct 02 10:47:59 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294898523 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.2294898523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.779170075 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 3480903262 ps |
| CPU time | 5.17 seconds |
| Started | Oct 02 10:47:48 PM UTC 24 |
| Finished | Oct 02 10:47:54 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779170075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.779170075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.2062798301 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 74737665333 ps |
| CPU time | 91.1 seconds |
| Started | Oct 02 10:47:49 PM UTC 24 |
| Finished | Oct 02 10:49:22 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062798301 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.2062798301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2184645079 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 62701370200 ps |
| CPU time | 105.56 seconds |
| Started | Oct 02 10:47:52 PM UTC 24 |
| Finished | Oct 02 10:49:39 PM UTC 24 |
| Peak memory | 211924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184645079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_with_pre_cond.2184645079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.450184906 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 5143395668 ps |
| CPU time | 2.32 seconds |
| Started | Oct 02 10:47:45 PM UTC 24 |
| Finished | Oct 02 10:47:48 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450184906 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.450184906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.761494211 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 3040034607 ps |
| CPU time | 4.36 seconds |
| Started | Oct 02 10:47:49 PM UTC 24 |
| Finished | Oct 02 10:47:55 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761494211 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.761494211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3703930441 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2613122745 ps |
| CPU time | 13.59 seconds |
| Started | Oct 02 10:47:43 PM UTC 24 |
| Finished | Oct 02 10:47:58 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703930441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.3703930441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.1647861507 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2459311823 ps |
| CPU time | 8.35 seconds |
| Started | Oct 02 10:47:38 PM UTC 24 |
| Finished | Oct 02 10:47:47 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647861507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.1647861507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.3979175726 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 2113928451 ps |
| CPU time | 9.09 seconds |
| Started | Oct 02 10:47:41 PM UTC 24 |
| Finished | Oct 02 10:47:51 PM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979175726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.3979175726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.4091953615 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2526063530 ps |
| CPU time | 4.16 seconds |
| Started | Oct 02 10:47:42 PM UTC 24 |
| Finished | Oct 02 10:47:47 PM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091953615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.4091953615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.3528154967 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 2130525262 ps |
| CPU time | 3.51 seconds |
| Started | Oct 02 10:47:37 PM UTC 24 |
| Finished | Oct 02 10:47:41 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528154967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.3528154967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.2343086205 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 7279810630 ps |
| CPU time | 7.84 seconds |
| Started | Oct 02 10:47:53 PM UTC 24 |
| Finished | Oct 02 10:48:02 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343086205 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.2343086205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1432149908 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 4333567961 ps |
| CPU time | 5.99 seconds |
| Started | Oct 02 10:47:48 PM UTC 24 |
| Finished | Oct 02 10:47:55 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432149908 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.1432149908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.3320238710 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 2050461377 ps |
| CPU time | 1.92 seconds |
| Started | Oct 02 10:48:04 PM UTC 24 |
| Finished | Oct 02 10:48:07 PM UTC 24 |
| Peak memory | 209300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320238710 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.3320238710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.25489499 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 143404988734 ps |
| CPU time | 447.34 seconds |
| Started | Oct 02 10:47:58 PM UTC 24 |
| Finished | Oct 02 10:55:31 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25489499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.25489499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.753864204 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 107897349130 ps |
| CPU time | 85.68 seconds |
| Started | Oct 02 10:47:59 PM UTC 24 |
| Finished | Oct 02 10:49:27 PM UTC 24 |
| Peak memory | 211728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753864204 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.753864204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3576423853 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 51311946161 ps |
| CPU time | 72.08 seconds |
| Started | Oct 02 10:48:02 PM UTC 24 |
| Finished | Oct 02 10:49:15 PM UTC 24 |
| Peak memory | 211868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576423853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_with_pre_cond.3576423853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.932015749 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 4084881772 ps |
| CPU time | 15.03 seconds |
| Started | Oct 02 10:47:58 PM UTC 24 |
| Finished | Oct 02 10:48:14 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932015749 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.932015749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.3338513952 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3404471057 ps |
| CPU time | 15.18 seconds |
| Started | Oct 02 10:48:01 PM UTC 24 |
| Finished | Oct 02 10:48:17 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338513952 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.3338513952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1796794763 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2624422024 ps |
| CPU time | 4.16 seconds |
| Started | Oct 02 10:47:58 PM UTC 24 |
| Finished | Oct 02 10:48:03 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796794763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.1796794763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1392184845 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2479622074 ps |
| CPU time | 3.51 seconds |
| Started | Oct 02 10:47:56 PM UTC 24 |
| Finished | Oct 02 10:48:01 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392184845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.1392184845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1245202420 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 2143496703 ps |
| CPU time | 2.51 seconds |
| Started | Oct 02 10:47:56 PM UTC 24 |
| Finished | Oct 02 10:47:59 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245202420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1245202420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.3824851496 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 2517660862 ps |
| CPU time | 6.82 seconds |
| Started | Oct 02 10:47:56 PM UTC 24 |
| Finished | Oct 02 10:48:04 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824851496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.3824851496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.2796105047 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2110482571 ps |
| CPU time | 7.59 seconds |
| Started | Oct 02 10:47:55 PM UTC 24 |
| Finished | Oct 02 10:48:03 PM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796105047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2796105047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.3479679912 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 11003113202 ps |
| CPU time | 9.8 seconds |
| Started | Oct 02 10:48:04 PM UTC 24 |
| Finished | Oct 02 10:48:15 PM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479679912 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.3479679912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3733528820 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 6853556137 ps |
| CPU time | 25.45 seconds |
| Started | Oct 02 10:48:03 PM UTC 24 |
| Finished | Oct 02 10:48:30 PM UTC 24 |
| Peak memory | 222092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3733528820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.3733528820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3335230715 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 6656175940 ps |
| CPU time | 4.01 seconds |
| Started | Oct 02 10:47:58 PM UTC 24 |
| Finished | Oct 02 10:48:03 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335230715 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.3335230715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.2097911107 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2020799474 ps |
| CPU time | 5.51 seconds |
| Started | Oct 02 10:48:15 PM UTC 24 |
| Finished | Oct 02 10:48:22 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097911107 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.2097911107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3207039305 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 240206584528 ps |
| CPU time | 331.94 seconds |
| Started | Oct 02 10:48:10 PM UTC 24 |
| Finished | Oct 02 10:53:47 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207039305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.3207039305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.1070787165 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 28573434641 ps |
| CPU time | 41.66 seconds |
| Started | Oct 02 10:48:13 PM UTC 24 |
| Finished | Oct 02 10:48:56 PM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070787165 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.1070787165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.459521197 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3714495505 ps |
| CPU time | 19.69 seconds |
| Started | Oct 02 10:48:09 PM UTC 24 |
| Finished | Oct 02 10:48:30 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459521197 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.459521197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.3837822580 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2506121016 ps |
| CPU time | 3.19 seconds |
| Started | Oct 02 10:48:14 PM UTC 24 |
| Finished | Oct 02 10:48:18 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837822580 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.3837822580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2541668512 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2626783243 ps |
| CPU time | 3.9 seconds |
| Started | Oct 02 10:48:08 PM UTC 24 |
| Finished | Oct 02 10:48:13 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541668512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2541668512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.217476440 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2440274055 ps |
| CPU time | 12.84 seconds |
| Started | Oct 02 10:48:04 PM UTC 24 |
| Finished | Oct 02 10:48:18 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217476440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.217476440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.4073376787 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2218462898 ps |
| CPU time | 8.06 seconds |
| Started | Oct 02 10:48:05 PM UTC 24 |
| Finished | Oct 02 10:48:14 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073376787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.4073376787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.713959048 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2530103381 ps |
| CPU time | 3.9 seconds |
| Started | Oct 02 10:48:07 PM UTC 24 |
| Finished | Oct 02 10:48:12 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713959048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.713959048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.69671787 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2127885437 ps |
| CPU time | 3.25 seconds |
| Started | Oct 02 10:48:04 PM UTC 24 |
| Finished | Oct 02 10:48:08 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69671787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.69671787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.27162157 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 7859941495 ps |
| CPU time | 10.08 seconds |
| Started | Oct 02 10:48:15 PM UTC 24 |
| Finished | Oct 02 10:48:26 PM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=27162157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.27162157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3752420238 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 9277306728 ps |
| CPU time | 2.8 seconds |
| Started | Oct 02 10:48:12 PM UTC 24 |
| Finished | Oct 02 10:48:15 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752420238 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.3752420238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.269460438 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2018434080 ps |
| CPU time | 4.46 seconds |
| Started | Oct 02 10:48:25 PM UTC 24 |
| Finished | Oct 02 10:48:31 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269460438 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.269460438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.466035233 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3527363368 ps |
| CPU time | 15.42 seconds |
| Started | Oct 02 10:48:19 PM UTC 24 |
| Finished | Oct 02 10:48:35 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466035233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.466035233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3433400328 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 26590051919 ps |
| CPU time | 36.47 seconds |
| Started | Oct 02 10:48:23 PM UTC 24 |
| Finished | Oct 02 10:49:01 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433400328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_with_pre_cond.3433400328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2159464448 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4741395356 ps |
| CPU time | 4.24 seconds |
| Started | Oct 02 10:48:19 PM UTC 24 |
| Finished | Oct 02 10:48:24 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159464448 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.2159464448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.3904031013 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2519959420 ps |
| CPU time | 3.36 seconds |
| Started | Oct 02 10:48:23 PM UTC 24 |
| Finished | Oct 02 10:48:27 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904031013 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.3904031013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3807467876 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2611625072 ps |
| CPU time | 8.57 seconds |
| Started | Oct 02 10:48:17 PM UTC 24 |
| Finished | Oct 02 10:48:27 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807467876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.3807467876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.214198753 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2472423447 ps |
| CPU time | 6.88 seconds |
| Started | Oct 02 10:48:16 PM UTC 24 |
| Finished | Oct 02 10:48:24 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214198753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.214198753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.2154138735 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 2207404022 ps |
| CPU time | 2.44 seconds |
| Started | Oct 02 10:48:16 PM UTC 24 |
| Finished | Oct 02 10:48:20 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154138735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.2154138735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3780031595 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 2513054350 ps |
| CPU time | 11.72 seconds |
| Started | Oct 02 10:48:17 PM UTC 24 |
| Finished | Oct 02 10:48:30 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780031595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.3780031595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.1906310298 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 2126963813 ps |
| CPU time | 3.12 seconds |
| Started | Oct 02 10:48:15 PM UTC 24 |
| Finished | Oct 02 10:48:19 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906310298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.1906310298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.1742299275 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 14833137186 ps |
| CPU time | 13.71 seconds |
| Started | Oct 02 10:48:25 PM UTC 24 |
| Finished | Oct 02 10:48:40 PM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742299275 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.1742299275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.67237487 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4785747912 ps |
| CPU time | 18.15 seconds |
| Started | Oct 02 10:48:24 PM UTC 24 |
| Finished | Oct 02 10:48:43 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=67237487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.67237487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.122291231 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 4812464788 ps |
| CPU time | 2.93 seconds |
| Started | Oct 02 10:48:20 PM UTC 24 |
| Finished | Oct 02 10:48:24 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122291231 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.122291231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2867351873 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 2015688466 ps |
| CPU time | 5.15 seconds |
| Started | Oct 02 10:48:34 PM UTC 24 |
| Finished | Oct 02 10:48:41 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867351873 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.2867351873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1463388165 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3733519328 ps |
| CPU time | 2.68 seconds |
| Started | Oct 02 10:48:30 PM UTC 24 |
| Finished | Oct 02 10:48:34 PM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463388165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1463388165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.3434379149 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 143563515150 ps |
| CPU time | 127.72 seconds |
| Started | Oct 02 10:48:31 PM UTC 24 |
| Finished | Oct 02 10:50:41 PM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434379149 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.3434379149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.292354332 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2604584002 ps |
| CPU time | 4 seconds |
| Started | Oct 02 10:48:29 PM UTC 24 |
| Finished | Oct 02 10:48:34 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292354332 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.292354332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.3062409847 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4830555925 ps |
| CPU time | 3.31 seconds |
| Started | Oct 02 10:48:32 PM UTC 24 |
| Finished | Oct 02 10:48:37 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062409847 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.3062409847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3054976029 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2613342626 ps |
| CPU time | 14.33 seconds |
| Started | Oct 02 10:48:29 PM UTC 24 |
| Finished | Oct 02 10:48:44 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054976029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.3054976029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.1937399471 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2472215774 ps |
| CPU time | 15.52 seconds |
| Started | Oct 02 10:48:27 PM UTC 24 |
| Finished | Oct 02 10:48:44 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937399471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.1937399471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.2087454594 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2035858703 ps |
| CPU time | 3.93 seconds |
| Started | Oct 02 10:48:29 PM UTC 24 |
| Finished | Oct 02 10:48:34 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087454594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2087454594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.4021107855 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 2516925483 ps |
| CPU time | 5.51 seconds |
| Started | Oct 02 10:48:29 PM UTC 24 |
| Finished | Oct 02 10:48:35 PM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021107855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.4021107855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.4143038115 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 2124934943 ps |
| CPU time | 3.5 seconds |
| Started | Oct 02 10:48:27 PM UTC 24 |
| Finished | Oct 02 10:48:32 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143038115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.4143038115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.1349599346 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 9292909915 ps |
| CPU time | 44.57 seconds |
| Started | Oct 02 10:48:34 PM UTC 24 |
| Finished | Oct 02 10:49:20 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349599346 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.1349599346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1189222214 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4473064199 ps |
| CPU time | 20.25 seconds |
| Started | Oct 02 10:48:33 PM UTC 24 |
| Finished | Oct 02 10:48:55 PM UTC 24 |
| Peak memory | 211832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1189222214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.1189222214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.91390225 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 6543149112667 ps |
| CPU time | 475.15 seconds |
| Started | Oct 02 10:48:31 PM UTC 24 |
| Finished | Oct 02 10:56:32 PM UTC 24 |
| Peak memory | 213060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91390225 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.91390225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.999214303 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2014539613 ps |
| CPU time | 7.07 seconds |
| Started | Oct 02 10:48:46 PM UTC 24 |
| Finished | Oct 02 10:48:54 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999214303 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.999214303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1310608077 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3025218263 ps |
| CPU time | 13.83 seconds |
| Started | Oct 02 10:48:42 PM UTC 24 |
| Finished | Oct 02 10:48:58 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310608077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.1310608077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.2250097078 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 101432530013 ps |
| CPU time | 299.69 seconds |
| Started | Oct 02 10:48:44 PM UTC 24 |
| Finished | Oct 02 10:53:48 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250097078 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.2250097078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1246286065 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 46499164972 ps |
| CPU time | 39.18 seconds |
| Started | Oct 02 10:48:45 PM UTC 24 |
| Finished | Oct 02 10:49:26 PM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246286065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_with_pre_cond.1246286065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.4130806098 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2800529173 ps |
| CPU time | 4.61 seconds |
| Started | Oct 02 10:48:42 PM UTC 24 |
| Finished | Oct 02 10:48:48 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130806098 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.4130806098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.176556040 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 3293743228 ps |
| CPU time | 12.41 seconds |
| Started | Oct 02 10:48:44 PM UTC 24 |
| Finished | Oct 02 10:48:58 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176556040 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.176556040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.660903013 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 2632383135 ps |
| CPU time | 3.01 seconds |
| Started | Oct 02 10:48:41 PM UTC 24 |
| Finished | Oct 02 10:48:46 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660903013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.660903013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.222893189 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2463699803 ps |
| CPU time | 11.91 seconds |
| Started | Oct 02 10:48:37 PM UTC 24 |
| Finished | Oct 02 10:48:50 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222893189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.222893189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.2613047106 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2049230337 ps |
| CPU time | 3.17 seconds |
| Started | Oct 02 10:48:37 PM UTC 24 |
| Finished | Oct 02 10:48:41 PM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613047106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.2613047106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.2337253244 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2528616638 ps |
| CPU time | 4.11 seconds |
| Started | Oct 02 10:48:38 PM UTC 24 |
| Finished | Oct 02 10:48:43 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337253244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2337253244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.1117164240 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2123338081 ps |
| CPU time | 4.99 seconds |
| Started | Oct 02 10:48:36 PM UTC 24 |
| Finished | Oct 02 10:48:42 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117164240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.1117164240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.2589405707 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 15277460392 ps |
| CPU time | 20.91 seconds |
| Started | Oct 02 10:48:46 PM UTC 24 |
| Finished | Oct 02 10:49:08 PM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589405707 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.2589405707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.430840977 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3929810620 ps |
| CPU time | 15.08 seconds |
| Started | Oct 02 10:48:46 PM UTC 24 |
| Finished | Oct 02 10:49:02 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=430840977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.430840977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1362257179 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3809284538 ps |
| CPU time | 5.49 seconds |
| Started | Oct 02 10:48:43 PM UTC 24 |
| Finished | Oct 02 10:48:50 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362257179 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.1362257179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.2256541393 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 2010510897 ps |
| CPU time | 6.08 seconds |
| Started | Oct 02 10:48:58 PM UTC 24 |
| Finished | Oct 02 10:49:05 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256541393 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.2256541393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2956012855 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 28637879301 ps |
| CPU time | 79.72 seconds |
| Started | Oct 02 10:48:52 PM UTC 24 |
| Finished | Oct 02 10:50:14 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956012855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.2956012855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.737233052 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 92204523204 ps |
| CPU time | 62.6 seconds |
| Started | Oct 02 10:48:54 PM UTC 24 |
| Finished | Oct 02 10:49:59 PM UTC 24 |
| Peak memory | 211800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737233052 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.737233052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.230912780 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 47189840755 ps |
| CPU time | 31.67 seconds |
| Started | Oct 02 10:48:56 PM UTC 24 |
| Finished | Oct 02 10:49:29 PM UTC 24 |
| Peak memory | 211872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230912780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_with_pre_cond.230912780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3239276515 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 4842134632 ps |
| CPU time | 15.3 seconds |
| Started | Oct 02 10:48:51 PM UTC 24 |
| Finished | Oct 02 10:49:08 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239276515 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.3239276515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.986035799 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5481699070 ps |
| CPU time | 22.93 seconds |
| Started | Oct 02 10:48:54 PM UTC 24 |
| Finished | Oct 02 10:49:19 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986035799 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.986035799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3714902425 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 2717155758 ps |
| CPU time | 1.8 seconds |
| Started | Oct 02 10:48:51 PM UTC 24 |
| Finished | Oct 02 10:48:54 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714902425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.3714902425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.373580074 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2489245140 ps |
| CPU time | 2.01 seconds |
| Started | Oct 02 10:48:49 PM UTC 24 |
| Finished | Oct 02 10:48:52 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373580074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.373580074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.2246515192 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2081052200 ps |
| CPU time | 2.1 seconds |
| Started | Oct 02 10:48:50 PM UTC 24 |
| Finished | Oct 02 10:48:53 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246515192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.2246515192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.1137135947 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 2519405867 ps |
| CPU time | 7.06 seconds |
| Started | Oct 02 10:48:50 PM UTC 24 |
| Finished | Oct 02 10:48:58 PM UTC 24 |
| Peak memory | 211788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137135947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1137135947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.3559058861 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 2109416071 ps |
| CPU time | 10.54 seconds |
| Started | Oct 02 10:48:47 PM UTC 24 |
| Finished | Oct 02 10:48:59 PM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559058861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.3559058861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.413379124 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 13252094734 ps |
| CPU time | 13.75 seconds |
| Started | Oct 02 10:48:58 PM UTC 24 |
| Finished | Oct 02 10:49:13 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413379124 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.413379124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3589850225 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 2450735071 ps |
| CPU time | 8.48 seconds |
| Started | Oct 02 10:48:57 PM UTC 24 |
| Finished | Oct 02 10:49:06 PM UTC 24 |
| Peak memory | 211832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3589850225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.3589850225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.967980996 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 2945996055 ps |
| CPU time | 3.55 seconds |
| Started | Oct 02 10:48:54 PM UTC 24 |
| Finished | Oct 02 10:48:59 PM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967980996 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.967980996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.3400297342 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2007207267 ps |
| CPU time | 7.56 seconds |
| Started | Oct 02 10:49:07 PM UTC 24 |
| Finished | Oct 02 10:49:16 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400297342 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.3400297342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1205809171 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3629869852 ps |
| CPU time | 12.66 seconds |
| Started | Oct 02 10:49:02 PM UTC 24 |
| Finished | Oct 02 10:49:16 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205809171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.1205809171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.306181440 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 193101563280 ps |
| CPU time | 487.38 seconds |
| Started | Oct 02 10:49:05 PM UTC 24 |
| Finished | Oct 02 10:57:17 PM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306181440 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.306181440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2712245019 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 60975714448 ps |
| CPU time | 94.87 seconds |
| Started | Oct 02 10:49:06 PM UTC 24 |
| Finished | Oct 02 10:50:43 PM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712245019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_with_pre_cond.2712245019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3880099218 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 899431163269 ps |
| CPU time | 2736.93 seconds |
| Started | Oct 02 10:49:01 PM UTC 24 |
| Finished | Oct 02 11:35:08 PM UTC 24 |
| Peak memory | 213328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880099218 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.3880099218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.3651641713 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 5207912916 ps |
| CPU time | 4.38 seconds |
| Started | Oct 02 10:49:05 PM UTC 24 |
| Finished | Oct 02 10:49:10 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651641713 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.3651641713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3148581509 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 2641834461 ps |
| CPU time | 2.73 seconds |
| Started | Oct 02 10:49:00 PM UTC 24 |
| Finished | Oct 02 10:49:04 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148581509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3148581509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.1072599718 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 2460773930 ps |
| CPU time | 6.15 seconds |
| Started | Oct 02 10:48:59 PM UTC 24 |
| Finished | Oct 02 10:49:06 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072599718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.1072599718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.4201893321 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 2259618171 ps |
| CPU time | 3.12 seconds |
| Started | Oct 02 10:48:59 PM UTC 24 |
| Finished | Oct 02 10:49:04 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201893321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.4201893321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3275296505 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 2514123789 ps |
| CPU time | 13.01 seconds |
| Started | Oct 02 10:48:59 PM UTC 24 |
| Finished | Oct 02 10:49:14 PM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275296505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.3275296505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.2489619645 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2129905248 ps |
| CPU time | 3.48 seconds |
| Started | Oct 02 10:48:59 PM UTC 24 |
| Finished | Oct 02 10:49:04 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489619645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.2489619645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.3885939628 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 9129471249 ps |
| CPU time | 8.16 seconds |
| Started | Oct 02 10:49:07 PM UTC 24 |
| Finished | Oct 02 10:49:16 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885939628 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.3885939628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2473505292 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 15802980130 ps |
| CPU time | 9.86 seconds |
| Started | Oct 02 10:49:06 PM UTC 24 |
| Finished | Oct 02 10:49:17 PM UTC 24 |
| Peak memory | 228448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2473505292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.2473505292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2037272900 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 4661479488 ps |
| CPU time | 3.59 seconds |
| Started | Oct 02 10:49:05 PM UTC 24 |
| Finished | Oct 02 10:49:09 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037272900 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.2037272900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.1832046746 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 2018813362 ps |
| CPU time | 4.34 seconds |
| Started | Oct 02 10:49:17 PM UTC 24 |
| Finished | Oct 02 10:49:23 PM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832046746 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.1832046746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.653678290 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3784654975 ps |
| CPU time | 11.24 seconds |
| Started | Oct 02 10:49:14 PM UTC 24 |
| Finished | Oct 02 10:49:26 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653678290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.653678290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.83370588 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 116909582794 ps |
| CPU time | 116.93 seconds |
| Started | Oct 02 10:49:16 PM UTC 24 |
| Finished | Oct 02 10:51:15 PM UTC 24 |
| Peak memory | 211856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83370588 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.83370588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1957742784 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 44975971715 ps |
| CPU time | 37.55 seconds |
| Started | Oct 02 10:49:17 PM UTC 24 |
| Finished | Oct 02 10:49:56 PM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957742784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_with_pre_cond.1957742784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3698767125 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2954839327 ps |
| CPU time | 4.23 seconds |
| Started | Oct 02 10:49:14 PM UTC 24 |
| Finished | Oct 02 10:49:19 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698767125 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.3698767125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.2398692371 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2730574205 ps |
| CPU time | 12.06 seconds |
| Started | Oct 02 10:49:17 PM UTC 24 |
| Finished | Oct 02 10:49:30 PM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398692371 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.2398692371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2771236788 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 2616776602 ps |
| CPU time | 6.83 seconds |
| Started | Oct 02 10:49:14 PM UTC 24 |
| Finished | Oct 02 10:49:21 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771236788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.2771236788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.3549615410 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2477891925 ps |
| CPU time | 2.64 seconds |
| Started | Oct 02 10:49:09 PM UTC 24 |
| Finished | Oct 02 10:49:13 PM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549615410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.3549615410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.3869584155 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 2169327968 ps |
| CPU time | 4.66 seconds |
| Started | Oct 02 10:49:10 PM UTC 24 |
| Finished | Oct 02 10:49:16 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869584155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.3869584155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.3161231667 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2538001377 ps |
| CPU time | 3.67 seconds |
| Started | Oct 02 10:49:11 PM UTC 24 |
| Finished | Oct 02 10:49:16 PM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161231667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.3161231667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.374293527 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 2108781386 ps |
| CPU time | 7.38 seconds |
| Started | Oct 02 10:49:08 PM UTC 24 |
| Finished | Oct 02 10:49:17 PM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374293527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.374293527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.1639748705 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 90621995615 ps |
| CPU time | 61.74 seconds |
| Started | Oct 02 10:49:17 PM UTC 24 |
| Finished | Oct 02 10:50:20 PM UTC 24 |
| Peak memory | 211856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639748705 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.1639748705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3064612252 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 6441638263 ps |
| CPU time | 18.73 seconds |
| Started | Oct 02 10:49:17 PM UTC 24 |
| Finished | Oct 02 10:49:37 PM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3064612252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.3064612252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3174297857 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 9238553145 ps |
| CPU time | 6.95 seconds |
| Started | Oct 02 10:49:15 PM UTC 24 |
| Finished | Oct 02 10:49:23 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174297857 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.3174297857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.1900063812 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2018144080 ps |
| CPU time | 4.12 seconds |
| Started | Oct 02 10:41:52 PM UTC 24 |
| Finished | Oct 02 10:41:57 PM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900063812 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.1900063812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3806836647 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3386578249 ps |
| CPU time | 15.24 seconds |
| Started | Oct 02 10:41:48 PM UTC 24 |
| Finished | Oct 02 10:42:05 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806836647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.3806836647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.4197663895 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 76211836742 ps |
| CPU time | 106.29 seconds |
| Started | Oct 02 10:41:50 PM UTC 24 |
| Finished | Oct 02 10:43:38 PM UTC 24 |
| Peak memory | 211804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197663895 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.4197663895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3235629509 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 27594989845 ps |
| CPU time | 16.74 seconds |
| Started | Oct 02 10:41:51 PM UTC 24 |
| Finished | Oct 02 10:42:09 PM UTC 24 |
| Peak memory | 211860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235629509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_with_pre_cond.3235629509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1672970286 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3091014415 ps |
| CPU time | 2.42 seconds |
| Started | Oct 02 10:41:47 PM UTC 24 |
| Finished | Oct 02 10:41:51 PM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672970286 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.1672970286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.984107680 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2852557921 ps |
| CPU time | 9.11 seconds |
| Started | Oct 02 10:41:51 PM UTC 24 |
| Finished | Oct 02 10:42:01 PM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984107680 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.984107680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3227982280 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2616928699 ps |
| CPU time | 5.62 seconds |
| Started | Oct 02 10:41:46 PM UTC 24 |
| Finished | Oct 02 10:41:53 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227982280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.3227982280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.336309110 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2473274880 ps |
| CPU time | 3.79 seconds |
| Started | Oct 02 10:41:45 PM UTC 24 |
| Finished | Oct 02 10:41:50 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336309110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.336309110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.927377025 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2119964340 ps |
| CPU time | 3.1 seconds |
| Started | Oct 02 10:41:45 PM UTC 24 |
| Finished | Oct 02 10:41:49 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927377025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.927377025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.997347572 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2515400884 ps |
| CPU time | 4.2 seconds |
| Started | Oct 02 10:41:46 PM UTC 24 |
| Finished | Oct 02 10:41:51 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997347572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.997347572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.3839202009 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 2113435638 ps |
| CPU time | 12.38 seconds |
| Started | Oct 02 10:41:44 PM UTC 24 |
| Finished | Oct 02 10:41:58 PM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839202009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.3839202009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4022275881 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 7746841058 ps |
| CPU time | 3.37 seconds |
| Started | Oct 02 10:41:49 PM UTC 24 |
| Finished | Oct 02 10:41:53 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022275881 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.4022275881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2942950592 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 173828118328 ps |
| CPU time | 286.74 seconds |
| Started | Oct 02 10:49:17 PM UTC 24 |
| Finished | Oct 02 10:54:08 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942950592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_with_pre_cond.2942950592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1498776988 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 59961966139 ps |
| CPU time | 56.9 seconds |
| Started | Oct 02 10:49:19 PM UTC 24 |
| Finished | Oct 02 10:50:18 PM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498776988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_with_pre_cond.1498776988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/52.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2082854025 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 54489770142 ps |
| CPU time | 43.85 seconds |
| Started | Oct 02 10:49:20 PM UTC 24 |
| Finished | Oct 02 10:50:05 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082854025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_with_pre_cond.2082854025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1460757768 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 122819309620 ps |
| CPU time | 180.48 seconds |
| Started | Oct 02 10:49:21 PM UTC 24 |
| Finished | Oct 02 10:52:24 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460757768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_with_pre_cond.1460757768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1586837651 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 65765204368 ps |
| CPU time | 59.82 seconds |
| Started | Oct 02 10:49:22 PM UTC 24 |
| Finished | Oct 02 10:50:23 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586837651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_with_pre_cond.1586837651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.846963445 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 31487851298 ps |
| CPU time | 69.52 seconds |
| Started | Oct 02 10:49:23 PM UTC 24 |
| Finished | Oct 02 10:50:34 PM UTC 24 |
| Peak memory | 211832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846963445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_with_pre_cond.846963445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3785867451 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 70300995660 ps |
| CPU time | 223.67 seconds |
| Started | Oct 02 10:49:23 PM UTC 24 |
| Finished | Oct 02 10:53:10 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785867451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_with_pre_cond.3785867451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1390869415 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 57606846505 ps |
| CPU time | 20.06 seconds |
| Started | Oct 02 10:49:24 PM UTC 24 |
| Finished | Oct 02 10:49:45 PM UTC 24 |
| Peak memory | 211872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390869415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_with_pre_cond.1390869415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.945457420 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 23728208870 ps |
| CPU time | 18.41 seconds |
| Started | Oct 02 10:49:24 PM UTC 24 |
| Finished | Oct 02 10:49:44 PM UTC 24 |
| Peak memory | 211912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945457420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_with_pre_cond.945457420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/59.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.1739748275 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 2039467988 ps |
| CPU time | 3.61 seconds |
| Started | Oct 02 10:42:00 PM UTC 24 |
| Finished | Oct 02 10:42:05 PM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739748275 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.1739748275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1669274310 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 160946920373 ps |
| CPU time | 25.78 seconds |
| Started | Oct 02 10:41:58 PM UTC 24 |
| Finished | Oct 02 10:42:25 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669274310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.1669274310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.3430473533 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 128127176044 ps |
| CPU time | 471.33 seconds |
| Started | Oct 02 10:41:58 PM UTC 24 |
| Finished | Oct 02 10:49:55 PM UTC 24 |
| Peak memory | 213408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430473533 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.3430473533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.361862488 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 85923299504 ps |
| CPU time | 181.25 seconds |
| Started | Oct 02 10:41:59 PM UTC 24 |
| Finished | Oct 02 10:45:03 PM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361862488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_with_pre_cond.361862488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1795001039 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 2592679280 ps |
| CPU time | 7.72 seconds |
| Started | Oct 02 10:41:55 PM UTC 24 |
| Finished | Oct 02 10:42:04 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795001039 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.1795001039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3000859023 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2635431331 ps |
| CPU time | 3.3 seconds |
| Started | Oct 02 10:41:55 PM UTC 24 |
| Finished | Oct 02 10:42:00 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000859023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3000859023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.2907395537 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2485485348 ps |
| CPU time | 4.74 seconds |
| Started | Oct 02 10:41:54 PM UTC 24 |
| Finished | Oct 02 10:42:00 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907395537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.2907395537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.2207591348 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2083850707 ps |
| CPU time | 2.23 seconds |
| Started | Oct 02 10:41:54 PM UTC 24 |
| Finished | Oct 02 10:41:57 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207591348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.2207591348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.668387494 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2523548089 ps |
| CPU time | 4.51 seconds |
| Started | Oct 02 10:41:54 PM UTC 24 |
| Finished | Oct 02 10:42:00 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668387494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.668387494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.1964508861 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2141858168 ps |
| CPU time | 2.04 seconds |
| Started | Oct 02 10:41:52 PM UTC 24 |
| Finished | Oct 02 10:41:55 PM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964508861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.1964508861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.777488512 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 6240931612 ps |
| CPU time | 23.32 seconds |
| Started | Oct 02 10:41:59 PM UTC 24 |
| Finished | Oct 02 10:42:23 PM UTC 24 |
| Peak memory | 222292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=777488512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.777488512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1190766985 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 58034388291 ps |
| CPU time | 198.78 seconds |
| Started | Oct 02 10:49:26 PM UTC 24 |
| Finished | Oct 02 10:52:48 PM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190766985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_with_pre_cond.1190766985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/60.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1313493874 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 58158631383 ps |
| CPU time | 94.55 seconds |
| Started | Oct 02 10:49:27 PM UTC 24 |
| Finished | Oct 02 10:51:04 PM UTC 24 |
| Peak memory | 211852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313493874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_with_pre_cond.1313493874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3095970671 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 25329427401 ps |
| CPU time | 79.23 seconds |
| Started | Oct 02 10:49:27 PM UTC 24 |
| Finished | Oct 02 10:50:49 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095970671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_with_pre_cond.3095970671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1278386546 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 113461271673 ps |
| CPU time | 310.57 seconds |
| Started | Oct 02 10:49:30 PM UTC 24 |
| Finished | Oct 02 10:54:44 PM UTC 24 |
| Peak memory | 211852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278386546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_with_pre_cond.1278386546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2450071912 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 75393136631 ps |
| CPU time | 72.65 seconds |
| Started | Oct 02 10:49:30 PM UTC 24 |
| Finished | Oct 02 10:50:44 PM UTC 24 |
| Peak memory | 211924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450071912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_with_pre_cond.2450071912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3149169916 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 70209733875 ps |
| CPU time | 99.73 seconds |
| Started | Oct 02 10:49:34 PM UTC 24 |
| Finished | Oct 02 10:51:16 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149169916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_with_pre_cond.3149169916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.843131894 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2088390189 ps |
| CPU time | 1.69 seconds |
| Started | Oct 02 10:42:06 PM UTC 24 |
| Finished | Oct 02 10:42:09 PM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843131894 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.843131894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.4208067203 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 23888807905 ps |
| CPU time | 22.59 seconds |
| Started | Oct 02 10:42:04 PM UTC 24 |
| Finished | Oct 02 10:42:28 PM UTC 24 |
| Peak memory | 211844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208067203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.4208067203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.4271575338 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 125806860336 ps |
| CPU time | 445.53 seconds |
| Started | Oct 02 10:42:05 PM UTC 24 |
| Finished | Oct 02 10:49:36 PM UTC 24 |
| Peak memory | 213440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271575338 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.4271575338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.709805718 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2998293614 ps |
| CPU time | 3.26 seconds |
| Started | Oct 02 10:42:05 PM UTC 24 |
| Finished | Oct 02 10:42:09 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709805718 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.709805718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.318385516 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2629978070 ps |
| CPU time | 4.64 seconds |
| Started | Oct 02 10:42:01 PM UTC 24 |
| Finished | Oct 02 10:42:07 PM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318385516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.318385516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.1648616371 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2470943872 ps |
| CPU time | 14.37 seconds |
| Started | Oct 02 10:42:01 PM UTC 24 |
| Finished | Oct 02 10:42:17 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648616371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.1648616371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.1456303383 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2159689736 ps |
| CPU time | 10.17 seconds |
| Started | Oct 02 10:42:01 PM UTC 24 |
| Finished | Oct 02 10:42:13 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456303383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1456303383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.3634062897 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2523825227 ps |
| CPU time | 4.42 seconds |
| Started | Oct 02 10:42:01 PM UTC 24 |
| Finished | Oct 02 10:42:07 PM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634062897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.3634062897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.1367760946 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2109387118 ps |
| CPU time | 6.19 seconds |
| Started | Oct 02 10:42:00 PM UTC 24 |
| Finished | Oct 02 10:42:07 PM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367760946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.1367760946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2733799982 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 10721864859 ps |
| CPU time | 8.06 seconds |
| Started | Oct 02 10:42:06 PM UTC 24 |
| Finished | Oct 02 10:42:15 PM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2733799982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.2733799982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.4189797671 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5555369017 ps |
| CPU time | 9.98 seconds |
| Started | Oct 02 10:42:04 PM UTC 24 |
| Finished | Oct 02 10:42:15 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189797671 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.4189797671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2352294273 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 117292835722 ps |
| CPU time | 94.98 seconds |
| Started | Oct 02 10:49:37 PM UTC 24 |
| Finished | Oct 02 10:51:14 PM UTC 24 |
| Peak memory | 211812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352294273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_with_pre_cond.2352294273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.579989328 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 26340478149 ps |
| CPU time | 43.27 seconds |
| Started | Oct 02 10:49:46 PM UTC 24 |
| Finished | Oct 02 10:50:31 PM UTC 24 |
| Peak memory | 211928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579989328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_with_pre_cond.579989328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3553162153 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 98868850617 ps |
| CPU time | 43.31 seconds |
| Started | Oct 02 10:49:56 PM UTC 24 |
| Finished | Oct 02 10:50:40 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553162153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_with_pre_cond.3553162153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1230646147 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 125845764947 ps |
| CPU time | 127.92 seconds |
| Started | Oct 02 10:49:57 PM UTC 24 |
| Finished | Oct 02 10:52:07 PM UTC 24 |
| Peak memory | 212124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230646147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_with_pre_cond.1230646147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/77.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4282373032 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 28834588397 ps |
| CPU time | 82.73 seconds |
| Started | Oct 02 10:49:59 PM UTC 24 |
| Finished | Oct 02 10:51:23 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282373032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_with_pre_cond.4282373032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1395007263 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 31301957510 ps |
| CPU time | 15.35 seconds |
| Started | Oct 02 10:50:00 PM UTC 24 |
| Finished | Oct 02 10:50:16 PM UTC 24 |
| Peak memory | 211808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395007263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_with_pre_cond.1395007263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.3532192754 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2054199131 ps |
| CPU time | 2.08 seconds |
| Started | Oct 02 10:42:14 PM UTC 24 |
| Finished | Oct 02 10:42:18 PM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532192754 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.3532192754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3183495565 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3634851752 ps |
| CPU time | 11.36 seconds |
| Started | Oct 02 10:42:10 PM UTC 24 |
| Finished | Oct 02 10:42:22 PM UTC 24 |
| Peak memory | 211844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183495565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.3183495565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.2985643057 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 128601050962 ps |
| CPU time | 348.78 seconds |
| Started | Oct 02 10:42:10 PM UTC 24 |
| Finished | Oct 02 10:48:03 PM UTC 24 |
| Peak memory | 211804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985643057 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.2985643057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3898338762 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 166278309217 ps |
| CPU time | 525.72 seconds |
| Started | Oct 02 10:42:13 PM UTC 24 |
| Finished | Oct 02 10:51:05 PM UTC 24 |
| Peak memory | 213468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898338762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_with_pre_cond.3898338762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3902764196 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2702842306 ps |
| CPU time | 14.21 seconds |
| Started | Oct 02 10:42:10 PM UTC 24 |
| Finished | Oct 02 10:42:25 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902764196 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.3902764196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.358088779 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2964603413 ps |
| CPU time | 2.32 seconds |
| Started | Oct 02 10:42:11 PM UTC 24 |
| Finished | Oct 02 10:42:15 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358088779 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.358088779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3608268000 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2625482118 ps |
| CPU time | 4.5 seconds |
| Started | Oct 02 10:42:10 PM UTC 24 |
| Finished | Oct 02 10:42:15 PM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608268000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.3608268000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.3414740677 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2477361174 ps |
| CPU time | 4.85 seconds |
| Started | Oct 02 10:42:07 PM UTC 24 |
| Finished | Oct 02 10:42:13 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414740677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.3414740677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.3475268953 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2074812177 ps |
| CPU time | 3.78 seconds |
| Started | Oct 02 10:42:09 PM UTC 24 |
| Finished | Oct 02 10:42:13 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475268953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3475268953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.805569171 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2511838862 ps |
| CPU time | 13.67 seconds |
| Started | Oct 02 10:42:09 PM UTC 24 |
| Finished | Oct 02 10:42:23 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805569171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.805569171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.1355238657 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2121378336 ps |
| CPU time | 6.57 seconds |
| Started | Oct 02 10:42:07 PM UTC 24 |
| Finished | Oct 02 10:42:15 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355238657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.1355238657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.990018909 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 6623501549 ps |
| CPU time | 20.2 seconds |
| Started | Oct 02 10:42:14 PM UTC 24 |
| Finished | Oct 02 10:42:36 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990018909 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.990018909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.938590331 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 9073611521 ps |
| CPU time | 7.72 seconds |
| Started | Oct 02 10:42:13 PM UTC 24 |
| Finished | Oct 02 10:42:22 PM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=938590331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.938590331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1106941347 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 45790444652 ps |
| CPU time | 155.46 seconds |
| Started | Oct 02 10:50:00 PM UTC 24 |
| Finished | Oct 02 10:52:38 PM UTC 24 |
| Peak memory | 211860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106941347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_with_pre_cond.1106941347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/80.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2924038496 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 66014743310 ps |
| CPU time | 51.92 seconds |
| Started | Oct 02 10:50:12 PM UTC 24 |
| Finished | Oct 02 10:51:06 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924038496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_with_pre_cond.2924038496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/82.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.737309646 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 57535581714 ps |
| CPU time | 170.2 seconds |
| Started | Oct 02 10:50:13 PM UTC 24 |
| Finished | Oct 02 10:53:07 PM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737309646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_with_pre_cond.737309646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2123979225 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 42534896893 ps |
| CPU time | 148.35 seconds |
| Started | Oct 02 10:50:14 PM UTC 24 |
| Finished | Oct 02 10:52:45 PM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123979225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_with_pre_cond.2123979225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1836118649 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 32092181809 ps |
| CPU time | 41.27 seconds |
| Started | Oct 02 10:50:17 PM UTC 24 |
| Finished | Oct 02 10:51:00 PM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836118649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_with_pre_cond.1836118649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1493658078 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 26335652001 ps |
| CPU time | 63.61 seconds |
| Started | Oct 02 10:50:19 PM UTC 24 |
| Finished | Oct 02 10:51:24 PM UTC 24 |
| Peak memory | 211924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493658078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_with_pre_cond.1493658078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.92011767 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 81988932550 ps |
| CPU time | 256.3 seconds |
| Started | Oct 02 10:50:22 PM UTC 24 |
| Finished | Oct 02 10:54:41 PM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92011767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_with_pre_cond.92011767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/88.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1545361072 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 38466501124 ps |
| CPU time | 149.62 seconds |
| Started | Oct 02 10:50:24 PM UTC 24 |
| Finished | Oct 02 10:52:56 PM UTC 24 |
| Peak memory | 211792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545361072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_with_pre_cond.1545361072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.251608164 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2019825915 ps |
| CPU time | 6.2 seconds |
| Started | Oct 02 10:42:22 PM UTC 24 |
| Finished | Oct 02 10:42:29 PM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251608164 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.251608164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3142839606 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3412196384 ps |
| CPU time | 13.2 seconds |
| Started | Oct 02 10:42:17 PM UTC 24 |
| Finished | Oct 02 10:42:31 PM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142839606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.3142839606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3219498435 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 59853270409 ps |
| CPU time | 166.32 seconds |
| Started | Oct 02 10:42:18 PM UTC 24 |
| Finished | Oct 02 10:45:07 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219498435 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.3219498435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1110144627 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 25608286506 ps |
| CPU time | 21.18 seconds |
| Started | Oct 02 10:42:19 PM UTC 24 |
| Finished | Oct 02 10:42:42 PM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110144627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_with_pre_cond.1110144627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1460551950 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 5450673339 ps |
| CPU time | 6.81 seconds |
| Started | Oct 02 10:42:17 PM UTC 24 |
| Finished | Oct 02 10:42:25 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460551950 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.1460551950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.3286220584 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4211632808 ps |
| CPU time | 3.37 seconds |
| Started | Oct 02 10:42:18 PM UTC 24 |
| Finished | Oct 02 10:42:23 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286220584 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.3286220584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1485869236 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2611079053 ps |
| CPU time | 9.75 seconds |
| Started | Oct 02 10:42:16 PM UTC 24 |
| Finished | Oct 02 10:42:27 PM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485869236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.1485869236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.837931110 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2481196156 ps |
| CPU time | 6.25 seconds |
| Started | Oct 02 10:42:16 PM UTC 24 |
| Finished | Oct 02 10:42:23 PM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837931110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.837931110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.2621678755 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2156941825 ps |
| CPU time | 9.1 seconds |
| Started | Oct 02 10:42:16 PM UTC 24 |
| Finished | Oct 02 10:42:26 PM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621678755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.2621678755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1632466775 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2514494429 ps |
| CPU time | 9.75 seconds |
| Started | Oct 02 10:42:16 PM UTC 24 |
| Finished | Oct 02 10:42:27 PM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632466775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.1632466775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.243705262 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2116863650 ps |
| CPU time | 4.37 seconds |
| Started | Oct 02 10:42:16 PM UTC 24 |
| Finished | Oct 02 10:42:21 PM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243705262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.243705262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.809132657 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 12375435213 ps |
| CPU time | 38.19 seconds |
| Started | Oct 02 10:42:22 PM UTC 24 |
| Finished | Oct 02 10:43:01 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809132657 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.809132657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1734954163 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4861499007 ps |
| CPU time | 13.42 seconds |
| Started | Oct 02 10:42:19 PM UTC 24 |
| Finished | Oct 02 10:42:34 PM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1734954163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.1734954163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3444077417 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3428912715 ps |
| CPU time | 8.68 seconds |
| Started | Oct 02 10:42:18 PM UTC 24 |
| Finished | Oct 02 10:42:28 PM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444077417 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.3444077417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.73859504 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 126263955703 ps |
| CPU time | 103.72 seconds |
| Started | Oct 02 10:50:31 PM UTC 24 |
| Finished | Oct 02 10:52:17 PM UTC 24 |
| Peak memory | 211852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73859504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_with_pre_cond.73859504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.4118199379 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 45800831298 ps |
| CPU time | 55.56 seconds |
| Started | Oct 02 10:50:31 PM UTC 24 |
| Finished | Oct 02 10:51:28 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118199379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_with_pre_cond.4118199379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3100552900 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 54991968362 ps |
| CPU time | 185.3 seconds |
| Started | Oct 02 10:50:32 PM UTC 24 |
| Finished | Oct 02 10:53:40 PM UTC 24 |
| Peak memory | 211812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100552900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_with_pre_cond.3100552900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.916930956 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 28584368528 ps |
| CPU time | 119.78 seconds |
| Started | Oct 02 10:50:32 PM UTC 24 |
| Finished | Oct 02 10:52:35 PM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916930956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_with_pre_cond.916930956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/94.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3151106757 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 26333813832 ps |
| CPU time | 87.5 seconds |
| Started | Oct 02 10:50:35 PM UTC 24 |
| Finished | Oct 02 10:52:05 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151106757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_with_pre_cond.3151106757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3686463333 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 132370792616 ps |
| CPU time | 250.23 seconds |
| Started | Oct 02 10:50:42 PM UTC 24 |
| Finished | Oct 02 10:54:55 PM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686463333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_with_pre_cond.3686463333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest |
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