Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	95.65	90.91		83.33	95.24	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	95.65	90.91		83.33	95.24	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T2 T12 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T16 T24 T54 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T16 T28 T24 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T16 T28 T24 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T16 T24 T54 
149        1/1                    cnt_en = 1'b1;
           Tests:       T16 T24 T54 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T16 T24 T54 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T16 T24 T54 
163        1/1                    state_d = IdleSt;
           Tests:       T24 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 
165        1/1                  end else if (cnt_done) begin
           Tests:       T16 T24 T54 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T54 T56 
167        1/1                    if (trigger_active) begin
           Tests:       T16 T54 T56 
168        1/1                      state_d = DetectSt;
           Tests:       T16 T54 T56 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T137 T138 T139 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T16 T54 T56 
182        1/1                  cnt_en = 1'b1;
           Tests:       T16 T54 T56 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T16 T54 T56 
186        1/1                    state_d = IdleSt;
           Tests:       T116 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T116 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T16 T54 T56 
191        1/1                      state_d = StableSt;
           Tests:       T16 T54 T56 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T16 T54 T56 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T16 T54 T56 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T16 T54 T56 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T16 T54 T56 
206        1/1                    state_d = IdleSt;
           Tests:       T16 T54 T56 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T16 T54 T56 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T12
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T12
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T16,T24,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T16,T24,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T16,T54,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T24,T54
1	0	Covered	T4,T12,T13
1	1	Covered	T16,T24,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T54,T56
0	1	Covered	T116
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T54,T56
0	1	Covered	T16,T54,T56
1	0	Covered	T31

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T54,T56
1	-	Covered	T16,T54,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T24,T54
DetectSt	168	Covered	T16,T54,T56
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T16,T54,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T54,T56
DebounceSt->IdleSt	163	Covered	T24,T140,T137
DetectSt->IdleSt	186	Covered	T116
DetectSt->StableSt	191	Covered	T16,T54,T56
IdleSt->DebounceSt	148	Covered	T16,T24,T54
StableSt->IdleSt	206	Covered	T16,T54,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T24,T54
0	1	Covered	T16,T24,T54
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T16,T54,T56
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T24,T54
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T54,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T137,T138,T139
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T24,T54
DetectSt	-	-	-	-	1	-	-	Covered	T116
DetectSt	-	-	-	-	0	1	-	Covered	T16,T54,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T54,T56
StableSt	-	-	-	-	-	-	0	Covered	T16,T54,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	189	0	0
CntIncr_A	5947631	394356	0	0
CntNoWrap_A	5947631	5481051	0	0
DetectStDropOut_A	5947631	1	0	0
DetectedOut_A	5947631	668	0	0
DetectedPulseOut_A	5947631	88	0	0
DisabledIdleSt_A	5947631	5082447	0	0
DisabledNoDetection_A	5947631	5084237	0	0
EnterDebounceSt_A	5947631	102	0	0
EnterDetectSt_A	5947631	89	0	0
EnterStableSt_A	5947631	88	0	0
PulseIsPulse_A	5947631	88	0	0
StayInStableSt	5947631	580	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5947631	5398	0	0
gen_low_level_sva.LowLevelEvent_A	5947631	5483067	0	0
gen_not_sticky_sva.StableStDropOut_A	5947631	87	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	189	0	0
T3	1327	0	0	0
T5	790	0	0	0
T16	716	4	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	1	0	0
T25	496	0	0	0
T29	471	0	0	0
T31	0	2	0	0
T54	0	2	0	0
T56	0	4	0	0
T57	0	2	0	0
T59	0	4	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	404	0	0	0
T63	725	0	0	0
T108	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	394356	0	0
T3	1327	0	0	0
T5	790	0	0	0
T16	716	69	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	15	0	0
T25	496	0	0	0
T29	471	0	0	0
T31	0	17	0	0
T54	0	95	0	0
T56	0	105	0	0
T57	0	67	0	0
T59	0	58	0	0
T60	0	62	0	0
T61	0	17	0	0
T62	404	0	0	0
T63	725	0	0	0
T108	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481051	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	311	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	1	0	0
T106	19294	0	0	0
T116	667	1	0	0
T117	25836	0	0	0
T123	425	0	0	0
T124	1334	0	0	0
T125	446	0	0	0
T126	521	0	0	0
T127	19239	0	0	0
T128	603	0	0	0
T129	951	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	668	0	0
T3	1327	0	0	0
T5	790	0	0	0
T16	716	16	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T25	496	0	0	0
T29	471	0	0	0
T31	0	22	0	0
T54	0	13	0	0
T56	0	21	0	0
T57	0	5	0	0
T59	0	21	0	0
T60	0	8	0	0
T61	0	2	0	0
T62	404	0	0	0
T63	725	0	0	0
T108	0	8	0	0
T131	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	88	0	0
T3	1327	0	0	0
T5	790	0	0	0
T16	716	2	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T25	496	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	404	0	0	0
T63	725	0	0	0
T108	0	1	0	0
T131	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5082447	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	152	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5084237	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	152	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	102	0	0
T3	1327	0	0	0
T5	790	0	0	0
T16	716	2	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T24	0	1	0	0
T25	496	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	404	0	0	0
T63	725	0	0	0
T108	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	89	0	0
T3	1327	0	0	0
T5	790	0	0	0
T16	716	2	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T25	496	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	404	0	0	0
T63	725	0	0	0
T108	0	1	0	0
T131	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	88	0	0
T3	1327	0	0	0
T5	790	0	0	0
T16	716	2	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T25	496	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	404	0	0	0
T63	725	0	0	0
T108	0	1	0	0
T131	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	88	0	0
T3	1327	0	0	0
T5	790	0	0	0
T16	716	2	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T25	496	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	404	0	0	0
T63	725	0	0	0
T108	0	1	0	0
T131	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	580	0	0
T3	1327	0	0	0
T5	790	0	0	0
T16	716	14	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T25	496	0	0	0
T29	471	0	0	0
T31	0	21	0	0
T54	0	12	0	0
T56	0	19	0	0
T57	0	4	0	0
T59	0	19	0	0
T60	0	7	0	0
T61	0	1	0	0
T62	404	0	0	0
T63	725	0	0	0
T108	0	7	0	0
T131	0	2	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5398	0	0
T2	681	0	0	0
T3	0	7	0	0
T4	420	1	0	0
T5	0	2	0	0
T12	527	4	0	0
T13	422	2	0	0
T14	452	0	0	0
T15	502	2	0	0
T16	716	3	0	0
T17	491	8	0	0
T18	1786	12	0	0
T23	710	0	0	0
T25	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	87	0	0
T3	1327	0	0	0
T5	790	0	0	0
T16	716	2	0	0
T17	491	0	0	0
T18	1786	0	0	0
T23	710	0	0	0
T25	496	0	0	0
T29	471	0	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	404	0	0	0
T63	725	0	0	0
T108	0	1	0	0
T131	0	1	0	0
T132	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T2 T12 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T24 T10 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T18 T3 T24 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T18 T3 T24 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T24 T10 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T24 T10 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T24 T10 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T24 T10 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T31 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T31 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T24 T10 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T10 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T10 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T66 T107 T99 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T10 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T10 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T10 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T68 T107 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T68 T107 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T10 T11 
191        1/1                      state_d = StableSt;
           Tests:       T3 T10 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T10 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T10 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T10 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T10 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T10 T11 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T10 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T12
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T12
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T24,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T24,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T24,T10
1	0	Covered	T4,T12,T13
1	1	Covered	T3,T24,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T68,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Unreachable
1	0	Covered	T3,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T24,T10
DetectSt	168	Covered	T3,T10,T11
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T11
DebounceSt->IdleSt	163	Covered	T24,T31,T66
DetectSt->IdleSt	186	Covered	T68,T107
DetectSt->StableSt	191	Covered	T3,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T24,T10
StableSt->IdleSt	206	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T24,T10
0	1	Covered	T3,T24,T10
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T24,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T31
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T66,T107,T99
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T24,T10
DetectSt	-	-	-	-	1	-	-	Covered	T68,T107
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	119	0	0
CntIncr_A	5947631	64256	0	0
CntNoWrap_A	5947631	5481121	0	0
DetectStDropOut_A	5947631	2	0	0
DetectedOut_A	5947631	536220	0	0
DetectedPulseOut_A	5947631	37	0	0
DisabledIdleSt_A	5947631	4261343	0	0
DisabledNoDetection_A	5947631	4263170	0	0
EnterDebounceSt_A	5947631	80	0	0
EnterDetectSt_A	5947631	39	0	0
EnterStableSt_A	5947631	37	0	0
PulseIsPulse_A	5947631	37	0	0
StayInStableSt	5947631	536183	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5947631	5398	0	0
gen_low_level_sva.LowLevelEvent_A	5947631	5483067	0	0
gen_sticky_sva.StableStDropOut_A	5947631	562624	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	119	0	0
T3	1327	4	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T24	0	2	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	2	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	3	0	0
T67	0	2	0	0
T68	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	2	0	0
T93	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	64256	0	0
T3	1327	154	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	74	0	0
T11	0	98	0	0
T24	0	44	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	26	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	282	0	0
T67	0	97	0	0
T68	0	95	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	19	0	0
T93	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481121	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	2	0	0
T45	984	0	0	0
T53	8265	0	0	0
T68	3021	1	0	0
T107	0	1	0	0
T141	664	0	0	0
T142	523	0	0	0
T143	1547	0	0	0
T144	447	0	0	0
T145	402	0	0	0
T146	502	0	0	0
T147	1271	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	536220	0	0
T3	1327	218	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	287	0	0
T11	0	163	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T67	0	725	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	86	0	0
T93	0	117	0	0
T133	0	74	0	0
T134	0	70	0	0
T135	0	170	0	0
T136	0	329	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	37	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T67	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T133	0	2	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	4261343	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	4263170	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	80	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T24	0	2	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	2	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	3	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	1	0	0
T93	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	39	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T107	0	1	0	0
T133	0	2	0	0
T134	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	37	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T67	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T133	0	2	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	37	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T67	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T133	0	2	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	536183	0	0
T3	1327	216	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	286	0	0
T11	0	162	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T67	0	724	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	85	0	0
T93	0	116	0	0
T133	0	72	0	0
T134	0	69	0	0
T135	0	169	0	0
T136	0	328	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5398	0	0
T2	681	0	0	0
T3	0	7	0	0
T4	420	1	0	0
T5	0	2	0	0
T12	527	4	0	0
T13	422	2	0	0
T14	452	0	0	0
T15	502	2	0	0
T16	716	3	0	0
T17	491	8	0	0
T18	1786	12	0	0
T23	710	0	0	0
T25	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	562624	0	0
T3	1327	97	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	63	0	0
T11	0	53	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T67	0	89	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	388	0	0
T93	0	57	0	0
T133	0	349	0	0
T134	0	359	0	0
T135	0	45	0	0
T136	0	90	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T2 T12 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T2 T12 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T24 T10 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T18 T3 T24 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T18 T3 T24 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T2 T12 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T2 T12 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T2 T12 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T2 T12 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T2 T12 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T2 T12 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T2 T12 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T2 T12 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T24 T10 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T24 T10 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T24 T10 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T24 T10 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T31 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T31 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T24 T10 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T10 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T10 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T92 T133 T107 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T10 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T10 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T10 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T98 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T98 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T10 T11 
191        1/1                      state_d = StableSt;
           Tests:       T3 T10 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T10 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T10 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T10 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T10 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T10 T11 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T10 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T4,T2,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T4,T2,T12
1	1	Covered	T4,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T24,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T24,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T24,T10
1	0	Covered	T4,T2,T12
1	1	Covered	T3,T24,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Unreachable
1	0	Covered	T3,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T24,T10
DetectSt	168	Covered	T3,T10,T11
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T11
DebounceSt->IdleSt	163	Covered	T24,T31,T92
DetectSt->IdleSt	186	Covered	T98
DetectSt->StableSt	191	Covered	T3,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T24,T10
StableSt->IdleSt	206	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T24,T10
0	1	Covered	T3,T24,T10
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T24,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T31
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T92,T133,T107
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T24,T10
DetectSt	-	-	-	-	1	-	-	Covered	T98
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	117	0	0
CntIncr_A	5947631	70085	0	0
CntNoWrap_A	5947631	5481123	0	0
DetectStDropOut_A	5947631	1	0	0
DetectedOut_A	5947631	318385	0	0
DetectedPulseOut_A	5947631	37	0	0
DisabledIdleSt_A	5947631	4261343	0	0
DisabledNoDetection_A	5947631	4263170	0	0
EnterDebounceSt_A	5947631	79	0	0
EnterDetectSt_A	5947631	38	0	0
EnterStableSt_A	5947631	37	0	0
PulseIsPulse_A	5947631	37	0	0
StayInStableSt	5947631	318348	0	0
gen_high_level_sva.HighLevelEvent_A	5947631	5483067	0	0
gen_sticky_sva.StableStDropOut_A	5947631	827543	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	117	0	0
T3	1327	4	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T24	0	2	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	2	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	3	0	0
T93	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	70085	0	0
T3	1327	174	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	18	0	0
T11	0	23	0	0
T24	0	45	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	24	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	55	0	0
T67	0	79	0	0
T68	0	81	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	249	0	0
T93	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481123	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	1	0	0
T98	32486	1	0	0
T148	64282	0	0	0
T149	4616	0	0	0
T150	20121	0	0	0
T151	6331	0	0	0
T152	23225	0	0	0
T153	10800	0	0	0
T154	22014	0	0	0
T155	18806	0	0	0
T156	8917	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	318385	0	0
T3	1327	220	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	48	0	0
T11	0	56	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	180	0	0
T67	0	510	0	0
T68	0	9	0	0
T69	423	0	0	0
T70	429	0	0	0
T93	0	42	0	0
T99	0	373	0	0
T100	0	236	0	0
T135	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	37	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T93	0	1	0	0
T99	0	1	0	0
T100	0	2	0	0
T135	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	4261343	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	4263170	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	79	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T24	0	2	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	2	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	3	0	0
T93	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	38	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T93	0	1	0	0
T99	0	1	0	0
T100	0	2	0	0
T135	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	37	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T93	0	1	0	0
T99	0	1	0	0
T100	0	2	0	0
T135	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	37	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T93	0	1	0	0
T99	0	1	0	0
T100	0	2	0	0
T135	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	318348	0	0
T3	1327	218	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	47	0	0
T11	0	55	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	179	0	0
T67	0	509	0	0
T68	0	8	0	0
T69	423	0	0	0
T70	429	0	0	0
T93	0	41	0	0
T99	0	372	0	0
T100	0	234	0	0
T135	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	827543	0	0
T3	1327	86	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	351	0	0
T11	0	234	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	204	0	0
T67	0	334	0	0
T68	0	26	0	0
T69	423	0	0	0
T70	429	0	0	0
T93	0	161	0	0
T99	0	278	0	0
T100	0	258	0	0
T135	0	255	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T2 T12 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T4 T2 T12 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T24 T10 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T18 T3 T24 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T18 T3 T24 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T2 T12 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T2 T12 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T2 T12 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T2 T12 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T2 T12 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T2 T12 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T2 T12 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T2 T12 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T24 T10 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T24 T10 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T24 T10 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T24 T10 
163        1/1                    state_d = IdleSt;
           Tests:       T24 T31 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T31 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T24 T10 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T10 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T10 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T68 T99 T100 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T10 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T10 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T10 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T101 T102 T103 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T101 T102 T103 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T10 T11 
191        1/1                      state_d = StableSt;
           Tests:       T3 T10 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T10 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T10 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T10 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T10 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T10 T11 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T10 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T4,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T24,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T24,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T24,T10
1	0	Covered	T4,T2,T12
1	1	Covered	T3,T24,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T101,T102,T103
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Unreachable
1	0	Covered	T3,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T24,T10
DetectSt	168	Covered	T3,T10,T11
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T11
DebounceSt->IdleSt	163	Covered	T24,T31,T68
DetectSt->IdleSt	186	Covered	T101,T102,T103
DetectSt->StableSt	191	Covered	T3,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T24,T10
StableSt->IdleSt	206	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		19	19	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T24,T10
0	1	Covered	T3,T24,T10
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T24,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T24,T31
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T68,T99,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T24,T10
DetectSt	-	-	-	-	1	-	-	Covered	T101,T102,T103
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	124	0	0
CntIncr_A	5947631	55336	0	0
CntNoWrap_A	5947631	5481116	0	0
DetectStDropOut_A	5947631	7	0	0
DetectedOut_A	5947631	189322	0	0
DetectedPulseOut_A	5947631	39	0	0
DisabledIdleSt_A	5947631	4261343	0	0
DisabledNoDetection_A	5947631	4263170	0	0
EnterDebounceSt_A	5947631	78	0	0
EnterDetectSt_A	5947631	46	0	0
EnterStableSt_A	5947631	39	0	0
PulseIsPulse_A	5947631	39	0	0
StayInStableSt	5947631	189283	0	0
gen_high_event_sva.HighLevelEvent_A	5947631	5483067	0	0
gen_high_level_sva.HighLevelEvent_A	5947631	5483067	0	0
gen_sticky_sva.StableStDropOut_A	5947631	708749	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	124	0	0
T3	1327	4	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T24	0	2	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	2	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	2	0	0
T93	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	55336	0	0
T3	1327	62	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	97	0	0
T11	0	27	0	0
T24	0	46	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	25	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	70	0	0
T67	0	47	0	0
T68	0	31	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	57	0	0
T93	0	41	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481116	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	7	0	0
T101	1342	2	0	0
T102	0	2	0	0
T103	0	1	0	0
T157	0	2	0	0
T158	421	0	0	0
T159	146611	0	0	0
T160	484	0	0	0
T161	426	0	0	0
T162	503	0	0	0
T163	502	0	0	0
T164	423	0	0	0
T165	505	0	0	0
T166	1407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	189322	0	0
T3	1327	166	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	242	0	0
T11	0	33	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	253	0	0
T67	0	248	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	234	0	0
T93	0	153	0	0
T99	0	103	0	0
T107	0	204	0	0
T133	0	234	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	39	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T99	0	1	0	0
T107	0	1	0	0
T133	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	4261343	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	4263170	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	78	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T24	0	2	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	2	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	1	0	0
T93	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	46	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T99	0	1	0	0
T107	0	1	0	0
T133	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	39	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T99	0	1	0	0
T107	0	1	0	0
T133	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	39	0	0
T3	1327	2	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T99	0	1	0	0
T107	0	1	0	0
T133	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	189283	0	0
T3	1327	164	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	241	0	0
T11	0	32	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	252	0	0
T67	0	247	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	233	0	0
T93	0	152	0	0
T99	0	102	0	0
T107	0	203	0	0
T133	0	232	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	708749	0	0
T3	1327	266	0	0
T5	790	0	0	0
T6	480	0	0	0
T10	0	94	0	0
T11	0	266	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T62	404	0	0	0
T63	725	0	0	0
T66	0	125	0	0
T67	0	631	0	0
T69	423	0	0	0
T70	429	0	0	0
T92	0	210	0	0
T93	0	41	0	0
T99	0	453	0	0
T107	0	99	0	0
T133	0	88	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T4 T2 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T5 T24 T31 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T5 T24 T31 
149        1/1                    cnt_en = 1'b1;
           Tests:       T5 T24 T31 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T5 T24 T31 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T5 T24 T31 
163        1/1                    state_d = IdleSt;
           Tests:       T24 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 
165        1/1                  end else if (cnt_done) begin
           Tests:       T5 T24 T31 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T5 T31 T47 
167        1/1                    if (trigger_active) begin
           Tests:       T5 T31 T47 
168        1/1                      state_d = DetectSt;
           Tests:       T5 T31 T47 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T95 T167 T168 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T5 T31 T47 
182        1/1                  cnt_en = 1'b1;
           Tests:       T5 T31 T47 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T5 T31 T47 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T5 T31 T47 
191        1/1                      state_d = StableSt;
           Tests:       T5 T31 T47 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T5 T31 T47 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T5 T31 T47 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T5 T31 T47 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T5 T31 T47 
206        1/1                    state_d = IdleSt;
           Tests:       T5 T31 T51 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T5 T31 T47 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T24,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T24,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T31,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T31
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T24,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T47
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T47
0	1	Covered	T5,T51,T169
1	0	Covered	T31

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T31,T47
1	-	Covered	T5,T51,T169

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T24,T31
DetectSt	168	Covered	T5,T31,T47
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T31,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T31,T47
DebounceSt->IdleSt	163	Covered	T24,T95,T167
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T5,T31,T47
IdleSt->DebounceSt	148	Covered	T5,T24,T31
StableSt->IdleSt	206	Covered	T5,T31,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T24,T31
0	1	Covered	T5,T24,T31
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T31,T47
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T24,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T31,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T95,T167,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T24,T31
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T5,T31,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T31,T51
StableSt	-	-	-	-	-	-	0	Covered	T5,T31,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	64	0	0
CntIncr_A	5947631	43324	0	0
CntNoWrap_A	5947631	5481176	0	0
DetectStDropOut_A	5947631	0	0	0
DetectedOut_A	5947631	1983	0	0
DetectedPulseOut_A	5947631	30	0	0
DisabledIdleSt_A	5947631	5299315	0	0
DisabledNoDetection_A	5947631	5301101	0	0
EnterDebounceSt_A	5947631	34	0	0
EnterDetectSt_A	5947631	30	0	0
EnterStableSt_A	5947631	30	0	0
PulseIsPulse_A	5947631	30	0	0
StayInStableSt	5947631	1934	0	0
gen_high_level_sva.HighLevelEvent_A	5947631	5483067	0	0
gen_not_sticky_sva.StableStDropOut_A	5947631	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	64	0	0
T5	790	2	0	0
T6	480	0	0	0
T24	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	2	0	0
T43	0	2	0	0
T45	0	2	0	0
T47	0	2	0	0
T51	0	4	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	4	0	0
T95	0	1	0	0
T169	0	2	0	0
T170	404	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	43324	0	0
T5	790	35	0	0
T6	480	0	0	0
T24	0	23	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	29	0	0
T43	0	45	0	0
T45	0	65	0	0
T47	0	31	0	0
T51	0	188	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	170	0	0
T95	0	21	0	0
T169	0	38	0	0
T170	404	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481176	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	1983	0	0
T5	790	204	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	17	0	0
T43	0	48	0	0
T45	0	75	0	0
T47	0	74	0	0
T51	0	93	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	228	0	0
T167	0	106	0	0
T169	0	30	0	0
T170	404	0	0	0
T171	0	124	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	30	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T51	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	2	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	404	0	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5299315	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5301101	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	34	0	0
T5	790	1	0	0
T6	480	0	0	0
T24	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T51	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	2	0	0
T95	0	1	0	0
T169	0	1	0	0
T170	404	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	30	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T51	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	2	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	404	0	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	30	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T51	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	2	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	404	0	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	30	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T51	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	2	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	404	0	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	1934	0	0
T5	790	203	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	16	0	0
T43	0	46	0	0
T45	0	73	0	0
T47	0	72	0	0
T51	0	90	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	225	0	0
T167	0	104	0	0
T169	0	29	0	0
T170	404	0	0	0
T171	0	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	10	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T51	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	1	0	0
T105	0	1	0	0
T169	0	1	0	0
T170	404	0	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T4 T2 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T2 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T2 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T2 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T5 T24 T31 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T2 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T2 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T5 T24 T31 
149        1/1                    cnt_en = 1'b1;
           Tests:       T5 T24 T31 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T5 T24 T31 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T5 T24 T31 
163        1/1                    state_d = IdleSt;
           Tests:       T24 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T24 
165        1/1                  end else if (cnt_done) begin
           Tests:       T5 T24 T31 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T5 T31 T47 
167        1/1                    if (trigger_active) begin
           Tests:       T5 T31 T47 
168        1/1                      state_d = DetectSt;
           Tests:       T5 T31 T47 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T51 T172 T177 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T5 T31 T47 
182        1/1                  cnt_en = 1'b1;
           Tests:       T5 T31 T47 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T5 T31 T47 
186        1/1                    state_d = IdleSt;
           Tests:       T94 T105 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T94 T105 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T5 T31 T47 
191        1/1                      state_d = StableSt;
           Tests:       T5 T31 T47 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T5 T31 T47 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T5 T31 T47 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T5 T31 T47 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T5 T31 T47 
206        1/1                    state_d = IdleSt;
           Tests:       T5 T31 T47 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T5 T31 T47 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T2 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T2 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T24,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T24,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T31,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T8
1	0	Covered	T4,T12,T13
1	1	Covered	T5,T24,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T47
0	1	Covered	T94,T105
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T47
0	1	Covered	T5,T47,T43
1	0	Covered	T31

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T31,T47
1	-	Covered	T5,T47,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T24,T31
DetectSt	168	Covered	T5,T31,T47
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T31,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T31,T47
DebounceSt->IdleSt	163	Covered	T24,T51,T172
DetectSt->IdleSt	186	Covered	T94,T105
DetectSt->StableSt	191	Covered	T5,T31,T47
IdleSt->DebounceSt	148	Covered	T5,T24,T31
StableSt->IdleSt	206	Covered	T5,T31,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T24,T31
0	1	Covered	T5,T24,T31
0	0	Covered	T1,T4,T2

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T31,T47
0	Covered	T1,T4,T2

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T24,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T24
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T31,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T172,T177
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T24,T31
DetectSt	-	-	-	-	1	-	-	Covered	T94,T105
DetectSt	-	-	-	-	0	1	-	Covered	T5,T31,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T31,T47
StableSt	-	-	-	-	-	-	0	Covered	T5,T31,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5947631	78	0	0
CntIncr_A	5947631	85000	0	0
CntNoWrap_A	5947631	5481162	0	0
DetectStDropOut_A	5947631	2	0	0
DetectedOut_A	5947631	48268	0	0
DetectedPulseOut_A	5947631	35	0	0
DisabledIdleSt_A	5947631	5301081	0	0
DisabledNoDetection_A	5947631	5302874	0	0
EnterDebounceSt_A	5947631	41	0	0
EnterDetectSt_A	5947631	37	0	0
EnterStableSt_A	5947631	35	0	0
PulseIsPulse_A	5947631	35	0	0
StayInStableSt	5947631	48220	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5947631	1660	0	0
gen_low_level_sva.LowLevelEvent_A	5947631	5483067	0	0
gen_not_sticky_sva.StableStDropOut_A	5947631	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	78	0	0
T5	790	4	0	0
T6	480	0	0	0
T24	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T45	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T51	0	3	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T170	404	0	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	85000	0	0
T5	790	70	0	0
T6	480	0	0	0
T24	0	22	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	29	0	0
T43	0	45	0	0
T44	0	32	0	0
T45	0	65	0	0
T47	0	31	0	0
T48	0	51	0	0
T51	0	188	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T170	404	0	0	0
T178	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5481162	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	2	0	0
T94	2603	1	0	0
T105	0	1	0	0
T133	1533	0	0	0
T179	732	0	0	0
T180	673	0	0	0
T181	502	0	0	0
T182	492	0	0	0
T183	442	0	0	0
T184	499	0	0	0
T185	696	0	0	0
T186	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	48268	0	0
T5	790	69	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	16	0	0
T43	0	107	0	0
T44	0	137	0	0
T45	0	368	0	0
T47	0	98	0	0
T48	0	289	0	0
T51	0	36	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	236	0	0
T170	404	0	0	0
T178	0	116	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	35	0	0
T5	790	2	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	2	0	0
T170	404	0	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5301081	0	0
T1	483	82	0	0
T2	681	280	0	0
T4	420	19	0	0
T12	527	126	0	0
T13	422	21	0	0
T14	452	51	0	0
T15	502	101	0	0
T16	716	315	0	0
T17	491	90	0	0
T18	1786	1385	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5302874	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	41	0	0
T5	790	2	0	0
T6	480	0	0	0
T24	0	1	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	2	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T170	404	0	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	37	0	0
T5	790	2	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	3	0	0
T170	404	0	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	35	0	0
T5	790	2	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	2	0	0
T170	404	0	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	35	0	0
T5	790	2	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	2	0	0
T170	404	0	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	48220	0	0
T5	790	66	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T31	0	15	0	0
T43	0	106	0	0
T44	0	134	0	0
T45	0	367	0	0
T47	0	97	0	0
T48	0	288	0	0
T51	0	35	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	233	0	0
T170	404	0	0	0
T178	0	114	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	1660	0	0
T2	681	0	0	0
T4	420	2	0	0
T5	0	2	0	0
T12	527	4	0	0
T13	422	2	0	0
T14	452	0	0	0
T15	502	7	0	0
T16	716	0	0	0
T17	491	6	0	0
T18	1786	0	0	0
T23	710	0	0	0
T25	0	4	0	0
T27	0	5	0	0
T69	0	2	0	0
T70	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	5483067	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947631	21	0	0
T5	790	1	0	0
T6	480	0	0	0
T25	496	0	0	0
T27	523	0	0	0
T29	471	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T69	423	0	0	0
T70	429	0	0	0
T80	502	0	0	0
T81	1447	0	0	0
T94	0	1	0	0
T170	404	0	0	0
T171	0	1	0	0
T172	0	1	0	0