Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	95.65	90.91		83.33	95.24	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	95.65	90.91		83.33	95.24	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T23 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T29 T30 T67 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T20 T29 T30 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T20 T29 T30 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T29 T30 T67 
149        1/1                    cnt_en = 1'b1;
           Tests:       T29 T30 T67 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T29 T30 T67 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T29 T30 T67 
163        1/1                    state_d = IdleSt;
           Tests:       T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T29 T30 T67 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T30 T67 
167        1/1                    if (trigger_active) begin
           Tests:       T29 T30 T67 
168        1/1                      state_d = DetectSt;
           Tests:       T29 T30 T67 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T69 T72 T114 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T29 T30 T67 
182        1/1                  cnt_en = 1'b1;
           Tests:       T29 T30 T67 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T29 T30 T67 
186        1/1                    state_d = IdleSt;
           Tests:       T117 T118 T121 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T117 T118 T121 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T29 T30 T67 
191        1/1                      state_d = StableSt;
           Tests:       T29 T30 T67 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T29 T30 T67 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T29 T30 T67 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T29 T30 T67 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T29 T30 T67 
206        1/1                    state_d = IdleSt;
           Tests:       T29 T30 T67 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T29 T30 T67 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T30,T67

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T30,T67

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T30,T67

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T67
1	0	Covered	T4,T5,T23
1	1	Covered	T29,T30,T67

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T67
0	1	Covered	T117,T118,T121
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T67
0	1	Covered	T29,T30,T67
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T30,T67
1	-	Covered	T29,T30,T67

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T30,T67
DetectSt	168	Covered	T29,T30,T67
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T29,T30,T67

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T30,T67
DebounceSt->IdleSt	163	Covered	T69,T72,T114
DetectSt->IdleSt	186	Covered	T117,T118,T121
DetectSt->StableSt	191	Covered	T29,T30,T67
IdleSt->DebounceSt	148	Covered	T29,T30,T67
StableSt->IdleSt	206	Covered	T29,T30,T67

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T30,T67
0	1	Covered	T29,T30,T67
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T67
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T30,T67
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T30,T67
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T72,T114
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T30,T67
DetectSt	-	-	-	-	1	-	-	Covered	T117,T118,T121
DetectSt	-	-	-	-	0	1	-	Covered	T29,T30,T67
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T30,T67
StableSt	-	-	-	-	-	-	0	Covered	T29,T30,T67
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	172	0	0
CntIncr_A	6803201	126443	0	0
CntNoWrap_A	6803201	6337914	0	0
DetectStDropOut_A	6803201	3	0	0
DetectedOut_A	6803201	538	0	0
DetectedPulseOut_A	6803201	76	0	0
DisabledIdleSt_A	6803201	6207699	0	0
DisabledNoDetection_A	6803201	6209623	0	0
EnterDebounceSt_A	6803201	94	0	0
EnterDetectSt_A	6803201	79	0	0
EnterStableSt_A	6803201	76	0	0
PulseIsPulse_A	6803201	76	0	0
StayInStableSt	6803201	462	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6803201	5685	0	0
gen_low_level_sva.LowLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	74	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	172	0	0
T9	494	0	0	0
T10	506	0	0	0
T28	495	0	0	0
T29	656	2	0	0
T30	650	2	0	0
T31	463	0	0	0
T65	445	0	0	0
T67	0	2	0	0
T69	0	7	0	0
T70	0	4	0	0
T71	0	4	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	4	0	0
T93	526	0	0	0
T114	0	3	0	0
T115	405	0	0	0
T116	427	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	126443	0	0
T9	494	0	0	0
T10	506	0	0	0
T28	495	0	0	0
T29	656	41	0	0
T30	650	36	0	0
T31	463	0	0	0
T65	445	0	0	0
T67	0	10	0	0
T69	0	153	0	0
T70	0	174	0	0
T71	0	102	0	0
T72	0	12	0	0
T73	0	47	0	0
T74	0	86	0	0
T93	526	0	0	0
T114	0	111	0	0
T115	405	0	0	0
T116	427	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6337914	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	3	0	0
T43	25643	0	0	0
T44	7393	0	0	0
T63	11190	0	0	0
T99	4816	0	0	0
T117	2468	1	0	0
T118	0	1	0	0
T121	0	1	0	0
T135	1588	0	0	0
T136	503	0	0	0
T137	577	0	0	0
T138	402	0	0	0
T139	2404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	538	0	0
T9	494	0	0	0
T10	506	0	0	0
T28	495	0	0	0
T29	656	11	0	0
T30	650	8	0	0
T31	463	0	0	0
T65	445	0	0	0
T67	0	3	0	0
T69	0	22	0	0
T70	0	19	0	0
T71	0	19	0	0
T73	0	1	0	0
T74	0	23	0	0
T93	526	0	0	0
T114	0	12	0	0
T115	405	0	0	0
T116	427	0	0	0
T128	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	76	0	0
T9	494	0	0	0
T10	506	0	0	0
T28	495	0	0	0
T29	656	1	0	0
T30	650	1	0	0
T31	463	0	0	0
T65	445	0	0	0
T67	0	1	0	0
T69	0	3	0	0
T70	0	2	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T93	526	0	0	0
T114	0	1	0	0
T115	405	0	0	0
T116	427	0	0	0
T128	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6207699	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6209623	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	94	0	0
T9	494	0	0	0
T10	506	0	0	0
T28	495	0	0	0
T29	656	1	0	0
T30	650	1	0	0
T31	463	0	0	0
T65	445	0	0	0
T67	0	1	0	0
T69	0	4	0	0
T70	0	2	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T93	526	0	0	0
T114	0	2	0	0
T115	405	0	0	0
T116	427	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	79	0	0
T9	494	0	0	0
T10	506	0	0	0
T28	495	0	0	0
T29	656	1	0	0
T30	650	1	0	0
T31	463	0	0	0
T65	445	0	0	0
T67	0	1	0	0
T69	0	3	0	0
T70	0	2	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T93	526	0	0	0
T114	0	1	0	0
T115	405	0	0	0
T116	427	0	0	0
T128	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	76	0	0
T9	494	0	0	0
T10	506	0	0	0
T28	495	0	0	0
T29	656	1	0	0
T30	650	1	0	0
T31	463	0	0	0
T65	445	0	0	0
T67	0	1	0	0
T69	0	3	0	0
T70	0	2	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T93	526	0	0	0
T114	0	1	0	0
T115	405	0	0	0
T116	427	0	0	0
T128	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	76	0	0
T9	494	0	0	0
T10	506	0	0	0
T28	495	0	0	0
T29	656	1	0	0
T30	650	1	0	0
T31	463	0	0	0
T65	445	0	0	0
T67	0	1	0	0
T69	0	3	0	0
T70	0	2	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T93	526	0	0	0
T114	0	1	0	0
T115	405	0	0	0
T116	427	0	0	0
T128	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	462	0	0
T9	494	0	0	0
T10	506	0	0	0
T28	495	0	0	0
T29	656	10	0	0
T30	650	7	0	0
T31	463	0	0	0
T65	445	0	0	0
T67	0	2	0	0
T69	0	19	0	0
T70	0	17	0	0
T71	0	17	0	0
T74	0	21	0	0
T93	526	0	0	0
T114	0	11	0	0
T115	405	0	0	0
T116	427	0	0	0
T128	0	7	0	0
T142	0	15	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5685	0	0
T1	486	0	0	0
T3	0	6	0	0
T4	505	6	0	0
T5	421	3	0	0
T6	460	0	0	0
T14	493	8	0	0
T15	445	2	0	0
T16	891	0	0	0
T17	527	5	0	0
T18	423	1	0	0
T20	0	3	0	0
T21	0	7	0	0
T23	421	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	74	0	0
T9	494	0	0	0
T10	506	0	0	0
T28	495	0	0	0
T29	656	1	0	0
T30	650	1	0	0
T31	463	0	0	0
T65	445	0	0	0
T67	0	1	0	0
T69	0	3	0	0
T70	0	2	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T93	526	0	0	0
T114	0	1	0	0
T115	405	0	0	0
T116	427	0	0	0
T128	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T23 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T8 T12 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T3 T7 T8 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T3 T7 T8 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T8 T12 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T8 T12 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T8 T12 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T8 T12 
163        1/1                    state_d = IdleSt;
           Tests:       T49 T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T49 T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T8 T12 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T8 T12 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T8 T12 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T8 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T12 T79 T143 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T8 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T8 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T8 T12 
186        1/1                    state_d = IdleSt;
           Tests:       T12 T80 T109 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T80 T109 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T8 T78 
191        1/1                      state_d = StableSt;
           Tests:       T3 T8 T78 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T8 T78 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T8 T78 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T8 T78 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T8 T78 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T8 T78 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T8 T78 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T12
1	0	Covered	T4,T5,T23
1	1	Covered	T3,T8,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T78
0	1	Covered	T12,T80,T109
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T78
0	1	Unreachable
1	0	Covered	T3,T8,T78

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T12
DetectSt	168	Covered	T3,T8,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T78

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T12
DebounceSt->IdleSt	163	Covered	T12,T79,T143
DetectSt->IdleSt	186	Covered	T12,T80,T109
DetectSt->StableSt	191	Covered	T3,T8,T78
IdleSt->DebounceSt	148	Covered	T3,T8,T12
StableSt->IdleSt	206	Covered	T3,T8,T78

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T8,T12
0	1	Covered	T3,T8,T12
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T12
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T62
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T79,T143
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T12
DetectSt	-	-	-	-	1	-	-	Covered	T12,T80,T109
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T78
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T78
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T78
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	150	0	0
CntIncr_A	6803201	249871	0	0
CntNoWrap_A	6803201	6337936	0	0
DetectStDropOut_A	6803201	13	0	0
DetectedOut_A	6803201	28153	0	0
DetectedPulseOut_A	6803201	41	0	0
DisabledIdleSt_A	6803201	4706387	0	0
DisabledNoDetection_A	6803201	4708337	0	0
EnterDebounceSt_A	6803201	98	0	0
EnterDetectSt_A	6803201	54	0	0
EnterStableSt_A	6803201	41	0	0
PulseIsPulse_A	6803201	41	0	0
StayInStableSt	6803201	28112	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6803201	5685	0	0
gen_low_level_sva.LowLevelEvent_A	6803201	6340037	0	0
gen_sticky_sva.StableStDropOut_A	6803201	780321	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	150	0	0
T3	1051	2	0	0
T7	2883	0	0	0
T8	1058	2	0	0
T12	0	13	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	2	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	4	0	0
T79	0	5	0	0
T80	0	6	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	4	0	0
T84	449	0	0	0
T85	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	249871	0	0
T3	1051	63	0	0
T7	2883	0	0	0
T8	1058	39	0	0
T12	0	315	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	32	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	164	0	0
T79	0	225	0	0
T80	0	30	0	0
T81	0	28	0	0
T82	0	63	0	0
T83	0	22	0	0
T84	449	0	0	0
T85	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6337936	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	13	0	0
T12	1227	6	0	0
T13	597	0	0	0
T40	531	0	0	0
T78	1358	0	0	0
T80	0	2	0	0
T86	1137	0	0	0
T89	496	0	0	0
T109	0	3	0	0
T147	0	2	0	0
T148	437	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	28153	0	0
T3	1051	219	0	0
T7	2883	0	0	0
T8	1058	118	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	237	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	357	0	0
T80	0	1	0	0
T81	0	131	0	0
T82	0	177	0	0
T83	0	108	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	337	0	0
T144	0	132	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	41	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	1	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	2	0	0
T144	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	4706387	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	4708337	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	98	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	1	0	0
T12	0	7	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	2	0	0
T79	0	5	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	449	0	0	0
T85	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	54	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	1	0	0
T12	0	6	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	2	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	41	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	1	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	2	0	0
T144	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	41	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	1	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	2	0	0
T144	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	28112	0	0
T3	1051	218	0	0
T7	2883	0	0	0
T8	1058	117	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	236	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	355	0	0
T81	0	130	0	0
T82	0	176	0	0
T83	0	106	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	335	0	0
T144	0	131	0	0
T145	0	100	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5685	0	0
T1	486	0	0	0
T3	0	6	0	0
T4	505	6	0	0
T5	421	3	0	0
T6	460	0	0	0
T14	493	8	0	0
T15	445	2	0	0
T16	891	0	0	0
T17	527	5	0	0
T18	423	1	0	0
T20	0	3	0	0
T21	0	7	0	0
T23	421	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	780321	0	0
T3	1051	119	0	0
T7	2883	0	0	0
T8	1058	91	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	306	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	202	0	0
T80	0	200	0	0
T81	0	347	0	0
T82	0	39	0	0
T83	0	391	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	315	0	0
T144	0	79	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T23 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T23 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T8 T12 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T3 T7 T8 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T3 T7 T8 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T23 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T23 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T23 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T23 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T23 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T23 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T23 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T23 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T8 T12 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T8 T12 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T8 T12 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T8 T12 
163        1/1                    state_d = IdleSt;
           Tests:       T49 T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T49 T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T8 T12 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T8 T12 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T8 T12 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T12 T78 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T8 T12 T81 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T12 T78 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T12 T78 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T12 T78 
186        1/1                    state_d = IdleSt;
           Tests:       T12 T82 T113 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T82 T113 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T12 T78 
191        1/1                      state_d = StableSt;
           Tests:       T3 T12 T78 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T12 T78 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T12 T78 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T12 T78 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T12 T78 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T12 T78 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T12 T78 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T23
1	1	Covered	T4,T5,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T78

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T12
1	0	Covered	T4,T5,T23
1	1	Covered	T3,T8,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T78
0	1	Covered	T12,T82,T113
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T78
0	1	Unreachable
1	0	Covered	T3,T12,T78

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T12
DetectSt	168	Covered	T3,T12,T78
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T12,T78

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T12,T78
DebounceSt->IdleSt	163	Covered	T8,T12,T81
DetectSt->IdleSt	186	Covered	T12,T82,T113
DetectSt->StableSt	191	Covered	T3,T12,T78
IdleSt->DebounceSt	148	Covered	T3,T8,T12
StableSt->IdleSt	206	Covered	T3,T12,T78

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T8,T12
0	1	Covered	T3,T8,T12
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T78
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T62
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T12,T78
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T12,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T12
DetectSt	-	-	-	-	1	-	-	Covered	T12,T82,T113
DetectSt	-	-	-	-	0	1	-	Covered	T3,T12,T78
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T12,T78
StableSt	-	-	-	-	-	-	0	Covered	T3,T12,T78
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	160	0	0
CntIncr_A	6803201	93259	0	0
CntNoWrap_A	6803201	6337926	0	0
DetectStDropOut_A	6803201	12	0	0
DetectedOut_A	6803201	373192	0	0
DetectedPulseOut_A	6803201	39	0	0
DisabledIdleSt_A	6803201	4706387	0	0
DisabledNoDetection_A	6803201	4708337	0	0
EnterDebounceSt_A	6803201	111	0	0
EnterDetectSt_A	6803201	51	0	0
EnterStableSt_A	6803201	39	0	0
PulseIsPulse_A	6803201	39	0	0
StayInStableSt	6803201	373153	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_sticky_sva.StableStDropOut_A	6803201	602906	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	160	0	0
T3	1051	2	0	0
T7	2883	0	0	0
T8	1058	2	0	0
T12	0	5	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	2	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	4	0	0
T79	0	4	0	0
T80	0	4	0	0
T81	0	4	0	0
T82	0	3	0	0
T83	0	4	0	0
T84	449	0	0	0
T85	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	93259	0	0
T3	1051	65	0	0
T7	2883	0	0	0
T8	1058	142	0	0
T12	0	75	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	87	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	164	0	0
T79	0	26	0	0
T80	0	194	0	0
T81	0	228	0	0
T82	0	170	0	0
T83	0	88	0	0
T84	449	0	0	0
T85	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6337926	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	12	0	0
T12	1227	1	0	0
T13	597	0	0	0
T40	531	0	0	0
T78	1358	0	0	0
T82	0	1	0	0
T86	1137	0	0	0
T89	496	0	0	0
T113	0	2	0	0
T148	437	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T152	0	1	0	0
T153	0	5	0	0
T154	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	373192	0	0
T3	1051	265	0	0
T7	2883	0	0	0
T8	1058	0	0	0
T12	0	106	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	392	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	521	0	0
T79	0	89	0	0
T80	0	581	0	0
T83	0	279	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	211	0	0
T143	0	5	0	0
T144	0	49	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	39	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	0	0	0
T12	0	1	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	2	0	0
T83	0	2	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	4706387	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	4708337	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	111	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	2	0	0
T12	0	3	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	2	0	0
T81	0	4	0	0
T82	0	2	0	0
T83	0	2	0	0
T84	449	0	0	0
T85	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	51	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	0	0	0
T12	0	2	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	2	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	4	0	0
T143	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	39	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	0	0	0
T12	0	1	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	2	0	0
T83	0	2	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	39	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	0	0	0
T12	0	1	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	2	0	0
T83	0	2	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	373153	0	0
T3	1051	264	0	0
T7	2883	0	0	0
T8	1058	0	0	0
T12	0	105	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	391	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	519	0	0
T79	0	87	0	0
T80	0	579	0	0
T83	0	277	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	209	0	0
T143	0	4	0	0
T144	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	602906	0	0
T3	1051	68	0	0
T7	2883	0	0	0
T8	1058	0	0	0
T12	0	203	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	94	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	157	0	0
T79	0	248	0	0
T80	0	98	0	0
T83	0	135	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	200	0	0
T143	0	75	0	0
T144	0	222	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T23 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T4 T5 T23 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T8 T12 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T3 T7 T8 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T3 T7 T8 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T23 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T23 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T23 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T23 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T23 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T23 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T23 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T23 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T8 T12 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T8 T12 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T8 T12 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T8 T12 
163        1/1                    state_d = IdleSt;
           Tests:       T49 T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T49 T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T8 T12 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T8 T12 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T8 T12 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T8 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T78 T79 T82 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T8 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T8 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T8 T12 
186        1/1                    state_d = IdleSt;
           Tests:       T82 T83 T109 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T82 T83 T109 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T8 T12 
191        1/1                      state_d = StableSt;
           Tests:       T3 T8 T12 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T8 T12 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T8 T12 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T8 T12 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T8 T12 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T8 T12 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T8 T12 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T12
1	0	Covered	T4,T5,T23
1	1	Covered	T3,T8,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T12
0	1	Covered	T82,T83,T109
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T12
0	1	Unreachable
1	0	Covered	T3,T8,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T12
DetectSt	168	Covered	T3,T8,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T12
DebounceSt->IdleSt	163	Covered	T78,T79,T82
DetectSt->IdleSt	186	Covered	T82,T83,T109
DetectSt->StableSt	191	Covered	T3,T8,T12
IdleSt->DebounceSt	148	Covered	T3,T8,T12
StableSt->IdleSt	206	Covered	T3,T8,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		19	19	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T8,T12
0	1	Covered	T3,T8,T12
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T12
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T62
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T79,T82
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T12
DetectSt	-	-	-	-	1	-	-	Covered	T82,T83,T109
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T12
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	165	0	0
CntIncr_A	6803201	708232	0	0
CntNoWrap_A	6803201	6337921	0	0
DetectStDropOut_A	6803201	17	0	0
DetectedOut_A	6803201	191304	0	0
DetectedPulseOut_A	6803201	36	0	0
DisabledIdleSt_A	6803201	4706387	0	0
DisabledNoDetection_A	6803201	4708337	0	0
EnterDebounceSt_A	6803201	114	0	0
EnterDetectSt_A	6803201	53	0	0
EnterStableSt_A	6803201	36	0	0
PulseIsPulse_A	6803201	36	0	0
StayInStableSt	6803201	191268	0	0
gen_high_event_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_sticky_sva.StableStDropOut_A	6803201	360643	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	165	0	0
T3	1051	2	0	0
T7	2883	0	0	0
T8	1058	2	0	0
T12	0	4	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	2	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	7	0	0
T79	0	5	0	0
T80	0	4	0	0
T81	0	2	0	0
T82	0	3	0	0
T83	0	9	0	0
T84	449	0	0	0
T85	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	708232	0	0
T3	1051	25	0	0
T7	2883	0	0	0
T8	1058	11	0	0
T12	0	44	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	79	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	196	0	0
T79	0	150	0	0
T80	0	46	0	0
T81	0	62	0	0
T82	0	82	0	0
T83	0	205	0	0
T84	449	0	0	0
T85	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6337921	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	17	0	0
T35	11234	0	0	0
T82	1430	1	0	0
T83	0	3	0	0
T109	0	4	0	0
T126	529	0	0	0
T127	755	0	0	0
T128	660	0	0	0
T129	522	0	0	0
T130	424	0	0	0
T131	672	0	0	0
T132	490	0	0	0
T133	790	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T158	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	191304	0	0
T3	1051	88	0	0
T7	2883	0	0	0
T8	1058	20	0	0
T12	0	233	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	322	0	0
T75	423	0	0	0
T76	403	0	0	0
T80	0	69	0	0
T81	0	216	0	0
T83	0	44	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	519	0	0
T145	0	69	0	0
T146	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	36	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	1	0	0
T12	0	2	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T80	0	2	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	4706387	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	4708337	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	114	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	1	0	0
T12	0	2	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T78	0	7	0	0
T79	0	5	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	5	0	0
T84	449	0	0	0
T85	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	53	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	1	0	0
T12	0	2	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	4	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	2	0	0
T145	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	36	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	1	0	0
T12	0	2	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T80	0	2	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	36	0	0
T3	1051	1	0	0
T7	2883	0	0	0
T8	1058	1	0	0
T12	0	2	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	1	0	0
T75	423	0	0	0
T76	403	0	0	0
T80	0	2	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	191268	0	0
T3	1051	87	0	0
T7	2883	0	0	0
T8	1058	19	0	0
T12	0	231	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	321	0	0
T75	423	0	0	0
T76	403	0	0	0
T80	0	67	0	0
T81	0	215	0	0
T83	0	43	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	517	0	0
T145	0	68	0	0
T146	0	36	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	360643	0	0
T3	1051	291	0	0
T7	2883	0	0	0
T8	1058	234	0	0
T12	0	226	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T69	0	177	0	0
T75	423	0	0	0
T76	403	0	0	0
T80	0	781	0	0
T81	0	231	0	0
T83	0	91	0	0
T84	449	0	0	0
T85	502	0	0	0
T113	0	95	0	0
T145	0	456	0	0
T146	0	312	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T58 T55 T48 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T58 T55 T48 
149        1/1                    cnt_en = 1'b1;
           Tests:       T58 T55 T48 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T58 T55 T48 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T58 T55 T48 
163        1/1                    state_d = IdleSt;
           Tests:       T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T58 T55 T48 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T58 T55 T48 
167        1/1                    if (trigger_active) begin
           Tests:       T58 T55 T48 
168        1/1                      state_d = DetectSt;
           Tests:       T58 T55 T48 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T159 T160 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T58 T55 T48 
182        1/1                  cnt_en = 1'b1;
           Tests:       T58 T55 T48 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T58 T55 T48 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T58 T55 T48 
191        1/1                      state_d = StableSt;
           Tests:       T58 T55 T48 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T58 T55 T48 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T58 T55 T48 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T58 T55 T48 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T58 T55 T48 
206        1/1                    state_d = IdleSt;
           Tests:       T48 T52 T49 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T58 T55 T48 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T58,T55,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T58,T55,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T58,T55,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T58,T55,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T58,T55,T48
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T58,T55,T48
0	1	Covered	T48,T52,T161
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T58,T55,T48
1	-	Covered	T48,T52,T161

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T58,T55,T48
DetectSt	168	Covered	T58,T55,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T58,T55,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T58,T55,T48
DebounceSt->IdleSt	163	Covered	T62,T159,T160
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T58,T55,T48
IdleSt->DebounceSt	148	Covered	T58,T55,T48
StableSt->IdleSt	206	Covered	T48,T52,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T58,T55,T48
0	1	Covered	T58,T55,T48
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T55,T48
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T58,T55,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T58,T55,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T159,T160
DebounceSt	-	0	0	-	-	-	-	Covered	T58,T55,T48
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T58,T55,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T52,T49
StableSt	-	-	-	-	-	-	0	Covered	T58,T55,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	51	0	0
CntIncr_A	6803201	11384	0	0
CntNoWrap_A	6803201	6338035	0	0
DetectStDropOut_A	6803201	0	0	0
DetectedOut_A	6803201	1827	0	0
DetectedPulseOut_A	6803201	24	0	0
DisabledIdleSt_A	6803201	6263758	0	0
DisabledNoDetection_A	6803201	6265678	0	0
EnterDebounceSt_A	6803201	27	0	0
EnterDetectSt_A	6803201	24	0	0
EnterStableSt_A	6803201	24	0	0
PulseIsPulse_A	6803201	24	0	0
StayInStableSt	6803201	1793	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	51	0	0
T48	0	4	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	498	0	0	0
T52	0	2	0	0
T55	0	2	0	0
T56	546	0	0	0
T58	1031	2	0	0
T62	0	1	0	0
T70	765	0	0	0
T71	646	0	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	2	0	0
T164	526	0	0	0
T165	724	0	0	0
T166	402	0	0	0
T167	522	0	0	0
T168	508	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	11384	0	0
T48	0	90	0	0
T49	0	16	0	0
T50	0	47	0	0
T51	498	0	0	0
T52	0	17	0	0
T55	0	13	0	0
T56	546	0	0	0
T58	1031	78	0	0
T62	0	39	0	0
T70	765	0	0	0
T71	646	0	0	0
T161	0	30	0	0
T162	0	26	0	0
T163	0	94	0	0
T164	526	0	0	0
T165	724	0	0	0
T166	402	0	0	0
T167	522	0	0	0
T168	508	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6338035	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1827	0	0
T48	0	85	0	0
T49	0	18	0	0
T50	0	55	0	0
T51	498	0	0	0
T52	0	16	0	0
T55	0	41	0	0
T56	546	0	0	0
T58	1031	240	0	0
T70	765	0	0	0
T71	646	0	0	0
T161	0	43	0	0
T162	0	136	0	0
T163	0	297	0	0
T164	526	0	0	0
T165	724	0	0	0
T166	402	0	0	0
T167	522	0	0	0
T168	508	0	0	0
T169	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	24	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	498	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	546	0	0	0
T58	1031	1	0	0
T70	765	0	0	0
T71	646	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	526	0	0	0
T165	724	0	0	0
T166	402	0	0	0
T167	522	0	0	0
T168	508	0	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6263758	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6265678	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	27	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	498	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	546	0	0	0
T58	1031	1	0	0
T62	0	1	0	0
T70	765	0	0	0
T71	646	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	526	0	0	0
T165	724	0	0	0
T166	402	0	0	0
T167	522	0	0	0
T168	508	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	24	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	498	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	546	0	0	0
T58	1031	1	0	0
T70	765	0	0	0
T71	646	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	526	0	0	0
T165	724	0	0	0
T166	402	0	0	0
T167	522	0	0	0
T168	508	0	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	24	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	498	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	546	0	0	0
T58	1031	1	0	0
T70	765	0	0	0
T71	646	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	526	0	0	0
T165	724	0	0	0
T166	402	0	0	0
T167	522	0	0	0
T168	508	0	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	24	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	498	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	546	0	0	0
T58	1031	1	0	0
T70	765	0	0	0
T71	646	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	526	0	0	0
T165	724	0	0	0
T166	402	0	0	0
T167	522	0	0	0
T168	508	0	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1793	0	0
T48	0	82	0	0
T49	0	17	0	0
T50	0	53	0	0
T51	498	0	0	0
T52	0	15	0	0
T55	0	39	0	0
T56	546	0	0	0
T58	1031	238	0	0
T70	765	0	0	0
T71	646	0	0	0
T161	0	42	0	0
T162	0	134	0	0
T163	0	295	0	0
T164	526	0	0	0
T165	724	0	0	0
T166	402	0	0	0
T167	522	0	0	0
T168	508	0	0	0
T169	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	13	0	0
T35	11234	0	0	0
T48	3129	1	0	0
T52	0	1	0	0
T53	771	0	0	0
T81	3731	0	0	0
T82	1430	0	0	0
T114	678	0	0	0
T126	529	0	0	0
T127	755	0	0	0
T161	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	2	0	0
T176	404	0	0	0
T177	506	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T9 T11 T13 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T9 T11 T13 
149        1/1                    cnt_en = 1'b1;
           Tests:       T9 T11 T13 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T9 T11 T13 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T9 T11 T13 
163        1/1                    state_d = IdleSt;
           Tests:       T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T9 T11 T13 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T11 T13 
167        1/1                    if (trigger_active) begin
           Tests:       T9 T11 T13 
168        1/1                      state_d = DetectSt;
           Tests:       T9 T11 T13 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T171 T178 T179 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T9 T11 T13 
182        1/1                  cnt_en = 1'b1;
           Tests:       T9 T11 T13 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T9 T11 T13 
186        1/1                    state_d = IdleSt;
           Tests:       T55 T169 T180 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T55 T169 T180 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T9 T11 T13 
191        1/1                      state_d = StableSt;
           Tests:       T9 T11 T13 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T9 T11 T13 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T9 T11 T13 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T9 T11 T13 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T9 T11 T13 
206        1/1                    state_d = IdleSt;
           Tests:       T48 T52 T49 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T9 T11 T13 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T11,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T11,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T11,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T13
1	0	Covered	T4,T5,T23
1	1	Covered	T9,T11,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T13
0	1	Covered	T55,T169,T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T13
0	1	Covered	T48,T52,T50
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T13
1	-	Covered	T48,T52,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T13
DetectSt	168	Covered	T9,T11,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T11,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T13
DebounceSt->IdleSt	163	Covered	T62,T171,T178
DetectSt->IdleSt	186	Covered	T55,T169,T180
DetectSt->StableSt	191	Covered	T9,T11,T13
IdleSt->DebounceSt	148	Covered	T9,T11,T13
StableSt->IdleSt	206	Covered	T48,T81,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T9,T11,T13
0	1	Covered	T9,T11,T13
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T13
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T171,T178,T179
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T13
DetectSt	-	-	-	-	1	-	-	Covered	T55,T169,T180
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T52,T49
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	107	0	0
CntIncr_A	6803201	103479	0	0
CntNoWrap_A	6803201	6337979	0	0
DetectStDropOut_A	6803201	3	0	0
DetectedOut_A	6803201	13859	0	0
DetectedPulseOut_A	6803201	47	0	0
DisabledIdleSt_A	6803201	6096958	0	0
DisabledNoDetection_A	6803201	6098872	0	0
EnterDebounceSt_A	6803201	57	0	0
EnterDetectSt_A	6803201	50	0	0
EnterStableSt_A	6803201	47	0	0
PulseIsPulse_A	6803201	47	0	0
StayInStableSt	6803201	13790	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6803201	1558	0	0
gen_low_level_sva.LowLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	107	0	0
T9	494	2	0	0
T10	506	0	0	0
T11	0	2	0	0
T13	0	2	0	0
T28	495	0	0	0
T30	650	0	0	0
T31	463	0	0	0
T48	0	8	0	0
T49	0	2	0	0
T52	0	4	0	0
T55	0	2	0	0
T57	0	2	0	0
T65	445	0	0	0
T81	0	2	0	0
T93	526	0	0	0
T94	504	0	0	0
T115	405	0	0	0
T116	427	0	0	0
T141	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	103479	0	0
T9	494	23	0	0
T10	506	0	0	0
T11	0	42	0	0
T13	0	20	0	0
T28	495	0	0	0
T30	650	0	0	0
T31	463	0	0	0
T48	0	278	0	0
T49	0	16	0	0
T52	0	34	0	0
T55	0	13	0	0
T57	0	81	0	0
T65	445	0	0	0
T81	0	28	0	0
T93	526	0	0	0
T94	504	0	0	0
T115	405	0	0	0
T116	427	0	0	0
T141	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6337979	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	3	0	0
T34	5767	0	0	0
T48	3129	0	0	0
T53	771	0	0	0
T55	477	1	0	0
T74	647	0	0	0
T114	678	0	0	0
T169	0	1	0	0
T176	404	0	0	0
T180	0	1	0	0
T181	523	0	0	0
T182	426	0	0	0
T183	456	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	13859	0	0
T9	494	38	0	0
T10	506	0	0	0
T11	0	146	0	0
T13	0	64	0	0
T28	495	0	0	0
T30	650	0	0	0
T31	463	0	0	0
T48	0	243	0	0
T49	0	20	0	0
T52	0	100	0	0
T57	0	132	0	0
T65	445	0	0	0
T81	0	70	0	0
T93	526	0	0	0
T94	504	0	0	0
T115	405	0	0	0
T116	427	0	0	0
T141	0	87	0	0
T184	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	47	0	0
T9	494	1	0	0
T10	506	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T28	495	0	0	0
T30	650	0	0	0
T31	463	0	0	0
T48	0	4	0	0
T49	0	1	0	0
T52	0	2	0	0
T57	0	1	0	0
T65	445	0	0	0
T81	0	1	0	0
T93	526	0	0	0
T94	504	0	0	0
T115	405	0	0	0
T116	427	0	0	0
T141	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6096958	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6098872	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	57	0	0
T9	494	1	0	0
T10	506	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T28	495	0	0	0
T30	650	0	0	0
T31	463	0	0	0
T48	0	4	0	0
T49	0	1	0	0
T52	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0
T65	445	0	0	0
T81	0	1	0	0
T93	526	0	0	0
T94	504	0	0	0
T115	405	0	0	0
T116	427	0	0	0
T141	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	50	0	0
T9	494	1	0	0
T10	506	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T28	495	0	0	0
T30	650	0	0	0
T31	463	0	0	0
T48	0	4	0	0
T49	0	1	0	0
T52	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0
T65	445	0	0	0
T81	0	1	0	0
T93	526	0	0	0
T94	504	0	0	0
T115	405	0	0	0
T116	427	0	0	0
T141	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	47	0	0
T9	494	1	0	0
T10	506	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T28	495	0	0	0
T30	650	0	0	0
T31	463	0	0	0
T48	0	4	0	0
T49	0	1	0	0
T52	0	2	0	0
T57	0	1	0	0
T65	445	0	0	0
T81	0	1	0	0
T93	526	0	0	0
T94	504	0	0	0
T115	405	0	0	0
T116	427	0	0	0
T141	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	47	0	0
T9	494	1	0	0
T10	506	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T28	495	0	0	0
T30	650	0	0	0
T31	463	0	0	0
T48	0	4	0	0
T49	0	1	0	0
T52	0	2	0	0
T57	0	1	0	0
T65	445	0	0	0
T81	0	1	0	0
T93	526	0	0	0
T94	504	0	0	0
T115	405	0	0	0
T116	427	0	0	0
T141	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	13790	0	0
T9	494	36	0	0
T10	506	0	0	0
T11	0	144	0	0
T13	0	62	0	0
T28	495	0	0	0
T30	650	0	0	0
T31	463	0	0	0
T48	0	238	0	0
T49	0	19	0	0
T52	0	97	0	0
T57	0	130	0	0
T65	445	0	0	0
T81	0	68	0	0
T93	526	0	0	0
T94	504	0	0	0
T115	405	0	0	0
T116	427	0	0	0
T141	0	85	0	0
T184	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1558	0	0
T1	486	0	0	0
T2	0	2	0	0
T4	505	4	0	0
T5	421	3	0	0
T6	460	0	0	0
T14	493	4	0	0
T15	445	2	0	0
T16	891	0	0	0
T17	527	5	0	0
T18	423	1	0	0
T21	0	3	0	0
T23	421	1	0	0
T75	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	24	0	0
T35	11234	0	0	0
T48	3129	3	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	771	0	0	0
T81	3731	0	0	0
T82	1430	0	0	0
T114	678	0	0	0
T126	529	0	0	0
T127	755	0	0	0
T161	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T176	404	0	0	0
T177	506	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0