Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	97.83	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	97.83	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T7 T57 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T7 T57 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T7 T57 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T7 T57 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T7 T57 
163        1/1                    state_d = IdleSt;
           Tests:       T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T7 T57 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T7 T57 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T7 T57 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T7 T57 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T185 T187 T171 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T7 T57 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T7 T57 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T7 T57 
186        1/1                    state_d = IdleSt;
           Tests:       T187 T208 T197 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T187 T208 T197 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T7 T57 
191        1/1                      state_d = StableSt;
           Tests:       T2 T7 T57 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T7 T57 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T7 T57 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T7 T57 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T7 T57 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T57 T49 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T7 T57 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T57

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T7,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T57
0	1	Covered	T187,T208,T197
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T57
0	1	Covered	T2,T57,T54
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T57
1	-	Covered	T2,T57,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T57
DetectSt	168	Covered	T2,T7,T57
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T7,T57

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T57
DebounceSt->IdleSt	163	Covered	T62,T185,T187
DetectSt->IdleSt	186	Covered	T187,T208,T197
DetectSt->StableSt	191	Covered	T2,T7,T57
IdleSt->DebounceSt	148	Covered	T2,T7,T57
StableSt->IdleSt	206	Covered	T2,T7,T57

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T7,T57
0	1	Covered	T2,T7,T57
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T57
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T57
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T185,T187,T171
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T57
DetectSt	-	-	-	-	1	-	-	Covered	T187,T208,T197
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T57
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T57,T49
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T57
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	86	0	0
CntIncr_A	6803201	154024	0	0
CntNoWrap_A	6803201	6338000	0	0
DetectStDropOut_A	6803201	4	0	0
DetectedOut_A	6803201	144120	0	0
DetectedPulseOut_A	6803201	36	0	0
DisabledIdleSt_A	6803201	5879362	0	0
DisabledNoDetection_A	6803201	5881283	0	0
EnterDebounceSt_A	6803201	46	0	0
EnterDetectSt_A	6803201	40	0	0
EnterStableSt_A	6803201	36	0	0
PulseIsPulse_A	6803201	36	0	0
StayInStableSt	6803201	144070	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	86	0	0
T2	701	4	0	0
T3	1051	0	0	0
T7	2883	2	0	0
T8	1058	0	0	0
T27	493	0	0	0
T49	0	2	0	0
T50	0	4	0	0
T54	0	4	0	0
T57	0	2	0	0
T62	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	4	0	0
T184	0	2	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	154024	0	0
T2	701	88	0	0
T3	1051	0	0	0
T7	2883	34	0	0
T8	1058	0	0	0
T27	493	0	0	0
T49	0	16	0	0
T50	0	94	0	0
T54	0	124	0	0
T57	0	81	0	0
T62	0	41	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	60	0	0
T184	0	79	0	0
T209	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6338000	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	4	0	0
T110	14366	0	0	0
T187	550	1	0	0
T197	0	1	0	0
T198	2800	0	0	0
T208	0	1	0	0
T210	0	1	0	0
T211	505	0	0	0
T212	527	0	0	0
T213	679	0	0	0
T214	410	0	0	0
T215	493	0	0	0
T216	40657	0	0	0
T217	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	144120	0	0
T2	701	119	0	0
T3	1051	0	0	0
T7	2883	183	0	0
T8	1058	0	0	0
T27	493	0	0	0
T49	0	19	0	0
T50	0	180	0	0
T54	0	155	0	0
T57	0	8	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	181	0	0
T184	0	40	0	0
T186	0	67	0	0
T209	0	404	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	36	0	0
T2	701	2	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T27	493	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T54	0	2	0	0
T57	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	2	0	0
T184	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5879362	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5881283	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	46	0	0
T2	701	2	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T27	493	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T54	0	2	0	0
T57	0	1	0	0
T62	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	2	0	0
T184	0	1	0	0
T209	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	40	0	0
T2	701	2	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T27	493	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T54	0	2	0	0
T57	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	2	0	0
T184	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	36	0	0
T2	701	2	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T27	493	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T54	0	2	0	0
T57	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	2	0	0
T184	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	36	0	0
T2	701	2	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T27	493	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T54	0	2	0	0
T57	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	2	0	0
T184	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	144070	0	0
T2	701	116	0	0
T3	1051	0	0	0
T7	2883	181	0	0
T8	1058	0	0	0
T27	493	0	0	0
T49	0	18	0	0
T50	0	178	0	0
T54	0	152	0	0
T57	0	7	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	179	0	0
T184	0	38	0	0
T186	0	65	0	0
T209	0	402	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	21	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	0	0	0
T8	1058	0	0	0
T27	493	0	0	0
T50	0	2	0	0
T54	0	1	0	0
T57	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	2	0	0
T171	0	1	0	0
T172	0	2	0	0
T178	0	1	0	0
T180	0	1	0	0
T202	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T13 T51 T48 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T13 T51 T48 
149        1/1                    cnt_en = 1'b1;
           Tests:       T13 T51 T48 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T13 T51 T48 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T13 T51 T48 
163        1/1                    state_d = IdleSt;
           Tests:       T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T13 T51 T48 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T51 T48 
167        1/1                    if (trigger_active) begin
           Tests:       T13 T51 T48 
168        1/1                      state_d = DetectSt;
           Tests:       T13 T51 T48 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T13 T51 T48 
182        1/1                  cnt_en = 1'b1;
           Tests:       T13 T51 T48 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T13 T51 T48 
186        1/1                    state_d = IdleSt;
           Tests:       T48 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T48 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T13 T51 T52 
191        1/1                      state_d = StableSt;
           Tests:       T13 T51 T52 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T13 T51 T52 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T13 T51 T52 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T13 T51 T52 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T13 T51 T52 
206        1/1                    state_d = IdleSt;
           Tests:       T49 T54 T50 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T13 T51 T52 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T51,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T51,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T51,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T13,T51
1	0	Covered	T4,T5,T6
1	1	Covered	T13,T51,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T51,T52
0	1	Covered	T48
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T51,T52
0	1	Covered	T54,T50,T161
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T51,T52
1	-	Covered	T54,T50,T161

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T51,T48
DetectSt	168	Covered	T13,T51,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T51,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T51,T48
DebounceSt->IdleSt	163	Covered	T62
DetectSt->IdleSt	186	Covered	T48
DetectSt->StableSt	191	Covered	T13,T51,T52
IdleSt->DebounceSt	148	Covered	T13,T51,T48
StableSt->IdleSt	206	Covered	T49,T54,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T51,T48
0	1	Covered	T13,T51,T48
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T51,T48
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T51,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T51,T48
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T51,T48
DetectSt	-	-	-	-	1	-	-	Covered	T48
DetectSt	-	-	-	-	0	1	-	Covered	T13,T51,T52
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T49,T54,T50
StableSt	-	-	-	-	-	-	0	Covered	T13,T51,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	47	0	0
CntIncr_A	6803201	84812	0	0
CntNoWrap_A	6803201	6338039	0	0
DetectStDropOut_A	6803201	1	0	0
DetectedOut_A	6803201	11856	0	0
DetectedPulseOut_A	6803201	22	0	0
DisabledIdleSt_A	6803201	5822264	0	0
DisabledNoDetection_A	6803201	5824186	0	0
EnterDebounceSt_A	6803201	24	0	0
EnterDetectSt_A	6803201	23	0	0
EnterStableSt_A	6803201	22	0	0
PulseIsPulse_A	6803201	22	0	0
StayInStableSt	6803201	11823	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6803201	5056	0	0
gen_low_level_sva.LowLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	47	0	0
T13	597	2	0	0
T40	531	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	4	0	0
T51	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T62	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T161	0	4	0	0
T185	0	4	0	0
T204	439	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	84812	0	0
T13	597	20	0	0
T40	531	0	0	0
T48	0	94	0	0
T49	0	16	0	0
T50	0	94	0	0
T51	0	33	0	0
T52	0	17	0	0
T54	0	62	0	0
T62	0	41	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T161	0	60	0	0
T185	0	100	0	0
T204	439	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6338039	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1	0	0
T35	11234	0	0	0
T48	3129	1	0	0
T53	771	0	0	0
T81	3731	0	0	0
T82	1430	0	0	0
T114	678	0	0	0
T126	529	0	0	0
T127	755	0	0	0
T176	404	0	0	0
T177	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	11856	0	0
T13	597	38	0	0
T40	531	0	0	0
T49	0	19	0	0
T50	0	68	0	0
T51	0	41	0	0
T52	0	128	0	0
T54	0	6	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T161	0	49	0	0
T173	0	116	0	0
T185	0	240	0	0
T187	0	82	0	0
T204	439	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	22	0	0
T13	597	1	0	0
T40	531	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T161	0	2	0	0
T173	0	1	0	0
T185	0	2	0	0
T187	0	2	0	0
T204	439	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5822264	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5824186	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	24	0	0
T13	597	1	0	0
T40	531	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T62	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T161	0	2	0	0
T185	0	2	0	0
T204	439	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	23	0	0
T13	597	1	0	0
T40	531	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T161	0	2	0	0
T185	0	2	0	0
T187	0	2	0	0
T204	439	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	22	0	0
T13	597	1	0	0
T40	531	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T161	0	2	0	0
T173	0	1	0	0
T185	0	2	0	0
T187	0	2	0	0
T204	439	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	22	0	0
T13	597	1	0	0
T40	531	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T161	0	2	0	0
T173	0	1	0	0
T185	0	2	0	0
T187	0	2	0	0
T204	439	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	11823	0	0
T13	597	36	0	0
T40	531	0	0	0
T49	0	18	0	0
T50	0	65	0	0
T51	0	39	0	0
T52	0	126	0	0
T54	0	5	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T161	0	46	0	0
T173	0	114	0	0
T185	0	237	0	0
T187	0	79	0	0
T204	439	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5056	0	0
T1	486	1	0	0
T4	505	3	0	0
T5	421	3	0	0
T6	460	1	0	0
T14	493	9	0	0
T15	445	3	0	0
T16	891	0	0	0
T17	527	6	0	0
T18	423	1	0	0
T19	0	1	0	0
T23	421	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	10	0	0
T50	0	1	0	0
T54	759	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T180	0	1	0	0
T185	0	1	0	0
T187	0	1	0	0
T197	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	429	0	0	0
T221	405	0	0	0
T222	447	0	0	0
T223	495	0	0	0
T224	3278	0	0	0
T225	930	0	0	0
T226	3037	0	0	0
T227	410	0	0	0
T228	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T7 T13 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T7 T13 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T7 T13 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T7 T13 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T7 T13 
163        1/1                    state_d = IdleSt;
           Tests:       T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T7 T13 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T7 T13 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T7 T13 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T7 T13 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T141 T186 T198 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T7 T13 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T7 T13 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T7 T13 
186        1/1                    state_d = IdleSt;
           Tests:       T7 T187 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T7 T187 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T7 T13 
191        1/1                      state_d = StableSt;
           Tests:       T2 T7 T13 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T7 T13 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T7 T13 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T7 T13 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T7 T13 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T13 T48 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T7 T13 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T7,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T13
0	1	Covered	T7,T187
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T13
0	1	Covered	T2,T13,T48
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T13
1	-	Covered	T2,T13,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T13
DetectSt	168	Covered	T2,T7,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T7,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T13
DebounceSt->IdleSt	163	Covered	T141,T62,T186
DetectSt->IdleSt	186	Covered	T7,T187
DetectSt->StableSt	191	Covered	T2,T7,T13
IdleSt->DebounceSt	148	Covered	T2,T7,T13
StableSt->IdleSt	206	Covered	T2,T7,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T7,T13
0	1	Covered	T2,T7,T13
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T13
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T141,T186,T198
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T13
DetectSt	-	-	-	-	1	-	-	Covered	T7,T187
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T13,T48
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	81	0	0
CntIncr_A	6803201	75727	0	0
CntNoWrap_A	6803201	6338005	0	0
DetectStDropOut_A	6803201	2	0	0
DetectedOut_A	6803201	26075	0	0
DetectedPulseOut_A	6803201	34	0	0
DisabledIdleSt_A	6803201	5944003	0	0
DisabledNoDetection_A	6803201	5945922	0	0
EnterDebounceSt_A	6803201	45	0	0
EnterDetectSt_A	6803201	36	0	0
EnterStableSt_A	6803201	34	0	0
PulseIsPulse_A	6803201	34	0	0
StayInStableSt	6803201	26028	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	81	0	0
T2	701	2	0	0
T3	1051	0	0	0
T7	2883	4	0	0
T8	1058	0	0	0
T13	0	2	0	0
T27	493	0	0	0
T48	0	4	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T141	0	1	0	0
T161	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	75727	0	0
T2	701	44	0	0
T3	1051	0	0	0
T7	2883	68	0	0
T8	1058	0	0	0
T13	0	20	0	0
T27	493	0	0	0
T48	0	188	0	0
T49	0	16	0	0
T51	0	33	0	0
T52	0	17	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T141	0	43	0	0
T161	0	30	0	0
T201	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6338005	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	2	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T9	494	0	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T187	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	26075	0	0
T2	701	8	0	0
T3	1051	0	0	0
T7	2883	47	0	0
T8	1058	0	0	0
T13	0	83	0	0
T27	493	0	0	0
T48	0	314	0	0
T49	0	19	0	0
T51	0	41	0	0
T52	0	4	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	100	0	0
T185	0	197	0	0
T201	0	19	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	34	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T13	0	1	0	0
T27	493	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	1	0	0
T185	0	2	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5944003	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5945922	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	45	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	2	0	0
T8	1058	0	0	0
T13	0	1	0	0
T27	493	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T141	0	1	0	0
T161	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	36	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	2	0	0
T8	1058	0	0	0
T13	0	1	0	0
T27	493	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	1	0	0
T185	0	2	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	34	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T13	0	1	0	0
T27	493	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	1	0	0
T185	0	2	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	34	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T13	0	1	0	0
T27	493	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	1	0	0
T185	0	2	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	26028	0	0
T2	701	7	0	0
T3	1051	0	0	0
T7	2883	45	0	0
T8	1058	0	0	0
T13	0	82	0	0
T27	493	0	0	0
T48	0	311	0	0
T49	0	18	0	0
T51	0	39	0	0
T52	0	3	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	99	0	0
T185	0	194	0	0
T201	0	18	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	20	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	0	0	0
T8	1058	0	0	0
T13	0	1	0	0
T27	493	0	0	0
T48	0	1	0	0
T52	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T161	0	1	0	0
T163	0	3	0	0
T185	0	1	0	0
T186	0	1	0	0
T198	0	1	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T7 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T7 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T7 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T7 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T7 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T7 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T7 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T7 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T7 T13 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T11 T175 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T7 T13 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T7 T13 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T7 T13 
186        1/1                    state_d = IdleSt;
           Tests:       T48 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T48 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T7 T13 
191        1/1                      state_d = StableSt;
           Tests:       T2 T7 T13 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T7 T13 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T7 T13 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T7 T13 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T7 T13 
206        1/1                    state_d = IdleSt;
           Tests:       T7 T49 T172 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T7 T13 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T13
0	1	Covered	T48
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T13
0	1	Covered	T7,T172,T180
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T13
1	-	Covered	T7,T172,T180

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T11
DetectSt	168	Covered	T2,T7,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T7,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T13
DebounceSt->IdleSt	163	Covered	T11,T62,T175
DetectSt->IdleSt	186	Covered	T48
DetectSt->StableSt	191	Covered	T2,T7,T13
IdleSt->DebounceSt	148	Covered	T2,T7,T11
StableSt->IdleSt	206	Covered	T7,T49,T172

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T7,T11
0	1	Covered	T2,T7,T11
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T13
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T175
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T48
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T49,T172
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	49	0	0
CntIncr_A	6803201	1103	0	0
CntNoWrap_A	6803201	6338037	0	0
DetectStDropOut_A	6803201	1	0	0
DetectedOut_A	6803201	1661	0	0
DetectedPulseOut_A	6803201	22	0	0
DisabledIdleSt_A	6803201	6108346	0	0
DisabledNoDetection_A	6803201	6110266	0	0
EnterDebounceSt_A	6803201	26	0	0
EnterDetectSt_A	6803201	23	0	0
EnterStableSt_A	6803201	22	0	0
PulseIsPulse_A	6803201	22	0	0
StayInStableSt	6803201	1624	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6803201	5116	0	0
gen_low_level_sva.LowLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	6	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	49	0	0
T2	701	2	0	0
T3	1051	0	0	0
T7	2883	2	0	0
T8	1058	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T27	493	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T52	0	2	0	0
T62	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T162	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1103	0	0
T2	701	44	0	0
T3	1051	0	0	0
T7	2883	34	0	0
T8	1058	0	0	0
T11	0	42	0	0
T13	0	20	0	0
T27	493	0	0	0
T48	0	94	0	0
T49	0	16	0	0
T52	0	17	0	0
T62	0	40	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T162	0	26	0	0
T201	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6338037	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1	0	0
T35	11234	0	0	0
T48	3129	1	0	0
T53	771	0	0	0
T81	3731	0	0	0
T82	1430	0	0	0
T114	678	0	0	0
T126	529	0	0	0
T127	755	0	0	0
T176	404	0	0	0
T177	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1661	0	0
T2	701	40	0	0
T3	1051	0	0	0
T7	2883	101	0	0
T8	1058	0	0	0
T13	0	64	0	0
T27	493	0	0	0
T49	0	19	0	0
T52	0	129	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T162	0	186	0	0
T187	0	103	0	0
T201	0	43	0	0
T202	0	42	0	0
T229	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	22	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T13	0	1	0	0
T27	493	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T162	0	1	0	0
T187	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T229	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6108346	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6110266	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	26	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T27	493	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T62	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T162	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	23	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T13	0	1	0	0
T27	493	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T162	0	1	0	0
T187	0	1	0	0
T201	0	1	0	0
T229	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	22	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T13	0	1	0	0
T27	493	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T162	0	1	0	0
T187	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T229	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	22	0	0
T2	701	1	0	0
T3	1051	0	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T13	0	1	0	0
T27	493	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T162	0	1	0	0
T187	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T229	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	1624	0	0
T2	701	38	0	0
T3	1051	0	0	0
T7	2883	100	0	0
T8	1058	0	0	0
T13	0	62	0	0
T27	493	0	0	0
T49	0	18	0	0
T52	0	127	0	0
T64	2980	0	0	0
T75	423	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T162	0	184	0	0
T187	0	101	0	0
T201	0	41	0	0
T202	0	40	0	0
T229	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5116	0	0
T1	486	1	0	0
T4	505	5	0	0
T5	421	3	0	0
T6	460	1	0	0
T14	493	4	0	0
T15	445	2	0	0
T16	891	0	0	0
T17	527	4	0	0
T18	423	1	0	0
T19	0	1	0	0
T23	421	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T9	494	0	0	0
T27	493	0	0	0
T29	656	0	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T172	0	1	0	0
T174	0	1	0	0
T180	0	1	0	0
T208	0	1	0	0
T219	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T23 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T23 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T7 T9 T58 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T23 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T23 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T23 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T23 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T23 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T23 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T23 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T23 
148        1/1                    state_d = DebounceSt;
           Tests:       T7 T9 T58 
149        1/1                    cnt_en = 1'b1;
           Tests:       T7 T9 T58 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T7 T9 T58 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T7 T9 T58 
163        1/1                    state_d = IdleSt;
           Tests:       T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T7 T9 T58 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T7 T9 T58 
167        1/1                    if (trigger_active) begin
           Tests:       T7 T9 T58 
168        1/1                      state_d = DetectSt;
           Tests:       T7 T9 T58 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T58 T141 T198 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T7 T9 T58 
182        1/1                  cnt_en = 1'b1;
           Tests:       T7 T9 T58 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T7 T9 T58 
186        1/1                    state_d = IdleSt;
           Tests:       T58 T171 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T58 T171 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T7 T9 T56 
191        1/1                      state_d = StableSt;
           Tests:       T7 T9 T56 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T7 T9 T56 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T7 T9 T56 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T7 T9 T56 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T7 T9 T56 
206        1/1                    state_d = IdleSt;
           Tests:       T7 T57 T52 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T7 T9 T56 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T23
1	1	Covered	T4,T5,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T9,T58

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T9,T58

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T9,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T11
1	0	Covered	T4,T5,T23
1	1	Covered	T7,T9,T58

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T56
0	1	Covered	T58,T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T56
0	1	Covered	T7,T57,T52
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T56
1	-	Covered	T7,T57,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T58
DetectSt	168	Covered	T7,T9,T58
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T9,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T58
DebounceSt->IdleSt	163	Covered	T58,T141,T62
DetectSt->IdleSt	186	Covered	T58,T171
DetectSt->StableSt	191	Covered	T7,T9,T56
IdleSt->DebounceSt	148	Covered	T7,T9,T58
StableSt->IdleSt	206	Covered	T7,T57,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T9,T58
0	1	Covered	T7,T9,T58
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T58
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T58
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T58,T141,T198
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T58
DetectSt	-	-	-	-	1	-	-	Covered	T58,T171
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T57,T52
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	101	0	0
CntIncr_A	6803201	84244	0	0
CntNoWrap_A	6803201	6337985	0	0
DetectStDropOut_A	6803201	2	0	0
DetectedOut_A	6803201	64762	0	0
DetectedPulseOut_A	6803201	45	0	0
DisabledIdleSt_A	6803201	5921901	0	0
DisabledNoDetection_A	6803201	5923812	0	0
EnterDebounceSt_A	6803201	54	0	0
EnterDetectSt_A	6803201	47	0	0
EnterStableSt_A	6803201	45	0	0
PulseIsPulse_A	6803201	45	0	0
StayInStableSt	6803201	64699	0	0
gen_high_level_sva.HighLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	101	0	0
T7	2883	2	0	0
T8	1058	0	0	0
T9	494	2	0	0
T27	493	0	0	0
T29	656	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	3	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T141	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	84244	0	0
T7	2883	34	0	0
T8	1058	0	0	0
T9	494	23	0	0
T27	493	0	0	0
T29	656	0	0	0
T48	0	45	0	0
T49	0	16	0	0
T52	0	17	0	0
T54	0	62	0	0
T56	0	47	0	0
T57	0	81	0	0
T58	0	156	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T141	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6337985	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	2	0	0
T51	498	0	0	0
T56	546	0	0	0
T58	1031	1	0	0
T70	765	0	0	0
T71	646	0	0	0
T164	526	0	0	0
T165	724	0	0	0
T166	402	0	0	0
T167	522	0	0	0
T168	508	0	0	0
T171	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	64762	0	0
T7	2883	101	0	0
T8	1058	0	0	0
T9	494	38	0	0
T27	493	0	0	0
T29	656	0	0	0
T48	0	215	0	0
T49	0	19	0	0
T52	0	63	0	0
T54	0	5	0	0
T56	0	42	0	0
T57	0	8	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T184	0	195	0	0
T209	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	45	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T9	494	1	0	0
T27	493	0	0	0
T29	656	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T184	0	1	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5921901	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5923812	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	54	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T9	494	1	0	0
T27	493	0	0	0
T29	656	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T141	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	47	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T9	494	1	0	0
T27	493	0	0	0
T29	656	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	45	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T9	494	1	0	0
T27	493	0	0	0
T29	656	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T184	0	1	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	45	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T9	494	1	0	0
T27	493	0	0	0
T29	656	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T184	0	1	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	64699	0	0
T7	2883	100	0	0
T8	1058	0	0	0
T9	494	36	0	0
T27	493	0	0	0
T29	656	0	0	0
T48	0	213	0	0
T49	0	18	0	0
T52	0	62	0	0
T54	0	4	0	0
T56	0	40	0	0
T57	0	7	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T184	0	193	0	0
T209	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	26	0	0
T7	2883	1	0	0
T8	1058	0	0	0
T9	494	0	0	0
T27	493	0	0	0
T29	656	0	0	0
T50	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T64	2980	0	0	0
T76	403	0	0	0
T84	449	0	0	0
T85	502	0	0	0
T115	405	0	0	0
T162	0	1	0	0
T163	0	1	0	0
T170	0	1	0	0
T187	0	1	0	0
T229	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T23 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T13 T48 T49 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T13 T48 T49 
149        1/1                    cnt_en = 1'b1;
           Tests:       T13 T48 T49 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T13 T48 T49 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T13 T48 T49 
163        1/1                    state_d = IdleSt;
           Tests:       T62 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T62 
165        1/1                  end else if (cnt_done) begin
           Tests:       T13 T48 T49 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T48 T49 
167        1/1                    if (trigger_active) begin
           Tests:       T13 T48 T49 
168        1/1                      state_d = DetectSt;
           Tests:       T13 T48 T49 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T189 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T13 T48 T49 
182        1/1                  cnt_en = 1'b1;
           Tests:       T13 T48 T49 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T13 T48 T49 
186        1/1                    state_d = IdleSt;
           Tests:       T174 T218 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T174 T218 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T13 T48 T49 
191        1/1                      state_d = StableSt;
           Tests:       T13 T48 T49 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T13 T48 T49 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T13 T48 T49 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T13 T48 T49 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T13 T48 T49 
206        1/1                    state_d = IdleSt;
           Tests:       T48 T49 T202 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T13 T48 T49 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T48,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T48,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T48,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T51,T56
1	0	Covered	T4,T5,T23
1	1	Covered	T13,T48,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T48,T49
0	1	Covered	T174,T218
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T48,T49
0	1	Covered	T48,T202,T170
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T48,T49
1	-	Covered	T48,T202,T170

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T48,T49
DetectSt	168	Covered	T13,T48,T49
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T48,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T48,T49
DebounceSt->IdleSt	163	Covered	T62,T189
DetectSt->IdleSt	186	Covered	T174,T218
DetectSt->StableSt	191	Covered	T13,T48,T49
IdleSt->DebounceSt	148	Covered	T13,T48,T49
StableSt->IdleSt	206	Covered	T48,T49,T202

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T48,T49
0	1	Covered	T13,T48,T49
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T48,T49
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T48,T49
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T48,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T189
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T48,T49
DetectSt	-	-	-	-	1	-	-	Covered	T174,T218
DetectSt	-	-	-	-	0	1	-	Covered	T13,T48,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T49,T202
StableSt	-	-	-	-	-	-	0	Covered	T13,T48,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6803201	52	0	0
CntIncr_A	6803201	52161	0	0
CntNoWrap_A	6803201	6338034	0	0
DetectStDropOut_A	6803201	2	0	0
DetectedOut_A	6803201	64280	0	0
DetectedPulseOut_A	6803201	23	0	0
DisabledIdleSt_A	6803201	5989432	0	0
DisabledNoDetection_A	6803201	5991353	0	0
EnterDebounceSt_A	6803201	27	0	0
EnterDetectSt_A	6803201	25	0	0
EnterStableSt_A	6803201	23	0	0
PulseIsPulse_A	6803201	23	0	0
StayInStableSt	6803201	64244	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6803201	5685	0	0
gen_low_level_sva.LowLevelEvent_A	6803201	6340037	0	0
gen_not_sticky_sva.StableStDropOut_A	6803201	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	52	0	0
T13	597	2	0	0
T40	531	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T62	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T169	0	2	0	0
T185	0	2	0	0
T198	0	2	0	0
T202	0	2	0	0
T204	439	0	0	0
T229	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	52161	0	0
T13	597	20	0	0
T40	531	0	0	0
T48	0	94	0	0
T49	0	16	0	0
T50	0	47	0	0
T62	0	40	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T169	0	42	0	0
T185	0	50	0	0
T198	0	75	0	0
T202	0	79	0	0
T204	439	0	0	0
T229	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6338034	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	2	0	0
T174	1084	1	0	0
T218	0	1	0	0
T230	696	0	0	0
T231	24381	0	0	0
T232	214271	0	0	0
T233	446	0	0	0
T234	18806	0	0	0
T235	502	0	0	0
T236	24056	0	0	0
T237	402	0	0	0
T238	600	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	64280	0	0
T13	597	65	0	0
T40	531	0	0	0
T48	0	139	0	0
T49	0	19	0	0
T50	0	56	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T169	0	44	0	0
T170	0	43	0	0
T185	0	182	0	0
T198	0	271	0	0
T202	0	41	0	0
T204	439	0	0	0
T229	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	23	0	0
T13	597	1	0	0
T40	531	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T169	0	1	0	0
T170	0	1	0	0
T185	0	1	0	0
T198	0	1	0	0
T202	0	1	0	0
T204	439	0	0	0
T229	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5989432	0	0
T1	486	85	0	0
T4	505	104	0	0
T5	421	20	0	0
T6	460	59	0	0
T14	493	92	0	0
T15	445	44	0	0
T16	891	490	0	0
T17	527	126	0	0
T18	423	22	0	0
T23	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5991353	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	27	0	0
T13	597	1	0	0
T40	531	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T62	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T169	0	1	0	0
T185	0	1	0	0
T198	0	1	0	0
T202	0	1	0	0
T204	439	0	0	0
T229	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	25	0	0
T13	597	1	0	0
T40	531	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T169	0	1	0	0
T170	0	1	0	0
T185	0	1	0	0
T198	0	1	0	0
T202	0	1	0	0
T204	439	0	0	0
T229	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	23	0	0
T13	597	1	0	0
T40	531	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T169	0	1	0	0
T170	0	1	0	0
T185	0	1	0	0
T198	0	1	0	0
T202	0	1	0	0
T204	439	0	0	0
T229	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	23	0	0
T13	597	1	0	0
T40	531	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T169	0	1	0	0
T170	0	1	0	0
T185	0	1	0	0
T198	0	1	0	0
T202	0	1	0	0
T204	439	0	0	0
T229	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	64244	0	0
T13	597	63	0	0
T40	531	0	0	0
T48	0	138	0	0
T49	0	18	0	0
T50	0	54	0	0
T68	443	0	0	0
T78	1358	0	0	0
T89	496	0	0	0
T95	504	0	0	0
T149	419	0	0	0
T150	553	0	0	0
T151	493	0	0	0
T169	0	42	0	0
T170	0	42	0	0
T185	0	180	0	0
T198	0	269	0	0
T202	0	40	0	0
T204	439	0	0	0
T229	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	5685	0	0
T1	486	0	0	0
T3	0	6	0	0
T4	505	6	0	0
T5	421	3	0	0
T6	460	0	0	0
T14	493	8	0	0
T15	445	2	0	0
T16	891	0	0	0
T17	527	5	0	0
T18	423	1	0	0
T20	0	3	0	0
T21	0	7	0	0
T23	421	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	6340037	0	0
T1	486	86	0	0
T4	505	105	0	0
T5	421	21	0	0
T6	460	60	0	0
T14	493	93	0	0
T15	445	45	0	0
T16	891	491	0	0
T17	527	127	0	0
T18	423	23	0	0
T23	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6803201	9	0	0
T35	11234	0	0	0
T48	3129	1	0	0
T53	771	0	0	0
T81	3731	0	0	0
T82	1430	0	0	0
T114	678	0	0	0
T126	529	0	0	0
T127	755	0	0	0
T170	0	1	0	0
T176	404	0	0	0
T177	506	0	0	0
T178	0	1	0	0
T189	0	1	0	0
T197	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T206	0	1	0	0