UART Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	32.160s	5.768ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	56.857us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	15.714us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.630s	261.554us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.700s	253.833us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.130s	39.823us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	15.714us	20	20	100.00
		uart_csr_aliasing	0.700s	253.833us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.083m	114.143ms	50	50	100.00
V2	parity	uart_smoke	32.160s	5.768ms	50	50	100.00
		uart_tx_rx	3.083m	114.143ms	50	50	100.00
V2	parity_error	uart_intr	59.489m	2.234s	48	50	96.00
		uart_rx_parity_err	10.951m	196.060ms	50	50	100.00
V2	watermark	uart_tx_rx	3.083m	114.143ms	50	50	100.00
		uart_intr	59.489m	2.234s	48	50	96.00
V2	fifo_full	uart_fifo_full	9.065m	397.710ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.833m	252.967ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	6.388m	164.980ms	300	300	100.00
V2	rx_frame_err	uart_intr	59.489m	2.234s	48	50	96.00
V2	rx_break_err	uart_intr	59.489m	2.234s	48	50	96.00
V2	rx_timeout	uart_intr	59.489m	2.234s	48	50	96.00
V2	perf	uart_perf	25.943m	31.143ms	50	50	100.00
V2	sys_loopback	uart_loopback	28.910s	14.208ms	50	50	100.00
V2	line_loopback	uart_loopback	28.910s	14.208ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.979m	124.436ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.539m	79.842ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	24.070s	6.911ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	39.220s	4.811ms	44	50	88.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.963m	143.668ms	50	50	100.00
V2	stress_all	uart_stress_all	1.143h	2.501s	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	48.198m	168.130ms	97	100	97.00
V2	alert_test	uart_alert_test	0.610s	70.918us	50	50	100.00
V2	intr_test	uart_intr_test	0.610s	13.071us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.070s	355.012us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.070s	355.012us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	56.857us	5	5	100.00
		uart_csr_rw	0.650s	15.714us	20	20	100.00
		uart_csr_aliasing	0.700s	253.833us	5	5	100.00
		uart_same_csr_outstanding	0.800s	43.332us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	56.857us	5	5	100.00
		uart_csr_rw	0.650s	15.714us	20	20	100.00
		uart_csr_aliasing	0.700s	253.833us	5	5	100.00
		uart_same_csr_outstanding	0.800s	43.332us	20	20	100.00
V2		TOTAL			1178	1190	98.99
V2S	tl_intg_err	uart_sec_cm	0.850s	115.282us	5	5	100.00
		uart_tl_intg_err	1.330s	82.384us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.330s	82.384us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1308	1320	99.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	15	78.95
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.80	98.45	100.00	--	99.76	100.00	97.59

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 6 failures:

Test uart_rx_oversample has 6 failures.

5.uart_rx_oversample.1896490546
Line 217, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 380591943 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (19498 [0x4c2a] vs 38996 [0x9854]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 389258575 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (4611 [0x1203] vs 9223 [0x2407]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 397711134 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/17
  UVM_ERROR @ 397925207 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (64559 [0xfc2f] vs 63583 [0xf85f]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 414016546 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/17

10.uart_rx_oversample.732398215
Line 218, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 759031760 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1005 [0x3ed] vs 22490 [0x57da]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 969366112 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/11
  UVM_INFO @ 1171270672 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/11
  UVM_INFO @ 1198255647 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/11
  UVM_INFO @ 1519532338 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 7/11

... and 4 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test uart_intr has 2 failures.

19.uart_intr.3894416246
Line 293, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_intr/latest/run.log

  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.uart_intr.1629901556
Line 223, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/24.uart_intr/latest/run.log

  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test uart_noise_filter has 1 failures.

42.uart_noise_filter.2444733889
Line 227, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/42.uart_noise_filter/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

32.uart_stress_all_with_rand_reset.262646556
Line 927, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 375348141235 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 375348141235 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (0 [0x0] vs 1 [0x1]) uart_intr name/val: TxWatermark/0, en_intr: 55
  UVM_INFO @ 375475232017 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 375572686465 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/201

98.uart_stress_all_with_rand_reset.1315568573
Line 480, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 250569382367 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 250569382367 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 7f
  UVM_ERROR @ 250956982367 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 250956982367 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 7f
  UVM_ERROR @ 251344582367 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

UVM_ERROR (uart_scoreboard.sv:418) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

2.uart_stress_all_with_rand_reset.2368306191
Line 882, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 273605664329 ps: (uart_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_ERROR @ 273605664329 ps: (uart_scoreboard.sv:420) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxWatermark
  UVM_ERROR @ 273609812473 ps: (uart_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_ERROR @ 273609812473 ps: (uart_scoreboard.sv:420) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxWatermark
  UVM_ERROR @ 273612738396 ps: (uart_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark