Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23054

1

T1

114

T2

3

T3

296

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19476	1			T1	47		T2	11		T3	77
values[0x0]	9677	1			T1	29		T2	6		T3	114
values[0x1]	10010	1			T1	38		T2	5		T3	130

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11573	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

27590

1

T1

114

T2

7

T3

312

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	136	1			T1	1		T3	1		T4	1
valid_sources[0x01]	119	1			T7	1		T5	4		T16	4
valid_sources[0x02]	152	1			T3	2		T7	6		T4	2
valid_sources[0x03]	165	1			T7	1		T16	2		T17	2
valid_sources[0x04]	227	1			T5	4		T17	1		T14	1
valid_sources[0x05]	126	1			T1	1		T7	5		T4	2
valid_sources[0x06]	130	1			T3	2		T7	1		T4	1
valid_sources[0x07]	91	1			T2	1		T3	3		T7	1
valid_sources[0x08]	124	1			T1	1		T3	1		T7	3
valid_sources[0x09]	157	1			T16	1		T17	1		T14	26
valid_sources[0x0a]	107	1			T3	2		T7	2		T16	1
valid_sources[0x0b]	179	1			T7	3		T4	1		T5	1
valid_sources[0x0c]	159	1			T7	1		T4	1		T8	6
valid_sources[0x0d]	161	1			T1	1		T4	1		T16	1
valid_sources[0x0e]	178	1			T1	1		T2	1		T7	3
valid_sources[0x0f]	205	1			T3	2		T7	6		T5	4
valid_sources[0x10]	148	1			T2	1		T3	3		T7	4
valid_sources[0x11]	132	1			T8	1		T14	7		T18	11
valid_sources[0x12]	138	1			T2	1		T7	1		T4	1
valid_sources[0x13]	102	1			T4	2		T6	1		T16	3
valid_sources[0x14]	147	1			T7	4		T16	3		T17	4
valid_sources[0x15]	154	1			T4	1		T16	1		T17	3
valid_sources[0x16]	134	1			T3	2		T7	2		T4	2
valid_sources[0x17]	115	1			T4	2		T6	3		T16	1
valid_sources[0x18]	268	1			T7	1		T4	2		T6	2
valid_sources[0x19]	146	1			T3	6		T7	2		T4	1
valid_sources[0x1a]	188	1			T7	7		T16	1		T8	2
valid_sources[0x1b]	143	1			T3	6		T7	5		T4	4
valid_sources[0x1c]	236	1			T7	2		T4	1		T14	14
valid_sources[0x1d]	109	1			T7	2		T4	3		T5	1
valid_sources[0x1e]	169	1			T1	1		T3	9		T7	2
valid_sources[0x1f]	115	1			T3	2		T4	2		T5	7
valid_sources[0x20]	173	1			T3	12		T7	2		T4	2
valid_sources[0x21]	152	1			T3	3		T7	2		T4	2
valid_sources[0x22]	155	1			T3	2		T7	4		T16	2
valid_sources[0x23]	130	1			T2	1		T7	8		T21	1
valid_sources[0x24]	116	1			T1	1		T7	1		T4	2
valid_sources[0x25]	195	1			T7	1		T4	1		T16	2
valid_sources[0x26]	104	1			T7	3		T4	2		T16	4
valid_sources[0x27]	178	1			T3	1		T7	3		T5	33
valid_sources[0x28]	127	1			T7	4		T4	2		T6	1
valid_sources[0x29]	103	1			T7	5		T4	2		T5	1
valid_sources[0x2a]	114	1			T3	2		T4	1		T5	1
valid_sources[0x2b]	174	1			T3	2		T4	1		T16	1
valid_sources[0x2c]	138	1			T2	1		T3	1		T7	4
valid_sources[0x2d]	151	1			T3	2		T7	4		T4	3
valid_sources[0x2e]	150	1			T7	3		T16	1		T8	2
valid_sources[0x2f]	138	1			T7	1		T4	1		T5	14
valid_sources[0x30]	123	1			T7	4		T4	5		T5	1
valid_sources[0x31]	114	1			T16	3		T17	2		T14	19
valid_sources[0x32]	140	1			T1	2		T7	1		T4	1
valid_sources[0x33]	145	1			T3	1		T7	2		T4	4
valid_sources[0x34]	130	1			T3	1		T7	7		T4	1
valid_sources[0x35]	165	1			T3	1		T7	2		T4	1
valid_sources[0x36]	96	1			T4	2		T16	3		T8	2
valid_sources[0x37]	131	1			T1	4		T7	1		T4	1
valid_sources[0x38]	165	1			T3	4		T7	1		T4	3
valid_sources[0x39]	113	1			T7	3		T4	2		T5	3
valid_sources[0x3a]	212	1			T1	2		T7	1		T4	2
valid_sources[0x3b]	105	1			T1	1		T3	2		T7	1
valid_sources[0x3c]	157	1			T3	3		T7	1		T4	1
valid_sources[0x3d]	91	1			T3	1		T4	3		T16	1
valid_sources[0x3e]	190	1			T3	3		T5	1		T16	1
valid_sources[0x3f]	111	1			T7	5		T4	1		T5	3
valid_sources[0x40]	109	1			T1	2		T7	2		T4	1
valid_sources[0x41]	284	1			T3	1		T7	2		T6	2
valid_sources[0x42]	131	1			T1	2		T7	4		T4	2
valid_sources[0x43]	122	1			T7	1		T4	1		T8	6
valid_sources[0x44]	159	1			T3	2		T5	22		T16	1
valid_sources[0x45]	125	1			T7	3		T16	1		T8	2
valid_sources[0x46]	126	1			T1	4		T4	3		T16	2
valid_sources[0x47]	170	1			T3	6		T7	1		T4	3
valid_sources[0x48]	150	1			T7	4		T4	3		T16	1
valid_sources[0x49]	289	1			T4	1		T16	3		T17	2
valid_sources[0x4a]	94	1			T1	6		T7	2		T4	1
valid_sources[0x4b]	100	1			T3	2		T7	2		T17	3
valid_sources[0x4c]	114	1			T7	1		T4	2		T14	9
valid_sources[0x4d]	115	1			T7	10		T16	3		T8	2
valid_sources[0x4e]	145	1			T3	4		T14	12		T20	3
valid_sources[0x4f]	108	1			T16	2		T8	5		T17	3
valid_sources[0x50]	129	1			T3	3		T4	3		T5	3
valid_sources[0x51]	152	1			T3	2		T7	2		T16	3
valid_sources[0x52]	160	1			T4	2		T16	1		T8	2
valid_sources[0x53]	148	1			T7	1		T4	2		T16	3
valid_sources[0x54]	134	1			T3	4		T7	5		T4	2
valid_sources[0x55]	135	1			T1	1		T4	5		T5	2
valid_sources[0x56]	149	1			T7	8		T4	1		T5	1
valid_sources[0x57]	180	1			T4	1		T5	2		T6	1
valid_sources[0x58]	138	1			T1	2		T3	1		T4	1
valid_sources[0x59]	136	1			T7	1		T16	3		T17	1
valid_sources[0x5a]	116	1			T3	12		T7	2		T4	3
valid_sources[0x5b]	287	1			T1	3		T7	2		T4	2
valid_sources[0x5c]	139	1			T4	3		T6	1		T16	2
valid_sources[0x5d]	164	1			T7	2		T4	2		T16	1
valid_sources[0x5e]	235	1			T7	2		T4	2		T16	2
valid_sources[0x5f]	153	1			T7	1		T4	1		T16	1
valid_sources[0x60]	83	1			T3	1		T7	1		T4	2
valid_sources[0x61]	259	1			T7	1		T5	7		T16	4
valid_sources[0x62]	129	1			T7	2		T8	7		T14	4
valid_sources[0x63]	147	1			T7	4		T8	3		T17	3
valid_sources[0x64]	109	1			T3	1		T4	1		T5	6
valid_sources[0x65]	110	1			T7	4		T16	1		T17	1
valid_sources[0x66]	129	1			T2	1		T3	1		T7	1
valid_sources[0x67]	121	1			T3	1		T4	2		T5	12
valid_sources[0x68]	154	1			T7	3		T4	1		T16	3
valid_sources[0x69]	147	1			T1	3		T7	2		T5	1
valid_sources[0x6a]	150	1			T2	1		T3	6		T7	8
valid_sources[0x6b]	286	1			T3	2		T16	2		T17	1
valid_sources[0x6c]	193	1			T1	2		T7	3		T4	1
valid_sources[0x6d]	144	1			T1	1		T3	1		T7	2
valid_sources[0x6e]	174	1			T3	2		T7	1		T4	1
valid_sources[0x6f]	147	1			T3	1		T7	1		T4	1
valid_sources[0x70]	111	1			T3	3		T7	2		T4	2
valid_sources[0x71]	118	1			T3	3		T7	1		T16	2
valid_sources[0x72]	163	1			T3	3		T7	1		T4	3
valid_sources[0x73]	125	1			T1	3		T3	5		T7	2
valid_sources[0x74]	156	1			T3	1		T4	1		T16	1
valid_sources[0x75]	272	1			T7	3		T17	2		T14	7
valid_sources[0x76]	137	1			T3	1		T7	4		T4	3
valid_sources[0x77]	125	1			T7	3		T4	1		T8	1
valid_sources[0x78]	152	1			T3	2		T7	3		T4	3
valid_sources[0x79]	124	1			T1	1		T7	3		T4	3
valid_sources[0x7a]	96	1			T16	1		T8	1		T14	2
valid_sources[0x7b]	177	1			T1	2		T7	3		T5	1
valid_sources[0x7c]	131	1			T7	1		T4	1		T16	2
valid_sources[0x7d]	155	1			T7	4		T5	5		T6	1
valid_sources[0x7e]	154	1			T3	3		T7	2		T4	1
valid_sources[0x7f]	228	1			T1	1		T7	2		T4	1
valid_sources[0x80]	114	1			T1	1		T7	1		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8621

1

T1

47

T3

70

T7

109

values[0x0]

all_enables

biggest_size

7652

1

T1

29

T2

1

T3

113

values[0x1]

all_enables

biggest_size

6781

1

T1

38

T2

2

T3

113