Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
32.95	0.00	0.00	98.86				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	462991	10243	0	0
ctrl_rd_A	462991	1571	0	0
intr_enable_rd_A	462991	1508	0	0
ovrd_rd_A	462991	639	0	0
timeout_ctrl_rd_A	462991	755	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462991	10243	0	0
T3	5838	361	0	0
T4	3448	3	0	0
T5	2522	206	0	0
T6	1335	0	0	0
T7	10020	445	0	0
T8	4064	2	0	0
T14	5121	0	0	0
T16	3329	621	0	0
T17	2649	236	0	0
T21	1101	1	0	0
T31	0	2	0	0
T33	0	7	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462991	1571	0	0
T9	1343	0	0	0
T15	3183	0	0	0
T18	2080	0	0	0
T19	2175	0	0	0
T22	9641	0	0	0
T23	0	28	0	0
T25	2698	0	0	0
T27	0	25	0	0
T29	0	26	0	0
T31	1298	6	0	0
T32	1027	0	0	0
T33	1691	0	0	0
T41	3294	26	0	0
T56	0	37	0	0
T57	0	6	0	0
T59	0	262	0	0
T67	0	34	0	0
T68	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462991	1508	0	0
T9	1343	0	0	0
T15	3183	0	0	0
T18	2080	0	0	0
T19	2175	0	0	0
T22	9641	0	0	0
T23	0	41	0	0
T25	2698	0	0	0
T27	0	11	0	0
T29	0	29	0	0
T31	1298	31	0	0
T32	1027	0	0	0
T33	1691	0	0	0
T41	3294	10	0	0
T56	0	55	0	0
T57	0	43	0	0
T59	0	247	0	0
T67	0	26	0	0
T69	0	7	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462991	639	0	0
T9	1343	0	0	0
T15	3183	0	0	0
T18	2080	0	0	0
T19	2175	0	0	0
T22	9641	0	0	0
T23	0	44	0	0
T25	2698	0	0	0
T27	0	35	0	0
T29	0	8	0	0
T31	1298	25	0	0
T32	1027	0	0	0
T33	1691	0	0	0
T34	0	4	0	0
T41	3294	7	0	0
T56	0	1	0	0
T57	0	4	0	0
T59	0	45	0	0
T67	0	42	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462991	755	0	0
T9	1343	0	0	0
T15	3183	0	0	0
T18	2080	0	0	0
T19	2175	0	0	0
T22	9641	0	0	0
T23	0	31	0	0
T25	2698	0	0	0
T27	0	7	0	0
T29	0	6	0	0
T31	1298	17	0	0
T32	1027	0	0	0
T33	1691	0	0	0
T34	0	1	0	0
T41	3294	28	0	0
T56	0	88	0	0
T57	0	19	0	0
T59	0	80	0	0
T67	0	35	0	0