UART Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	21.880s	5.382ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.580s	18.425us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	43.575us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.550s	509.627us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	27.255us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.590s	34.022us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	43.575us	20	20	100.00
		uart_csr_aliasing	0.780s	27.255us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.418m	97.476ms	50	50	100.00
V2	parity	uart_smoke	21.880s	5.382ms	50	50	100.00
		uart_tx_rx	3.418m	97.476ms	50	50	100.00
V2	parity_error	uart_intr	27.204m	1.247s	47	50	94.00
		uart_rx_parity_err	5.216m	402.780ms	50	50	100.00
V2	watermark	uart_tx_rx	3.418m	97.476ms	50	50	100.00
		uart_intr	27.204m	1.247s	47	50	94.00
V2	fifo_full	uart_fifo_full	13.017m	124.633ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.632m	174.351ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.929m	248.355ms	300	300	100.00
V2	rx_frame_err	uart_intr	27.204m	1.247s	47	50	94.00
V2	rx_break_err	uart_intr	27.204m	1.247s	47	50	94.00
V2	rx_timeout	uart_intr	27.204m	1.247s	47	50	94.00
V2	perf	uart_perf	31.788m	37.001ms	50	50	100.00
V2	sys_loopback	uart_loopback	27.850s	10.353ms	42	50	84.00
V2	line_loopback	uart_loopback	27.850s	10.353ms	42	50	84.00
V2	rx_noise_filter	uart_noise_filter	12.379m	219.191ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.008m	40.705ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	40.270s	12.486ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	44.230s	4.911ms	37	50	74.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.346m	165.507ms	50	50	100.00
V2	stress_all	uart_stress_all	35.914m	753.468ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	41.629m	79.080ms	96	100	96.00
V2	alert_test	uart_alert_test	0.620s	19.094us	50	50	100.00
V2	intr_test	uart_intr_test	0.610s	10.976us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.540s	601.095us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.540s	601.095us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.580s	18.425us	5	5	100.00
		uart_csr_rw	0.650s	43.575us	20	20	100.00
		uart_csr_aliasing	0.780s	27.255us	5	5	100.00
		uart_same_csr_outstanding	0.770s	355.812us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.580s	18.425us	5	5	100.00
		uart_csr_rw	0.650s	43.575us	20	20	100.00
		uart_csr_aliasing	0.780s	27.255us	5	5	100.00
		uart_same_csr_outstanding	0.770s	355.812us	20	20	100.00
V2		TOTAL			1162	1190	97.65
V2S	tl_intg_err	uart_sec_cm	0.830s	71.459us	5	5	100.00
		uart_tl_intg_err	1.310s	166.006us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.310s	166.006us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1292	1320	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	15	78.95
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.29	99.79	98.45	100.00	--	99.76	100.00	97.73

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 13 failures:

Test uart_rx_oversample has 13 failures.

1.uart_rx_oversample.61481332040805593193747130156037973618727751149625376524928851883157447090165
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 775398286 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (49959 [0xc327] vs 49571 [0xc1a3]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 783405001 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/6
  UVM_ERROR @ 784112563 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (12318 [0x301e] vs 37406 [0x921e]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 811404973 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/6
  UVM_ERROR @ 831112516 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (63355 [0xf77b] vs 55155 [0xd773]) Regname: uart_reg_block.val.rx reset value: 0x0

2.uart_rx_oversample.68509910792981664326556218825745591557853901257368108586726157648954244962211
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 853825539 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (29673 [0x73e9] vs 47604 [0xb9f4]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 871973187 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 7/8
  UVM_INFO @ 1078013984 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 8/8
  UVM_INFO @ 2258086733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 7 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

2.uart_stress_all_with_rand_reset.50855829192399086029689071997214940587081136323519931630130207455044012016259
Line 498, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14600093666 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (99 [0x63] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 14600093666 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 99 [0x63]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 14600153666 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 2/13
  UVM_INFO @ 14647433666 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 39/711
  UVM_INFO @ 14697263666 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 40/711

Test uart_loopback has 6 failures.

3.uart_loopback.73330404206888419656575679500630011565169868910276890811150621015911440044354
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_loopback/latest/run.log

  UVM_ERROR @ 3144778393 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (139 [0x8b] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 3144778393 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (255 [0xff] vs 139 [0x8b]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_ERROR @ 3145528393 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (28 [0x1c] vs 60 [0x3c]) Regname: uart_reg_block.status reset value: 0x3c
  UVM_INFO @ 3146153393 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/6
  UVM_ERROR @ 3252403393 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (85 [0x55] vs 139 [0x8b]) reg name: uart_reg_block.rdata

4.uart_loopback.113684882899804710800815049351344183795967915878193391455777260879492579923500
Line 261, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_loopback/latest/run.log

  UVM_ERROR @ 9985813174 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (79 [0x4f] vs 0 [0x0]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 9985813174 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 79 [0x4f]) Regname: uart_reg_block.rdata reset value: 0x0
  UVM_INFO @ 9986166118 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 14/19
  UVM_INFO @ 10075696246 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 15/19
  UVM_INFO @ 10088225758 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 16/19

... and 4 more failures.

UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:

Test uart_loopback has 2 failures.

2.uart_loopback.29836796240918669516389218622077930038327800891418241750362975188059432668911
Line 266, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_loopback/latest/run.log

  UVM_ERROR @ 10347902466 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 10347902466 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_INFO @ 10352942870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.uart_loopback.13018393851456650115393831000638979702179309600974096911043485864646189005561
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/24.uart_loopback/latest/run.log

  UVM_ERROR @ 3774843707 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 3774843707 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_INFO @ 3779883707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test uart_intr has 2 failures.
  - 7.uart_intr.56562586739991536714928608270797852928513222160813143114689889279875974197125
    Line 277, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.uart_intr.89634782084236733728853523020183250215002672726531814941928900355549908323964
    Line 298, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

29.uart_stress_all_with_rand_reset.89140151377914778394493267371684649606404944832094945936778626544859523457634
Line 552, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 327329013758 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 327459213758 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout
  UVM_INFO @ 328177613758 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 25/371
  UVM_INFO @ 329072613758 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 26/371

53.uart_stress_all_with_rand_reset.63788303206027399144222965039338928141310925470917186309726792750621730751116
Line 480, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 60635190540 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 60635190540 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (0 [0x0] vs 1 [0x1]) uart_intr name/val: TxWatermark/0, en_intr: c3
  UVM_INFO @ 60810990540 ps: (uart_intr_vseq.sv:42) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 2/3
  UVM_INFO @ 60811750540 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr

Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test uart_intr has 1 failures.
  - 20.uart_intr.103380752404367029522534274172406941536812243131126878619709477075168168185284
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_intr/latest/run.log
```
  Job ID: smart:acd432d6-7a53-4504-9472-3dedd63dfd71
```

UVM_ERROR (uart_scoreboard.sv:499) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

79.uart_stress_all_with_rand_reset.81039303212356370657843565052180926806412965300408926630685127304735405248025
Line 279, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16249128168 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 16404776472 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 8/8
  UVM_INFO @ 16621660560 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 24/434
  UVM_INFO @ 17136723504 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 25/434
  UVM_INFO @ 17203135800 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 1/10