UART Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	21.690s	5.991ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.040s	1.031ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	11.221us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.290s	108.341us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.800s	89.325us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.420s	32.517us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	11.221us	20	20	100.00
		uart_csr_aliasing	0.800s	89.325us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.915m	276.057ms	50	50	100.00
V2	parity	uart_smoke	21.690s	5.991ms	50	50	100.00
		uart_tx_rx	2.915m	276.057ms	50	50	100.00
V2	parity_error	uart_intr	7.291m	134.630ms	48	50	96.00
		uart_rx_parity_err	18.176m	253.546ms	50	50	100.00
V2	watermark	uart_tx_rx	2.915m	276.057ms	50	50	100.00
		uart_intr	7.291m	134.630ms	48	50	96.00
V2	fifo_full	uart_fifo_full	4.819m	189.954ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	14.415m	197.847ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.381m	97.190ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.291m	134.630ms	48	50	96.00
V2	rx_break_err	uart_intr	7.291m	134.630ms	48	50	96.00
V2	rx_timeout	uart_intr	7.291m	134.630ms	48	50	96.00
V2	perf	uart_perf	22.988m	24.369ms	50	50	100.00
V2	sys_loopback	uart_loopback	45.270s	13.748ms	50	50	100.00
V2	line_loopback	uart_loopback	45.270s	13.748ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.042m	134.253ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.416m	65.397ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	51.850s	12.666ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.130m	7.371ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	20.081m	110.362ms	49	50	98.00
V2	stress_all	uart_stress_all	25.042m	305.912ms	48	50	96.00
V2	alert_test	uart_alert_test	0.620s	79.408us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	141.574us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.310s	51.599us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.310s	51.599us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.040s	1.031ms	5	5	100.00
		uart_csr_rw	0.680s	11.221us	20	20	100.00
		uart_csr_aliasing	0.800s	89.325us	5	5	100.00
		uart_same_csr_outstanding	0.880s	36.355us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.040s	1.031ms	5	5	100.00
		uart_csr_rw	0.680s	11.221us	20	20	100.00
		uart_csr_aliasing	0.800s	89.325us	5	5	100.00
		uart_same_csr_outstanding	0.880s	36.355us	20	20	100.00
V2		TOTAL			1085	1090	99.54
V2S	tl_intg_err	uart_sec_cm	0.930s	61.050us	5	5	100.00
		uart_tl_intg_err	1.380s	169.371us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.380s	169.371us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	27.330m	79.962ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1312	1320	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.62

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 6 failures:

Test uart_intr has 1 failures.

5.uart_intr.11740420923187528331119979335279821937390177992004673035761523113041796208325
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_intr/latest/run.log

  UVM_ERROR @ 6001233252 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 6001233252 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 6087833252 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 7129673252 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_stress_all has 2 failures.

15.uart_stress_all.76972345835595923339638001044205940262287427286621371868620572442072075030521
Line 276, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_stress_all/latest/run.log

  UVM_ERROR @ 59396882893 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 59474175178 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr
  UVM_INFO @ 59552759140 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr

17.uart_stress_all.104953154050582720724405668219876164228810419518776879167473040868136011312629
Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_stress_all/latest/run.log

  UVM_ERROR @ 158552243214 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 158945003439 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/7
  UVM_INFO @ 160379504349 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/7
  UVM_INFO @ 161470753809 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/7
  UVM_INFO @ 161705621184 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/7

Test uart_stress_all_with_rand_reset has 3 failures.

37.uart_stress_all_with_rand_reset.115141012810984442634785694791498961552870881130534985757008403556870252963923
Line 456, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 55593480522 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 55643855925 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow
  UVM_INFO @ 55780232016 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 31/375
  UVM_INFO @ 55896691281 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 32/375

47.uart_stress_all_with_rand_reset.70979939645994554096687413746430706743525969219825659966950238278076499111337
Line 583, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 37005474063 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 37144107398 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 5/5
  UVM_INFO @ 37144235060 ps: (cip_base_vseq.sv:760) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/5

... and 1 more failures.

UVM_ERROR (uart_intr_vseq.sv:312) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_intr has 1 failures.

20.uart_intr.44207210318459962045384625313319239920047128754902154586866948110321142000060
Line 269, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_intr/latest/run.log

  UVM_ERROR @ 14193381185 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 14554581185 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 14964381185 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 15344181185 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 15693381185 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

26.uart_long_xfer_wo_dly.4454335388818763389225130440332114798792593079289232241728714831016425787943
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 115465743509 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 115802275613 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 116365633061 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 7/7
  UVM_INFO @ 131578048837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---