UART Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	27.140s	11.575ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	15.177us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	27.363us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.450s	872.664us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.800s	51.578us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.460s	37.019us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	27.363us	20	20	100.00
		uart_csr_aliasing	0.800s	51.578us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.213m	96.428ms	50	50	100.00
V2	parity	uart_smoke	27.140s	11.575ms	50	50	100.00
		uart_tx_rx	5.213m	96.428ms	50	50	100.00
V2	parity_error	uart_intr	3.835m	286.599ms	49	50	98.00
		uart_rx_parity_err	6.803m	161.801ms	50	50	100.00
V2	watermark	uart_tx_rx	5.213m	96.428ms	50	50	100.00
		uart_intr	3.835m	286.599ms	49	50	98.00
V2	fifo_full	uart_fifo_full	7.368m	177.065ms	49	50	98.00
V2	fifo_overflow	uart_fifo_overflow	4.177m	112.809ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.401m	128.190ms	298	300	99.33
V2	rx_frame_err	uart_intr	3.835m	286.599ms	49	50	98.00
V2	rx_break_err	uart_intr	3.835m	286.599ms	49	50	98.00
V2	rx_timeout	uart_intr	3.835m	286.599ms	49	50	98.00
V2	perf	uart_perf	30.356m	30.790ms	50	50	100.00
V2	sys_loopback	uart_loopback	58.600s	10.293ms	50	50	100.00
V2	line_loopback	uart_loopback	58.600s	10.293ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	7.760m	81.493ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.318m	86.076ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	28.220s	6.258ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.121m	6.718ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.884m	146.100ms	50	50	100.00
V2	stress_all	uart_stress_all	28.058m	568.148ms	49	50	98.00
V2	alert_test	uart_alert_test	0.630s	35.199us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	117.457us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.510s	239.243us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.510s	239.243us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	15.177us	5	5	100.00
		uart_csr_rw	0.680s	27.363us	20	20	100.00
		uart_csr_aliasing	0.800s	51.578us	5	5	100.00
		uart_same_csr_outstanding	0.810s	55.680us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	15.177us	5	5	100.00
		uart_csr_rw	0.680s	27.363us	20	20	100.00
		uart_csr_aliasing	0.800s	51.578us	5	5	100.00
		uart_same_csr_outstanding	0.810s	55.680us	20	20	100.00
V2		TOTAL			1085	1090	99.54
V2S	tl_intg_err	uart_sec_cm	0.900s	205.046us	5	5	100.00
		uart_tl_intg_err	1.440s	399.226us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.440s	399.226us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	37.606m	203.907ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1314	1320	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	14	77.78
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.53

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 5 failures:

Test uart_stress_all has 1 failures.

7.uart_stress_all.69894934923788836612776312173886408091322312832351134261042797959091779414122
Line 268, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_stress_all/latest/run.log

  UVM_ERROR @ 128751309161 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 128751309161 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 133834474826 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/6
  UVM_INFO @ 165479019647 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/6
  UVM_INFO @ 174535883768 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/6

Test uart_intr has 1 failures.

28.uart_intr.99361663529871408702854769229478468880305162297075208596277702659580076230834
Line 275, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/28.uart_intr/latest/run.log

  UVM_ERROR @ 15813021745 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 15890577313 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 16046909465 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow

Test uart_fifo_full has 1 failures.

30.uart_fifo_full.50383452133839990122003311511827760463449792756718018664559959457206166079318
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/30.uart_fifo_full/latest/run.log

  UVM_ERROR @ 143147718633 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 143147718633 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 184489111739 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 7/7
  UVM_INFO @ 188272457278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test uart_fifo_reset has 2 failures.

278.uart_fifo_reset.21678111662107246245678302027308522205416285150026266059491964526769970194920
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/278.uart_fifo_reset/latest/run.log

  UVM_ERROR @   1858084 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @  48797086 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/7
  UVM_INFO @ 94926385155 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7
  UVM_INFO @ 95872873775 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7
  UVM_INFO @ 97263584943 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/7

297.uart_fifo_reset.5769432710310364741776044546848010804209855030802001661694082861865868999282
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/297.uart_fifo_reset/latest/run.log

  UVM_ERROR @   1205095 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 246285640 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/8
  UVM_INFO @ 2719792087 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/8
  UVM_INFO @ 60243361949 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/8
  UVM_INFO @ 70273516237 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/8

UVM_ERROR (cip_base_vseq.sv:749) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

75.uart_stress_all_with_rand_reset.101912134023332099895120611466015592663922681218761202667721930462842269440389
Line 715, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 58987534239 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 58987534239 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 58987716055 ps: (cip_base_vseq.sv:760) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 7/10