| T208 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/143.uart_fifo_reset.2704055667 |
|
|
Aug 23 04:08:22 AM UTC 24 |
Aug 23 04:09:55 AM UTC 24 |
104970175877 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/169.uart_fifo_reset.486419636 |
|
|
Aug 23 04:09:32 AM UTC 24 |
Aug 23 04:09:56 AM UTC 24 |
12639091429 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/172.uart_fifo_reset.3539709757 |
|
|
Aug 23 04:09:43 AM UTC 24 |
Aug 23 04:09:59 AM UTC 24 |
9441225603 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/106.uart_fifo_reset.4176436611 |
|
|
Aug 23 04:06:55 AM UTC 24 |
Aug 23 04:09:59 AM UTC 24 |
129989444192 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/148.uart_fifo_reset.2432143710 |
|
|
Aug 23 04:08:34 AM UTC 24 |
Aug 23 04:10:04 AM UTC 24 |
190668658496 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/161.uart_fifo_reset.1830668620 |
|
|
Aug 23 04:09:10 AM UTC 24 |
Aug 23 04:10:08 AM UTC 24 |
28884620585 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/175.uart_fifo_reset.1441948935 |
|
|
Aug 23 04:09:49 AM UTC 24 |
Aug 23 04:10:15 AM UTC 24 |
119835556005 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/179.uart_fifo_reset.2199964810 |
|
|
Aug 23 04:09:54 AM UTC 24 |
Aug 23 04:10:17 AM UTC 24 |
171942467474 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/180.uart_fifo_reset.1940919985 |
|
|
Aug 23 04:09:56 AM UTC 24 |
Aug 23 04:10:21 AM UTC 24 |
16051942937 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/151.uart_fifo_reset.3126680386 |
|
|
Aug 23 04:08:46 AM UTC 24 |
Aug 23 04:10:22 AM UTC 24 |
113317137087 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/174.uart_fifo_reset.3401184408 |
|
|
Aug 23 04:09:49 AM UTC 24 |
Aug 23 04:10:22 AM UTC 24 |
42643733927 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/181.uart_fifo_reset.1943500807 |
|
|
Aug 23 04:09:56 AM UTC 24 |
Aug 23 04:10:30 AM UTC 24 |
21547369140 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/188.uart_fifo_reset.3878906929 |
|
|
Aug 23 04:10:18 AM UTC 24 |
Aug 23 04:10:35 AM UTC 24 |
19534796141 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_stress_all.3144858405 |
|
|
Aug 23 04:02:09 AM UTC 24 |
Aug 23 04:10:35 AM UTC 24 |
202461538796 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/186.uart_fifo_reset.2148392679 |
|
|
Aug 23 04:10:10 AM UTC 24 |
Aug 23 04:10:38 AM UTC 24 |
36622315947 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/187.uart_fifo_reset.2866939263 |
|
|
Aug 23 04:10:16 AM UTC 24 |
Aug 23 04:10:39 AM UTC 24 |
16482987442 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/178.uart_fifo_reset.3841536595 |
|
|
Aug 23 04:09:50 AM UTC 24 |
Aug 23 04:10:44 AM UTC 24 |
63113119428 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/171.uart_fifo_reset.4075942840 |
|
|
Aug 23 04:09:35 AM UTC 24 |
Aug 23 04:10:48 AM UTC 24 |
48774602319 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_perf.3866120941 |
|
|
Aug 23 03:59:51 AM UTC 24 |
Aug 23 04:10:53 AM UTC 24 |
11183608209 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/195.uart_fifo_reset.1261215558 |
|
|
Aug 23 04:10:39 AM UTC 24 |
Aug 23 04:10:55 AM UTC 24 |
169945564850 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3940788706 |
|
|
Aug 23 04:10:36 AM UTC 24 |
Aug 23 04:10:55 AM UTC 24 |
27718669972 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/165.uart_fifo_reset.3766240039 |
|
|
Aug 23 04:09:21 AM UTC 24 |
Aug 23 04:11:00 AM UTC 24 |
252907754539 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/194.uart_fifo_reset.2471242155 |
|
|
Aug 23 04:10:36 AM UTC 24 |
Aug 23 04:11:05 AM UTC 24 |
50679072083 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/183.uart_fifo_reset.2066849427 |
|
|
Aug 23 04:10:00 AM UTC 24 |
Aug 23 04:11:09 AM UTC 24 |
149118413117 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/197.uart_fifo_reset.2869271953 |
|
|
Aug 23 04:10:44 AM UTC 24 |
Aug 23 04:11:11 AM UTC 24 |
15945795562 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/189.uart_fifo_reset.1154250242 |
|
|
Aug 23 04:10:22 AM UTC 24 |
Aug 23 04:11:11 AM UTC 24 |
122445623949 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/199.uart_fifo_reset.3575397104 |
|
|
Aug 23 04:10:54 AM UTC 24 |
Aug 23 04:11:16 AM UTC 24 |
69732514790 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/184.uart_fifo_reset.645635644 |
|
|
Aug 23 04:10:01 AM UTC 24 |
Aug 23 04:11:17 AM UTC 24 |
93611933226 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/153.uart_fifo_reset.605448011 |
|
|
Aug 23 04:08:50 AM UTC 24 |
Aug 23 04:11:17 AM UTC 24 |
92618386316 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/203.uart_fifo_reset.1321384784 |
|
|
Aug 23 04:11:06 AM UTC 24 |
Aug 23 04:11:26 AM UTC 24 |
56636875665 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/201.uart_fifo_reset.1253346382 |
|
|
Aug 23 04:10:56 AM UTC 24 |
Aug 23 04:11:29 AM UTC 24 |
18687415862 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/166.uart_fifo_reset.3476923087 |
|
|
Aug 23 04:09:21 AM UTC 24 |
Aug 23 04:11:32 AM UTC 24 |
90757505547 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/191.uart_fifo_reset.528104710 |
|
|
Aug 23 04:10:23 AM UTC 24 |
Aug 23 04:11:35 AM UTC 24 |
54313874653 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/136.uart_fifo_reset.481796845 |
|
|
Aug 23 04:08:02 AM UTC 24 |
Aug 23 04:11:36 AM UTC 24 |
91254614137 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/190.uart_fifo_reset.3008844346 |
|
|
Aug 23 04:10:23 AM UTC 24 |
Aug 23 04:11:38 AM UTC 24 |
122340590672 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/185.uart_fifo_reset.3960708801 |
|
|
Aug 23 04:10:05 AM UTC 24 |
Aug 23 04:11:39 AM UTC 24 |
53656738026 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3038791994 |
|
|
Aug 23 04:11:27 AM UTC 24 |
Aug 23 04:11:42 AM UTC 24 |
38188704359 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/177.uart_fifo_reset.2586698463 |
|
|
Aug 23 04:09:49 AM UTC 24 |
Aug 23 04:11:44 AM UTC 24 |
151135670375 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2587846422 |
|
|
Aug 23 04:11:09 AM UTC 24 |
Aug 23 04:11:50 AM UTC 24 |
81853658298 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/120.uart_fifo_reset.833965394 |
|
|
Aug 23 04:07:25 AM UTC 24 |
Aug 23 04:11:51 AM UTC 24 |
131018758282 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/200.uart_fifo_reset.2709742033 |
|
|
Aug 23 04:10:56 AM UTC 24 |
Aug 23 04:11:54 AM UTC 24 |
80419236895 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/214.uart_fifo_reset.3840035092 |
|
|
Aug 23 04:11:37 AM UTC 24 |
Aug 23 04:11:54 AM UTC 24 |
16613135599 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/155.uart_fifo_reset.3284475178 |
|
|
Aug 23 04:08:54 AM UTC 24 |
Aug 23 04:11:59 AM UTC 24 |
64235633126 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/202.uart_fifo_reset.722717051 |
|
|
Aug 23 04:11:02 AM UTC 24 |
Aug 23 04:11:59 AM UTC 24 |
64040406254 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/196.uart_fifo_reset.2009254613 |
|
|
Aug 23 04:10:41 AM UTC 24 |
Aug 23 04:12:01 AM UTC 24 |
216845711089 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/208.uart_fifo_reset.1615785057 |
|
|
Aug 23 04:11:18 AM UTC 24 |
Aug 23 04:12:02 AM UTC 24 |
24820173150 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/192.uart_fifo_reset.9887256 |
|
|
Aug 23 04:10:30 AM UTC 24 |
Aug 23 04:12:04 AM UTC 24 |
180206270191 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1110872708 |
|
|
Aug 23 04:11:46 AM UTC 24 |
Aug 23 04:12:08 AM UTC 24 |
29989784551 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/182.uart_fifo_reset.950606759 |
|
|
Aug 23 04:09:56 AM UTC 24 |
Aug 23 04:12:09 AM UTC 24 |
103754709819 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/170.uart_fifo_reset.2105041501 |
|
|
Aug 23 04:09:32 AM UTC 24 |
Aug 23 04:12:09 AM UTC 24 |
108848832935 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2477708262 |
|
|
Aug 23 04:11:51 AM UTC 24 |
Aug 23 04:12:13 AM UTC 24 |
64252073965 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/225.uart_fifo_reset.4049716217 |
|
|
Aug 23 04:12:02 AM UTC 24 |
Aug 23 04:12:18 AM UTC 24 |
10487655601 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/221.uart_fifo_reset.4109248979 |
|
|
Aug 23 04:11:55 AM UTC 24 |
Aug 23 04:12:24 AM UTC 24 |
49319397956 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/226.uart_fifo_reset.3395074804 |
|
|
Aug 23 04:12:02 AM UTC 24 |
Aug 23 04:12:29 AM UTC 24 |
34026177996 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/205.uart_fifo_reset.302080411 |
|
|
Aug 23 04:11:12 AM UTC 24 |
Aug 23 04:12:29 AM UTC 24 |
40127563003 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2710029309 |
|
|
Aug 23 04:11:39 AM UTC 24 |
Aug 23 04:12:30 AM UTC 24 |
113577838557 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/213.uart_fifo_reset.2716978779 |
|
|
Aug 23 04:11:36 AM UTC 24 |
Aug 23 04:12:34 AM UTC 24 |
86491640265 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/217.uart_fifo_reset.4073935105 |
|
|
Aug 23 04:11:43 AM UTC 24 |
Aug 23 04:12:34 AM UTC 24 |
137269951019 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/220.uart_fifo_reset.687058604 |
|
|
Aug 23 04:11:52 AM UTC 24 |
Aug 23 04:12:39 AM UTC 24 |
61009404142 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/206.uart_fifo_reset.3156869079 |
|
|
Aug 23 04:11:12 AM UTC 24 |
Aug 23 04:12:40 AM UTC 24 |
135232283259 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/216.uart_fifo_reset.958050490 |
|
|
Aug 23 04:11:40 AM UTC 24 |
Aug 23 04:12:41 AM UTC 24 |
44800880186 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/233.uart_fifo_reset.3407226152 |
|
|
Aug 23 04:12:26 AM UTC 24 |
Aug 23 04:12:45 AM UTC 24 |
20784406272 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/231.uart_fifo_reset.2083926651 |
|
|
Aug 23 04:12:14 AM UTC 24 |
Aug 23 04:12:46 AM UTC 24 |
46130208938 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/235.uart_fifo_reset.3117645664 |
|
|
Aug 23 04:12:31 AM UTC 24 |
Aug 23 04:12:46 AM UTC 24 |
93992975901 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/234.uart_fifo_reset.2118313701 |
|
|
Aug 23 04:12:31 AM UTC 24 |
Aug 23 04:12:47 AM UTC 24 |
16560216104 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/232.uart_fifo_reset.2707218075 |
|
|
Aug 23 04:12:19 AM UTC 24 |
Aug 23 04:12:48 AM UTC 24 |
17268076665 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/238.uart_fifo_reset.515737045 |
|
|
Aug 23 04:12:35 AM UTC 24 |
Aug 23 04:12:51 AM UTC 24 |
32289147086 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.750879857 |
|
|
Aug 23 04:02:06 AM UTC 24 |
Aug 23 04:12:53 AM UTC 24 |
141216200279 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/239.uart_fifo_reset.860216243 |
|
|
Aug 23 04:12:40 AM UTC 24 |
Aug 23 04:12:58 AM UTC 24 |
11788827017 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/244.uart_fifo_reset.1978893909 |
|
|
Aug 23 04:12:47 AM UTC 24 |
Aug 23 04:12:59 AM UTC 24 |
8767342556 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/224.uart_fifo_reset.1373215215 |
|
|
Aug 23 04:12:01 AM UTC 24 |
Aug 23 04:12:59 AM UTC 24 |
104812019922 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/240.uart_fifo_reset.3396181606 |
|
|
Aug 23 04:12:41 AM UTC 24 |
Aug 23 04:13:01 AM UTC 24 |
15262483276 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/248.uart_fifo_reset.1139404514 |
|
|
Aug 23 04:12:53 AM UTC 24 |
Aug 23 04:13:03 AM UTC 24 |
41826840716 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1587810740 |
|
|
Aug 23 04:12:47 AM UTC 24 |
Aug 23 04:13:07 AM UTC 24 |
50904686317 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3601870975 |
|
|
Aug 23 04:12:48 AM UTC 24 |
Aug 23 04:13:09 AM UTC 24 |
50487249702 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/246.uart_fifo_reset.4182220571 |
|
|
Aug 23 04:12:50 AM UTC 24 |
Aug 23 04:13:13 AM UTC 24 |
16662975379 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/230.uart_fifo_reset.1012908888 |
|
|
Aug 23 04:12:11 AM UTC 24 |
Aug 23 04:13:13 AM UTC 24 |
47104511438 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/247.uart_fifo_reset.176723105 |
|
|
Aug 23 04:12:52 AM UTC 24 |
Aug 23 04:13:14 AM UTC 24 |
20858613318 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/198.uart_fifo_reset.1069831272 |
|
|
Aug 23 04:10:48 AM UTC 24 |
Aug 23 04:13:19 AM UTC 24 |
101209063054 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/253.uart_fifo_reset.2488909847 |
|
|
Aug 23 04:13:04 AM UTC 24 |
Aug 23 04:13:20 AM UTC 24 |
39175522269 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/227.uart_fifo_reset.821770081 |
|
|
Aug 23 04:12:05 AM UTC 24 |
Aug 23 04:13:20 AM UTC 24 |
36626735358 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/287.uart_fifo_reset.2600920229 |
|
|
Aug 23 04:14:16 AM UTC 24 |
Aug 23 04:14:43 AM UTC 24 |
39165272169 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_stress_all.1175953344 |
|
|
Aug 23 03:53:12 AM UTC 24 |
Aug 23 04:13:21 AM UTC 24 |
286127280117 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/163.uart_fifo_reset.3055384033 |
|
|
Aug 23 04:09:12 AM UTC 24 |
Aug 23 04:13:23 AM UTC 24 |
128474382817 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/241.uart_fifo_reset.3618252762 |
|
|
Aug 23 04:12:42 AM UTC 24 |
Aug 23 04:13:23 AM UTC 24 |
25031538998 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/209.uart_fifo_reset.273345484 |
|
|
Aug 23 04:11:19 AM UTC 24 |
Aug 23 04:13:27 AM UTC 24 |
151383846233 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/258.uart_fifo_reset.1567896208 |
|
|
Aug 23 04:13:15 AM UTC 24 |
Aug 23 04:13:28 AM UTC 24 |
9203479975 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/255.uart_fifo_reset.172374709 |
|
|
Aug 23 04:13:11 AM UTC 24 |
Aug 23 04:13:31 AM UTC 24 |
11216818173 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/252.uart_fifo_reset.1531229568 |
|
|
Aug 23 04:13:03 AM UTC 24 |
Aug 23 04:13:31 AM UTC 24 |
18788648840 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/256.uart_fifo_reset.2561240100 |
|
|
Aug 23 04:13:14 AM UTC 24 |
Aug 23 04:13:33 AM UTC 24 |
38468052652 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/260.uart_fifo_reset.1635736520 |
|
|
Aug 23 04:13:21 AM UTC 24 |
Aug 23 04:13:35 AM UTC 24 |
33169714786 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/257.uart_fifo_reset.1301512602 |
|
|
Aug 23 04:13:15 AM UTC 24 |
Aug 23 04:13:37 AM UTC 24 |
51189159011 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/261.uart_fifo_reset.3493298497 |
|
|
Aug 23 04:13:21 AM UTC 24 |
Aug 23 04:13:39 AM UTC 24 |
50912055720 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/237.uart_fifo_reset.764207583 |
|
|
Aug 23 04:12:35 AM UTC 24 |
Aug 23 04:13:41 AM UTC 24 |
38534938281 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/173.uart_fifo_reset.3935215248 |
|
|
Aug 23 04:09:46 AM UTC 24 |
Aug 23 04:13:48 AM UTC 24 |
51348889313 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/267.uart_fifo_reset.899748991 |
|
|
Aug 23 04:13:32 AM UTC 24 |
Aug 23 04:13:49 AM UTC 24 |
12454437434 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/212.uart_fifo_reset.914488352 |
|
|
Aug 23 04:11:33 AM UTC 24 |
Aug 23 04:13:49 AM UTC 24 |
86457026284 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/272.uart_fifo_reset.814607273 |
|
|
Aug 23 04:13:40 AM UTC 24 |
Aug 23 04:13:49 AM UTC 24 |
20778814255 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/265.uart_fifo_reset.4124832964 |
|
|
Aug 23 04:13:29 AM UTC 24 |
Aug 23 04:13:50 AM UTC 24 |
51533804193 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1653995707 |
|
|
Aug 23 04:13:00 AM UTC 24 |
Aug 23 04:13:52 AM UTC 24 |
29150288515 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/266.uart_fifo_reset.4228023386 |
|
|
Aug 23 04:13:29 AM UTC 24 |
Aug 23 04:13:58 AM UTC 24 |
18058240348 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/269.uart_fifo_reset.2369225218 |
|
|
Aug 23 04:13:34 AM UTC 24 |
Aug 23 04:14:00 AM UTC 24 |
59502833799 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/275.uart_fifo_reset.4187427834 |
|
|
Aug 23 04:13:51 AM UTC 24 |
Aug 23 04:14:07 AM UTC 24 |
10607581563 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1987998511 |
|
|
Aug 23 04:13:07 AM UTC 24 |
Aug 23 04:14:11 AM UTC 24 |
48382496772 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/274.uart_fifo_reset.2685737760 |
|
|
Aug 23 04:13:49 AM UTC 24 |
Aug 23 04:14:13 AM UTC 24 |
22119836766 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/262.uart_fifo_reset.559842092 |
|
|
Aug 23 04:13:23 AM UTC 24 |
Aug 23 04:14:14 AM UTC 24 |
34307892829 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/176.uart_fifo_reset.530966503 |
|
|
Aug 23 04:09:49 AM UTC 24 |
Aug 23 04:14:14 AM UTC 24 |
147480014567 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/264.uart_fifo_reset.4250964972 |
|
|
Aug 23 04:13:25 AM UTC 24 |
Aug 23 04:14:16 AM UTC 24 |
44068209753 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/280.uart_fifo_reset.1521291957 |
|
|
Aug 23 04:13:59 AM UTC 24 |
Aug 23 04:14:17 AM UTC 24 |
48048636090 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/251.uart_fifo_reset.578572025 |
|
|
Aug 23 04:13:00 AM UTC 24 |
Aug 23 04:14:17 AM UTC 24 |
49703429134 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/211.uart_fifo_reset.1066003174 |
|
|
Aug 23 04:11:31 AM UTC 24 |
Aug 23 04:14:19 AM UTC 24 |
86334318412 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/279.uart_fifo_reset.4290382758 |
|
|
Aug 23 04:13:53 AM UTC 24 |
Aug 23 04:14:19 AM UTC 24 |
30743358159 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1914296950 |
|
|
Aug 23 04:13:38 AM UTC 24 |
Aug 23 04:14:20 AM UTC 24 |
50811165196 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/270.uart_fifo_reset.743134065 |
|
|
Aug 23 04:13:37 AM UTC 24 |
Aug 23 04:14:25 AM UTC 24 |
131966692948 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/222.uart_fifo_reset.1775920009 |
|
|
Aug 23 04:11:55 AM UTC 24 |
Aug 23 04:14:26 AM UTC 24 |
110440872692 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/289.uart_fifo_reset.2891777848 |
|
|
Aug 23 04:14:17 AM UTC 24 |
Aug 23 04:14:28 AM UTC 24 |
6473429664 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/228.uart_fifo_reset.2773220780 |
|
|
Aug 23 04:12:09 AM UTC 24 |
Aug 23 04:14:30 AM UTC 24 |
94044587100 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/273.uart_fifo_reset.3305334974 |
|
|
Aug 23 04:13:42 AM UTC 24 |
Aug 23 04:14:32 AM UTC 24 |
133640103430 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2998374345 |
|
|
Aug 23 04:14:06 AM UTC 24 |
Aug 23 04:14:34 AM UTC 24 |
19873133570 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/288.uart_fifo_reset.810000010 |
|
|
Aug 23 04:14:17 AM UTC 24 |
Aug 23 04:14:35 AM UTC 24 |
39830078020 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1341988291 |
|
|
Aug 23 04:14:21 AM UTC 24 |
Aug 23 04:14:35 AM UTC 24 |
14709804438 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/283.uart_fifo_reset.693288495 |
|
|
Aug 23 04:14:08 AM UTC 24 |
Aug 23 04:14:41 AM UTC 24 |
116550732768 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/284.uart_fifo_reset.3976934233 |
|
|
Aug 23 04:14:13 AM UTC 24 |
Aug 23 04:14:48 AM UTC 24 |
21973588666 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/276.uart_fifo_reset.3698872746 |
|
|
Aug 23 04:13:51 AM UTC 24 |
Aug 23 04:14:48 AM UTC 24 |
127592019843 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/223.uart_fifo_reset.63207474 |
|
|
Aug 23 04:12:01 AM UTC 24 |
Aug 23 04:14:53 AM UTC 24 |
92346451761 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/156.uart_fifo_reset.3611495620 |
|
|
Aug 23 04:09:02 AM UTC 24 |
Aug 23 04:14:57 AM UTC 24 |
99571780619 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/299.uart_fifo_reset.2284957615 |
|
|
Aug 23 04:14:35 AM UTC 24 |
Aug 23 04:14:58 AM UTC 24 |
56099616081 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/295.uart_fifo_reset.3271829840 |
|
|
Aug 23 04:14:28 AM UTC 24 |
Aug 23 04:15:03 AM UTC 24 |
154788895979 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/278.uart_fifo_reset.64807289 |
|
|
Aug 23 04:13:53 AM UTC 24 |
Aug 23 04:15:04 AM UTC 24 |
60250698019 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/281.uart_fifo_reset.918334384 |
|
|
Aug 23 04:14:02 AM UTC 24 |
Aug 23 04:15:05 AM UTC 24 |
17214181057 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/236.uart_fifo_reset.440460340 |
|
|
Aug 23 04:12:31 AM UTC 24 |
Aug 23 04:15:07 AM UTC 24 |
123173271739 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/297.uart_fifo_reset.1356697458 |
|
|
Aug 23 04:14:31 AM UTC 24 |
Aug 23 04:15:14 AM UTC 24 |
132279383512 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/259.uart_fifo_reset.324137197 |
|
|
Aug 23 04:13:20 AM UTC 24 |
Aug 23 04:15:15 AM UTC 24 |
125554006963 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/298.uart_fifo_reset.3326094940 |
|
|
Aug 23 04:14:34 AM UTC 24 |
Aug 23 04:15:20 AM UTC 24 |
29886841945 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/134.uart_fifo_reset.1557157949 |
|
|
Aug 23 04:07:59 AM UTC 24 |
Aug 23 04:15:22 AM UTC 24 |
119797185035 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/229.uart_fifo_reset.4183891208 |
|
|
Aug 23 04:12:09 AM UTC 24 |
Aug 23 04:15:26 AM UTC 24 |
123473229269 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1566804154 |
|
|
Aug 23 04:12:47 AM UTC 24 |
Aug 23 04:15:37 AM UTC 24 |
123924035753 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2398793107 |
|
|
Aug 23 04:14:19 AM UTC 24 |
Aug 23 04:15:40 AM UTC 24 |
104811283914 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/294.uart_fifo_reset.1308519289 |
|
|
Aug 23 04:14:26 AM UTC 24 |
Aug 23 04:15:44 AM UTC 24 |
122617972269 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/296.uart_fifo_reset.2837060077 |
|
|
Aug 23 04:14:29 AM UTC 24 |
Aug 23 04:15:53 AM UTC 24 |
49008499572 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/286.uart_fifo_reset.1512808931 |
|
|
Aug 23 04:14:16 AM UTC 24 |
Aug 23 04:15:59 AM UTC 24 |
74788143387 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/263.uart_fifo_reset.3873723861 |
|
|
Aug 23 04:13:25 AM UTC 24 |
Aug 23 04:16:03 AM UTC 24 |
152608092091 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/285.uart_fifo_reset.2243902978 |
|
|
Aug 23 04:14:14 AM UTC 24 |
Aug 23 04:16:11 AM UTC 24 |
83590084004 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2444254164 |
|
|
Aug 23 04:11:18 AM UTC 24 |
Aug 23 04:16:23 AM UTC 24 |
203285946357 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_perf.806857746 |
|
|
Aug 23 03:58:10 AM UTC 24 |
Aug 23 04:16:23 AM UTC 24 |
21363410436 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/277.uart_fifo_reset.1221407859 |
|
|
Aug 23 04:13:51 AM UTC 24 |
Aug 23 04:17:28 AM UTC 24 |
70737107381 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/249.uart_fifo_reset.2507677518 |
|
|
Aug 23 04:12:59 AM UTC 24 |
Aug 23 04:17:34 AM UTC 24 |
160453141611 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/293.uart_fifo_reset.343559031 |
|
|
Aug 23 04:14:21 AM UTC 24 |
Aug 23 04:17:41 AM UTC 24 |
268950733135 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/292.uart_fifo_reset.3066316034 |
|
|
Aug 23 04:14:21 AM UTC 24 |
Aug 23 04:17:46 AM UTC 24 |
130193330641 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/268.uart_fifo_reset.1084059855 |
|
|
Aug 23 04:13:33 AM UTC 24 |
Aug 23 04:18:04 AM UTC 24 |
76917720583 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.1212602400 |
|
|
Aug 23 03:21:13 AM UTC 24 |
Aug 23 03:21:15 AM UTC 24 |
14053885 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.1922561974 |
|
|
Aug 23 03:21:13 AM UTC 24 |
Aug 23 03:21:15 AM UTC 24 |
304404951 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.161656595 |
|
|
Aug 23 03:21:13 AM UTC 24 |
Aug 23 03:21:16 AM UTC 24 |
150851129 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1451890943 |
|
|
Aug 23 03:21:15 AM UTC 24 |
Aug 23 03:21:17 AM UTC 24 |
21155296 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.4109045183 |
|
|
Aug 23 03:21:15 AM UTC 24 |
Aug 23 03:21:17 AM UTC 24 |
28372178 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.2778115928 |
|
|
Aug 23 03:21:17 AM UTC 24 |
Aug 23 03:21:18 AM UTC 24 |
49549879 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3087107214 |
|
|
Aug 23 03:21:17 AM UTC 24 |
Aug 23 03:21:18 AM UTC 24 |
43560108 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1128969289 |
|
|
Aug 23 03:21:17 AM UTC 24 |
Aug 23 03:21:19 AM UTC 24 |
122340420 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1803930995 |
|
|
Aug 23 03:21:18 AM UTC 24 |
Aug 23 03:21:20 AM UTC 24 |
87837811 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.1078118026 |
|
|
Aug 23 03:21:19 AM UTC 24 |
Aug 23 03:21:20 AM UTC 24 |
26132067 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1195859586 |
|
|
Aug 23 03:21:18 AM UTC 24 |
Aug 23 03:21:21 AM UTC 24 |
162741331 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2762911351 |
|
|
Aug 23 03:21:19 AM UTC 24 |
Aug 23 03:21:21 AM UTC 24 |
121040525 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.4285414618 |
|
|
Aug 23 03:21:20 AM UTC 24 |
Aug 23 03:21:22 AM UTC 24 |
22811575 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.2293217388 |
|
|
Aug 23 03:21:20 AM UTC 24 |
Aug 23 03:21:22 AM UTC 24 |
24620754 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.1089093064 |
|
|
Aug 23 03:21:20 AM UTC 24 |
Aug 23 03:21:23 AM UTC 24 |
73637865 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.850450040 |
|
|
Aug 23 03:21:21 AM UTC 24 |
Aug 23 03:21:23 AM UTC 24 |
19740026 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.3594936446 |
|
|
Aug 23 03:21:21 AM UTC 24 |
Aug 23 03:21:23 AM UTC 24 |
54835233 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.235594208 |
|
|
Aug 23 03:21:22 AM UTC 24 |
Aug 23 03:21:23 AM UTC 24 |
123367402 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.4203973510 |
|
|
Aug 23 03:21:23 AM UTC 24 |
Aug 23 03:21:25 AM UTC 24 |
182880528 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.2845256147 |
|
|
Aug 23 03:21:23 AM UTC 24 |
Aug 23 03:21:25 AM UTC 24 |
167014928 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2449092367 |
|
|
Aug 23 03:21:24 AM UTC 24 |
Aug 23 03:21:25 AM UTC 24 |
71438870 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.449794431 |
|
|
Aug 23 03:21:24 AM UTC 24 |
Aug 23 03:21:25 AM UTC 24 |
16715489 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.205757113 |
|
|
Aug 23 03:21:24 AM UTC 24 |
Aug 23 03:21:25 AM UTC 24 |
12296022 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.4076149696 |
|
|
Aug 23 03:21:24 AM UTC 24 |
Aug 23 03:21:27 AM UTC 24 |
207665708 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.1802429872 |
|
|
Aug 23 03:21:26 AM UTC 24 |
Aug 23 03:21:27 AM UTC 24 |
14071344 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.2721833679 |
|
|
Aug 23 03:21:26 AM UTC 24 |
Aug 23 03:21:27 AM UTC 24 |
16423445 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.932222338 |
|
|
Aug 23 03:21:26 AM UTC 24 |
Aug 23 03:21:28 AM UTC 24 |
100343096 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.416232371 |
|
|
Aug 23 03:21:26 AM UTC 24 |
Aug 23 03:21:28 AM UTC 24 |
471878711 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.1077989000 |
|
|
Aug 23 03:21:26 AM UTC 24 |
Aug 23 03:21:29 AM UTC 24 |
38224952 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.324055611 |
|
|
Aug 23 03:21:28 AM UTC 24 |
Aug 23 03:21:29 AM UTC 24 |
21640731 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.2552868363 |
|
|
Aug 23 03:21:28 AM UTC 24 |
Aug 23 03:21:30 AM UTC 24 |
37759233 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.1320623635 |
|
|
Aug 23 03:21:28 AM UTC 24 |
Aug 23 03:21:30 AM UTC 24 |
58461909 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.3716358602 |
|
|
Aug 23 03:21:29 AM UTC 24 |
Aug 23 03:21:31 AM UTC 24 |
60591956 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.3112728721 |
|
|
Aug 23 03:21:29 AM UTC 24 |
Aug 23 03:21:31 AM UTC 24 |
238049712 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3161017412 |
|
|
Aug 23 03:21:30 AM UTC 24 |
Aug 23 03:21:32 AM UTC 24 |
97273919 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2457160336 |
|
|
Aug 23 03:21:29 AM UTC 24 |
Aug 23 03:21:33 AM UTC 24 |
255082991 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.2250284582 |
|
|
Aug 23 03:21:30 AM UTC 24 |
Aug 23 03:21:33 AM UTC 24 |
93052657 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.2049810167 |
|
|
Aug 23 03:21:30 AM UTC 24 |
Aug 23 03:21:33 AM UTC 24 |
298303909 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.400031359 |
|
|
Aug 23 03:21:32 AM UTC 24 |
Aug 23 03:21:33 AM UTC 24 |
15635814 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3861127492 |
|
|
Aug 23 03:21:32 AM UTC 24 |
Aug 23 03:21:33 AM UTC 24 |
43186914 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.319833173 |
|
|
Aug 23 03:21:32 AM UTC 24 |
Aug 23 03:21:33 AM UTC 24 |
21714209 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.1770443148 |
|
|
Aug 23 03:21:34 AM UTC 24 |
Aug 23 03:21:36 AM UTC 24 |
113608512 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2559249555 |
|
|
Aug 23 03:21:34 AM UTC 24 |
Aug 23 03:21:36 AM UTC 24 |
49666113 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.2498851055 |
|
|
Aug 23 03:21:34 AM UTC 24 |
Aug 23 03:21:36 AM UTC 24 |
21599471 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.70604258 |
|
|
Aug 23 03:21:34 AM UTC 24 |
Aug 23 03:21:36 AM UTC 24 |
87424213 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.1392750888 |
|
|
Aug 23 03:21:34 AM UTC 24 |
Aug 23 03:21:36 AM UTC 24 |
97166465 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.1955536937 |
|
|
Aug 23 03:21:33 AM UTC 24 |
Aug 23 03:21:36 AM UTC 24 |
1378220174 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.2953411430 |
|
|
Aug 23 03:21:34 AM UTC 24 |
Aug 23 03:21:36 AM UTC 24 |
329426432 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.4146936621 |
|
|
Aug 23 03:21:36 AM UTC 24 |
Aug 23 03:21:38 AM UTC 24 |
16190237 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.4088613420 |
|
|
Aug 23 03:21:36 AM UTC 24 |
Aug 23 03:21:38 AM UTC 24 |
155721992 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1672444504 |
|
|
Aug 23 03:21:36 AM UTC 24 |
Aug 23 03:21:38 AM UTC 24 |
76807507 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.105333683 |
|
|
Aug 23 03:21:36 AM UTC 24 |
Aug 23 03:21:38 AM UTC 24 |
204195204 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.3573860635 |
|
|
Aug 23 03:21:38 AM UTC 24 |
Aug 23 03:21:39 AM UTC 24 |
34752158 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1471556363 |
|
|
Aug 23 03:21:38 AM UTC 24 |
Aug 23 03:21:39 AM UTC 24 |
43371807 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.4146873830 |
|
|
Aug 23 03:21:38 AM UTC 24 |
Aug 23 03:21:39 AM UTC 24 |
80082814 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2981529175 |
|
|
Aug 23 03:21:36 AM UTC 24 |
Aug 23 03:21:39 AM UTC 24 |
102868414 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.1234010632 |
|
|
Aug 23 03:21:39 AM UTC 24 |
Aug 23 03:21:40 AM UTC 24 |
46378838 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2495306950 |
|
|
Aug 23 03:21:39 AM UTC 24 |
Aug 23 03:21:41 AM UTC 24 |
73320997 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.1832748877 |
|
|
Aug 23 03:21:39 AM UTC 24 |
Aug 23 03:21:41 AM UTC 24 |
46904282 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.3079598957 |
|
|
Aug 23 03:21:39 AM UTC 24 |
Aug 23 03:21:42 AM UTC 24 |
364374181 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.504181629 |
|
|
Aug 23 03:21:41 AM UTC 24 |
Aug 23 03:21:42 AM UTC 24 |
13948505 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.2310784769 |
|
|
Aug 23 03:21:41 AM UTC 24 |
Aug 23 03:21:42 AM UTC 24 |
44279240 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.4098666028 |
|
|
Aug 23 03:21:41 AM UTC 24 |
Aug 23 03:21:42 AM UTC 24 |
20982665 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.920087833 |
|
|
Aug 23 03:21:41 AM UTC 24 |
Aug 23 03:21:42 AM UTC 24 |
26714509 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1047344271 |
|
|
Aug 23 03:21:41 AM UTC 24 |
Aug 23 03:21:43 AM UTC 24 |
32814298 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.4018668607 |
|
|
Aug 23 03:21:41 AM UTC 24 |
Aug 23 03:21:43 AM UTC 24 |
200772726 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.357943008 |
|
|
Aug 23 03:21:42 AM UTC 24 |
Aug 23 03:21:44 AM UTC 24 |
29857244 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2289157640 |
|
|
Aug 23 03:21:42 AM UTC 24 |
Aug 23 03:21:44 AM UTC 24 |
94019116 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1894393965 |
|
|
Aug 23 03:21:41 AM UTC 24 |
Aug 23 03:21:44 AM UTC 24 |
93734553 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2422131142 |
|
|
Aug 23 03:21:43 AM UTC 24 |
Aug 23 03:21:45 AM UTC 24 |
13808032 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.3635534580 |
|
|
Aug 23 03:21:43 AM UTC 24 |
Aug 23 03:21:45 AM UTC 24 |
21669425 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3954861167 |
|
|
Aug 23 03:21:43 AM UTC 24 |
Aug 23 03:21:45 AM UTC 24 |
23497459 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.125398436 |
|
|
Aug 23 03:21:43 AM UTC 24 |
Aug 23 03:21:45 AM UTC 24 |
19135310 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.1443062316 |
|
|
Aug 23 03:21:43 AM UTC 24 |
Aug 23 03:21:45 AM UTC 24 |
44841253 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.2785171011 |
|
|
Aug 23 03:21:43 AM UTC 24 |
Aug 23 03:21:45 AM UTC 24 |
53329260 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.3836284317 |
|
|
Aug 23 03:21:45 AM UTC 24 |
Aug 23 03:21:46 AM UTC 24 |
44739544 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.3464380024 |
|
|
Aug 23 03:21:45 AM UTC 24 |
Aug 23 03:21:46 AM UTC 24 |
25421346 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.2704128567 |
|
|
Aug 23 03:21:45 AM UTC 24 |
Aug 23 03:21:46 AM UTC 24 |
28489627 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1867752348 |
|
|
Aug 23 03:21:45 AM UTC 24 |
Aug 23 03:21:47 AM UTC 24 |
69446806 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.944790061 |
|
|
Aug 23 03:21:46 AM UTC 24 |
Aug 23 03:21:48 AM UTC 24 |
71918377 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1514965943 |
|
|
Aug 23 03:21:45 AM UTC 24 |
Aug 23 03:21:48 AM UTC 24 |
92605146 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.3299047500 |
|
|
Aug 23 03:21:46 AM UTC 24 |
Aug 23 03:21:48 AM UTC 24 |
45436654 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3147084711 |
|
|
Aug 23 03:21:46 AM UTC 24 |
Aug 23 03:21:48 AM UTC 24 |
123449362 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.2966929426 |
|
|
Aug 23 03:21:46 AM UTC 24 |
Aug 23 03:21:48 AM UTC 24 |
64201815 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1612795845 |
|
|
Aug 23 03:21:46 AM UTC 24 |
Aug 23 03:21:48 AM UTC 24 |
20561117 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3014798309 |
|
|
Aug 23 03:21:46 AM UTC 24 |
Aug 23 03:21:48 AM UTC 24 |
444064527 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.4008373925 |
|
|
Aug 23 03:21:47 AM UTC 24 |
Aug 23 03:21:49 AM UTC 24 |
12762902 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.3586740387 |
|
|
Aug 23 03:21:47 AM UTC 24 |
Aug 23 03:21:49 AM UTC 24 |
177132025 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1274751102 |
|
|
Aug 23 03:21:47 AM UTC 24 |
Aug 23 03:21:49 AM UTC 24 |
21740433 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3790130941 |
|
|
Aug 23 03:21:47 AM UTC 24 |
Aug 23 03:21:49 AM UTC 24 |
55068739 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.4119087322 |
|
|
Aug 23 03:21:48 AM UTC 24 |
Aug 23 03:21:50 AM UTC 24 |
59253180 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.3473993342 |
|
|
Aug 23 03:21:48 AM UTC 24 |
Aug 23 03:21:50 AM UTC 24 |
246300319 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2622728993 |
|
|
Aug 23 03:21:48 AM UTC 24 |
Aug 23 03:21:50 AM UTC 24 |
14232178 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.553752537 |
|
|
Aug 23 03:21:48 AM UTC 24 |
Aug 23 03:21:50 AM UTC 24 |
26290751 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.788285069 |
|
|
Aug 23 03:21:48 AM UTC 24 |
Aug 23 03:21:51 AM UTC 24 |
132474473 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.948773466 |
|
|
Aug 23 03:21:48 AM UTC 24 |
Aug 23 03:21:51 AM UTC 24 |
139659474 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.3247133249 |
|
|
Aug 23 03:21:49 AM UTC 24 |
Aug 23 03:21:51 AM UTC 24 |
130064032 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.2048604597 |
|
|
Aug 23 03:21:49 AM UTC 24 |
Aug 23 03:21:51 AM UTC 24 |
25891221 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.814299818 |
|
|
Aug 23 03:21:50 AM UTC 24 |
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Aug 23 03:21:51 AM UTC 24 |
Aug 23 03:21:52 AM UTC 24 |
45090770 ps |