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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.48


Total test records in report: 1315
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T1251 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1743813720 Aug 23 03:21:51 AM UTC 24 Aug 23 03:21:52 AM UTC 24 41448750 ps
T1252 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.1288917154 Aug 23 03:21:50 AM UTC 24 Aug 23 03:21:52 AM UTC 24 38196488 ps
T1253 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2424992751 Aug 23 03:21:51 AM UTC 24 Aug 23 03:21:52 AM UTC 24 28763110 ps
T1254 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.2464425044 Aug 23 03:21:51 AM UTC 24 Aug 23 03:21:53 AM UTC 24 176234944 ps
T1255 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.730634132 Aug 23 03:21:52 AM UTC 24 Aug 23 03:21:54 AM UTC 24 32326484 ps
T1256 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.41170001 Aug 23 03:21:52 AM UTC 24 Aug 23 03:21:54 AM UTC 24 14190771 ps
T1257 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3411190928 Aug 23 03:21:52 AM UTC 24 Aug 23 03:21:54 AM UTC 24 70243586 ps
T1258 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2659682580 Aug 23 03:21:53 AM UTC 24 Aug 23 03:21:54 AM UTC 24 57445641 ps
T1259 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.338323070 Aug 23 03:21:52 AM UTC 24 Aug 23 03:21:54 AM UTC 24 60328104 ps
T1260 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.2522117380 Aug 23 03:21:52 AM UTC 24 Aug 23 03:21:54 AM UTC 24 48479044 ps
T1261 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4107276211 Aug 23 03:21:53 AM UTC 24 Aug 23 03:21:55 AM UTC 24 104521518 ps
T1262 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.759297845 Aug 23 03:21:53 AM UTC 24 Aug 23 03:21:55 AM UTC 24 270265103 ps
T1263 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.3486550158 Aug 23 03:21:54 AM UTC 24 Aug 23 03:21:55 AM UTC 24 12317401 ps
T1264 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.511420566 Aug 23 03:21:54 AM UTC 24 Aug 23 03:21:55 AM UTC 24 56971230 ps
T1265 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1810320879 Aug 23 03:21:54 AM UTC 24 Aug 23 03:21:55 AM UTC 24 27228213 ps
T1266 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.276418142 Aug 23 03:21:54 AM UTC 24 Aug 23 03:21:56 AM UTC 24 81817653 ps
T1267 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2485696054 Aug 23 03:21:54 AM UTC 24 Aug 23 03:21:56 AM UTC 24 377330326 ps
T1268 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.4030091155 Aug 23 03:21:55 AM UTC 24 Aug 23 03:21:56 AM UTC 24 14809708 ps
T1269 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.1171023053 Aug 23 03:21:55 AM UTC 24 Aug 23 03:21:56 AM UTC 24 13458438 ps
T1270 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.2231618264 Aug 23 03:21:55 AM UTC 24 Aug 23 03:21:57 AM UTC 24 33845187 ps
T1271 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3202173359 Aug 23 03:21:55 AM UTC 24 Aug 23 03:21:57 AM UTC 24 191031527 ps
T1272 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3179970196 Aug 23 03:21:55 AM UTC 24 Aug 23 03:21:57 AM UTC 24 32283610 ps
T1273 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.13401156 Aug 23 03:21:55 AM UTC 24 Aug 23 03:21:57 AM UTC 24 153535176 ps
T1274 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.1720322792 Aug 23 03:21:56 AM UTC 24 Aug 23 03:21:58 AM UTC 24 10978648 ps
T1275 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3691604981 Aug 23 03:21:56 AM UTC 24 Aug 23 03:21:58 AM UTC 24 49740892 ps
T1276 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.158380740 Aug 23 03:21:56 AM UTC 24 Aug 23 03:21:58 AM UTC 24 23277751 ps
T1277 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.4033238495 Aug 23 03:21:56 AM UTC 24 Aug 23 03:21:58 AM UTC 24 154223821 ps
T1278 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2456012042 Aug 23 03:21:56 AM UTC 24 Aug 23 03:21:58 AM UTC 24 21686561 ps
T1279 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3141842521 Aug 23 03:21:56 AM UTC 24 Aug 23 03:21:58 AM UTC 24 275756402 ps
T1280 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.707443248 Aug 23 03:21:57 AM UTC 24 Aug 23 03:21:59 AM UTC 24 41878509 ps
T1281 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.3251728138 Aug 23 03:21:57 AM UTC 24 Aug 23 03:21:59 AM UTC 24 14163702 ps
T1282 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.835896095 Aug 23 03:21:57 AM UTC 24 Aug 23 03:21:59 AM UTC 24 104557754 ps
T1283 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3379831024 Aug 23 03:21:57 AM UTC 24 Aug 23 03:21:59 AM UTC 24 209846962 ps
T1284 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2549200484 Aug 23 03:21:57 AM UTC 24 Aug 23 03:22:00 AM UTC 24 52896523 ps
T1285 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.3088480274 Aug 23 03:21:57 AM UTC 24 Aug 23 03:22:00 AM UTC 24 433624275 ps
T1286 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.613475841 Aug 23 03:21:58 AM UTC 24 Aug 23 03:22:00 AM UTC 24 16487322 ps
T1287 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1150245201 Aug 23 03:21:58 AM UTC 24 Aug 23 03:22:00 AM UTC 24 16499918 ps
T1288 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.1329449839 Aug 23 03:21:58 AM UTC 24 Aug 23 03:22:00 AM UTC 24 12522282 ps
T1289 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1723773474 Aug 23 03:21:58 AM UTC 24 Aug 23 03:22:00 AM UTC 24 32972050 ps
T1290 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.1453192386 Aug 23 03:21:59 AM UTC 24 Aug 23 03:22:00 AM UTC 24 156762652 ps
T1291 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.1956939845 Aug 23 03:21:59 AM UTC 24 Aug 23 03:22:00 AM UTC 24 56882342 ps
T1292 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2805825860 Aug 23 03:21:59 AM UTC 24 Aug 23 03:22:00 AM UTC 24 15966149 ps
T1293 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.4186855562 Aug 23 03:22:00 AM UTC 24 Aug 23 03:22:01 AM UTC 24 96291142 ps
T1294 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2176702158 Aug 23 03:22:00 AM UTC 24 Aug 23 03:22:01 AM UTC 24 99260565 ps
T1295 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.1774851269 Aug 23 03:22:00 AM UTC 24 Aug 23 03:22:01 AM UTC 24 33822027 ps
T1296 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.637355446 Aug 23 03:22:00 AM UTC 24 Aug 23 03:22:01 AM UTC 24 31147153 ps
T1297 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2727206598 Aug 23 03:22:01 AM UTC 24 Aug 23 03:22:02 AM UTC 24 15532082 ps
T1298 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.1754986547 Aug 23 03:22:01 AM UTC 24 Aug 23 03:22:02 AM UTC 24 18875781 ps
T1299 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.3590523838 Aug 23 03:22:01 AM UTC 24 Aug 23 03:22:02 AM UTC 24 48528476 ps
T1300 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.4063874207 Aug 23 03:22:01 AM UTC 24 Aug 23 03:22:02 AM UTC 24 14101293 ps
T1301 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3180295914 Aug 23 03:22:01 AM UTC 24 Aug 23 03:22:02 AM UTC 24 28321590 ps
T1302 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.1714739192 Aug 23 03:22:01 AM UTC 24 Aug 23 03:22:02 AM UTC 24 15837574 ps
T1303 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2411184587 Aug 23 03:22:01 AM UTC 24 Aug 23 03:22:02 AM UTC 24 11981999 ps
T1304 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.1440702750 Aug 23 03:22:01 AM UTC 24 Aug 23 03:22:03 AM UTC 24 11911315 ps
T1305 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.2643470769 Aug 23 03:22:01 AM UTC 24 Aug 23 03:22:03 AM UTC 24 11831728 ps
T1306 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.871508781 Aug 23 03:22:02 AM UTC 24 Aug 23 03:22:04 AM UTC 24 98319833 ps
T1307 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.884896649 Aug 23 03:22:02 AM UTC 24 Aug 23 03:22:04 AM UTC 24 28777812 ps
T1308 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.3130878921 Aug 23 03:22:02 AM UTC 24 Aug 23 03:22:04 AM UTC 24 43937700 ps
T1309 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.3055997553 Aug 23 03:22:02 AM UTC 24 Aug 23 03:22:04 AM UTC 24 14593708 ps
T1310 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1772115355 Aug 23 03:22:02 AM UTC 24 Aug 23 03:22:04 AM UTC 24 21728344 ps
T1311 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.493361722 Aug 23 03:22:04 AM UTC 24 Aug 23 03:22:05 AM UTC 24 44152089 ps
T1312 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2553604179 Aug 23 03:22:04 AM UTC 24 Aug 23 03:22:05 AM UTC 24 16991984 ps
T1313 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.3900280812 Aug 23 03:22:04 AM UTC 24 Aug 23 03:22:05 AM UTC 24 18400166 ps
T1314 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.1368031061 Aug 23 03:22:04 AM UTC 24 Aug 23 03:22:05 AM UTC 24 41605344 ps
T1315 /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3683475388 Aug 23 03:22:04 AM UTC 24 Aug 23 03:22:05 AM UTC 24 58661909 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_loopback.3163191088
Short name T6
Test name
Test status
Simulation time 3556823178 ps
CPU time 6.18 seconds
Started Aug 23 03:23:03 AM UTC 24
Finished Aug 23 03:23:10 AM UTC 24
Peak memory 207340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163191088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3163191088
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.1595951912
Short name T13
Test name
Test status
Simulation time 5485423185 ps
CPU time 28.02 seconds
Started Aug 23 03:23:04 AM UTC 24
Finished Aug 23 03:23:33 AM UTC 24
Peak memory 217936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1595951912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_
with_rand_reset.1595951912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_stress_all.2478479572
Short name T46
Test name
Test status
Simulation time 197390913890 ps
CPU time 153.76 seconds
Started Aug 23 03:23:04 AM UTC 24
Finished Aug 23 03:25:40 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478479572 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2478479572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_stress_all.4111728099
Short name T201
Test name
Test status
Simulation time 367801449019 ps
CPU time 412.73 seconds
Started Aug 23 03:25:00 AM UTC 24
Finished Aug 23 03:31:58 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111728099 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.4111728099
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_intr.3461924574
Short name T23
Test name
Test status
Simulation time 56444381156 ps
CPU time 30.24 seconds
Started Aug 23 03:24:39 AM UTC 24
Finished Aug 23 03:25:11 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461924574 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3461924574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.1823482280
Short name T11
Test name
Test status
Simulation time 47484487385 ps
CPU time 17.1 seconds
Started Aug 23 03:23:08 AM UTC 24
Finished Aug 23 03:23:26 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823482280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1823482280
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.2522553605
Short name T258
Test name
Test status
Simulation time 59378109453 ps
CPU time 225.29 seconds
Started Aug 23 03:26:19 AM UTC 24
Finished Aug 23 03:30:08 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522553605 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2522553605
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.1638395750
Short name T287
Test name
Test status
Simulation time 125848079717 ps
CPU time 211.36 seconds
Started Aug 23 03:25:41 AM UTC 24
Finished Aug 23 03:29:15 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638395750 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1638395750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_stress_all.2077030985
Short name T103
Test name
Test status
Simulation time 451625899763 ps
CPU time 401.98 seconds
Started Aug 23 03:30:13 AM UTC 24
Finished Aug 23 03:37:00 AM UTC 24
Peak memory 220616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077030985 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2077030985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_stress_all.3685260261
Short name T141
Test name
Test status
Simulation time 641755531840 ps
CPU time 277.47 seconds
Started Aug 23 03:27:48 AM UTC 24
Finished Aug 23 03:32:29 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685260261 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3685260261
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_stress_all.1884079553
Short name T195
Test name
Test status
Simulation time 205904355659 ps
CPU time 669.64 seconds
Started Aug 23 03:23:28 AM UTC 24
Finished Aug 23 03:34:45 AM UTC 24
Peak memory 212208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884079553 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1884079553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_sec_cm.1025966804
Short name T3
Test name
Test status
Simulation time 238035482 ps
CPU time 0.8 seconds
Started Aug 23 03:23:04 AM UTC 24
Finished Aug 23 03:23:06 AM UTC 24
Peak memory 240132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025966804 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1025966804
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_fifo_full.578436074
Short name T127
Test name
Test status
Simulation time 250520181062 ps
CPU time 116.54 seconds
Started Aug 23 03:27:58 AM UTC 24
Finished Aug 23 03:29:57 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578436074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.578436074
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_stress_all.1442104841
Short name T311
Test name
Test status
Simulation time 213217282195 ps
CPU time 170.16 seconds
Started Aug 23 03:36:24 AM UTC 24
Finished Aug 23 03:39:16 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442104841 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1442104841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_stress_all.2476867174
Short name T124
Test name
Test status
Simulation time 152965652156 ps
CPU time 99.33 seconds
Started Aug 23 03:25:49 AM UTC 24
Finished Aug 23 03:27:30 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476867174 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2476867174
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1451890943
Short name T48
Test name
Test status
Simulation time 21155296 ps
CPU time 0.51 seconds
Started Aug 23 03:21:15 AM UTC 24
Finished Aug 23 03:21:17 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451890943 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1451890943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.3728894227
Short name T133
Test name
Test status
Simulation time 158855803319 ps
CPU time 156.68 seconds
Started Aug 23 03:32:07 AM UTC 24
Finished Aug 23 03:34:46 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728894227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3728894227
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.2307440329
Short name T140
Test name
Test status
Simulation time 68353885304 ps
CPU time 46.97 seconds
Started Aug 23 03:27:33 AM UTC 24
Finished Aug 23 03:28:22 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307440329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2307440329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_stress_all.1788222196
Short name T93
Test name
Test status
Simulation time 275872838871 ps
CPU time 467.18 seconds
Started Aug 23 03:26:19 AM UTC 24
Finished Aug 23 03:34:12 AM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788222196 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1788222196
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.1586891301
Short name T272
Test name
Test status
Simulation time 127244032963 ps
CPU time 97.31 seconds
Started Aug 23 03:30:32 AM UTC 24
Finished Aug 23 03:32:11 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586891301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1586891301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.1789340281
Short name T122
Test name
Test status
Simulation time 132026075350 ps
CPU time 62.24 seconds
Started Aug 23 03:26:28 AM UTC 24
Finished Aug 23 03:27:31 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789340281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1789340281
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.297888752
Short name T116
Test name
Test status
Simulation time 46150865582 ps
CPU time 45.37 seconds
Started Aug 23 03:25:28 AM UTC 24
Finished Aug 23 03:26:15 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297888752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.297888752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_fifo_full.3604702505
Short name T99
Test name
Test status
Simulation time 90748919366 ps
CPU time 41.87 seconds
Started Aug 23 03:28:34 AM UTC 24
Finished Aug 23 03:29:17 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604702505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3604702505
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.2953411430
Short name T79
Test name
Test status
Simulation time 329426432 ps
CPU time 1.16 seconds
Started Aug 23 03:21:34 AM UTC 24
Finished Aug 23 03:21:36 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953411430 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2953411430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_stress_all.4169295682
Short name T289
Test name
Test status
Simulation time 252399436494 ps
CPU time 233.13 seconds
Started Aug 23 03:29:27 AM UTC 24
Finished Aug 23 03:33:24 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169295682 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4169295682
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_alert_test.2106612352
Short name T4
Test name
Test status
Simulation time 58465662 ps
CPU time 0.47 seconds
Started Aug 23 03:23:05 AM UTC 24
Finished Aug 23 03:23:07 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106612352 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2106612352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_fifo_reset.47567987
Short name T15
Test name
Test status
Simulation time 72583027118 ps
CPU time 31.09 seconds
Started Aug 23 03:23:10 AM UTC 24
Finished Aug 23 03:23:42 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47567987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.47567987
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_perf.634868754
Short name T265
Test name
Test status
Simulation time 25626838856 ps
CPU time 303.55 seconds
Started Aug 23 03:26:18 AM UTC 24
Finished Aug 23 03:31:26 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634868754 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.634868754
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.2208183681
Short name T38
Test name
Test status
Simulation time 14407318824 ps
CPU time 25.53 seconds
Started Aug 23 03:30:12 AM UTC 24
Finished Aug 23 03:30:39 AM UTC 24
Peak memory 219788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2208183681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all
_with_rand_reset.2208183681
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.1004344483
Short name T98
Test name
Test status
Simulation time 248755633768 ps
CPU time 35.26 seconds
Started Aug 23 03:25:12 AM UTC 24
Finished Aug 23 03:25:48 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004344483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1004344483
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3087107214
Short name T63
Test name
Test status
Simulation time 43560108 ps
CPU time 0.62 seconds
Started Aug 23 03:21:17 AM UTC 24
Finished Aug 23 03:21:18 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087107214 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.3087107214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.1954025766
Short name T271
Test name
Test status
Simulation time 33275466428 ps
CPU time 283.28 seconds
Started Aug 23 03:30:10 AM UTC 24
Finished Aug 23 03:34:57 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954025766 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1954025766
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_noise_filter.2777146684
Short name T254
Test name
Test status
Simulation time 123255574522 ps
CPU time 157.52 seconds
Started Aug 23 03:24:10 AM UTC 24
Finished Aug 23 03:26:50 AM UTC 24
Peak memory 208532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777146684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2777146684
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.572819466
Short name T166
Test name
Test status
Simulation time 120236558356 ps
CPU time 51.61 seconds
Started Aug 23 03:36:49 AM UTC 24
Finished Aug 23 03:37:42 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572819466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.572819466
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.1040433814
Short name T26
Test name
Test status
Simulation time 35242547074 ps
CPU time 56.03 seconds
Started Aug 23 03:23:44 AM UTC 24
Finished Aug 23 03:24:42 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040433814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1040433814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_fifo_full.4123080876
Short name T137
Test name
Test status
Simulation time 70294725757 ps
CPU time 26.63 seconds
Started Aug 23 03:29:42 AM UTC 24
Finished Aug 23 03:30:10 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123080876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.4123080876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.2252731663
Short name T379
Test name
Test status
Simulation time 182449815955 ps
CPU time 368.13 seconds
Started Aug 23 03:34:00 AM UTC 24
Finished Aug 23 03:40:13 AM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252731663 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2252731663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.4165819355
Short name T356
Test name
Test status
Simulation time 15866970683 ps
CPU time 55.65 seconds
Started Aug 23 03:39:23 AM UTC 24
Finished Aug 23 03:40:20 AM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4165819355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all
_with_rand_reset.4165819355
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_stress_all.1193190916
Short name T144
Test name
Test status
Simulation time 297051631791 ps
CPU time 127.43 seconds
Started Aug 23 03:41:03 AM UTC 24
Finished Aug 23 03:43:13 AM UTC 24
Peak memory 221864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193190916 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1193190916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.4018668607
Short name T78
Test name
Test status
Simulation time 200772726 ps
CPU time 1.23 seconds
Started Aug 23 03:21:41 AM UTC 24
Finished Aug 23 03:21:43 AM UTC 24
Peak memory 201712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018668607 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.4018668607
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_fifo_full.3261650019
Short name T332
Test name
Test status
Simulation time 29825799504 ps
CPU time 46.83 seconds
Started Aug 23 03:31:41 AM UTC 24
Finished Aug 23 03:32:29 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261650019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3261650019
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_noise_filter.3902107483
Short name T322
Test name
Test status
Simulation time 242193696837 ps
CPU time 83.64 seconds
Started Aug 23 03:39:15 AM UTC 24
Finished Aug 23 03:40:40 AM UTC 24
Peak memory 217532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902107483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3902107483
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2762911351
Short name T74
Test name
Test status
Simulation time 121040525 ps
CPU time 0.85 seconds
Started Aug 23 03:21:19 AM UTC 24
Finished Aug 23 03:21:21 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762911351 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2762911351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/146.uart_fifo_reset.2620761455
Short name T229
Test name
Test status
Simulation time 42397821909 ps
CPU time 17.41 seconds
Started Aug 23 04:08:29 AM UTC 24
Finished Aug 23 04:08:47 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620761455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2620761455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/146.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_fifo_reset.1581854576
Short name T157
Test name
Test status
Simulation time 108753943585 ps
CPU time 35.37 seconds
Started Aug 23 03:36:50 AM UTC 24
Finished Aug 23 03:37:27 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581854576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1581854576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_stress_all.3971036141
Short name T161
Test name
Test status
Simulation time 344667671805 ps
CPU time 1219.5 seconds
Started Aug 23 03:43:14 AM UTC 24
Finished Aug 23 04:03:46 AM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971036141 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3971036141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_perf.934763501
Short name T715
Test name
Test status
Simulation time 23582619826 ps
CPU time 228.17 seconds
Started Aug 23 03:47:55 AM UTC 24
Finished Aug 23 03:51:46 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934763501 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.934763501
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/81.uart_fifo_reset.3554818640
Short name T159
Test name
Test status
Simulation time 85279056738 ps
CPU time 39.8 seconds
Started Aug 23 04:05:16 AM UTC 24
Finished Aug 23 04:05:58 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554818640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3554818640
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/81.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_fifo_reset.1952699789
Short name T132
Test name
Test status
Simulation time 62646354285 ps
CPU time 84.89 seconds
Started Aug 23 03:31:45 AM UTC 24
Finished Aug 23 03:33:11 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952699789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1952699789
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_fifo_reset.2954316260
Short name T189
Test name
Test status
Simulation time 20093368015 ps
CPU time 37.8 seconds
Started Aug 23 03:32:38 AM UTC 24
Finished Aug 23 03:33:17 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954316260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2954316260
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.1054589361
Short name T35
Test name
Test status
Simulation time 1984005881 ps
CPU time 17.72 seconds
Started Aug 23 03:27:46 AM UTC 24
Finished Aug 23 03:28:05 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1054589361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_
with_rand_reset.1054589361
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/109.uart_fifo_reset.1285066514
Short name T178
Test name
Test status
Simulation time 9859366992 ps
CPU time 16.85 seconds
Started Aug 23 04:07:02 AM UTC 24
Finished Aug 23 04:07:20 AM UTC 24
Peak memory 208296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285066514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1285066514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/109.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/112.uart_fifo_reset.686089890
Short name T194
Test name
Test status
Simulation time 33733996751 ps
CPU time 29.31 seconds
Started Aug 23 04:07:11 AM UTC 24
Finished Aug 23 04:07:41 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686089890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.686089890
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/112.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/123.uart_fifo_reset.1303568837
Short name T242
Test name
Test status
Simulation time 36398668066 ps
CPU time 20.55 seconds
Started Aug 23 04:07:28 AM UTC 24
Finished Aug 23 04:07:50 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303568837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1303568837
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/123.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/131.uart_fifo_reset.1506027241
Short name T1038
Test name
Test status
Simulation time 79289081363 ps
CPU time 34.11 seconds
Started Aug 23 04:07:52 AM UTC 24
Finished Aug 23 04:08:27 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506027241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1506027241
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/131.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_fifo_reset.1678628732
Short name T180
Test name
Test status
Simulation time 16761093721 ps
CPU time 23.78 seconds
Started Aug 23 03:39:06 AM UTC 24
Finished Aug 23 03:39:31 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678628732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1678628732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/270.uart_fifo_reset.743134065
Short name T1154
Test name
Test status
Simulation time 131966692948 ps
CPU time 47.12 seconds
Started Aug 23 04:13:37 AM UTC 24
Finished Aug 23 04:14:25 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743134065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.743134065
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/270.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.3833630537
Short name T92
Test name
Test status
Simulation time 15048415801 ps
CPU time 18.49 seconds
Started Aug 23 03:51:14 AM UTC 24
Finished Aug 23 03:51:34 AM UTC 24
Peak memory 221752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3833630537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all
_with_rand_reset.3833630537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.2047114481
Short name T147
Test name
Test status
Simulation time 59322149333 ps
CPU time 75.69 seconds
Started Aug 23 03:53:37 AM UTC 24
Finished Aug 23 03:54:54 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047114481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2047114481
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.3104987573
Short name T260
Test name
Test status
Simulation time 166007801942 ps
CPU time 106.04 seconds
Started Aug 23 03:23:02 AM UTC 24
Finished Aug 23 03:24:50 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104987573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3104987573
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.4159313332
Short name T255
Test name
Test status
Simulation time 69310985683 ps
CPU time 25.57 seconds
Started Aug 23 03:30:04 AM UTC 24
Finished Aug 23 03:30:31 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159313332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4159313332
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/143.uart_fifo_reset.2704055667
Short name T208
Test name
Test status
Simulation time 104970175877 ps
CPU time 90.89 seconds
Started Aug 23 04:08:22 AM UTC 24
Finished Aug 23 04:09:55 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704055667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2704055667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/143.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/151.uart_fifo_reset.3126680386
Short name T212
Test name
Test status
Simulation time 113317137087 ps
CPU time 93.2 seconds
Started Aug 23 04:08:46 AM UTC 24
Finished Aug 23 04:10:22 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126680386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3126680386
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/151.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/183.uart_fifo_reset.2066849427
Short name T199
Test name
Test status
Simulation time 149118413117 ps
CPU time 66.89 seconds
Started Aug 23 04:10:00 AM UTC 24
Finished Aug 23 04:11:09 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066849427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2066849427
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/183.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_tx_rx.3293176393
Short name T282
Test name
Test status
Simulation time 95388052390 ps
CPU time 149.27 seconds
Started Aug 23 03:23:32 AM UTC 24
Finished Aug 23 03:26:03 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293176393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3293176393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2710029309
Short name T251
Test name
Test status
Simulation time 113577838557 ps
CPU time 49.25 seconds
Started Aug 23 04:11:39 AM UTC 24
Finished Aug 23 04:12:30 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710029309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2710029309
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/215.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/269.uart_fifo_reset.2369225218
Short name T224
Test name
Test status
Simulation time 59502833799 ps
CPU time 24.7 seconds
Started Aug 23 04:13:34 AM UTC 24
Finished Aug 23 04:14:00 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369225218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2369225218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/269.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_fifo_reset.4268338435
Short name T168
Test name
Test status
Simulation time 39612209892 ps
CPU time 31.93 seconds
Started Aug 23 03:43:22 AM UTC 24
Finished Aug 23 03:43:55 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268338435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.4268338435
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_fifo_reset.3170859693
Short name T183
Test name
Test status
Simulation time 71400024344 ps
CPU time 111.29 seconds
Started Aug 23 03:59:01 AM UTC 24
Finished Aug 23 04:00:55 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170859693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3170859693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_intr.3054583416
Short name T305
Test name
Test status
Simulation time 216925251210 ps
CPU time 376.15 seconds
Started Aug 23 03:25:22 AM UTC 24
Finished Aug 23 03:31:42 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054583416 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3054583416
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.684006664
Short name T110
Test name
Test status
Simulation time 54045927363 ps
CPU time 78.13 seconds
Started Aug 23 03:23:01 AM UTC 24
Finished Aug 23 03:24:20 AM UTC 24
Peak memory 208476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684006664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.684006664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/106.uart_fifo_reset.4176436611
Short name T250
Test name
Test status
Simulation time 129989444192 ps
CPU time 182.23 seconds
Started Aug 23 04:06:55 AM UTC 24
Finished Aug 23 04:09:59 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176436611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.4176436611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/106.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/114.uart_fifo_reset.3558074826
Short name T236
Test name
Test status
Simulation time 56005699524 ps
CPU time 78.71 seconds
Started Aug 23 04:07:19 AM UTC 24
Finished Aug 23 04:08:40 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558074826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3558074826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/114.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_noise_filter.641002901
Short name T308
Test name
Test status
Simulation time 114408910324 ps
CPU time 51.25 seconds
Started Aug 23 03:30:47 AM UTC 24
Finished Aug 23 03:31:40 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641002901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.641002901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/121.uart_fifo_reset.637428947
Short name T227
Test name
Test status
Simulation time 46284812258 ps
CPU time 66.75 seconds
Started Aug 23 04:07:25 AM UTC 24
Finished Aug 23 04:08:34 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637428947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.637428947
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/121.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/124.uart_fifo_reset.2237736890
Short name T154
Test name
Test status
Simulation time 239114804328 ps
CPU time 98.52 seconds
Started Aug 23 04:07:40 AM UTC 24
Finished Aug 23 04:09:20 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237736890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2237736890
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/124.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/134.uart_fifo_reset.1557157949
Short name T1172
Test name
Test status
Simulation time 119797185035 ps
CPU time 437.59 seconds
Started Aug 23 04:07:59 AM UTC 24
Finished Aug 23 04:15:22 AM UTC 24
Peak memory 212148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557157949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1557157949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/134.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/172.uart_fifo_reset.3539709757
Short name T196
Test name
Test status
Simulation time 9441225603 ps
CPU time 14.6 seconds
Started Aug 23 04:09:43 AM UTC 24
Finished Aug 23 04:09:59 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539709757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3539709757
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/172.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/181.uart_fifo_reset.1943500807
Short name T222
Test name
Test status
Simulation time 21547369140 ps
CPU time 32.24 seconds
Started Aug 23 04:09:56 AM UTC 24
Finished Aug 23 04:10:30 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943500807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1943500807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/181.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/188.uart_fifo_reset.3878906929
Short name T204
Test name
Test status
Simulation time 19534796141 ps
CPU time 15.1 seconds
Started Aug 23 04:10:18 AM UTC 24
Finished Aug 23 04:10:35 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878906929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3878906929
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/188.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_fifo_reset.3345909520
Short name T219
Test name
Test status
Simulation time 15995993804 ps
CPU time 27.7 seconds
Started Aug 23 03:37:31 AM UTC 24
Finished Aug 23 03:38:00 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345909520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3345909520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3038791994
Short name T252
Test name
Test status
Simulation time 38188704359 ps
CPU time 13.61 seconds
Started Aug 23 04:11:27 AM UTC 24
Finished Aug 23 04:11:42 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038791994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3038791994
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/210.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1566804154
Short name T239
Test name
Test status
Simulation time 123924035753 ps
CPU time 167.33 seconds
Started Aug 23 04:12:47 AM UTC 24
Finished Aug 23 04:15:37 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566804154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1566804154
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/242.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.234789910
Short name T394
Test name
Test status
Simulation time 3068336914 ps
CPU time 22.63 seconds
Started Aug 23 03:42:21 AM UTC 24
Finished Aug 23 03:42:45 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=234789910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all_
with_rand_reset.234789910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/281.uart_fifo_reset.918334384
Short name T241
Test name
Test status
Simulation time 17214181057 ps
CPU time 61.47 seconds
Started Aug 23 04:14:02 AM UTC 24
Finished Aug 23 04:15:05 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918334384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.918334384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/281.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1341988291
Short name T238
Test name
Test status
Simulation time 14709804438 ps
CPU time 13.4 seconds
Started Aug 23 04:14:21 AM UTC 24
Finished Aug 23 04:14:35 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341988291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1341988291
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/291.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_fifo_reset.2875692413
Short name T246
Test name
Test status
Simulation time 57118349606 ps
CPU time 31.65 seconds
Started Aug 23 03:55:49 AM UTC 24
Finished Aug 23 03:56:22 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875692413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2875692413
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/50.uart_fifo_reset.2312197873
Short name T187
Test name
Test status
Simulation time 46832498634 ps
CPU time 29.67 seconds
Started Aug 23 04:02:11 AM UTC 24
Finished Aug 23 04:02:41 AM UTC 24
Peak memory 208984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312197873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2312197873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/50.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/51.uart_fifo_reset.1454976248
Short name T245
Test name
Test status
Simulation time 42557551374 ps
CPU time 46.38 seconds
Started Aug 23 04:02:17 AM UTC 24
Finished Aug 23 04:03:05 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454976248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1454976248
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/51.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.2778115928
Short name T50
Test name
Test status
Simulation time 49549879 ps
CPU time 0.68 seconds
Started Aug 23 03:21:17 AM UTC 24
Finished Aug 23 03:21:18 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778115928 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2778115928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1128969289
Short name T1189
Test name
Test status
Simulation time 122340420 ps
CPU time 1.3 seconds
Started Aug 23 03:21:17 AM UTC 24
Finished Aug 23 03:21:19 AM UTC 24
Peak memory 201824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128969289 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1128969289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1803930995
Short name T1190
Test name
Test status
Simulation time 87837811 ps
CPU time 0.8 seconds
Started Aug 23 03:21:18 AM UTC 24
Finished Aug 23 03:21:20 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1803930995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r
eset.1803930995
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.4109045183
Short name T49
Test name
Test status
Simulation time 28372178 ps
CPU time 0.57 seconds
Started Aug 23 03:21:15 AM UTC 24
Finished Aug 23 03:21:17 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109045183 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.4109045183
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.1212602400
Short name T1187
Test name
Test status
Simulation time 14053885 ps
CPU time 0.51 seconds
Started Aug 23 03:21:13 AM UTC 24
Finished Aug 23 03:21:15 AM UTC 24
Peak memory 201764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212602400 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1212602400
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.161656595
Short name T1188
Test name
Test status
Simulation time 150851129 ps
CPU time 2.26 seconds
Started Aug 23 03:21:13 AM UTC 24
Finished Aug 23 03:21:16 AM UTC 24
Peak memory 204748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161656595 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.161656595
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.1922561974
Short name T73
Test name
Test status
Simulation time 304404951 ps
CPU time 1.19 seconds
Started Aug 23 03:21:13 AM UTC 24
Finished Aug 23 03:21:15 AM UTC 24
Peak memory 201712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922561974 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1922561974
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.3594936446
Short name T52
Test name
Test status
Simulation time 54835233 ps
CPU time 0.68 seconds
Started Aug 23 03:21:21 AM UTC 24
Finished Aug 23 03:21:23 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594936446 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3594936446
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.1089093064
Short name T1193
Test name
Test status
Simulation time 73637865 ps
CPU time 1.27 seconds
Started Aug 23 03:21:20 AM UTC 24
Finished Aug 23 03:21:23 AM UTC 24
Peak memory 201824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089093064 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1089093064
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.2293217388
Short name T51
Test name
Test status
Simulation time 24620754 ps
CPU time 0.54 seconds
Started Aug 23 03:21:20 AM UTC 24
Finished Aug 23 03:21:22 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293217388 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2293217388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.235594208
Short name T1194
Test name
Test status
Simulation time 123367402 ps
CPU time 0.83 seconds
Started Aug 23 03:21:22 AM UTC 24
Finished Aug 23 03:21:23 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=235594208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_re
set.235594208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.4285414618
Short name T64
Test name
Test status
Simulation time 22811575 ps
CPU time 0.52 seconds
Started Aug 23 03:21:20 AM UTC 24
Finished Aug 23 03:21:22 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285414618 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.4285414618
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.1078118026
Short name T1191
Test name
Test status
Simulation time 26132067 ps
CPU time 0.5 seconds
Started Aug 23 03:21:19 AM UTC 24
Finished Aug 23 03:21:20 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078118026 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1078118026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.850450040
Short name T65
Test name
Test status
Simulation time 19740026 ps
CPU time 0.58 seconds
Started Aug 23 03:21:21 AM UTC 24
Finished Aug 23 03:21:23 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850450040 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.850450040
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1195859586
Short name T1192
Test name
Test status
Simulation time 162741331 ps
CPU time 1.7 seconds
Started Aug 23 03:21:18 AM UTC 24
Finished Aug 23 03:21:21 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195859586 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1195859586
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3147084711
Short name T1236
Test name
Test status
Simulation time 123449362 ps
CPU time 0.75 seconds
Started Aug 23 03:21:46 AM UTC 24
Finished Aug 23 03:21:48 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3147084711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_
reset.3147084711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.2704128567
Short name T61
Test name
Test status
Simulation time 28489627 ps
CPU time 0.55 seconds
Started Aug 23 03:21:45 AM UTC 24
Finished Aug 23 03:21:46 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704128567 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2704128567
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.3836284317
Short name T1230
Test name
Test status
Simulation time 44739544 ps
CPU time 0.52 seconds
Started Aug 23 03:21:45 AM UTC 24
Finished Aug 23 03:21:46 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836284317 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3836284317
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.3464380024
Short name T1231
Test name
Test status
Simulation time 25421346 ps
CPU time 0.58 seconds
Started Aug 23 03:21:45 AM UTC 24
Finished Aug 23 03:21:46 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464380024 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.3464380024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1514965943
Short name T1234
Test name
Test status
Simulation time 92605146 ps
CPU time 1.77 seconds
Started Aug 23 03:21:45 AM UTC 24
Finished Aug 23 03:21:48 AM UTC 24
Peak memory 201576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514965943 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1514965943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1867752348
Short name T1232
Test name
Test status
Simulation time 69446806 ps
CPU time 0.86 seconds
Started Aug 23 03:21:45 AM UTC 24
Finished Aug 23 03:21:47 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867752348 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1867752348
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1274751102
Short name T1241
Test name
Test status
Simulation time 21740433 ps
CPU time 0.88 seconds
Started Aug 23 03:21:47 AM UTC 24
Finished Aug 23 03:21:49 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1274751102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_
reset.1274751102
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.3299047500
Short name T1235
Test name
Test status
Simulation time 45436654 ps
CPU time 0.51 seconds
Started Aug 23 03:21:46 AM UTC 24
Finished Aug 23 03:21:48 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299047500 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3299047500
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.944790061
Short name T1233
Test name
Test status
Simulation time 71918377 ps
CPU time 0.52 seconds
Started Aug 23 03:21:46 AM UTC 24
Finished Aug 23 03:21:48 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944790061 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.944790061
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1612795845
Short name T1238
Test name
Test status
Simulation time 20561117 ps
CPU time 0.7 seconds
Started Aug 23 03:21:46 AM UTC 24
Finished Aug 23 03:21:48 AM UTC 24
Peak memory 205724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612795845 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.1612795845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3014798309
Short name T1239
Test name
Test status
Simulation time 444064527 ps
CPU time 0.98 seconds
Started Aug 23 03:21:46 AM UTC 24
Finished Aug 23 03:21:48 AM UTC 24
Peak memory 201560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014798309 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3014798309
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.2966929426
Short name T1237
Test name
Test status
Simulation time 64201815 ps
CPU time 0.88 seconds
Started Aug 23 03:21:46 AM UTC 24
Finished Aug 23 03:21:48 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966929426 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2966929426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.553752537
Short name T1245
Test name
Test status
Simulation time 26290751 ps
CPU time 1.04 seconds
Started Aug 23 03:21:48 AM UTC 24
Finished Aug 23 03:21:50 AM UTC 24
Peak memory 201636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=553752537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_r
eset.553752537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.4119087322
Short name T62
Test name
Test status
Simulation time 59253180 ps
CPU time 0.6 seconds
Started Aug 23 03:21:48 AM UTC 24
Finished Aug 23 03:21:50 AM UTC 24
Peak memory 201608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119087322 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.4119087322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.4008373925
Short name T1240
Test name
Test status
Simulation time 12762902 ps
CPU time 0.51 seconds
Started Aug 23 03:21:47 AM UTC 24
Finished Aug 23 03:21:49 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008373925 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.4008373925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.3473993342
Short name T1243
Test name
Test status
Simulation time 246300319 ps
CPU time 0.62 seconds
Started Aug 23 03:21:48 AM UTC 24
Finished Aug 23 03:21:50 AM UTC 24
Peak memory 201700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473993342 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.3473993342
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3790130941
Short name T1242
Test name
Test status
Simulation time 55068739 ps
CPU time 1.17 seconds
Started Aug 23 03:21:47 AM UTC 24
Finished Aug 23 03:21:49 AM UTC 24
Peak memory 201576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790130941 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3790130941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.3586740387
Short name T80
Test name
Test status
Simulation time 177132025 ps
CPU time 0.83 seconds
Started Aug 23 03:21:47 AM UTC 24
Finished Aug 23 03:21:49 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586740387 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3586740387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.814299818
Short name T1249
Test name
Test status
Simulation time 75866406 ps
CPU time 0.91 seconds
Started Aug 23 03:21:50 AM UTC 24
Finished Aug 23 03:21:51 AM UTC 24
Peak memory 201636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=814299818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_r
eset.814299818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.2048604597
Short name T1248
Test name
Test status
Simulation time 25891221 ps
CPU time 0.55 seconds
Started Aug 23 03:21:49 AM UTC 24
Finished Aug 23 03:21:51 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048604597 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2048604597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2622728993
Short name T1244
Test name
Test status
Simulation time 14232178 ps
CPU time 0.55 seconds
Started Aug 23 03:21:48 AM UTC 24
Finished Aug 23 03:21:50 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622728993 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2622728993
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.3247133249
Short name T1247
Test name
Test status
Simulation time 130064032 ps
CPU time 0.58 seconds
Started Aug 23 03:21:49 AM UTC 24
Finished Aug 23 03:21:51 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247133249 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.3247133249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.788285069
Short name T1246
Test name
Test status
Simulation time 132474473 ps
CPU time 1.18 seconds
Started Aug 23 03:21:48 AM UTC 24
Finished Aug 23 03:21:51 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788285069 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.788285069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.948773466
Short name T108
Test name
Test status
Simulation time 139659474 ps
CPU time 1.2 seconds
Started Aug 23 03:21:48 AM UTC 24
Finished Aug 23 03:21:51 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948773466 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.948773466
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.730634132
Short name T1255
Test name
Test status
Simulation time 32326484 ps
CPU time 0.6 seconds
Started Aug 23 03:21:52 AM UTC 24
Finished Aug 23 03:21:54 AM UTC 24
Peak memory 201636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=730634132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_r
eset.730634132
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.1514764155
Short name T1250
Test name
Test status
Simulation time 45090770 ps
CPU time 0.52 seconds
Started Aug 23 03:21:51 AM UTC 24
Finished Aug 23 03:21:52 AM UTC 24
Peak memory 201744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514764155 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1514764155
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1743813720
Short name T1251
Test name
Test status
Simulation time 41448750 ps
CPU time 0.52 seconds
Started Aug 23 03:21:51 AM UTC 24
Finished Aug 23 03:21:52 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743813720 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1743813720
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2424992751
Short name T1253
Test name
Test status
Simulation time 28763110 ps
CPU time 0.6 seconds
Started Aug 23 03:21:51 AM UTC 24
Finished Aug 23 03:21:52 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424992751 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.2424992751
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.1288917154
Short name T1252
Test name
Test status
Simulation time 38196488 ps
CPU time 1.81 seconds
Started Aug 23 03:21:50 AM UTC 24
Finished Aug 23 03:21:52 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288917154 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1288917154
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.2464425044
Short name T1254
Test name
Test status
Simulation time 176234944 ps
CPU time 1.24 seconds
Started Aug 23 03:21:51 AM UTC 24
Finished Aug 23 03:21:53 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464425044 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2464425044
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4107276211
Short name T1261
Test name
Test status
Simulation time 104521518 ps
CPU time 1.01 seconds
Started Aug 23 03:21:53 AM UTC 24
Finished Aug 23 03:21:55 AM UTC 24
Peak memory 203616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4107276211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_
reset.4107276211
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3411190928
Short name T1257
Test name
Test status
Simulation time 70243586 ps
CPU time 0.51 seconds
Started Aug 23 03:21:52 AM UTC 24
Finished Aug 23 03:21:54 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411190928 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3411190928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.41170001
Short name T1256
Test name
Test status
Simulation time 14190771 ps
CPU time 0.5 seconds
Started Aug 23 03:21:52 AM UTC 24
Finished Aug 23 03:21:54 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41170001 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.41170001
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2659682580
Short name T1258
Test name
Test status
Simulation time 57445641 ps
CPU time 0.67 seconds
Started Aug 23 03:21:53 AM UTC 24
Finished Aug 23 03:21:54 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659682580 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.2659682580
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.338323070
Short name T1259
Test name
Test status
Simulation time 60328104 ps
CPU time 0.89 seconds
Started Aug 23 03:21:52 AM UTC 24
Finished Aug 23 03:21:54 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338323070 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.338323070
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.2522117380
Short name T1260
Test name
Test status
Simulation time 48479044 ps
CPU time 0.87 seconds
Started Aug 23 03:21:52 AM UTC 24
Finished Aug 23 03:21:54 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522117380 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2522117380
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.276418142
Short name T1266
Test name
Test status
Simulation time 81817653 ps
CPU time 0.7 seconds
Started Aug 23 03:21:54 AM UTC 24
Finished Aug 23 03:21:56 AM UTC 24
Peak memory 201636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=276418142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_r
eset.276418142
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.511420566
Short name T1264
Test name
Test status
Simulation time 56971230 ps
CPU time 0.54 seconds
Started Aug 23 03:21:54 AM UTC 24
Finished Aug 23 03:21:55 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511420566 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.511420566
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.3486550158
Short name T1263
Test name
Test status
Simulation time 12317401 ps
CPU time 0.5 seconds
Started Aug 23 03:21:54 AM UTC 24
Finished Aug 23 03:21:55 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486550158 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3486550158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1810320879
Short name T1265
Test name
Test status
Simulation time 27228213 ps
CPU time 0.66 seconds
Started Aug 23 03:21:54 AM UTC 24
Finished Aug 23 03:21:55 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810320879 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.1810320879
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.759297845
Short name T1262
Test name
Test status
Simulation time 270265103 ps
CPU time 1.48 seconds
Started Aug 23 03:21:53 AM UTC 24
Finished Aug 23 03:21:55 AM UTC 24
Peak memory 203736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759297845 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.759297845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2485696054
Short name T1267
Test name
Test status
Simulation time 377330326 ps
CPU time 1.25 seconds
Started Aug 23 03:21:54 AM UTC 24
Finished Aug 23 03:21:56 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485696054 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2485696054
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3179970196
Short name T1272
Test name
Test status
Simulation time 32283610 ps
CPU time 0.86 seconds
Started Aug 23 03:21:55 AM UTC 24
Finished Aug 23 03:21:57 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3179970196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_
reset.3179970196
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.1171023053
Short name T1269
Test name
Test status
Simulation time 13458438 ps
CPU time 0.55 seconds
Started Aug 23 03:21:55 AM UTC 24
Finished Aug 23 03:21:56 AM UTC 24
Peak memory 201540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171023053 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1171023053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.4030091155
Short name T1268
Test name
Test status
Simulation time 14809708 ps
CPU time 0.55 seconds
Started Aug 23 03:21:55 AM UTC 24
Finished Aug 23 03:21:56 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030091155 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4030091155
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.2231618264
Short name T1270
Test name
Test status
Simulation time 33845187 ps
CPU time 0.67 seconds
Started Aug 23 03:21:55 AM UTC 24
Finished Aug 23 03:21:57 AM UTC 24
Peak memory 201524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231618264 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.2231618264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.13401156
Short name T1273
Test name
Test status
Simulation time 153535176 ps
CPU time 1.11 seconds
Started Aug 23 03:21:55 AM UTC 24
Finished Aug 23 03:21:57 AM UTC 24
Peak memory 201644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13401156 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.13401156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3202173359
Short name T1271
Test name
Test status
Simulation time 191031527 ps
CPU time 0.91 seconds
Started Aug 23 03:21:55 AM UTC 24
Finished Aug 23 03:21:57 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202173359 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3202173359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2456012042
Short name T1278
Test name
Test status
Simulation time 21686561 ps
CPU time 0.81 seconds
Started Aug 23 03:21:56 AM UTC 24
Finished Aug 23 03:21:58 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2456012042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_
reset.2456012042
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3691604981
Short name T1275
Test name
Test status
Simulation time 49740892 ps
CPU time 0.59 seconds
Started Aug 23 03:21:56 AM UTC 24
Finished Aug 23 03:21:58 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691604981 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3691604981
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.1720322792
Short name T1274
Test name
Test status
Simulation time 10978648 ps
CPU time 0.59 seconds
Started Aug 23 03:21:56 AM UTC 24
Finished Aug 23 03:21:58 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720322792 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1720322792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.158380740
Short name T1276
Test name
Test status
Simulation time 23277751 ps
CPU time 0.62 seconds
Started Aug 23 03:21:56 AM UTC 24
Finished Aug 23 03:21:58 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158380740 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.158380740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.4033238495
Short name T1277
Test name
Test status
Simulation time 154223821 ps
CPU time 0.96 seconds
Started Aug 23 03:21:56 AM UTC 24
Finished Aug 23 03:21:58 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033238495 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.4033238495
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3141842521
Short name T1279
Test name
Test status
Simulation time 275756402 ps
CPU time 1.09 seconds
Started Aug 23 03:21:56 AM UTC 24
Finished Aug 23 03:21:58 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141842521 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3141842521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2549200484
Short name T1284
Test name
Test status
Simulation time 52896523 ps
CPU time 1.14 seconds
Started Aug 23 03:21:57 AM UTC 24
Finished Aug 23 03:22:00 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2549200484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_
reset.2549200484
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.3251728138
Short name T1281
Test name
Test status
Simulation time 14163702 ps
CPU time 0.55 seconds
Started Aug 23 03:21:57 AM UTC 24
Finished Aug 23 03:21:59 AM UTC 24
Peak memory 201744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251728138 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3251728138
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.707443248
Short name T1280
Test name
Test status
Simulation time 41878509 ps
CPU time 0.52 seconds
Started Aug 23 03:21:57 AM UTC 24
Finished Aug 23 03:21:59 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707443248 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.707443248
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.835896095
Short name T1282
Test name
Test status
Simulation time 104557754 ps
CPU time 0.67 seconds
Started Aug 23 03:21:57 AM UTC 24
Finished Aug 23 03:21:59 AM UTC 24
Peak memory 205724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835896095 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.835896095
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.3088480274
Short name T1285
Test name
Test status
Simulation time 433624275 ps
CPU time 1.56 seconds
Started Aug 23 03:21:57 AM UTC 24
Finished Aug 23 03:22:00 AM UTC 24
Peak memory 201576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088480274 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3088480274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3379831024
Short name T1283
Test name
Test status
Simulation time 209846962 ps
CPU time 0.88 seconds
Started Aug 23 03:21:57 AM UTC 24
Finished Aug 23 03:21:59 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379831024 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3379831024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.2721833679
Short name T1197
Test name
Test status
Simulation time 16423445 ps
CPU time 0.61 seconds
Started Aug 23 03:21:26 AM UTC 24
Finished Aug 23 03:21:27 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721833679 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2721833679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.4076149696
Short name T58
Test name
Test status
Simulation time 207665708 ps
CPU time 2.02 seconds
Started Aug 23 03:21:24 AM UTC 24
Finished Aug 23 03:21:27 AM UTC 24
Peak memory 202824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076149696 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4076149696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.449794431
Short name T53
Test name
Test status
Simulation time 16715489 ps
CPU time 0.54 seconds
Started Aug 23 03:21:24 AM UTC 24
Finished Aug 23 03:21:25 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449794431 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.449794431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.932222338
Short name T1198
Test name
Test status
Simulation time 100343096 ps
CPU time 0.79 seconds
Started Aug 23 03:21:26 AM UTC 24
Finished Aug 23 03:21:28 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=932222338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_re
set.932222338
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.205757113
Short name T54
Test name
Test status
Simulation time 12296022 ps
CPU time 0.51 seconds
Started Aug 23 03:21:24 AM UTC 24
Finished Aug 23 03:21:25 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205757113 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.205757113
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2449092367
Short name T1196
Test name
Test status
Simulation time 71438870 ps
CPU time 0.49 seconds
Started Aug 23 03:21:24 AM UTC 24
Finished Aug 23 03:21:25 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449092367 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2449092367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.1802429872
Short name T66
Test name
Test status
Simulation time 14071344 ps
CPU time 0.61 seconds
Started Aug 23 03:21:26 AM UTC 24
Finished Aug 23 03:21:27 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802429872 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.1802429872
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.4203973510
Short name T1195
Test name
Test status
Simulation time 182880528 ps
CPU time 1.13 seconds
Started Aug 23 03:21:23 AM UTC 24
Finished Aug 23 03:21:25 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203973510 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4203973510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.2845256147
Short name T75
Test name
Test status
Simulation time 167014928 ps
CPU time 1.21 seconds
Started Aug 23 03:21:23 AM UTC 24
Finished Aug 23 03:21:25 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845256147 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2845256147
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.1329449839
Short name T1288
Test name
Test status
Simulation time 12522282 ps
CPU time 0.53 seconds
Started Aug 23 03:21:58 AM UTC 24
Finished Aug 23 03:22:00 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329449839 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1329449839
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1723773474
Short name T1289
Test name
Test status
Simulation time 32972050 ps
CPU time 0.49 seconds
Started Aug 23 03:21:58 AM UTC 24
Finished Aug 23 03:22:00 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723773474 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1723773474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.613475841
Short name T1286
Test name
Test status
Simulation time 16487322 ps
CPU time 0.5 seconds
Started Aug 23 03:21:58 AM UTC 24
Finished Aug 23 03:22:00 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613475841 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.613475841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1150245201
Short name T1287
Test name
Test status
Simulation time 16499918 ps
CPU time 0.51 seconds
Started Aug 23 03:21:58 AM UTC 24
Finished Aug 23 03:22:00 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150245201 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1150245201
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2805825860
Short name T1292
Test name
Test status
Simulation time 15966149 ps
CPU time 0.52 seconds
Started Aug 23 03:21:59 AM UTC 24
Finished Aug 23 03:22:00 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805825860 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2805825860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.1956939845
Short name T1291
Test name
Test status
Simulation time 56882342 ps
CPU time 0.5 seconds
Started Aug 23 03:21:59 AM UTC 24
Finished Aug 23 03:22:00 AM UTC 24
Peak memory 201560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956939845 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1956939845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.1453192386
Short name T1290
Test name
Test status
Simulation time 156762652 ps
CPU time 0.49 seconds
Started Aug 23 03:21:59 AM UTC 24
Finished Aug 23 03:22:00 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453192386 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1453192386
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.4186855562
Short name T1293
Test name
Test status
Simulation time 96291142 ps
CPU time 0.51 seconds
Started Aug 23 03:22:00 AM UTC 24
Finished Aug 23 03:22:01 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186855562 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.4186855562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.1774851269
Short name T1295
Test name
Test status
Simulation time 33822027 ps
CPU time 0.51 seconds
Started Aug 23 03:22:00 AM UTC 24
Finished Aug 23 03:22:01 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774851269 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1774851269
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2176702158
Short name T1294
Test name
Test status
Simulation time 99260565 ps
CPU time 0.53 seconds
Started Aug 23 03:22:00 AM UTC 24
Finished Aug 23 03:22:01 AM UTC 24
Peak memory 201288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176702158 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2176702158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.3112728721
Short name T56
Test name
Test status
Simulation time 238049712 ps
CPU time 0.75 seconds
Started Aug 23 03:21:29 AM UTC 24
Finished Aug 23 03:21:31 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112728721 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3112728721
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2457160336
Short name T1202
Test name
Test status
Simulation time 255082991 ps
CPU time 2.42 seconds
Started Aug 23 03:21:29 AM UTC 24
Finished Aug 23 03:21:33 AM UTC 24
Peak memory 202304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457160336 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2457160336
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.1320623635
Short name T55
Test name
Test status
Simulation time 58461909 ps
CPU time 0.55 seconds
Started Aug 23 03:21:28 AM UTC 24
Finished Aug 23 03:21:30 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320623635 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1320623635
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3161017412
Short name T1201
Test name
Test status
Simulation time 97273919 ps
CPU time 0.76 seconds
Started Aug 23 03:21:30 AM UTC 24
Finished Aug 23 03:21:32 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3161017412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r
eset.3161017412
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.324055611
Short name T67
Test name
Test status
Simulation time 21640731 ps
CPU time 0.5 seconds
Started Aug 23 03:21:28 AM UTC 24
Finished Aug 23 03:21:29 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324055611 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.324055611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.2552868363
Short name T1200
Test name
Test status
Simulation time 37759233 ps
CPU time 0.5 seconds
Started Aug 23 03:21:28 AM UTC 24
Finished Aug 23 03:21:30 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552868363 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2552868363
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.3716358602
Short name T68
Test name
Test status
Simulation time 60591956 ps
CPU time 0.67 seconds
Started Aug 23 03:21:29 AM UTC 24
Finished Aug 23 03:21:31 AM UTC 24
Peak memory 204964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716358602 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.3716358602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.1077989000
Short name T1199
Test name
Test status
Simulation time 38224952 ps
CPU time 1.74 seconds
Started Aug 23 03:21:26 AM UTC 24
Finished Aug 23 03:21:29 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077989000 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1077989000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.416232371
Short name T81
Test name
Test status
Simulation time 471878711 ps
CPU time 0.91 seconds
Started Aug 23 03:21:26 AM UTC 24
Finished Aug 23 03:21:28 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416232371 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.416232371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.637355446
Short name T1296
Test name
Test status
Simulation time 31147153 ps
CPU time 0.52 seconds
Started Aug 23 03:22:00 AM UTC 24
Finished Aug 23 03:22:01 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637355446 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.637355446
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2727206598
Short name T1297
Test name
Test status
Simulation time 15532082 ps
CPU time 0.5 seconds
Started Aug 23 03:22:01 AM UTC 24
Finished Aug 23 03:22:02 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727206598 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2727206598
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.1754986547
Short name T1298
Test name
Test status
Simulation time 18875781 ps
CPU time 0.48 seconds
Started Aug 23 03:22:01 AM UTC 24
Finished Aug 23 03:22:02 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754986547 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1754986547
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.3590523838
Short name T1299
Test name
Test status
Simulation time 48528476 ps
CPU time 0.5 seconds
Started Aug 23 03:22:01 AM UTC 24
Finished Aug 23 03:22:02 AM UTC 24
Peak memory 201560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590523838 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3590523838
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3180295914
Short name T1301
Test name
Test status
Simulation time 28321590 ps
CPU time 0.53 seconds
Started Aug 23 03:22:01 AM UTC 24
Finished Aug 23 03:22:02 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180295914 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3180295914
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.1714739192
Short name T1302
Test name
Test status
Simulation time 15837574 ps
CPU time 0.49 seconds
Started Aug 23 03:22:01 AM UTC 24
Finished Aug 23 03:22:02 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714739192 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1714739192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.4063874207
Short name T1300
Test name
Test status
Simulation time 14101293 ps
CPU time 0.5 seconds
Started Aug 23 03:22:01 AM UTC 24
Finished Aug 23 03:22:02 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063874207 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.4063874207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.1440702750
Short name T1304
Test name
Test status
Simulation time 11911315 ps
CPU time 0.52 seconds
Started Aug 23 03:22:01 AM UTC 24
Finished Aug 23 03:22:03 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440702750 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1440702750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2411184587
Short name T1303
Test name
Test status
Simulation time 11981999 ps
CPU time 0.48 seconds
Started Aug 23 03:22:01 AM UTC 24
Finished Aug 23 03:22:02 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411184587 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2411184587
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.2643470769
Short name T1305
Test name
Test status
Simulation time 11831728 ps
CPU time 0.49 seconds
Started Aug 23 03:22:01 AM UTC 24
Finished Aug 23 03:22:03 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643470769 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2643470769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.1770443148
Short name T59
Test name
Test status
Simulation time 113608512 ps
CPU time 0.58 seconds
Started Aug 23 03:21:34 AM UTC 24
Finished Aug 23 03:21:36 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770443148 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1770443148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.1955536937
Short name T60
Test name
Test status
Simulation time 1378220174 ps
CPU time 2.39 seconds
Started Aug 23 03:21:33 AM UTC 24
Finished Aug 23 03:21:36 AM UTC 24
Peak memory 202824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955536937 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1955536937
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3861127492
Short name T1205
Test name
Test status
Simulation time 43186914 ps
CPU time 0.52 seconds
Started Aug 23 03:21:32 AM UTC 24
Finished Aug 23 03:21:33 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861127492 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3861127492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.70604258
Short name T1207
Test name
Test status
Simulation time 87424213 ps
CPU time 0.84 seconds
Started Aug 23 03:21:34 AM UTC 24
Finished Aug 23 03:21:36 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=70604258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.70604258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.319833173
Short name T57
Test name
Test status
Simulation time 21714209 ps
CPU time 0.5 seconds
Started Aug 23 03:21:32 AM UTC 24
Finished Aug 23 03:21:33 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319833173 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.319833173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.400031359
Short name T1204
Test name
Test status
Simulation time 15635814 ps
CPU time 0.52 seconds
Started Aug 23 03:21:32 AM UTC 24
Finished Aug 23 03:21:33 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400031359 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.400031359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2559249555
Short name T69
Test name
Test status
Simulation time 49666113 ps
CPU time 0.66 seconds
Started Aug 23 03:21:34 AM UTC 24
Finished Aug 23 03:21:36 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559249555 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.2559249555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.2049810167
Short name T1203
Test name
Test status
Simulation time 298303909 ps
CPU time 1.6 seconds
Started Aug 23 03:21:30 AM UTC 24
Finished Aug 23 03:21:33 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049810167 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2049810167
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.2250284582
Short name T76
Test name
Test status
Simulation time 93052657 ps
CPU time 1.28 seconds
Started Aug 23 03:21:30 AM UTC 24
Finished Aug 23 03:21:33 AM UTC 24
Peak memory 201712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250284582 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2250284582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.3130878921
Short name T1308
Test name
Test status
Simulation time 43937700 ps
CPU time 0.52 seconds
Started Aug 23 03:22:02 AM UTC 24
Finished Aug 23 03:22:04 AM UTC 24
Peak memory 201448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130878921 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3130878921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.884896649
Short name T1307
Test name
Test status
Simulation time 28777812 ps
CPU time 0.49 seconds
Started Aug 23 03:22:02 AM UTC 24
Finished Aug 23 03:22:04 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884896649 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.884896649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.871508781
Short name T1306
Test name
Test status
Simulation time 98319833 ps
CPU time 0.49 seconds
Started Aug 23 03:22:02 AM UTC 24
Finished Aug 23 03:22:04 AM UTC 24
Peak memory 201468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871508781 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.871508781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.3055997553
Short name T1309
Test name
Test status
Simulation time 14593708 ps
CPU time 0.53 seconds
Started Aug 23 03:22:02 AM UTC 24
Finished Aug 23 03:22:04 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055997553 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3055997553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1772115355
Short name T1310
Test name
Test status
Simulation time 21728344 ps
CPU time 0.53 seconds
Started Aug 23 03:22:02 AM UTC 24
Finished Aug 23 03:22:04 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772115355 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1772115355
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.3900280812
Short name T1313
Test name
Test status
Simulation time 18400166 ps
CPU time 0.56 seconds
Started Aug 23 03:22:04 AM UTC 24
Finished Aug 23 03:22:05 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900280812 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3900280812
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.493361722
Short name T1311
Test name
Test status
Simulation time 44152089 ps
CPU time 0.51 seconds
Started Aug 23 03:22:04 AM UTC 24
Finished Aug 23 03:22:05 AM UTC 24
Peak memory 201472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493361722 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.493361722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2553604179
Short name T1312
Test name
Test status
Simulation time 16991984 ps
CPU time 0.53 seconds
Started Aug 23 03:22:04 AM UTC 24
Finished Aug 23 03:22:05 AM UTC 24
Peak memory 201480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553604179 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2553604179
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.1368031061
Short name T1314
Test name
Test status
Simulation time 41605344 ps
CPU time 0.52 seconds
Started Aug 23 03:22:04 AM UTC 24
Finished Aug 23 03:22:05 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368031061 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1368031061
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3683475388
Short name T1315
Test name
Test status
Simulation time 58661909 ps
CPU time 0.54 seconds
Started Aug 23 03:22:04 AM UTC 24
Finished Aug 23 03:22:05 AM UTC 24
Peak memory 201620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683475388 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3683475388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1672444504
Short name T1209
Test name
Test status
Simulation time 76807507 ps
CPU time 0.82 seconds
Started Aug 23 03:21:36 AM UTC 24
Finished Aug 23 03:21:38 AM UTC 24
Peak memory 202712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1672444504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r
eset.1672444504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.4088613420
Short name T71
Test name
Test status
Simulation time 155721992 ps
CPU time 0.52 seconds
Started Aug 23 03:21:36 AM UTC 24
Finished Aug 23 03:21:38 AM UTC 24
Peak memory 201736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088613420 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.4088613420
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.2498851055
Short name T1206
Test name
Test status
Simulation time 21599471 ps
CPU time 0.52 seconds
Started Aug 23 03:21:34 AM UTC 24
Finished Aug 23 03:21:36 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498851055 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2498851055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.4146936621
Short name T70
Test name
Test status
Simulation time 16190237 ps
CPU time 0.55 seconds
Started Aug 23 03:21:36 AM UTC 24
Finished Aug 23 03:21:38 AM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146936621 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.4146936621
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.1392750888
Short name T1208
Test name
Test status
Simulation time 97166465 ps
CPU time 1.17 seconds
Started Aug 23 03:21:34 AM UTC 24
Finished Aug 23 03:21:36 AM UTC 24
Peak memory 201652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392750888 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1392750888
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2495306950
Short name T1215
Test name
Test status
Simulation time 73320997 ps
CPU time 0.9 seconds
Started Aug 23 03:21:39 AM UTC 24
Finished Aug 23 03:21:41 AM UTC 24
Peak memory 203680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2495306950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_r
eset.2495306950
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1471556363
Short name T1211
Test name
Test status
Simulation time 43371807 ps
CPU time 0.52 seconds
Started Aug 23 03:21:38 AM UTC 24
Finished Aug 23 03:21:39 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471556363 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1471556363
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.3573860635
Short name T1210
Test name
Test status
Simulation time 34752158 ps
CPU time 0.54 seconds
Started Aug 23 03:21:38 AM UTC 24
Finished Aug 23 03:21:39 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573860635 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3573860635
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.4146873830
Short name T1212
Test name
Test status
Simulation time 80082814 ps
CPU time 0.58 seconds
Started Aug 23 03:21:38 AM UTC 24
Finished Aug 23 03:21:39 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146873830 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.4146873830
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2981529175
Short name T1213
Test name
Test status
Simulation time 102868414 ps
CPU time 1.79 seconds
Started Aug 23 03:21:36 AM UTC 24
Finished Aug 23 03:21:39 AM UTC 24
Peak memory 203696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981529175 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2981529175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.105333683
Short name T82
Test name
Test status
Simulation time 204195204 ps
CPU time 0.83 seconds
Started Aug 23 03:21:36 AM UTC 24
Finished Aug 23 03:21:38 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105333683 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.105333683
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1047344271
Short name T1221
Test name
Test status
Simulation time 32814298 ps
CPU time 0.7 seconds
Started Aug 23 03:21:41 AM UTC 24
Finished Aug 23 03:21:43 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1047344271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_r
eset.1047344271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.2310784769
Short name T1218
Test name
Test status
Simulation time 44279240 ps
CPU time 0.6 seconds
Started Aug 23 03:21:41 AM UTC 24
Finished Aug 23 03:21:42 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310784769 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2310784769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.1234010632
Short name T1214
Test name
Test status
Simulation time 46378838 ps
CPU time 0.51 seconds
Started Aug 23 03:21:39 AM UTC 24
Finished Aug 23 03:21:40 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234010632 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1234010632
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.4098666028
Short name T1219
Test name
Test status
Simulation time 20982665 ps
CPU time 0.59 seconds
Started Aug 23 03:21:41 AM UTC 24
Finished Aug 23 03:21:42 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098666028 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.4098666028
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.3079598957
Short name T1216
Test name
Test status
Simulation time 364374181 ps
CPU time 2.06 seconds
Started Aug 23 03:21:39 AM UTC 24
Finished Aug 23 03:21:42 AM UTC 24
Peak memory 204804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079598957 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3079598957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.1832748877
Short name T77
Test name
Test status
Simulation time 46904282 ps
CPU time 0.87 seconds
Started Aug 23 03:21:39 AM UTC 24
Finished Aug 23 03:21:41 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832748877 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1832748877
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2289157640
Short name T1223
Test name
Test status
Simulation time 94019116 ps
CPU time 0.73 seconds
Started Aug 23 03:21:42 AM UTC 24
Finished Aug 23 03:21:44 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2289157640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r
eset.2289157640
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.920087833
Short name T1220
Test name
Test status
Simulation time 26714509 ps
CPU time 0.54 seconds
Started Aug 23 03:21:41 AM UTC 24
Finished Aug 23 03:21:42 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920087833 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.920087833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.504181629
Short name T1217
Test name
Test status
Simulation time 13948505 ps
CPU time 0.52 seconds
Started Aug 23 03:21:41 AM UTC 24
Finished Aug 23 03:21:42 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504181629 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.504181629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.357943008
Short name T1222
Test name
Test status
Simulation time 29857244 ps
CPU time 0.6 seconds
Started Aug 23 03:21:42 AM UTC 24
Finished Aug 23 03:21:44 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357943008 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.357943008
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1894393965
Short name T1224
Test name
Test status
Simulation time 93734553 ps
CPU time 1.91 seconds
Started Aug 23 03:21:41 AM UTC 24
Finished Aug 23 03:21:44 AM UTC 24
Peak memory 203696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894393965 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1894393965
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3954861167
Short name T1227
Test name
Test status
Simulation time 23497459 ps
CPU time 0.6 seconds
Started Aug 23 03:21:43 AM UTC 24
Finished Aug 23 03:21:45 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3954861167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r
eset.3954861167
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.3635534580
Short name T1226
Test name
Test status
Simulation time 21669425 ps
CPU time 0.52 seconds
Started Aug 23 03:21:43 AM UTC 24
Finished Aug 23 03:21:45 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635534580 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3635534580
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2422131142
Short name T1225
Test name
Test status
Simulation time 13808032 ps
CPU time 0.52 seconds
Started Aug 23 03:21:43 AM UTC 24
Finished Aug 23 03:21:45 AM UTC 24
Peak memory 201488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422131142 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2422131142
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.125398436
Short name T1228
Test name
Test status
Simulation time 19135310 ps
CPU time 0.63 seconds
Started Aug 23 03:21:43 AM UTC 24
Finished Aug 23 03:21:45 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125398436 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.125398436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.2785171011
Short name T1229
Test name
Test status
Simulation time 53329260 ps
CPU time 1.3 seconds
Started Aug 23 03:21:43 AM UTC 24
Finished Aug 23 03:21:45 AM UTC 24
Peak memory 201440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785171011 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2785171011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.1443062316
Short name T83
Test name
Test status
Simulation time 44841253 ps
CPU time 0.81 seconds
Started Aug 23 03:21:43 AM UTC 24
Finished Aug 23 03:21:45 AM UTC 24
Peak memory 201712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443062316 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1443062316
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_fifo_full.1289961825
Short name T16
Test name
Test status
Simulation time 39180492537 ps
CPU time 41.34 seconds
Started Aug 23 03:23:01 AM UTC 24
Finished Aug 23 03:23:43 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289961825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1289961825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_fifo_reset.799629527
Short name T12
Test name
Test status
Simulation time 19589970664 ps
CPU time 28.97 seconds
Started Aug 23 03:23:01 AM UTC 24
Finished Aug 23 03:23:31 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799629527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.799629527
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_intr.2424756549
Short name T384
Test name
Test status
Simulation time 134388860561 ps
CPU time 183.75 seconds
Started Aug 23 03:23:01 AM UTC 24
Finished Aug 23 03:26:07 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424756549 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2424756549
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.1123562941
Short name T466
Test name
Test status
Simulation time 105427808589 ps
CPU time 632.65 seconds
Started Aug 23 03:23:04 AM UTC 24
Finished Aug 23 03:33:43 AM UTC 24
Peak memory 212428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123562941 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1123562941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_noise_filter.2646855576
Short name T94
Test name
Test status
Simulation time 67341928586 ps
CPU time 102.13 seconds
Started Aug 23 03:23:02 AM UTC 24
Finished Aug 23 03:24:46 AM UTC 24
Peak memory 217876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646855576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2646855576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_perf.717479072
Short name T539
Test name
Test status
Simulation time 19704539013 ps
CPU time 1049.69 seconds
Started Aug 23 03:23:03 AM UTC 24
Finished Aug 23 03:40:44 AM UTC 24
Peak memory 212468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717479072 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.717479072
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_rx_oversample.2378861845
Short name T20
Test name
Test status
Simulation time 4688078765 ps
CPU time 29.13 seconds
Started Aug 23 03:23:01 AM UTC 24
Finished Aug 23 03:23:31 AM UTC 24
Peak memory 207216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378861845 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2378861845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.1233818925
Short name T8
Test name
Test status
Simulation time 38848762183 ps
CPU time 14.33 seconds
Started Aug 23 03:23:02 AM UTC 24
Finished Aug 23 03:23:17 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233818925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1233818925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_smoke.521498758
Short name T1
Test name
Test status
Simulation time 289314580 ps
CPU time 1.42 seconds
Started Aug 23 03:23:01 AM UTC 24
Finished Aug 23 03:23:03 AM UTC 24
Peak memory 206580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521498758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.uart_smoke.521498758
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.3741487707
Short name T2
Test name
Test status
Simulation time 5257218129 ps
CPU time 1.48 seconds
Started Aug 23 03:23:02 AM UTC 24
Finished Aug 23 03:23:04 AM UTC 24
Peak memory 207428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741487707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3741487707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/0.uart_tx_rx.4151267456
Short name T43
Test name
Test status
Simulation time 90787660347 ps
CPU time 74.73 seconds
Started Aug 23 03:23:01 AM UTC 24
Finished Aug 23 03:24:17 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151267456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.4151267456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/0.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_alert_test.3645448882
Short name T30
Test name
Test status
Simulation time 56896079 ps
CPU time 0.51 seconds
Started Aug 23 03:23:32 AM UTC 24
Finished Aug 23 03:23:33 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645448882 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3645448882
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_fifo_full.2508331763
Short name T17
Test name
Test status
Simulation time 154887773027 ps
CPU time 34.78 seconds
Started Aug 23 03:23:08 AM UTC 24
Finished Aug 23 03:23:44 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508331763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2508331763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_intr.1736437989
Short name T22
Test name
Test status
Simulation time 38372209032 ps
CPU time 55.04 seconds
Started Aug 23 03:23:13 AM UTC 24
Finished Aug 23 03:24:10 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736437989 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1736437989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.2104788603
Short name T302
Test name
Test status
Simulation time 58812647492 ps
CPU time 416.15 seconds
Started Aug 23 03:23:28 AM UTC 24
Finished Aug 23 03:30:29 AM UTC 24
Peak memory 212148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104788603 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2104788603
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_loopback.146634421
Short name T24
Test name
Test status
Simulation time 4055479541 ps
CPU time 4.73 seconds
Started Aug 23 03:23:26 AM UTC 24
Finished Aug 23 03:23:32 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146634421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.uart_loopback.146634421
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_noise_filter.2069691810
Short name T10
Test name
Test status
Simulation time 51871637467 ps
CPU time 7.18 seconds
Started Aug 23 03:23:17 AM UTC 24
Finished Aug 23 03:23:26 AM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069691810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2069691810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_perf.1265771662
Short name T325
Test name
Test status
Simulation time 10793511538 ps
CPU time 271.21 seconds
Started Aug 23 03:23:27 AM UTC 24
Finished Aug 23 03:28:02 AM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265771662 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1265771662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_rx_oversample.1355498672
Short name T7
Test name
Test status
Simulation time 1862988600 ps
CPU time 4.75 seconds
Started Aug 23 03:23:11 AM UTC 24
Finished Aug 23 03:23:16 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355498672 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1355498672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.37253781
Short name T18
Test name
Test status
Simulation time 114205485865 ps
CPU time 25.85 seconds
Started Aug 23 03:23:21 AM UTC 24
Finished Aug 23 03:23:49 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37253781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.37253781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.1542316560
Short name T9
Test name
Test status
Simulation time 1593501164 ps
CPU time 1.17 seconds
Started Aug 23 03:23:18 AM UTC 24
Finished Aug 23 03:23:21 AM UTC 24
Peak memory 204436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542316560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1542316560
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_sec_cm.208746513
Short name T29
Test name
Test status
Simulation time 145839903 ps
CPU time 0.75 seconds
Started Aug 23 03:23:30 AM UTC 24
Finished Aug 23 03:23:32 AM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208746513 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.208746513
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_smoke.2949177131
Short name T5
Test name
Test status
Simulation time 543150368 ps
CPU time 1 seconds
Started Aug 23 03:23:07 AM UTC 24
Finished Aug 23 03:23:09 AM UTC 24
Peak memory 206376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949177131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2949177131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.2655146913
Short name T14
Test name
Test status
Simulation time 863383521 ps
CPU time 2.7 seconds
Started Aug 23 03:23:24 AM UTC 24
Finished Aug 23 03:23:28 AM UTC 24
Peak memory 207104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655146913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2655146913
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/1.uart_tx_rx.3993501487
Short name T312
Test name
Test status
Simulation time 65292730469 ps
CPU time 136.14 seconds
Started Aug 23 03:23:07 AM UTC 24
Finished Aug 23 03:25:25 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993501487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3993501487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_alert_test.2338082022
Short name T446
Test name
Test status
Simulation time 11591400 ps
CPU time 0.46 seconds
Started Aug 23 03:29:37 AM UTC 24
Finished Aug 23 03:29:38 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338082022 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2338082022
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.307323247
Short name T125
Test name
Test status
Simulation time 119697849966 ps
CPU time 95.67 seconds
Started Aug 23 03:28:37 AM UTC 24
Finished Aug 23 03:30:14 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307323247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.307323247
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_fifo_reset.3853661411
Short name T300
Test name
Test status
Simulation time 251473294823 ps
CPU time 67.59 seconds
Started Aug 23 03:28:40 AM UTC 24
Finished Aug 23 03:29:49 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853661411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3853661411
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_intr.1165301271
Short name T100
Test name
Test status
Simulation time 40039853837 ps
CPU time 19.01 seconds
Started Aug 23 03:29:06 AM UTC 24
Finished Aug 23 03:29:26 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165301271 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1165301271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.2343845710
Short name T278
Test name
Test status
Simulation time 63541314419 ps
CPU time 327.53 seconds
Started Aug 23 03:29:24 AM UTC 24
Finished Aug 23 03:34:56 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343845710 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2343845710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_loopback.3386801055
Short name T445
Test name
Test status
Simulation time 2091775429 ps
CPU time 2.08 seconds
Started Aug 23 03:29:22 AM UTC 24
Finished Aug 23 03:29:25 AM UTC 24
Peak memory 204972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386801055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3386801055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_noise_filter.3616412864
Short name T350
Test name
Test status
Simulation time 12305927585 ps
CPU time 18.1 seconds
Started Aug 23 03:29:16 AM UTC 24
Finished Aug 23 03:29:35 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616412864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3616412864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_perf.4221731012
Short name T315
Test name
Test status
Simulation time 10588381803 ps
CPU time 225.96 seconds
Started Aug 23 03:29:22 AM UTC 24
Finished Aug 23 03:33:11 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221731012 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4221731012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_rx_oversample.3713168383
Short name T448
Test name
Test status
Simulation time 6970205643 ps
CPU time 50.78 seconds
Started Aug 23 03:28:58 AM UTC 24
Finished Aug 23 03:29:50 AM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713168383 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3713168383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.810387809
Short name T136
Test name
Test status
Simulation time 16974554488 ps
CPU time 14.7 seconds
Started Aug 23 03:29:21 AM UTC 24
Finished Aug 23 03:29:37 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810387809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.810387809
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.3799854679
Short name T334
Test name
Test status
Simulation time 5935966750 ps
CPU time 2.79 seconds
Started Aug 23 03:29:18 AM UTC 24
Finished Aug 23 03:29:22 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799854679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3799854679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_smoke.3006842198
Short name T313
Test name
Test status
Simulation time 661795133 ps
CPU time 1.2 seconds
Started Aug 23 03:28:31 AM UTC 24
Finished Aug 23 03:28:33 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006842198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3006842198
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.380615804
Short name T37
Test name
Test status
Simulation time 5968441063 ps
CPU time 30.1 seconds
Started Aug 23 03:29:26 AM UTC 24
Finished Aug 23 03:29:58 AM UTC 24
Peak memory 217592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=380615804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all_
with_rand_reset.380615804
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.373748960
Short name T370
Test name
Test status
Simulation time 5578159278 ps
CPU time 1.49 seconds
Started Aug 23 03:29:21 AM UTC 24
Finished Aug 23 03:29:24 AM UTC 24
Peak memory 207764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373748960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.373748960
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/10.uart_tx_rx.3941735785
Short name T337
Test name
Test status
Simulation time 74845278493 ps
CPU time 30.92 seconds
Started Aug 23 03:28:33 AM UTC 24
Finished Aug 23 03:29:05 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941735785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3941735785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/10.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/100.uart_fifo_reset.726616918
Short name T1025
Test name
Test status
Simulation time 47525260833 ps
CPU time 63.62 seconds
Started Aug 23 04:06:37 AM UTC 24
Finished Aug 23 04:07:42 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726616918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.726616918
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/100.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/101.uart_fifo_reset.616075000
Short name T1016
Test name
Test status
Simulation time 21702679385 ps
CPU time 21.72 seconds
Started Aug 23 04:06:47 AM UTC 24
Finished Aug 23 04:07:10 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616075000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.616075000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/101.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/102.uart_fifo_reset.1269308632
Short name T1020
Test name
Test status
Simulation time 22479124457 ps
CPU time 32.26 seconds
Started Aug 23 04:06:48 AM UTC 24
Finished Aug 23 04:07:22 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269308632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1269308632
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/102.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/103.uart_fifo_reset.4143841423
Short name T190
Test name
Test status
Simulation time 68429355103 ps
CPU time 25.49 seconds
Started Aug 23 04:06:50 AM UTC 24
Finished Aug 23 04:07:16 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143841423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.4143841423
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/103.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/104.uart_fifo_reset.1395427026
Short name T1015
Test name
Test status
Simulation time 37707757494 ps
CPU time 15.07 seconds
Started Aug 23 04:06:52 AM UTC 24
Finished Aug 23 04:07:08 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395427026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1395427026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/104.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/105.uart_fifo_reset.3671353539
Short name T1029
Test name
Test status
Simulation time 136681591313 ps
CPU time 55.51 seconds
Started Aug 23 04:06:53 AM UTC 24
Finished Aug 23 04:07:50 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671353539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3671353539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/105.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/107.uart_fifo_reset.3980205513
Short name T1026
Test name
Test status
Simulation time 248406718965 ps
CPU time 46.96 seconds
Started Aug 23 04:06:57 AM UTC 24
Finished Aug 23 04:07:45 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980205513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3980205513
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/107.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/108.uart_fifo_reset.3638262991
Short name T1018
Test name
Test status
Simulation time 15339401934 ps
CPU time 21.05 seconds
Started Aug 23 04:06:58 AM UTC 24
Finished Aug 23 04:07:21 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638262991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3638262991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/108.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_alert_test.2346794024
Short name T450
Test name
Test status
Simulation time 12064235 ps
CPU time 0.47 seconds
Started Aug 23 03:30:15 AM UTC 24
Finished Aug 23 03:30:17 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346794024 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2346794024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.46856042
Short name T357
Test name
Test status
Simulation time 109908189353 ps
CPU time 165.14 seconds
Started Aug 23 03:29:50 AM UTC 24
Finished Aug 23 03:32:37 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46856042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.46856042
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_fifo_reset.1240205043
Short name T263
Test name
Test status
Simulation time 9370671138 ps
CPU time 13.03 seconds
Started Aug 23 03:29:51 AM UTC 24
Finished Aug 23 03:30:05 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240205043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1240205043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_intr.1522548933
Short name T96
Test name
Test status
Simulation time 12610427291 ps
CPU time 14.4 seconds
Started Aug 23 03:29:57 AM UTC 24
Finished Aug 23 03:30:13 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522548933 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1522548933
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_loopback.3809340056
Short name T449
Test name
Test status
Simulation time 366811591 ps
CPU time 0.96 seconds
Started Aug 23 03:30:09 AM UTC 24
Finished Aug 23 03:30:11 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809340056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3809340056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_noise_filter.841239343
Short name T344
Test name
Test status
Simulation time 73347484032 ps
CPU time 31.43 seconds
Started Aug 23 03:29:59 AM UTC 24
Finished Aug 23 03:30:32 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841239343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.841239343
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_perf.1865693575
Short name T361
Test name
Test status
Simulation time 12867308507 ps
CPU time 180.23 seconds
Started Aug 23 03:30:09 AM UTC 24
Finished Aug 23 03:33:12 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865693575 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1865693575
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_rx_oversample.95205734
Short name T453
Test name
Test status
Simulation time 7786433521 ps
CPU time 54.36 seconds
Started Aug 23 03:29:56 AM UTC 24
Finished Aug 23 03:30:52 AM UTC 24
Peak memory 207356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95205734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.95205734
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.2091175028
Short name T314
Test name
Test status
Simulation time 85432003077 ps
CPU time 81.09 seconds
Started Aug 23 03:30:00 AM UTC 24
Finished Aug 23 03:31:23 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091175028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2091175028
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_smoke.3266492264
Short name T447
Test name
Test status
Simulation time 526851224 ps
CPU time 1.93 seconds
Started Aug 23 03:29:38 AM UTC 24
Finished Aug 23 03:29:41 AM UTC 24
Peak memory 207436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266492264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3266492264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.537234288
Short name T317
Test name
Test status
Simulation time 1411704105 ps
CPU time 1.47 seconds
Started Aug 23 03:30:06 AM UTC 24
Finished Aug 23 03:30:09 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537234288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.537234288
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/11.uart_tx_rx.592645160
Short name T343
Test name
Test status
Simulation time 13427453625 ps
CPU time 19.15 seconds
Started Aug 23 03:29:39 AM UTC 24
Finished Aug 23 03:29:59 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592645160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.592645160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/11.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/110.uart_fifo_reset.1913678290
Short name T185
Test name
Test status
Simulation time 31555349206 ps
CPU time 52.31 seconds
Started Aug 23 04:07:06 AM UTC 24
Finished Aug 23 04:08:00 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913678290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1913678290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/110.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/111.uart_fifo_reset.1795775482
Short name T228
Test name
Test status
Simulation time 139886829917 ps
CPU time 49.47 seconds
Started Aug 23 04:07:09 AM UTC 24
Finished Aug 23 04:08:01 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795775482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1795775482
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/111.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/113.uart_fifo_reset.3967569716
Short name T970
Test name
Test status
Simulation time 52503686362 ps
CPU time 35.74 seconds
Started Aug 23 04:07:17 AM UTC 24
Finished Aug 23 04:07:54 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967569716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3967569716
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/113.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/115.uart_fifo_reset.511882736
Short name T1028
Test name
Test status
Simulation time 9296667990 ps
CPU time 26.42 seconds
Started Aug 23 04:07:21 AM UTC 24
Finished Aug 23 04:07:48 AM UTC 24
Peak memory 208736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511882736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.511882736
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/115.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/116.uart_fifo_reset.578302771
Short name T1032
Test name
Test status
Simulation time 123867284081 ps
CPU time 38.41 seconds
Started Aug 23 04:07:23 AM UTC 24
Finished Aug 23 04:08:03 AM UTC 24
Peak memory 208348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578302771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.578302771
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/116.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/117.uart_fifo_reset.882195817
Short name T1030
Test name
Test status
Simulation time 17483009168 ps
CPU time 26.52 seconds
Started Aug 23 04:07:23 AM UTC 24
Finished Aug 23 04:07:51 AM UTC 24
Peak memory 208280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882195817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.882195817
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/117.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/118.uart_fifo_reset.4062691409
Short name T1027
Test name
Test status
Simulation time 9496843623 ps
CPU time 23.05 seconds
Started Aug 23 04:07:23 AM UTC 24
Finished Aug 23 04:07:47 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062691409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4062691409
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/118.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/119.uart_fifo_reset.3828750979
Short name T1050
Test name
Test status
Simulation time 154128947294 ps
CPU time 103.33 seconds
Started Aug 23 04:07:23 AM UTC 24
Finished Aug 23 04:09:08 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828750979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3828750979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/119.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_alert_test.3828765751
Short name T455
Test name
Test status
Simulation time 12939745 ps
CPU time 0.49 seconds
Started Aug 23 03:31:26 AM UTC 24
Finished Aug 23 03:31:28 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828765751 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3828765751
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_fifo_full.3831894023
Short name T138
Test name
Test status
Simulation time 190266664599 ps
CPU time 411.01 seconds
Started Aug 23 03:30:31 AM UTC 24
Finished Aug 23 03:37:26 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831894023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3831894023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_fifo_reset.3081119785
Short name T380
Test name
Test status
Simulation time 27978697902 ps
CPU time 12.56 seconds
Started Aug 23 03:30:33 AM UTC 24
Finished Aug 23 03:30:46 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081119785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3081119785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_intr.3154195420
Short name T101
Test name
Test status
Simulation time 30792543055 ps
CPU time 14.58 seconds
Started Aug 23 03:30:45 AM UTC 24
Finished Aug 23 03:31:01 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154195420 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3154195420
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.223938836
Short name T333
Test name
Test status
Simulation time 92451652438 ps
CPU time 294.95 seconds
Started Aug 23 03:31:05 AM UTC 24
Finished Aug 23 03:36:04 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223938836 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.223938836
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_loopback.4241955688
Short name T454
Test name
Test status
Simulation time 4062325461 ps
CPU time 2.17 seconds
Started Aug 23 03:31:01 AM UTC 24
Finished Aug 23 03:31:04 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241955688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4241955688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_perf.485477464
Short name T326
Test name
Test status
Simulation time 15757475781 ps
CPU time 152.05 seconds
Started Aug 23 03:31:03 AM UTC 24
Finished Aug 23 03:33:38 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485477464 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.485477464
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_rx_oversample.3376069891
Short name T452
Test name
Test status
Simulation time 2714875348 ps
CPU time 3.7 seconds
Started Aug 23 03:30:40 AM UTC 24
Finished Aug 23 03:30:44 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376069891 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3376069891
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.4259852594
Short name T292
Test name
Test status
Simulation time 26581172021 ps
CPU time 42.18 seconds
Started Aug 23 03:31:00 AM UTC 24
Finished Aug 23 03:31:44 AM UTC 24
Peak memory 208204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259852594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4259852594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.656260436
Short name T374
Test name
Test status
Simulation time 2909999171 ps
CPU time 5.01 seconds
Started Aug 23 03:30:53 AM UTC 24
Finished Aug 23 03:30:59 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656260436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.656260436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_smoke.2410191492
Short name T451
Test name
Test status
Simulation time 242670080 ps
CPU time 1.11 seconds
Started Aug 23 03:30:17 AM UTC 24
Finished Aug 23 03:30:20 AM UTC 24
Peak memory 206380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410191492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2410191492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_stress_all.1262200622
Short name T363
Test name
Test status
Simulation time 72102296180 ps
CPU time 57.43 seconds
Started Aug 23 03:31:24 AM UTC 24
Finished Aug 23 03:32:23 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262200622 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1262200622
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.3599938750
Short name T39
Test name
Test status
Simulation time 7854876342 ps
CPU time 36.35 seconds
Started Aug 23 03:31:23 AM UTC 24
Finished Aug 23 03:32:01 AM UTC 24
Peak memory 217736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3599938750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all
_with_rand_reset.3599938750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.579607365
Short name T360
Test name
Test status
Simulation time 559566270 ps
CPU time 1.52 seconds
Started Aug 23 03:31:00 AM UTC 24
Finished Aug 23 03:31:03 AM UTC 24
Peak memory 206416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579607365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.579607365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/12.uart_tx_rx.2246963234
Short name T264
Test name
Test status
Simulation time 42172241143 ps
CPU time 37.24 seconds
Started Aug 23 03:30:21 AM UTC 24
Finished Aug 23 03:30:59 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246963234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2246963234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/12.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/120.uart_fifo_reset.833965394
Short name T1093
Test name
Test status
Simulation time 131018758282 ps
CPU time 262.44 seconds
Started Aug 23 04:07:25 AM UTC 24
Finished Aug 23 04:11:51 AM UTC 24
Peak memory 212048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833965394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.833965394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/120.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/122.uart_fifo_reset.2172030438
Short name T1024
Test name
Test status
Simulation time 25351516151 ps
CPU time 11.89 seconds
Started Aug 23 04:07:25 AM UTC 24
Finished Aug 23 04:07:38 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172030438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2172030438
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/122.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/125.uart_fifo_reset.4136273622
Short name T1034
Test name
Test status
Simulation time 40832779918 ps
CPU time 28.18 seconds
Started Aug 23 04:07:42 AM UTC 24
Finished Aug 23 04:08:11 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136273622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.4136273622
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/125.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/126.uart_fifo_reset.4077056878
Short name T1041
Test name
Test status
Simulation time 170996756226 ps
CPU time 60.56 seconds
Started Aug 23 04:07:43 AM UTC 24
Finished Aug 23 04:08:45 AM UTC 24
Peak memory 208516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077056878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.4077056878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/126.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/127.uart_fifo_reset.2288412505
Short name T1043
Test name
Test status
Simulation time 89846447930 ps
CPU time 64.4 seconds
Started Aug 23 04:07:47 AM UTC 24
Finished Aug 23 04:08:52 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288412505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2288412505
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/127.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/128.uart_fifo_reset.2779505350
Short name T231
Test name
Test status
Simulation time 79012947957 ps
CPU time 30.13 seconds
Started Aug 23 04:07:49 AM UTC 24
Finished Aug 23 04:08:20 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779505350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2779505350
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/128.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/129.uart_fifo_reset.1255901874
Short name T1033
Test name
Test status
Simulation time 11750842835 ps
CPU time 17.94 seconds
Started Aug 23 04:07:50 AM UTC 24
Finished Aug 23 04:08:09 AM UTC 24
Peak memory 208480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255901874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1255901874
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/129.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_alert_test.486134995
Short name T460
Test name
Test status
Simulation time 23301839 ps
CPU time 0.48 seconds
Started Aug 23 03:32:29 AM UTC 24
Finished Aug 23 03:32:31 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486134995 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.486134995
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.4246335431
Short name T342
Test name
Test status
Simulation time 29735056496 ps
CPU time 23.42 seconds
Started Aug 23 03:31:43 AM UTC 24
Finished Aug 23 03:32:07 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246335431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.4246335431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_intr.3925768457
Short name T375
Test name
Test status
Simulation time 17617309148 ps
CPU time 10.15 seconds
Started Aug 23 03:31:59 AM UTC 24
Finished Aug 23 03:32:10 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925768457 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3925768457
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.25808117
Short name T496
Test name
Test status
Simulation time 81148147130 ps
CPU time 322.96 seconds
Started Aug 23 03:32:12 AM UTC 24
Finished Aug 23 03:37:39 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25808117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.25808117
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_loopback.339208511
Short name T459
Test name
Test status
Simulation time 8119867534 ps
CPU time 13.92 seconds
Started Aug 23 03:32:11 AM UTC 24
Finished Aug 23 03:32:26 AM UTC 24
Peak memory 207892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339208511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.uart_loopback.339208511
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_noise_filter.990899722
Short name T352
Test name
Test status
Simulation time 87320265076 ps
CPU time 61.13 seconds
Started Aug 23 03:31:59 AM UTC 24
Finished Aug 23 03:33:01 AM UTC 24
Peak memory 208984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990899722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.990899722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_perf.590422686
Short name T523
Test name
Test status
Simulation time 9602807337 ps
CPU time 430.66 seconds
Started Aug 23 03:32:11 AM UTC 24
Finished Aug 23 03:39:27 AM UTC 24
Peak memory 212272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590422686 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.590422686
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_rx_oversample.3495216974
Short name T457
Test name
Test status
Simulation time 1888501922 ps
CPU time 4.05 seconds
Started Aug 23 03:31:53 AM UTC 24
Finished Aug 23 03:31:58 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495216974 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3495216974
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.2513156044
Short name T458
Test name
Test status
Simulation time 3265097714 ps
CPU time 3.09 seconds
Started Aug 23 03:32:02 AM UTC 24
Finished Aug 23 03:32:06 AM UTC 24
Peak memory 205104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513156044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2513156044
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_smoke.1635003544
Short name T369
Test name
Test status
Simulation time 5574855995 ps
CPU time 7.3 seconds
Started Aug 23 03:31:28 AM UTC 24
Finished Aug 23 03:31:37 AM UTC 24
Peak memory 208844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635003544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1635003544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_stress_all.1163568733
Short name T719
Test name
Test status
Simulation time 269419703900 ps
CPU time 1153.85 seconds
Started Aug 23 03:32:27 AM UTC 24
Finished Aug 23 03:51:53 AM UTC 24
Peak memory 212192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163568733 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1163568733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.1880100871
Short name T391
Test name
Test status
Simulation time 977681695 ps
CPU time 9.53 seconds
Started Aug 23 03:32:24 AM UTC 24
Finished Aug 23 03:32:35 AM UTC 24
Peak memory 222020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1880100871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all
_with_rand_reset.1880100871
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.2698066617
Short name T329
Test name
Test status
Simulation time 3045393914 ps
CPU time 1.68 seconds
Started Aug 23 03:32:08 AM UTC 24
Finished Aug 23 03:32:11 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698066617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2698066617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/13.uart_tx_rx.3115457874
Short name T456
Test name
Test status
Simulation time 35801965139 ps
CPU time 13.34 seconds
Started Aug 23 03:31:37 AM UTC 24
Finished Aug 23 03:31:52 AM UTC 24
Peak memory 208552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115457874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3115457874
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/13.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/130.uart_fifo_reset.2197322835
Short name T1031
Test name
Test status
Simulation time 12996211691 ps
CPU time 4.86 seconds
Started Aug 23 04:07:52 AM UTC 24
Finished Aug 23 04:07:58 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197322835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2197322835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/130.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/132.uart_fifo_reset.3884074259
Short name T1053
Test name
Test status
Simulation time 65654102731 ps
CPU time 85.97 seconds
Started Aug 23 04:07:52 AM UTC 24
Finished Aug 23 04:09:20 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884074259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3884074259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/132.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/133.uart_fifo_reset.848962098
Short name T1036
Test name
Test status
Simulation time 15038113686 ps
CPU time 20.03 seconds
Started Aug 23 04:07:55 AM UTC 24
Finished Aug 23 04:08:17 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848962098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.848962098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/133.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/135.uart_fifo_reset.1233501709
Short name T1056
Test name
Test status
Simulation time 43330996517 ps
CPU time 89.74 seconds
Started Aug 23 04:07:59 AM UTC 24
Finished Aug 23 04:09:31 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233501709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1233501709
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/135.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/136.uart_fifo_reset.481796845
Short name T1088
Test name
Test status
Simulation time 91254614137 ps
CPU time 211.68 seconds
Started Aug 23 04:08:02 AM UTC 24
Finished Aug 23 04:11:36 AM UTC 24
Peak memory 208424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481796845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.481796845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/136.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/137.uart_fifo_reset.240124986
Short name T1042
Test name
Test status
Simulation time 57177905710 ps
CPU time 45.39 seconds
Started Aug 23 04:08:02 AM UTC 24
Finished Aug 23 04:08:49 AM UTC 24
Peak memory 208344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240124986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.240124986
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/137.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/138.uart_fifo_reset.1788629581
Short name T233
Test name
Test status
Simulation time 25866023196 ps
CPU time 20.43 seconds
Started Aug 23 04:08:04 AM UTC 24
Finished Aug 23 04:08:26 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788629581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1788629581
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/138.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/139.uart_fifo_reset.1923637218
Short name T1039
Test name
Test status
Simulation time 55759473197 ps
CPU time 19.68 seconds
Started Aug 23 04:08:10 AM UTC 24
Finished Aug 23 04:08:31 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923637218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1923637218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/139.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_alert_test.3522012851
Short name T464
Test name
Test status
Simulation time 12755273 ps
CPU time 0.46 seconds
Started Aug 23 03:33:24 AM UTC 24
Finished Aug 23 03:33:26 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522012851 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3522012851
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_fifo_full.208850662
Short name T335
Test name
Test status
Simulation time 84259918210 ps
CPU time 32.27 seconds
Started Aug 23 03:32:34 AM UTC 24
Finished Aug 23 03:33:08 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208850662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.208850662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.1165009743
Short name T129
Test name
Test status
Simulation time 24897851475 ps
CPU time 10.53 seconds
Started Aug 23 03:32:36 AM UTC 24
Finished Aug 23 03:32:47 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165009743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1165009743
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_intr.561340509
Short name T348
Test name
Test status
Simulation time 176417868557 ps
CPU time 357.86 seconds
Started Aug 23 03:32:50 AM UTC 24
Finished Aug 23 03:38:52 AM UTC 24
Peak memory 208528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561340509 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.561340509
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.4191994314
Short name T501
Test name
Test status
Simulation time 78110221461 ps
CPU time 275.78 seconds
Started Aug 23 03:33:15 AM UTC 24
Finished Aug 23 03:37:54 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191994314 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4191994314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_loopback.1215510488
Short name T463
Test name
Test status
Simulation time 10517614778 ps
CPU time 9.26 seconds
Started Aug 23 03:33:13 AM UTC 24
Finished Aug 23 03:33:23 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215510488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1215510488
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_noise_filter.1846080049
Short name T366
Test name
Test status
Simulation time 62066115733 ps
CPU time 49.93 seconds
Started Aug 23 03:33:02 AM UTC 24
Finished Aug 23 03:33:53 AM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846080049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1846080049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_perf.3398950002
Short name T529
Test name
Test status
Simulation time 32276658392 ps
CPU time 405.07 seconds
Started Aug 23 03:33:15 AM UTC 24
Finished Aug 23 03:40:05 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398950002 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3398950002
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_rx_oversample.1428331103
Short name T467
Test name
Test status
Simulation time 6768942846 ps
CPU time 58.51 seconds
Started Aug 23 03:32:48 AM UTC 24
Finished Aug 23 03:33:48 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428331103 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1428331103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.2974142420
Short name T347
Test name
Test status
Simulation time 40194768779 ps
CPU time 32.04 seconds
Started Aug 23 03:33:12 AM UTC 24
Finished Aug 23 03:33:45 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974142420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2974142420
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.472069383
Short name T461
Test name
Test status
Simulation time 5818657911 ps
CPU time 4.38 seconds
Started Aug 23 03:33:09 AM UTC 24
Finished Aug 23 03:33:14 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472069383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.472069383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_smoke.869878719
Short name T362
Test name
Test status
Simulation time 714598017 ps
CPU time 2.49 seconds
Started Aug 23 03:32:30 AM UTC 24
Finished Aug 23 03:32:34 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869878719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.uart_smoke.869878719
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_stress_all.932802679
Short name T104
Test name
Test status
Simulation time 141937569086 ps
CPU time 251.48 seconds
Started Aug 23 03:33:24 AM UTC 24
Finished Aug 23 03:37:39 AM UTC 24
Peak memory 208976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932802679 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.932802679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.615705093
Short name T86
Test name
Test status
Simulation time 1326102152 ps
CPU time 7.74 seconds
Started Aug 23 03:33:17 AM UTC 24
Finished Aug 23 03:33:26 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=615705093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all_
with_rand_reset.615705093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.469900055
Short name T462
Test name
Test status
Simulation time 824034789 ps
CPU time 1.36 seconds
Started Aug 23 03:33:12 AM UTC 24
Finished Aug 23 03:33:14 AM UTC 24
Peak memory 207116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469900055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.469900055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/14.uart_tx_rx.463812693
Short name T320
Test name
Test status
Simulation time 73741529067 ps
CPU time 51.42 seconds
Started Aug 23 03:32:31 AM UTC 24
Finished Aug 23 03:33:24 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463812693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.463812693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/14.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/140.uart_fifo_reset.270820209
Short name T1046
Test name
Test status
Simulation time 29775114666 ps
CPU time 47.41 seconds
Started Aug 23 04:08:13 AM UTC 24
Finished Aug 23 04:09:01 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270820209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.270820209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/140.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/141.uart_fifo_reset.1358466441
Short name T1060
Test name
Test status
Simulation time 79527968371 ps
CPU time 90.4 seconds
Started Aug 23 04:08:14 AM UTC 24
Finished Aug 23 04:09:46 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358466441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1358466441
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/141.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/142.uart_fifo_reset.2809964669
Short name T1052
Test name
Test status
Simulation time 139504503381 ps
CPU time 54.01 seconds
Started Aug 23 04:08:17 AM UTC 24
Finished Aug 23 04:09:13 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809964669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2809964669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/142.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/144.uart_fifo_reset.2949186339
Short name T1063
Test name
Test status
Simulation time 183714587189 ps
CPU time 83.62 seconds
Started Aug 23 04:08:22 AM UTC 24
Finished Aug 23 04:09:47 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949186339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2949186339
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/144.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/145.uart_fifo_reset.762843888
Short name T1057
Test name
Test status
Simulation time 151649378573 ps
CPU time 63.02 seconds
Started Aug 23 04:08:26 AM UTC 24
Finished Aug 23 04:09:31 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762843888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.762843888
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/145.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/147.uart_fifo_reset.257266602
Short name T179
Test name
Test status
Simulation time 101645294801 ps
CPU time 35.47 seconds
Started Aug 23 04:08:32 AM UTC 24
Finished Aug 23 04:09:09 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257266602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.257266602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/147.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/148.uart_fifo_reset.2432143710
Short name T1068
Test name
Test status
Simulation time 190668658496 ps
CPU time 87.72 seconds
Started Aug 23 04:08:34 AM UTC 24
Finished Aug 23 04:10:04 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432143710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2432143710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/148.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/149.uart_fifo_reset.1101118666
Short name T1048
Test name
Test status
Simulation time 64141755193 ps
CPU time 25.13 seconds
Started Aug 23 04:08:39 AM UTC 24
Finished Aug 23 04:09:05 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101118666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1101118666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/149.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_alert_test.748017764
Short name T471
Test name
Test status
Simulation time 14166699 ps
CPU time 0.47 seconds
Started Aug 23 03:34:09 AM UTC 24
Finished Aug 23 03:34:11 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748017764 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.748017764
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_fifo_full.3531868828
Short name T469
Test name
Test status
Simulation time 36467610585 ps
CPU time 26.75 seconds
Started Aug 23 03:33:27 AM UTC 24
Finished Aug 23 03:33:55 AM UTC 24
Peak memory 208380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531868828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3531868828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.2308882366
Short name T386
Test name
Test status
Simulation time 155500129878 ps
CPU time 27.71 seconds
Started Aug 23 03:33:29 AM UTC 24
Finished Aug 23 03:33:59 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308882366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2308882366
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_fifo_reset.817856815
Short name T353
Test name
Test status
Simulation time 18428919216 ps
CPU time 54.9 seconds
Started Aug 23 03:33:36 AM UTC 24
Finished Aug 23 03:34:32 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817856815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.817856815
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_intr.1010415815
Short name T405
Test name
Test status
Simulation time 16559844998 ps
CPU time 13.71 seconds
Started Aug 23 03:33:45 AM UTC 24
Finished Aug 23 03:34:00 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010415815 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1010415815
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_loopback.2931007713
Short name T470
Test name
Test status
Simulation time 4790514604 ps
CPU time 7.15 seconds
Started Aug 23 03:33:56 AM UTC 24
Finished Aug 23 03:34:04 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931007713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2931007713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_noise_filter.4256059678
Short name T296
Test name
Test status
Simulation time 109259577744 ps
CPU time 46.76 seconds
Started Aug 23 03:33:46 AM UTC 24
Finished Aug 23 03:34:34 AM UTC 24
Peak memory 208496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256059678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.4256059678
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_perf.773874994
Short name T484
Test name
Test status
Simulation time 15788126505 ps
CPU time 141.7 seconds
Started Aug 23 03:33:59 AM UTC 24
Finished Aug 23 03:36:23 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773874994 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.773874994
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_rx_oversample.2953784795
Short name T468
Test name
Test status
Simulation time 5510850579 ps
CPU time 10.57 seconds
Started Aug 23 03:33:39 AM UTC 24
Finished Aug 23 03:33:50 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953784795 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2953784795
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.2048328121
Short name T307
Test name
Test status
Simulation time 73752675414 ps
CPU time 32.31 seconds
Started Aug 23 03:33:51 AM UTC 24
Finished Aug 23 03:34:25 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048328121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2048328121
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.1512706819
Short name T339
Test name
Test status
Simulation time 51792103298 ps
CPU time 18.17 seconds
Started Aug 23 03:33:49 AM UTC 24
Finished Aug 23 03:34:08 AM UTC 24
Peak memory 205160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512706819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1512706819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_smoke.27676098
Short name T368
Test name
Test status
Simulation time 546286959 ps
CPU time 1.63 seconds
Started Aug 23 03:33:25 AM UTC 24
Finished Aug 23 03:33:28 AM UTC 24
Peak memory 207800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27676098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_smoke.27676098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_stress_all.346018351
Short name T418
Test name
Test status
Simulation time 100243535715 ps
CPU time 986.02 seconds
Started Aug 23 03:34:05 AM UTC 24
Finished Aug 23 03:50:41 AM UTC 24
Peak memory 212404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346018351 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.346018351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.3597776094
Short name T87
Test name
Test status
Simulation time 13753703631 ps
CPU time 43 seconds
Started Aug 23 03:34:01 AM UTC 24
Finished Aug 23 03:34:45 AM UTC 24
Peak memory 225360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3597776094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all
_with_rand_reset.3597776094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.3205093045
Short name T381
Test name
Test status
Simulation time 1411077994 ps
CPU time 3.46 seconds
Started Aug 23 03:33:54 AM UTC 24
Finished Aug 23 03:33:58 AM UTC 24
Peak memory 207492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205093045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3205093045
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/15.uart_tx_rx.2968426024
Short name T465
Test name
Test status
Simulation time 5366978554 ps
CPU time 7.51 seconds
Started Aug 23 03:33:26 AM UTC 24
Finished Aug 23 03:33:35 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968426024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2968426024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/15.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/150.uart_fifo_reset.3252093324
Short name T1044
Test name
Test status
Simulation time 92083278114 ps
CPU time 10.36 seconds
Started Aug 23 04:08:41 AM UTC 24
Finished Aug 23 04:08:53 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252093324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3252093324
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/150.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/152.uart_fifo_reset.2870503312
Short name T1047
Test name
Test status
Simulation time 36849485173 ps
CPU time 14.13 seconds
Started Aug 23 04:08:49 AM UTC 24
Finished Aug 23 04:09:04 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870503312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2870503312
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/152.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/153.uart_fifo_reset.605448011
Short name T1084
Test name
Test status
Simulation time 92618386316 ps
CPU time 144.74 seconds
Started Aug 23 04:08:50 AM UTC 24
Finished Aug 23 04:11:17 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605448011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.605448011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/153.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/154.uart_fifo_reset.4008819510
Short name T1049
Test name
Test status
Simulation time 30246322186 ps
CPU time 12.73 seconds
Started Aug 23 04:08:54 AM UTC 24
Finished Aug 23 04:09:08 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008819510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4008819510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/154.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/155.uart_fifo_reset.3284475178
Short name T1096
Test name
Test status
Simulation time 64235633126 ps
CPU time 182.71 seconds
Started Aug 23 04:08:54 AM UTC 24
Finished Aug 23 04:11:59 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284475178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3284475178
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/155.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/156.uart_fifo_reset.3611495620
Short name T1164
Test name
Test status
Simulation time 99571780619 ps
CPU time 350.39 seconds
Started Aug 23 04:09:02 AM UTC 24
Finished Aug 23 04:14:57 AM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611495620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3611495620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/156.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/157.uart_fifo_reset.1281312295
Short name T207
Test name
Test status
Simulation time 38410480017 ps
CPU time 28.72 seconds
Started Aug 23 04:09:03 AM UTC 24
Finished Aug 23 04:09:33 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281312295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1281312295
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/157.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/158.uart_fifo_reset.1474821047
Short name T1061
Test name
Test status
Simulation time 22803827664 ps
CPU time 40.32 seconds
Started Aug 23 04:09:05 AM UTC 24
Finished Aug 23 04:09:46 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474821047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1474821047
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/158.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/159.uart_fifo_reset.3948593290
Short name T1054
Test name
Test status
Simulation time 118733553417 ps
CPU time 14.05 seconds
Started Aug 23 04:09:06 AM UTC 24
Finished Aug 23 04:09:21 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948593290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3948593290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/159.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_alert_test.2382657243
Short name T476
Test name
Test status
Simulation time 42105612 ps
CPU time 0.46 seconds
Started Aug 23 03:35:09 AM UTC 24
Finished Aug 23 03:35:10 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382657243 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2382657243
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_fifo_full.526420392
Short name T327
Test name
Test status
Simulation time 263014770000 ps
CPU time 151.04 seconds
Started Aug 23 03:34:15 AM UTC 24
Finished Aug 23 03:36:49 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526420392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.526420392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.3128058254
Short name T477
Test name
Test status
Simulation time 28452321346 ps
CPU time 45.15 seconds
Started Aug 23 03:34:25 AM UTC 24
Finished Aug 23 03:35:12 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128058254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3128058254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_fifo_reset.2189590323
Short name T131
Test name
Test status
Simulation time 139119221740 ps
CPU time 80.89 seconds
Started Aug 23 03:34:33 AM UTC 24
Finished Aug 23 03:35:56 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189590323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2189590323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_intr.2603070353
Short name T102
Test name
Test status
Simulation time 22176104886 ps
CPU time 19.01 seconds
Started Aug 23 03:34:45 AM UTC 24
Finished Aug 23 03:35:06 AM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603070353 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2603070353
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.3330189794
Short name T506
Test name
Test status
Simulation time 248254714853 ps
CPU time 221.07 seconds
Started Aug 23 03:34:58 AM UTC 24
Finished Aug 23 03:38:42 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330189794 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3330189794
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_loopback.3950913970
Short name T475
Test name
Test status
Simulation time 5587911577 ps
CPU time 10.68 seconds
Started Aug 23 03:34:57 AM UTC 24
Finished Aug 23 03:35:08 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950913970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3950913970
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_noise_filter.274063820
Short name T341
Test name
Test status
Simulation time 132029048726 ps
CPU time 142.44 seconds
Started Aug 23 03:34:46 AM UTC 24
Finished Aug 23 03:37:11 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274063820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.274063820
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_perf.4155891388
Short name T535
Test name
Test status
Simulation time 12970574094 ps
CPU time 325.77 seconds
Started Aug 23 03:34:57 AM UTC 24
Finished Aug 23 03:40:26 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155891388 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.4155891388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_rx_oversample.2664521583
Short name T474
Test name
Test status
Simulation time 3055751901 ps
CPU time 24.22 seconds
Started Aug 23 03:34:35 AM UTC 24
Finished Aug 23 03:35:01 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664521583 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2664521583
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.679180169
Short name T371
Test name
Test status
Simulation time 19533900014 ps
CPU time 32.98 seconds
Started Aug 23 03:34:53 AM UTC 24
Finished Aug 23 03:35:27 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679180169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.679180169
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.1144567431
Short name T472
Test name
Test status
Simulation time 2837772179 ps
CPU time 4.7 seconds
Started Aug 23 03:34:47 AM UTC 24
Finished Aug 23 03:34:52 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144567431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1144567431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_smoke.2401873285
Short name T345
Test name
Test status
Simulation time 885830020 ps
CPU time 2.39 seconds
Started Aug 23 03:34:11 AM UTC 24
Finished Aug 23 03:34:15 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401873285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2401873285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_stress_all.2606342372
Short name T106
Test name
Test status
Simulation time 35089199507 ps
CPU time 93.43 seconds
Started Aug 23 03:35:07 AM UTC 24
Finished Aug 23 03:36:43 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606342372 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2606342372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.449194819
Short name T88
Test name
Test status
Simulation time 9623461297 ps
CPU time 24.12 seconds
Started Aug 23 03:35:02 AM UTC 24
Finished Aug 23 03:35:27 AM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=449194819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all_
with_rand_reset.449194819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.1568109480
Short name T473
Test name
Test status
Simulation time 487031766 ps
CPU time 1.74 seconds
Started Aug 23 03:34:54 AM UTC 24
Finished Aug 23 03:34:56 AM UTC 24
Peak memory 206940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568109480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1568109480
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/16.uart_tx_rx.537414705
Short name T387
Test name
Test status
Simulation time 25290131271 ps
CPU time 39.33 seconds
Started Aug 23 03:34:12 AM UTC 24
Finished Aug 23 03:34:53 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537414705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.537414705
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/16.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/160.uart_fifo_reset.39439125
Short name T1055
Test name
Test status
Simulation time 29951485397 ps
CPU time 15.56 seconds
Started Aug 23 04:09:08 AM UTC 24
Finished Aug 23 04:09:25 AM UTC 24
Peak memory 208512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39439125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.39439125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/160.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/161.uart_fifo_reset.1830668620
Short name T1069
Test name
Test status
Simulation time 28884620585 ps
CPU time 56.86 seconds
Started Aug 23 04:09:10 AM UTC 24
Finished Aug 23 04:10:08 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830668620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1830668620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/161.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/162.uart_fifo_reset.3371200341
Short name T1062
Test name
Test status
Simulation time 110404480985 ps
CPU time 35.4 seconds
Started Aug 23 04:09:10 AM UTC 24
Finished Aug 23 04:09:46 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371200341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3371200341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/162.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/163.uart_fifo_reset.3055384033
Short name T1131
Test name
Test status
Simulation time 128474382817 ps
CPU time 247.44 seconds
Started Aug 23 04:09:12 AM UTC 24
Finished Aug 23 04:13:23 AM UTC 24
Peak memory 210352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055384033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3055384033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/163.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/164.uart_fifo_reset.4039394938
Short name T1064
Test name
Test status
Simulation time 89290423513 ps
CPU time 34.42 seconds
Started Aug 23 04:09:13 AM UTC 24
Finished Aug 23 04:09:49 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039394938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.4039394938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/164.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/165.uart_fifo_reset.3766240039
Short name T1080
Test name
Test status
Simulation time 252907754539 ps
CPU time 97.36 seconds
Started Aug 23 04:09:21 AM UTC 24
Finished Aug 23 04:11:00 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766240039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3766240039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/165.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/166.uart_fifo_reset.3476923087
Short name T1086
Test name
Test status
Simulation time 90757505547 ps
CPU time 128.56 seconds
Started Aug 23 04:09:21 AM UTC 24
Finished Aug 23 04:11:32 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476923087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3476923087
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/166.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/167.uart_fifo_reset.1840599123
Short name T1066
Test name
Test status
Simulation time 20775392222 ps
CPU time 30.33 seconds
Started Aug 23 04:09:22 AM UTC 24
Finished Aug 23 04:09:54 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840599123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1840599123
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/167.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/168.uart_fifo_reset.1968591538
Short name T1058
Test name
Test status
Simulation time 34708031702 ps
CPU time 14.65 seconds
Started Aug 23 04:09:26 AM UTC 24
Finished Aug 23 04:09:42 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968591538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1968591538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/168.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/169.uart_fifo_reset.486419636
Short name T1067
Test name
Test status
Simulation time 12639091429 ps
CPU time 21.84 seconds
Started Aug 23 04:09:32 AM UTC 24
Finished Aug 23 04:09:56 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486419636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.486419636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/169.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_alert_test.1539456365
Short name T486
Test name
Test status
Simulation time 38639754 ps
CPU time 0.46 seconds
Started Aug 23 03:36:26 AM UTC 24
Finished Aug 23 03:36:27 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539456365 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1539456365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_fifo_full.2661378259
Short name T504
Test name
Test status
Simulation time 139335993934 ps
CPU time 189.66 seconds
Started Aug 23 03:35:14 AM UTC 24
Finished Aug 23 03:38:26 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661378259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2661378259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.920371311
Short name T163
Test name
Test status
Simulation time 31894438148 ps
CPU time 15.3 seconds
Started Aug 23 03:35:28 AM UTC 24
Finished Aug 23 03:35:45 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920371311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.920371311
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_fifo_reset.1928559790
Short name T209
Test name
Test status
Simulation time 79010688767 ps
CPU time 33.99 seconds
Started Aug 23 03:35:28 AM UTC 24
Finished Aug 23 03:36:04 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928559790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1928559790
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_intr.473176440
Short name T489
Test name
Test status
Simulation time 61757340550 ps
CPU time 82.91 seconds
Started Aug 23 03:35:43 AM UTC 24
Finished Aug 23 03:37:08 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473176440 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.473176440
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.2203161139
Short name T563
Test name
Test status
Simulation time 58483094754 ps
CPU time 343.56 seconds
Started Aug 23 03:36:19 AM UTC 24
Finished Aug 23 03:42:06 AM UTC 24
Peak memory 212204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203161139 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2203161139
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_loopback.3492607314
Short name T485
Test name
Test status
Simulation time 9160936278 ps
CPU time 19.08 seconds
Started Aug 23 03:36:05 AM UTC 24
Finished Aug 23 03:36:25 AM UTC 24
Peak memory 207740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492607314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3492607314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_noise_filter.2013239237
Short name T481
Test name
Test status
Simulation time 6769845405 ps
CPU time 7.51 seconds
Started Aug 23 03:35:45 AM UTC 24
Finished Aug 23 03:35:54 AM UTC 24
Peak memory 207484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013239237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2013239237
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_perf.2463523084
Short name T383
Test name
Test status
Simulation time 15611976528 ps
CPU time 198.22 seconds
Started Aug 23 03:36:05 AM UTC 24
Finished Aug 23 03:39:26 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463523084 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2463523084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_rx_oversample.823098473
Short name T480
Test name
Test status
Simulation time 5296668926 ps
CPU time 9.69 seconds
Started Aug 23 03:35:31 AM UTC 24
Finished Aug 23 03:35:42 AM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823098473 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.823098473
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.2802718194
Short name T303
Test name
Test status
Simulation time 102884384910 ps
CPU time 109.41 seconds
Started Aug 23 03:35:56 AM UTC 24
Finished Aug 23 03:37:48 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802718194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2802718194
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.2091962149
Short name T482
Test name
Test status
Simulation time 4401141752 ps
CPU time 1.48 seconds
Started Aug 23 03:35:54 AM UTC 24
Finished Aug 23 03:35:57 AM UTC 24
Peak memory 204500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091962149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2091962149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_smoke.4251624812
Short name T478
Test name
Test status
Simulation time 110595958 ps
CPU time 0.63 seconds
Started Aug 23 03:35:11 AM UTC 24
Finished Aug 23 03:35:13 AM UTC 24
Peak memory 206492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251624812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4251624812
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.3576781472
Short name T393
Test name
Test status
Simulation time 4291479691 ps
CPU time 55.39 seconds
Started Aug 23 03:36:20 AM UTC 24
Finished Aug 23 03:37:17 AM UTC 24
Peak memory 217736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3576781472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all
_with_rand_reset.3576781472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.3504518994
Short name T290
Test name
Test status
Simulation time 7388746046 ps
CPU time 19.86 seconds
Started Aug 23 03:35:58 AM UTC 24
Finished Aug 23 03:36:19 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504518994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3504518994
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/17.uart_tx_rx.1657662543
Short name T479
Test name
Test status
Simulation time 49303887252 ps
CPU time 15.46 seconds
Started Aug 23 03:35:13 AM UTC 24
Finished Aug 23 03:35:30 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657662543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1657662543
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/17.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/170.uart_fifo_reset.2105041501
Short name T1103
Test name
Test status
Simulation time 108848832935 ps
CPU time 154.38 seconds
Started Aug 23 04:09:32 AM UTC 24
Finished Aug 23 04:12:09 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105041501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2105041501
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/170.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/171.uart_fifo_reset.4075942840
Short name T1076
Test name
Test status
Simulation time 48774602319 ps
CPU time 71.47 seconds
Started Aug 23 04:09:35 AM UTC 24
Finished Aug 23 04:10:48 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075942840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.4075942840
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/171.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/173.uart_fifo_reset.3935215248
Short name T1140
Test name
Test status
Simulation time 51348889313 ps
CPU time 238.85 seconds
Started Aug 23 04:09:46 AM UTC 24
Finished Aug 23 04:13:48 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935215248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3935215248
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/173.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/174.uart_fifo_reset.3401184408
Short name T197
Test name
Test status
Simulation time 42643733927 ps
CPU time 32.57 seconds
Started Aug 23 04:09:49 AM UTC 24
Finished Aug 23 04:10:22 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401184408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3401184408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/174.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/175.uart_fifo_reset.1441948935
Short name T1070
Test name
Test status
Simulation time 119835556005 ps
CPU time 25.23 seconds
Started Aug 23 04:09:49 AM UTC 24
Finished Aug 23 04:10:15 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441948935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1441948935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/175.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/176.uart_fifo_reset.530966503
Short name T1147
Test name
Test status
Simulation time 147480014567 ps
CPU time 262.36 seconds
Started Aug 23 04:09:49 AM UTC 24
Finished Aug 23 04:14:14 AM UTC 24
Peak memory 210376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530966503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.530966503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/176.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/177.uart_fifo_reset.2586698463
Short name T1091
Test name
Test status
Simulation time 151135670375 ps
CPU time 113.57 seconds
Started Aug 23 04:09:49 AM UTC 24
Finished Aug 23 04:11:44 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586698463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2586698463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/177.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/178.uart_fifo_reset.3841536595
Short name T1075
Test name
Test status
Simulation time 63113119428 ps
CPU time 52.07 seconds
Started Aug 23 04:09:50 AM UTC 24
Finished Aug 23 04:10:44 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841536595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3841536595
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/178.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/179.uart_fifo_reset.2199964810
Short name T1071
Test name
Test status
Simulation time 171942467474 ps
CPU time 21.62 seconds
Started Aug 23 04:09:54 AM UTC 24
Finished Aug 23 04:10:17 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199964810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2199964810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/179.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_alert_test.1006829591
Short name T492
Test name
Test status
Simulation time 12698415 ps
CPU time 0.51 seconds
Started Aug 23 03:37:27 AM UTC 24
Finished Aug 23 03:37:28 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006829591 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1006829591
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_fifo_full.2874624407
Short name T149
Test name
Test status
Simulation time 72410041201 ps
CPU time 11.89 seconds
Started Aug 23 03:36:43 AM UTC 24
Finished Aug 23 03:36:56 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874624407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2874624407
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_intr.1524037459
Short name T585
Test name
Test status
Simulation time 257165232510 ps
CPU time 380.14 seconds
Started Aug 23 03:36:57 AM UTC 24
Finished Aug 23 03:43:22 AM UTC 24
Peak memory 212272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524037459 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1524037459
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.3676845914
Short name T567
Test name
Test status
Simulation time 181095318529 ps
CPU time 299.02 seconds
Started Aug 23 03:37:18 AM UTC 24
Finished Aug 23 03:42:21 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676845914 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3676845914
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_loopback.1567514691
Short name T490
Test name
Test status
Simulation time 2897223953 ps
CPU time 1.88 seconds
Started Aug 23 03:37:12 AM UTC 24
Finished Aug 23 03:37:15 AM UTC 24
Peak memory 206444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567514691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1567514691
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_noise_filter.1463771432
Short name T495
Test name
Test status
Simulation time 19675711226 ps
CPU time 32.72 seconds
Started Aug 23 03:37:00 AM UTC 24
Finished Aug 23 03:37:35 AM UTC 24
Peak memory 208972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463771432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1463771432
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_perf.999347778
Short name T377
Test name
Test status
Simulation time 22254682242 ps
CPU time 117 seconds
Started Aug 23 03:37:16 AM UTC 24
Finished Aug 23 03:39:15 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999347778 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.999347778
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1111031892
Short name T488
Test name
Test status
Simulation time 6725609843 ps
CPU time 3.25 seconds
Started Aug 23 03:36:55 AM UTC 24
Finished Aug 23 03:37:00 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111031892 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1111031892
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.4087012974
Short name T355
Test name
Test status
Simulation time 14381705171 ps
CPU time 26.43 seconds
Started Aug 23 03:37:00 AM UTC 24
Finished Aug 23 03:37:28 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087012974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.4087012974
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.3007542321
Short name T376
Test name
Test status
Simulation time 38096635037 ps
CPU time 23.84 seconds
Started Aug 23 03:37:00 AM UTC 24
Finished Aug 23 03:37:26 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007542321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3007542321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_smoke.3780659882
Short name T487
Test name
Test status
Simulation time 470196859 ps
CPU time 2.1 seconds
Started Aug 23 03:36:28 AM UTC 24
Finished Aug 23 03:36:31 AM UTC 24
Peak memory 207476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780659882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3780659882
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_stress_all.2219539203
Short name T128
Test name
Test status
Simulation time 273233048970 ps
CPU time 95.52 seconds
Started Aug 23 03:37:27 AM UTC 24
Finished Aug 23 03:39:04 AM UTC 24
Peak memory 219620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219539203 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2219539203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.3023947186
Short name T493
Test name
Test status
Simulation time 1276160254 ps
CPU time 5.06 seconds
Started Aug 23 03:37:23 AM UTC 24
Finished Aug 23 03:37:29 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3023947186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all
_with_rand_reset.3023947186
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.3426797336
Short name T491
Test name
Test status
Simulation time 6230844017 ps
CPU time 12.19 seconds
Started Aug 23 03:37:08 AM UTC 24
Finished Aug 23 03:37:22 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426797336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3426797336
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/18.uart_tx_rx.2877015932
Short name T385
Test name
Test status
Simulation time 60366078061 ps
CPU time 20.96 seconds
Started Aug 23 03:36:32 AM UTC 24
Finished Aug 23 03:36:54 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877015932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2877015932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/18.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/180.uart_fifo_reset.1940919985
Short name T1072
Test name
Test status
Simulation time 16051942937 ps
CPU time 23.36 seconds
Started Aug 23 04:09:56 AM UTC 24
Finished Aug 23 04:10:21 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940919985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1940919985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/180.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/182.uart_fifo_reset.950606759
Short name T1102
Test name
Test status
Simulation time 103754709819 ps
CPU time 130.07 seconds
Started Aug 23 04:09:56 AM UTC 24
Finished Aug 23 04:12:09 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950606759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.950606759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/182.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/184.uart_fifo_reset.645635644
Short name T198
Test name
Test status
Simulation time 93611933226 ps
CPU time 73.88 seconds
Started Aug 23 04:10:01 AM UTC 24
Finished Aug 23 04:11:17 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645635644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.645635644
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/184.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/185.uart_fifo_reset.3960708801
Short name T1090
Test name
Test status
Simulation time 53656738026 ps
CPU time 91.69 seconds
Started Aug 23 04:10:05 AM UTC 24
Finished Aug 23 04:11:39 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960708801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3960708801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/185.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/186.uart_fifo_reset.2148392679
Short name T1074
Test name
Test status
Simulation time 36622315947 ps
CPU time 27.2 seconds
Started Aug 23 04:10:10 AM UTC 24
Finished Aug 23 04:10:38 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148392679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2148392679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/186.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/187.uart_fifo_reset.2866939263
Short name T205
Test name
Test status
Simulation time 16482987442 ps
CPU time 22.04 seconds
Started Aug 23 04:10:16 AM UTC 24
Finished Aug 23 04:10:39 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866939263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2866939263
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/187.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/189.uart_fifo_reset.1154250242
Short name T1082
Test name
Test status
Simulation time 122445623949 ps
CPU time 47.75 seconds
Started Aug 23 04:10:22 AM UTC 24
Finished Aug 23 04:11:11 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154250242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1154250242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/189.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_alert_test.4115134646
Short name T502
Test name
Test status
Simulation time 14434229 ps
CPU time 0.46 seconds
Started Aug 23 03:38:07 AM UTC 24
Finished Aug 23 03:38:08 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115134646 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.4115134646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_fifo_full.4066481573
Short name T139
Test name
Test status
Simulation time 64668470220 ps
CPU time 55.65 seconds
Started Aug 23 03:37:29 AM UTC 24
Finished Aug 23 03:38:26 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066481573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4066481573
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.3923565514
Short name T416
Test name
Test status
Simulation time 24747782388 ps
CPU time 34.06 seconds
Started Aug 23 03:37:30 AM UTC 24
Finished Aug 23 03:38:05 AM UTC 24
Peak memory 208408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923565514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3923565514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_intr.4177101068
Short name T513
Test name
Test status
Simulation time 144649964286 ps
CPU time 80.69 seconds
Started Aug 23 03:37:40 AM UTC 24
Finished Aug 23 03:39:02 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177101068 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4177101068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.909249956
Short name T546
Test name
Test status
Simulation time 40274911267 ps
CPU time 199.9 seconds
Started Aug 23 03:37:52 AM UTC 24
Finished Aug 23 03:41:15 AM UTC 24
Peak memory 208976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909249956 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.909249956
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_loopback.3258336839
Short name T499
Test name
Test status
Simulation time 1548272275 ps
CPU time 1.79 seconds
Started Aug 23 03:37:48 AM UTC 24
Finished Aug 23 03:37:51 AM UTC 24
Peak memory 207932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258336839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3258336839
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_noise_filter.502750620
Short name T422
Test name
Test status
Simulation time 509922516720 ps
CPU time 57.34 seconds
Started Aug 23 03:37:40 AM UTC 24
Finished Aug 23 03:38:39 AM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502750620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.502750620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_perf.1961672134
Short name T575
Test name
Test status
Simulation time 5698676764 ps
CPU time 309.75 seconds
Started Aug 23 03:37:51 AM UTC 24
Finished Aug 23 03:43:05 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961672134 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1961672134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_rx_oversample.486809669
Short name T505
Test name
Test status
Simulation time 7575057047 ps
CPU time 58.67 seconds
Started Aug 23 03:37:35 AM UTC 24
Finished Aug 23 03:38:35 AM UTC 24
Peak memory 207944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486809669 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.486809669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.3671489858
Short name T514
Test name
Test status
Simulation time 62574528693 ps
CPU time 74.81 seconds
Started Aug 23 03:37:47 AM UTC 24
Finished Aug 23 03:39:04 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671489858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3671489858
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.1430089297
Short name T497
Test name
Test status
Simulation time 1871547838 ps
CPU time 2.46 seconds
Started Aug 23 03:37:43 AM UTC 24
Finished Aug 23 03:37:47 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430089297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1430089297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_smoke.2923814106
Short name T494
Test name
Test status
Simulation time 502521781 ps
CPU time 0.89 seconds
Started Aug 23 03:37:28 AM UTC 24
Finished Aug 23 03:37:30 AM UTC 24
Peak memory 206380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923814106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2923814106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_stress_all.1849772788
Short name T425
Test name
Test status
Simulation time 67721526907 ps
CPU time 32.35 seconds
Started Aug 23 03:38:01 AM UTC 24
Finished Aug 23 03:38:34 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849772788 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1849772788
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.3700545051
Short name T105
Test name
Test status
Simulation time 11771382734 ps
CPU time 58 seconds
Started Aug 23 03:37:56 AM UTC 24
Finished Aug 23 03:38:55 AM UTC 24
Peak memory 221960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3700545051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all
_with_rand_reset.3700545051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.3827533707
Short name T500
Test name
Test status
Simulation time 806095676 ps
CPU time 2.53 seconds
Started Aug 23 03:37:48 AM UTC 24
Finished Aug 23 03:37:52 AM UTC 24
Peak memory 208364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827533707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3827533707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/19.uart_tx_rx.1074629884
Short name T498
Test name
Test status
Simulation time 10516229288 ps
CPU time 17.45 seconds
Started Aug 23 03:37:29 AM UTC 24
Finished Aug 23 03:37:48 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074629884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1074629884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/19.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/190.uart_fifo_reset.3008844346
Short name T1089
Test name
Test status
Simulation time 122340590672 ps
CPU time 73.09 seconds
Started Aug 23 04:10:23 AM UTC 24
Finished Aug 23 04:11:38 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008844346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3008844346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/190.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/191.uart_fifo_reset.528104710
Short name T1087
Test name
Test status
Simulation time 54313874653 ps
CPU time 70.28 seconds
Started Aug 23 04:10:23 AM UTC 24
Finished Aug 23 04:11:35 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528104710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.528104710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/191.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/192.uart_fifo_reset.9887256
Short name T1100
Test name
Test status
Simulation time 180206270191 ps
CPU time 91.65 seconds
Started Aug 23 04:10:30 AM UTC 24
Finished Aug 23 04:12:04 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9887256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.9887256
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/192.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3940788706
Short name T1079
Test name
Test status
Simulation time 27718669972 ps
CPU time 17.93 seconds
Started Aug 23 04:10:36 AM UTC 24
Finished Aug 23 04:10:55 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940788706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3940788706
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/193.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/194.uart_fifo_reset.2471242155
Short name T1081
Test name
Test status
Simulation time 50679072083 ps
CPU time 27.29 seconds
Started Aug 23 04:10:36 AM UTC 24
Finished Aug 23 04:11:05 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471242155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2471242155
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/194.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/195.uart_fifo_reset.1261215558
Short name T1078
Test name
Test status
Simulation time 169945564850 ps
CPU time 14.06 seconds
Started Aug 23 04:10:39 AM UTC 24
Finished Aug 23 04:10:55 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261215558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1261215558
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/195.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/196.uart_fifo_reset.2009254613
Short name T1098
Test name
Test status
Simulation time 216845711089 ps
CPU time 79.06 seconds
Started Aug 23 04:10:41 AM UTC 24
Finished Aug 23 04:12:01 AM UTC 24
Peak memory 208420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009254613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2009254613
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/196.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/197.uart_fifo_reset.2869271953
Short name T200
Test name
Test status
Simulation time 15945795562 ps
CPU time 25.76 seconds
Started Aug 23 04:10:44 AM UTC 24
Finished Aug 23 04:11:11 AM UTC 24
Peak memory 208516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869271953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2869271953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/197.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/198.uart_fifo_reset.1069831272
Short name T220
Test name
Test status
Simulation time 101209063054 ps
CPU time 148.29 seconds
Started Aug 23 04:10:48 AM UTC 24
Finished Aug 23 04:13:19 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069831272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1069831272
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/198.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/199.uart_fifo_reset.3575397104
Short name T1083
Test name
Test status
Simulation time 69732514790 ps
CPU time 21.12 seconds
Started Aug 23 04:10:54 AM UTC 24
Finished Aug 23 04:11:16 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575397104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3575397104
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/199.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_alert_test.1313230979
Short name T31
Test name
Test status
Simulation time 49141676 ps
CPU time 0.48 seconds
Started Aug 23 03:23:55 AM UTC 24
Finished Aug 23 03:23:56 AM UTC 24
Peak memory 204504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313230979 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1313230979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_fifo_full.2018371882
Short name T95
Test name
Test status
Simulation time 47084227397 ps
CPU time 16.32 seconds
Started Aug 23 03:23:33 AM UTC 24
Finished Aug 23 03:23:50 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018371882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2018371882
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.1460106547
Short name T41
Test name
Test status
Simulation time 19444322749 ps
CPU time 11.47 seconds
Started Aug 23 03:23:34 AM UTC 24
Finished Aug 23 03:23:47 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460106547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1460106547
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_fifo_reset.3824531585
Short name T113
Test name
Test status
Simulation time 120512843096 ps
CPU time 31.49 seconds
Started Aug 23 03:23:34 AM UTC 24
Finished Aug 23 03:24:07 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824531585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3824531585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_intr.1478437886
Short name T19
Test name
Test status
Simulation time 16377539068 ps
CPU time 7.07 seconds
Started Aug 23 03:23:41 AM UTC 24
Finished Aug 23 03:23:49 AM UTC 24
Peak memory 207572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478437886 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1478437886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.4290987600
Short name T483
Test name
Test status
Simulation time 138110413009 ps
CPU time 738.73 seconds
Started Aug 23 03:23:51 AM UTC 24
Finished Aug 23 03:36:18 AM UTC 24
Peak memory 212340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290987600 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4290987600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_loopback.957078417
Short name T25
Test name
Test status
Simulation time 6626058113 ps
CPU time 12.36 seconds
Started Aug 23 03:23:47 AM UTC 24
Finished Aug 23 03:24:01 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957078417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.uart_loopback.957078417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_noise_filter.4214044356
Short name T266
Test name
Test status
Simulation time 196649214396 ps
CPU time 41.17 seconds
Started Aug 23 03:23:43 AM UTC 24
Finished Aug 23 03:24:26 AM UTC 24
Peak memory 208844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214044356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.4214044356
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_perf.2165670648
Short name T275
Test name
Test status
Simulation time 12205746119 ps
CPU time 130.04 seconds
Started Aug 23 03:23:49 AM UTC 24
Finished Aug 23 03:26:02 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165670648 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2165670648
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_rx_oversample.3262792330
Short name T21
Test name
Test status
Simulation time 2653452107 ps
CPU time 4.33 seconds
Started Aug 23 03:23:35 AM UTC 24
Finished Aug 23 03:23:40 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262792330 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3262792330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.2917166585
Short name T338
Test name
Test status
Simulation time 5604025017 ps
CPU time 7.67 seconds
Started Aug 23 03:23:43 AM UTC 24
Finished Aug 23 03:23:52 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917166585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2917166585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_sec_cm.2689831830
Short name T32
Test name
Test status
Simulation time 68757733 ps
CPU time 0.74 seconds
Started Aug 23 03:23:53 AM UTC 24
Finished Aug 23 03:23:55 AM UTC 24
Peak memory 240132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689831830 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2689831830
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_smoke.2564681583
Short name T40
Test name
Test status
Simulation time 264657979 ps
CPU time 1.46 seconds
Started Aug 23 03:23:32 AM UTC 24
Finished Aug 23 03:23:34 AM UTC 24
Peak memory 206244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564681583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2564681583
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_stress_all.3442464957
Short name T109
Test name
Test status
Simulation time 31008277591 ps
CPU time 16.15 seconds
Started Aug 23 03:23:52 AM UTC 24
Finished Aug 23 03:24:09 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442464957 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3442464957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1712598177
Short name T27
Test name
Test status
Simulation time 2158559664 ps
CPU time 12.17 seconds
Started Aug 23 03:23:51 AM UTC 24
Finished Aug 23 03:24:04 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1712598177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_
with_rand_reset.1712598177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.3087395923
Short name T42
Test name
Test status
Simulation time 14499799683 ps
CPU time 13.88 seconds
Started Aug 23 03:23:44 AM UTC 24
Finished Aug 23 03:23:59 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087395923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3087395923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/2.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_alert_test.3802112763
Short name T515
Test name
Test status
Simulation time 39408702 ps
CPU time 0.46 seconds
Started Aug 23 03:39:04 AM UTC 24
Finished Aug 23 03:39:05 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802112763 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3802112763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_fifo_full.402623117
Short name T512
Test name
Test status
Simulation time 39418154779 ps
CPU time 30.11 seconds
Started Aug 23 03:38:27 AM UTC 24
Finished Aug 23 03:38:58 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402623117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.402623117
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.3596815812
Short name T543
Test name
Test status
Simulation time 72522274942 ps
CPU time 162.6 seconds
Started Aug 23 03:38:27 AM UTC 24
Finished Aug 23 03:41:12 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596815812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3596815812
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_fifo_reset.531192506
Short name T145
Test name
Test status
Simulation time 37609235267 ps
CPU time 28.62 seconds
Started Aug 23 03:38:35 AM UTC 24
Finished Aug 23 03:39:05 AM UTC 24
Peak memory 208380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531192506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.531192506
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_intr.2954656595
Short name T413
Test name
Test status
Simulation time 64214626981 ps
CPU time 84.22 seconds
Started Aug 23 03:38:40 AM UTC 24
Finished Aug 23 03:40:06 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954656595 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2954656595
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.2337051720
Short name T573
Test name
Test status
Simulation time 105752159192 ps
CPU time 220.19 seconds
Started Aug 23 03:38:55 AM UTC 24
Finished Aug 23 03:42:39 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337051720 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2337051720
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_loopback.3640856917
Short name T510
Test name
Test status
Simulation time 2528921233 ps
CPU time 1.2 seconds
Started Aug 23 03:38:52 AM UTC 24
Finished Aug 23 03:38:55 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640856917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3640856917
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_noise_filter.1023557119
Short name T516
Test name
Test status
Simulation time 52744847040 ps
CPU time 21.87 seconds
Started Aug 23 03:38:42 AM UTC 24
Finished Aug 23 03:39:05 AM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023557119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1023557119
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_perf.1284405668
Short name T421
Test name
Test status
Simulation time 37575838855 ps
CPU time 116.8 seconds
Started Aug 23 03:38:55 AM UTC 24
Finished Aug 23 03:40:54 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284405668 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1284405668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_rx_oversample.1909581749
Short name T508
Test name
Test status
Simulation time 3385018265 ps
CPU time 10.27 seconds
Started Aug 23 03:38:36 AM UTC 24
Finished Aug 23 03:38:47 AM UTC 24
Peak memory 207868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909581749 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1909581749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.887984144
Short name T164
Test name
Test status
Simulation time 69584599777 ps
CPU time 25.33 seconds
Started Aug 23 03:38:48 AM UTC 24
Finished Aug 23 03:39:15 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887984144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.887984144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.112210908
Short name T509
Test name
Test status
Simulation time 3273388334 ps
CPU time 3.1 seconds
Started Aug 23 03:38:46 AM UTC 24
Finished Aug 23 03:38:51 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112210908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.112210908
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_smoke.1418311779
Short name T503
Test name
Test status
Simulation time 312969456 ps
CPU time 1.28 seconds
Started Aug 23 03:38:09 AM UTC 24
Finished Aug 23 03:38:11 AM UTC 24
Peak memory 207880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418311779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1418311779
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_stress_all.1073254238
Short name T408
Test name
Test status
Simulation time 275485642761 ps
CPU time 822.56 seconds
Started Aug 23 03:38:58 AM UTC 24
Finished Aug 23 03:52:50 AM UTC 24
Peak memory 212208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073254238 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1073254238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.3264077355
Short name T392
Test name
Test status
Simulation time 3919961115 ps
CPU time 40.04 seconds
Started Aug 23 03:38:57 AM UTC 24
Finished Aug 23 03:39:39 AM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3264077355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all
_with_rand_reset.3264077355
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.3002849002
Short name T378
Test name
Test status
Simulation time 6619166036 ps
CPU time 12.38 seconds
Started Aug 23 03:38:51 AM UTC 24
Finished Aug 23 03:39:05 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002849002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3002849002
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/20.uart_tx_rx.3965342792
Short name T507
Test name
Test status
Simulation time 23842550428 ps
CPU time 31.94 seconds
Started Aug 23 03:38:12 AM UTC 24
Finished Aug 23 03:38:45 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965342792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3965342792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/20.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/200.uart_fifo_reset.2709742033
Short name T1094
Test name
Test status
Simulation time 80419236895 ps
CPU time 55.96 seconds
Started Aug 23 04:10:56 AM UTC 24
Finished Aug 23 04:11:54 AM UTC 24
Peak memory 208860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709742033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2709742033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/200.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/201.uart_fifo_reset.1253346382
Short name T223
Test name
Test status
Simulation time 18687415862 ps
CPU time 31.96 seconds
Started Aug 23 04:10:56 AM UTC 24
Finished Aug 23 04:11:29 AM UTC 24
Peak memory 208860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253346382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1253346382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/201.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/202.uart_fifo_reset.722717051
Short name T1097
Test name
Test status
Simulation time 64040406254 ps
CPU time 56.2 seconds
Started Aug 23 04:11:02 AM UTC 24
Finished Aug 23 04:11:59 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722717051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.722717051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/202.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/203.uart_fifo_reset.1321384784
Short name T1085
Test name
Test status
Simulation time 56636875665 ps
CPU time 18.61 seconds
Started Aug 23 04:11:06 AM UTC 24
Finished Aug 23 04:11:26 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321384784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1321384784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/203.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2587846422
Short name T1092
Test name
Test status
Simulation time 81853658298 ps
CPU time 39.9 seconds
Started Aug 23 04:11:09 AM UTC 24
Finished Aug 23 04:11:50 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587846422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2587846422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/204.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/205.uart_fifo_reset.302080411
Short name T1106
Test name
Test status
Simulation time 40127563003 ps
CPU time 75.66 seconds
Started Aug 23 04:11:12 AM UTC 24
Finished Aug 23 04:12:29 AM UTC 24
Peak memory 208336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302080411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.302080411
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/205.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/206.uart_fifo_reset.3156869079
Short name T1110
Test name
Test status
Simulation time 135232283259 ps
CPU time 86.38 seconds
Started Aug 23 04:11:12 AM UTC 24
Finished Aug 23 04:12:40 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156869079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3156869079
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/206.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2444254164
Short name T1180
Test name
Test status
Simulation time 203285946357 ps
CPU time 301.73 seconds
Started Aug 23 04:11:18 AM UTC 24
Finished Aug 23 04:16:23 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444254164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2444254164
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/207.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/208.uart_fifo_reset.1615785057
Short name T1099
Test name
Test status
Simulation time 24820173150 ps
CPU time 42.72 seconds
Started Aug 23 04:11:18 AM UTC 24
Finished Aug 23 04:12:02 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615785057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1615785057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/208.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/209.uart_fifo_reset.273345484
Short name T1133
Test name
Test status
Simulation time 151383846233 ps
CPU time 126.38 seconds
Started Aug 23 04:11:19 AM UTC 24
Finished Aug 23 04:13:27 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273345484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.273345484
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/209.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_alert_test.2805176792
Short name T524
Test name
Test status
Simulation time 13113939 ps
CPU time 0.48 seconds
Started Aug 23 03:39:26 AM UTC 24
Finished Aug 23 03:39:28 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805176792 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2805176792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_fifo_full.3504821923
Short name T528
Test name
Test status
Simulation time 42655248600 ps
CPU time 56.15 seconds
Started Aug 23 03:39:06 AM UTC 24
Finished Aug 23 03:40:04 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504821923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3504821923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.664725718
Short name T372
Test name
Test status
Simulation time 131296252324 ps
CPU time 134.47 seconds
Started Aug 23 03:39:06 AM UTC 24
Finished Aug 23 03:41:23 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664725718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.664725718
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_intr.1074772303
Short name T647
Test name
Test status
Simulation time 325973841066 ps
CPU time 530.79 seconds
Started Aug 23 03:39:10 AM UTC 24
Finished Aug 23 03:48:06 AM UTC 24
Peak memory 212116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074772303 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1074772303
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.3609438576
Short name T589
Test name
Test status
Simulation time 89411570686 ps
CPU time 260.33 seconds
Started Aug 23 03:39:20 AM UTC 24
Finished Aug 23 03:43:44 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609438576 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3609438576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_loopback.820815634
Short name T522
Test name
Test status
Simulation time 3146462657 ps
CPU time 3.75 seconds
Started Aug 23 03:39:18 AM UTC 24
Finished Aug 23 03:39:23 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820815634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.uart_loopback.820815634
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_perf.4195751731
Short name T551
Test name
Test status
Simulation time 11446567355 ps
CPU time 136.33 seconds
Started Aug 23 03:39:19 AM UTC 24
Finished Aug 23 03:41:38 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195751731 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.4195751731
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_rx_oversample.1302242708
Short name T517
Test name
Test status
Simulation time 1899859397 ps
CPU time 1.64 seconds
Started Aug 23 03:39:06 AM UTC 24
Finished Aug 23 03:39:09 AM UTC 24
Peak memory 206432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302242708 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1302242708
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.3638624820
Short name T526
Test name
Test status
Simulation time 15004983187 ps
CPU time 15.85 seconds
Started Aug 23 03:39:16 AM UTC 24
Finished Aug 23 03:39:33 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638624820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3638624820
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.3355027705
Short name T519
Test name
Test status
Simulation time 3940782513 ps
CPU time 1.48 seconds
Started Aug 23 03:39:16 AM UTC 24
Finished Aug 23 03:39:18 AM UTC 24
Peak memory 204500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355027705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3355027705
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_smoke.4014819985
Short name T330
Test name
Test status
Simulation time 6171644964 ps
CPU time 11.06 seconds
Started Aug 23 03:39:05 AM UTC 24
Finished Aug 23 03:39:17 AM UTC 24
Peak memory 208400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014819985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.4014819985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_stress_all.3588980384
Short name T639
Test name
Test status
Simulation time 206096795325 ps
CPU time 476.94 seconds
Started Aug 23 03:39:23 AM UTC 24
Finished Aug 23 03:47:26 AM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588980384 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3588980384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.2404679025
Short name T520
Test name
Test status
Simulation time 2065509628 ps
CPU time 1.52 seconds
Started Aug 23 03:39:17 AM UTC 24
Finished Aug 23 03:39:19 AM UTC 24
Peak memory 206428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404679025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2404679025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/21.uart_tx_rx.3611584105
Short name T518
Test name
Test status
Simulation time 23533509055 ps
CPU time 8.53 seconds
Started Aug 23 03:39:05 AM UTC 24
Finished Aug 23 03:39:14 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611584105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3611584105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/21.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/211.uart_fifo_reset.1066003174
Short name T1151
Test name
Test status
Simulation time 86334318412 ps
CPU time 165.26 seconds
Started Aug 23 04:11:31 AM UTC 24
Finished Aug 23 04:14:19 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066003174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1066003174
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/211.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/212.uart_fifo_reset.914488352
Short name T225
Test name
Test status
Simulation time 86457026284 ps
CPU time 133.88 seconds
Started Aug 23 04:11:33 AM UTC 24
Finished Aug 23 04:13:49 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914488352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.914488352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/212.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/213.uart_fifo_reset.2716978779
Short name T1107
Test name
Test status
Simulation time 86491640265 ps
CPU time 55.98 seconds
Started Aug 23 04:11:36 AM UTC 24
Finished Aug 23 04:12:34 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716978779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2716978779
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/213.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/214.uart_fifo_reset.3840035092
Short name T1095
Test name
Test status
Simulation time 16613135599 ps
CPU time 15.38 seconds
Started Aug 23 04:11:37 AM UTC 24
Finished Aug 23 04:11:54 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840035092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3840035092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/214.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/216.uart_fifo_reset.958050490
Short name T1111
Test name
Test status
Simulation time 44800880186 ps
CPU time 59.05 seconds
Started Aug 23 04:11:40 AM UTC 24
Finished Aug 23 04:12:41 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958050490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.958050490
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/216.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/217.uart_fifo_reset.4073935105
Short name T1108
Test name
Test status
Simulation time 137269951019 ps
CPU time 49.15 seconds
Started Aug 23 04:11:43 AM UTC 24
Finished Aug 23 04:12:34 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073935105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.4073935105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/217.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1110872708
Short name T1101
Test name
Test status
Simulation time 29989784551 ps
CPU time 21.22 seconds
Started Aug 23 04:11:46 AM UTC 24
Finished Aug 23 04:12:08 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110872708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1110872708
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/218.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2477708262
Short name T253
Test name
Test status
Simulation time 64252073965 ps
CPU time 20.54 seconds
Started Aug 23 04:11:51 AM UTC 24
Finished Aug 23 04:12:13 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477708262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2477708262
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/219.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_alert_test.4278603412
Short name T534
Test name
Test status
Simulation time 61817759 ps
CPU time 0.47 seconds
Started Aug 23 03:40:23 AM UTC 24
Finished Aug 23 03:40:25 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278603412 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4278603412
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_fifo_full.1339678700
Short name T321
Test name
Test status
Simulation time 77813259205 ps
CPU time 60.64 seconds
Started Aug 23 03:39:30 AM UTC 24
Finished Aug 23 03:40:33 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339678700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1339678700
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.4127228456
Short name T536
Test name
Test status
Simulation time 42466352347 ps
CPU time 57.65 seconds
Started Aug 23 03:39:32 AM UTC 24
Finished Aug 23 03:40:31 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127228456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4127228456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_fifo_reset.1271769990
Short name T226
Test name
Test status
Simulation time 57509632939 ps
CPU time 79.99 seconds
Started Aug 23 03:39:34 AM UTC 24
Finished Aug 23 03:40:55 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271769990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1271769990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_intr.786874782
Short name T530
Test name
Test status
Simulation time 27114997516 ps
CPU time 9.27 seconds
Started Aug 23 03:39:56 AM UTC 24
Finished Aug 23 03:40:06 AM UTC 24
Peak memory 208492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786874782 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.786874782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.1581394821
Short name T602
Test name
Test status
Simulation time 97312332165 ps
CPU time 271.91 seconds
Started Aug 23 03:40:13 AM UTC 24
Finished Aug 23 03:44:48 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581394821 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1581394821
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_loopback.3676112095
Short name T533
Test name
Test status
Simulation time 5158405139 ps
CPU time 3.27 seconds
Started Aug 23 03:40:10 AM UTC 24
Finished Aug 23 03:40:14 AM UTC 24
Peak memory 208508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676112095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3676112095
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_noise_filter.1599211987
Short name T382
Test name
Test status
Simulation time 208610056400 ps
CPU time 101.6 seconds
Started Aug 23 03:40:05 AM UTC 24
Finished Aug 23 03:41:48 AM UTC 24
Peak memory 208976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599211987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1599211987
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_perf.3909612562
Short name T820
Test name
Test status
Simulation time 20527008526 ps
CPU time 1019.74 seconds
Started Aug 23 03:40:13 AM UTC 24
Finished Aug 23 03:57:23 AM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909612562 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3909612562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_rx_oversample.26301021
Short name T527
Test name
Test status
Simulation time 4126470294 ps
CPU time 13.86 seconds
Started Aug 23 03:39:40 AM UTC 24
Finished Aug 23 03:39:55 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26301021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.26301021
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.4117141391
Short name T537
Test name
Test status
Simulation time 98093974334 ps
CPU time 28.09 seconds
Started Aug 23 03:40:07 AM UTC 24
Finished Aug 23 03:40:36 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117141391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.4117141391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.2815511601
Short name T532
Test name
Test status
Simulation time 3035206928 ps
CPU time 4.89 seconds
Started Aug 23 03:40:06 AM UTC 24
Finished Aug 23 03:40:12 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815511601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2815511601
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_smoke.266523657
Short name T525
Test name
Test status
Simulation time 286026476 ps
CPU time 0.84 seconds
Started Aug 23 03:39:27 AM UTC 24
Finished Aug 23 03:39:29 AM UTC 24
Peak memory 206448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266523657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.uart_smoke.266523657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_stress_all.1039023801
Short name T134
Test name
Test status
Simulation time 378534646878 ps
CPU time 82.79 seconds
Started Aug 23 03:40:21 AM UTC 24
Finished Aug 23 03:41:46 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039023801 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1039023801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.1575768949
Short name T400
Test name
Test status
Simulation time 9456048824 ps
CPU time 28.16 seconds
Started Aug 23 03:40:15 AM UTC 24
Finished Aug 23 03:40:45 AM UTC 24
Peak memory 224676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1575768949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all
_with_rand_reset.1575768949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.805196334
Short name T531
Test name
Test status
Simulation time 254364576 ps
CPU time 1.07 seconds
Started Aug 23 03:40:07 AM UTC 24
Finished Aug 23 03:40:09 AM UTC 24
Peak memory 206492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805196334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.805196334
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/22.uart_tx_rx.3513360763
Short name T324
Test name
Test status
Simulation time 49169788267 ps
CPU time 82.77 seconds
Started Aug 23 03:39:28 AM UTC 24
Finished Aug 23 03:40:53 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513360763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3513360763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/22.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/220.uart_fifo_reset.687058604
Short name T1109
Test name
Test status
Simulation time 61009404142 ps
CPU time 45.17 seconds
Started Aug 23 04:11:52 AM UTC 24
Finished Aug 23 04:12:39 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687058604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.687058604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/220.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/221.uart_fifo_reset.4109248979
Short name T1105
Test name
Test status
Simulation time 49319397956 ps
CPU time 27.81 seconds
Started Aug 23 04:11:55 AM UTC 24
Finished Aug 23 04:12:24 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109248979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.4109248979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/221.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/222.uart_fifo_reset.1775920009
Short name T1155
Test name
Test status
Simulation time 110440872692 ps
CPU time 148.31 seconds
Started Aug 23 04:11:55 AM UTC 24
Finished Aug 23 04:14:26 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775920009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1775920009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/222.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/223.uart_fifo_reset.63207474
Short name T1163
Test name
Test status
Simulation time 92346451761 ps
CPU time 170.03 seconds
Started Aug 23 04:12:01 AM UTC 24
Finished Aug 23 04:14:53 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63207474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.63207474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/223.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/224.uart_fifo_reset.1373215215
Short name T1120
Test name
Test status
Simulation time 104812019922 ps
CPU time 56.45 seconds
Started Aug 23 04:12:01 AM UTC 24
Finished Aug 23 04:12:59 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373215215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1373215215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/224.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/225.uart_fifo_reset.4049716217
Short name T1104
Test name
Test status
Simulation time 10487655601 ps
CPU time 14.36 seconds
Started Aug 23 04:12:02 AM UTC 24
Finished Aug 23 04:12:18 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049716217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.4049716217
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/225.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/226.uart_fifo_reset.3395074804
Short name T248
Test name
Test status
Simulation time 34026177996 ps
CPU time 25.02 seconds
Started Aug 23 04:12:02 AM UTC 24
Finished Aug 23 04:12:29 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395074804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3395074804
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/226.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/227.uart_fifo_reset.821770081
Short name T1128
Test name
Test status
Simulation time 36626735358 ps
CPU time 73.3 seconds
Started Aug 23 04:12:05 AM UTC 24
Finished Aug 23 04:13:20 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821770081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.821770081
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/227.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/228.uart_fifo_reset.2773220780
Short name T1157
Test name
Test status
Simulation time 94044587100 ps
CPU time 138.42 seconds
Started Aug 23 04:12:09 AM UTC 24
Finished Aug 23 04:14:30 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773220780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2773220780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/228.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/229.uart_fifo_reset.4183891208
Short name T1173
Test name
Test status
Simulation time 123473229269 ps
CPU time 193.75 seconds
Started Aug 23 04:12:09 AM UTC 24
Finished Aug 23 04:15:26 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183891208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.4183891208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/229.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_alert_test.1339278754
Short name T545
Test name
Test status
Simulation time 22149759 ps
CPU time 0.46 seconds
Started Aug 23 03:41:12 AM UTC 24
Finished Aug 23 03:41:14 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339278754 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1339278754
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_fifo_full.2967401902
Short name T281
Test name
Test status
Simulation time 191708240967 ps
CPU time 144.37 seconds
Started Aug 23 03:40:31 AM UTC 24
Finished Aug 23 03:42:58 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967401902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2967401902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.253579295
Short name T155
Test name
Test status
Simulation time 51938661051 ps
CPU time 10.35 seconds
Started Aug 23 03:40:33 AM UTC 24
Finished Aug 23 03:40:45 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253579295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.253579295
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_fifo_reset.3500254476
Short name T542
Test name
Test status
Simulation time 74525833158 ps
CPU time 24.9 seconds
Started Aug 23 03:40:36 AM UTC 24
Finished Aug 23 03:41:03 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500254476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3500254476
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_intr.1140984190
Short name T560
Test name
Test status
Simulation time 45466737475 ps
CPU time 73.52 seconds
Started Aug 23 03:40:44 AM UTC 24
Finished Aug 23 03:41:59 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140984190 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1140984190
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.1671862690
Short name T571
Test name
Test status
Simulation time 153208908312 ps
CPU time 91.82 seconds
Started Aug 23 03:40:56 AM UTC 24
Finished Aug 23 03:42:30 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671862690 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1671862690
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_loopback.2496451696
Short name T541
Test name
Test status
Simulation time 5740510541 ps
CPU time 3.33 seconds
Started Aug 23 03:40:54 AM UTC 24
Finished Aug 23 03:40:58 AM UTC 24
Peak memory 208396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496451696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2496451696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_noise_filter.960455814
Short name T562
Test name
Test status
Simulation time 90701833645 ps
CPU time 79.78 seconds
Started Aug 23 03:40:45 AM UTC 24
Finished Aug 23 03:42:06 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960455814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.960455814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_perf.1156763789
Short name T723
Test name
Test status
Simulation time 12297513165 ps
CPU time 657.18 seconds
Started Aug 23 03:40:55 AM UTC 24
Finished Aug 23 03:52:00 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156763789 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1156763789
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_rx_oversample.89035628
Short name T548
Test name
Test status
Simulation time 6918676746 ps
CPU time 45.64 seconds
Started Aug 23 03:40:41 AM UTC 24
Finished Aug 23 03:41:29 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89035628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.89035628
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.3109801975
Short name T151
Test name
Test status
Simulation time 40227088019 ps
CPU time 62.85 seconds
Started Aug 23 03:40:46 AM UTC 24
Finished Aug 23 03:41:50 AM UTC 24
Peak memory 208588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109801975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3109801975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.2870452999
Short name T540
Test name
Test status
Simulation time 3842410420 ps
CPU time 1.03 seconds
Started Aug 23 03:40:46 AM UTC 24
Finished Aug 23 03:40:48 AM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870452999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2870452999
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_smoke.2341464871
Short name T538
Test name
Test status
Simulation time 5387276119 ps
CPU time 16.46 seconds
Started Aug 23 03:40:25 AM UTC 24
Finished Aug 23 03:40:43 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341464871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2341464871
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.2664583305
Short name T401
Test name
Test status
Simulation time 4461198206 ps
CPU time 48.69 seconds
Started Aug 23 03:40:59 AM UTC 24
Finished Aug 23 03:41:49 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2664583305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all
_with_rand_reset.2664583305
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.3304705115
Short name T544
Test name
Test status
Simulation time 6569492080 ps
CPU time 23.64 seconds
Started Aug 23 03:40:49 AM UTC 24
Finished Aug 23 03:41:14 AM UTC 24
Peak memory 208480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304705115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3304705115
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/23.uart_tx_rx.3821636554
Short name T365
Test name
Test status
Simulation time 58655280786 ps
CPU time 63.4 seconds
Started Aug 23 03:40:27 AM UTC 24
Finished Aug 23 03:41:33 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821636554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3821636554
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/23.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/230.uart_fifo_reset.1012908888
Short name T1126
Test name
Test status
Simulation time 47104511438 ps
CPU time 61.08 seconds
Started Aug 23 04:12:11 AM UTC 24
Finished Aug 23 04:13:13 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012908888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1012908888
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/230.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/231.uart_fifo_reset.2083926651
Short name T217
Test name
Test status
Simulation time 46130208938 ps
CPU time 30.13 seconds
Started Aug 23 04:12:14 AM UTC 24
Finished Aug 23 04:12:46 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083926651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2083926651
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/231.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/232.uart_fifo_reset.2707218075
Short name T1115
Test name
Test status
Simulation time 17268076665 ps
CPU time 27.53 seconds
Started Aug 23 04:12:19 AM UTC 24
Finished Aug 23 04:12:48 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707218075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2707218075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/232.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/233.uart_fifo_reset.3407226152
Short name T1112
Test name
Test status
Simulation time 20784406272 ps
CPU time 18.34 seconds
Started Aug 23 04:12:26 AM UTC 24
Finished Aug 23 04:12:45 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407226152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3407226152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/233.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/234.uart_fifo_reset.2118313701
Short name T1114
Test name
Test status
Simulation time 16560216104 ps
CPU time 15.04 seconds
Started Aug 23 04:12:31 AM UTC 24
Finished Aug 23 04:12:47 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118313701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2118313701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/234.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/235.uart_fifo_reset.3117645664
Short name T1113
Test name
Test status
Simulation time 93992975901 ps
CPU time 14.04 seconds
Started Aug 23 04:12:31 AM UTC 24
Finished Aug 23 04:12:46 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117645664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3117645664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/235.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/236.uart_fifo_reset.440460340
Short name T1168
Test name
Test status
Simulation time 123173271739 ps
CPU time 153.63 seconds
Started Aug 23 04:12:31 AM UTC 24
Finished Aug 23 04:15:07 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440460340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.440460340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/236.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/237.uart_fifo_reset.764207583
Short name T1139
Test name
Test status
Simulation time 38534938281 ps
CPU time 63.68 seconds
Started Aug 23 04:12:35 AM UTC 24
Finished Aug 23 04:13:41 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764207583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.764207583
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/237.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/238.uart_fifo_reset.515737045
Short name T1116
Test name
Test status
Simulation time 32289147086 ps
CPU time 14.34 seconds
Started Aug 23 04:12:35 AM UTC 24
Finished Aug 23 04:12:51 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515737045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.515737045
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/238.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/239.uart_fifo_reset.860216243
Short name T1118
Test name
Test status
Simulation time 11788827017 ps
CPU time 17.19 seconds
Started Aug 23 04:12:40 AM UTC 24
Finished Aug 23 04:12:58 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860216243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.860216243
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/239.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_alert_test.1217494900
Short name T556
Test name
Test status
Simulation time 34869332 ps
CPU time 0.47 seconds
Started Aug 23 03:41:50 AM UTC 24
Finished Aug 23 03:41:51 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217494900 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1217494900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_fifo_full.3835439548
Short name T547
Test name
Test status
Simulation time 31429759934 ps
CPU time 11.98 seconds
Started Aug 23 03:41:16 AM UTC 24
Finished Aug 23 03:41:29 AM UTC 24
Peak memory 208124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835439548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3835439548
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.3392575198
Short name T148
Test name
Test status
Simulation time 212080036393 ps
CPU time 32.71 seconds
Started Aug 23 03:41:24 AM UTC 24
Finished Aug 23 03:41:58 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392575198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3392575198
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_fifo_reset.954523628
Short name T554
Test name
Test status
Simulation time 19485277760 ps
CPU time 13.84 seconds
Started Aug 23 03:41:30 AM UTC 24
Finished Aug 23 03:41:45 AM UTC 24
Peak memory 207880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954523628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.954523628
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_intr.170773864
Short name T552
Test name
Test status
Simulation time 31223150773 ps
CPU time 6.37 seconds
Started Aug 23 03:41:34 AM UTC 24
Finished Aug 23 03:41:41 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170773864 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.170773864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.2740708480
Short name T583
Test name
Test status
Simulation time 87766618484 ps
CPU time 91.23 seconds
Started Aug 23 03:41:47 AM UTC 24
Finished Aug 23 03:43:21 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740708480 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2740708480
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_loopback.3315984130
Short name T559
Test name
Test status
Simulation time 5686077766 ps
CPU time 12.28 seconds
Started Aug 23 03:41:42 AM UTC 24
Finished Aug 23 03:41:56 AM UTC 24
Peak memory 208592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315984130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3315984130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_noise_filter.3667133191
Short name T354
Test name
Test status
Simulation time 188743158958 ps
CPU time 45.14 seconds
Started Aug 23 03:41:34 AM UTC 24
Finished Aug 23 03:42:20 AM UTC 24
Peak memory 217664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667133191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3667133191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_perf.3117514597
Short name T592
Test name
Test status
Simulation time 18467513537 ps
CPU time 146.55 seconds
Started Aug 23 03:41:45 AM UTC 24
Finished Aug 23 03:44:14 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117514597 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3117514597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_rx_oversample.1553809843
Short name T550
Test name
Test status
Simulation time 4655479454 ps
CPU time 6.69 seconds
Started Aug 23 03:41:30 AM UTC 24
Finished Aug 23 03:41:38 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553809843 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1553809843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.3489457151
Short name T558
Test name
Test status
Simulation time 45073329195 ps
CPU time 15.29 seconds
Started Aug 23 03:41:38 AM UTC 24
Finished Aug 23 03:41:54 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489457151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3489457151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.4062459835
Short name T553
Test name
Test status
Simulation time 2934893127 ps
CPU time 2.72 seconds
Started Aug 23 03:41:38 AM UTC 24
Finished Aug 23 03:41:42 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062459835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.4062459835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_smoke.599933833
Short name T549
Test name
Test status
Simulation time 6077397078 ps
CPU time 17.42 seconds
Started Aug 23 03:41:14 AM UTC 24
Finished Aug 23 03:41:33 AM UTC 24
Peak memory 208348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599933833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.uart_smoke.599933833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_stress_all.2385440967
Short name T420
Test name
Test status
Simulation time 341922943907 ps
CPU time 304.62 seconds
Started Aug 23 03:41:49 AM UTC 24
Finished Aug 23 03:46:57 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385440967 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2385440967
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.3496660449
Short name T568
Test name
Test status
Simulation time 2646650564 ps
CPU time 32.64 seconds
Started Aug 23 03:41:48 AM UTC 24
Finished Aug 23 03:42:21 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3496660449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all
_with_rand_reset.3496660449
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.701036954
Short name T555
Test name
Test status
Simulation time 1228463173 ps
CPU time 3.56 seconds
Started Aug 23 03:41:42 AM UTC 24
Finished Aug 23 03:41:47 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701036954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.701036954
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/24.uart_tx_rx.3338131286
Short name T426
Test name
Test status
Simulation time 464703012503 ps
CPU time 50.84 seconds
Started Aug 23 03:41:14 AM UTC 24
Finished Aug 23 03:42:07 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338131286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3338131286
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/24.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/240.uart_fifo_reset.3396181606
Short name T1121
Test name
Test status
Simulation time 15262483276 ps
CPU time 19.34 seconds
Started Aug 23 04:12:41 AM UTC 24
Finished Aug 23 04:13:01 AM UTC 24
Peak memory 208564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396181606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3396181606
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/240.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/241.uart_fifo_reset.3618252762
Short name T1132
Test name
Test status
Simulation time 25031538998 ps
CPU time 39.62 seconds
Started Aug 23 04:12:42 AM UTC 24
Finished Aug 23 04:13:23 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618252762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3618252762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/241.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1587810740
Short name T1123
Test name
Test status
Simulation time 50904686317 ps
CPU time 18.21 seconds
Started Aug 23 04:12:47 AM UTC 24
Finished Aug 23 04:13:07 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587810740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1587810740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/243.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/244.uart_fifo_reset.1978893909
Short name T1119
Test name
Test status
Simulation time 8767342556 ps
CPU time 10.47 seconds
Started Aug 23 04:12:47 AM UTC 24
Finished Aug 23 04:12:59 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978893909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1978893909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/244.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3601870975
Short name T1124
Test name
Test status
Simulation time 50487249702 ps
CPU time 19.77 seconds
Started Aug 23 04:12:48 AM UTC 24
Finished Aug 23 04:13:09 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601870975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3601870975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/245.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/246.uart_fifo_reset.4182220571
Short name T1125
Test name
Test status
Simulation time 16662975379 ps
CPU time 22.28 seconds
Started Aug 23 04:12:50 AM UTC 24
Finished Aug 23 04:13:13 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182220571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.4182220571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/246.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/247.uart_fifo_reset.176723105
Short name T1127
Test name
Test status
Simulation time 20858613318 ps
CPU time 20.57 seconds
Started Aug 23 04:12:52 AM UTC 24
Finished Aug 23 04:13:14 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176723105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.176723105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/247.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/248.uart_fifo_reset.1139404514
Short name T1122
Test name
Test status
Simulation time 41826840716 ps
CPU time 8.89 seconds
Started Aug 23 04:12:53 AM UTC 24
Finished Aug 23 04:13:03 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139404514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1139404514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/248.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/249.uart_fifo_reset.2507677518
Short name T1183
Test name
Test status
Simulation time 160453141611 ps
CPU time 272.01 seconds
Started Aug 23 04:12:59 AM UTC 24
Finished Aug 23 04:17:34 AM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507677518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2507677518
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/249.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_alert_test.1757749367
Short name T569
Test name
Test status
Simulation time 13968015 ps
CPU time 0.47 seconds
Started Aug 23 03:42:22 AM UTC 24
Finished Aug 23 03:42:24 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757749367 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1757749367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_fifo_full.2876070781
Short name T790
Test name
Test status
Simulation time 284820356243 ps
CPU time 825.19 seconds
Started Aug 23 03:41:55 AM UTC 24
Finished Aug 23 03:55:49 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876070781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2876070781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.469268256
Short name T586
Test name
Test status
Simulation time 141437565338 ps
CPU time 91.94 seconds
Started Aug 23 03:41:55 AM UTC 24
Finished Aug 23 03:43:29 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469268256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.469268256
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_fifo_reset.60791018
Short name T578
Test name
Test status
Simulation time 55748523099 ps
CPU time 76.41 seconds
Started Aug 23 03:41:56 AM UTC 24
Finished Aug 23 03:43:14 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60791018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.60791018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.3105049416
Short name T620
Test name
Test status
Simulation time 68582372474 ps
CPU time 226.01 seconds
Started Aug 23 03:42:19 AM UTC 24
Finished Aug 23 03:46:08 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105049416 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3105049416
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_loopback.1280976510
Short name T570
Test name
Test status
Simulation time 6827036767 ps
CPU time 11.1 seconds
Started Aug 23 03:42:13 AM UTC 24
Finished Aug 23 03:42:25 AM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280976510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1280976510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_noise_filter.2289955824
Short name T417
Test name
Test status
Simulation time 131700106620 ps
CPU time 273.69 seconds
Started Aug 23 03:42:01 AM UTC 24
Finished Aug 23 03:46:39 AM UTC 24
Peak memory 208844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289955824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2289955824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_perf.350189807
Short name T285
Test name
Test status
Simulation time 10096381566 ps
CPU time 115.07 seconds
Started Aug 23 03:42:15 AM UTC 24
Finished Aug 23 03:44:12 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350189807 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.350189807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_rx_oversample.2292498427
Short name T561
Test name
Test status
Simulation time 1213032380 ps
CPU time 0.67 seconds
Started Aug 23 03:41:58 AM UTC 24
Finished Aug 23 03:42:00 AM UTC 24
Peak memory 204432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292498427 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2292498427
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.2451917129
Short name T564
Test name
Test status
Simulation time 7484330933 ps
CPU time 3.07 seconds
Started Aug 23 03:42:08 AM UTC 24
Finished Aug 23 03:42:12 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451917129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2451917129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.653264811
Short name T566
Test name
Test status
Simulation time 6223437782 ps
CPU time 9.03 seconds
Started Aug 23 03:42:08 AM UTC 24
Finished Aug 23 03:42:18 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653264811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.653264811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_smoke.3940797213
Short name T557
Test name
Test status
Simulation time 645837572 ps
CPU time 2.64 seconds
Started Aug 23 03:41:51 AM UTC 24
Finished Aug 23 03:41:54 AM UTC 24
Peak memory 207988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940797213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3940797213
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_stress_all.3260296545
Short name T590
Test name
Test status
Simulation time 66239616770 ps
CPU time 95.01 seconds
Started Aug 23 03:42:22 AM UTC 24
Finished Aug 23 03:43:59 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260296545 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3260296545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.3656467469
Short name T565
Test name
Test status
Simulation time 8908700040 ps
CPU time 4.94 seconds
Started Aug 23 03:42:08 AM UTC 24
Finished Aug 23 03:42:14 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656467469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3656467469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/25.uart_tx_rx.2487965422
Short name T280
Test name
Test status
Simulation time 28963519634 ps
CPU time 51.06 seconds
Started Aug 23 03:41:52 AM UTC 24
Finished Aug 23 03:42:44 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487965422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2487965422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1653995707
Short name T1142
Test name
Test status
Simulation time 29150288515 ps
CPU time 50.04 seconds
Started Aug 23 04:13:00 AM UTC 24
Finished Aug 23 04:13:52 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653995707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1653995707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/250.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/251.uart_fifo_reset.578572025
Short name T1150
Test name
Test status
Simulation time 49703429134 ps
CPU time 74.73 seconds
Started Aug 23 04:13:00 AM UTC 24
Finished Aug 23 04:14:17 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578572025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.578572025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/251.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/252.uart_fifo_reset.1531229568
Short name T1135
Test name
Test status
Simulation time 18788648840 ps
CPU time 26.89 seconds
Started Aug 23 04:13:03 AM UTC 24
Finished Aug 23 04:13:31 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531229568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1531229568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/252.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/253.uart_fifo_reset.2488909847
Short name T215
Test name
Test status
Simulation time 39175522269 ps
CPU time 14.57 seconds
Started Aug 23 04:13:04 AM UTC 24
Finished Aug 23 04:13:20 AM UTC 24
Peak memory 208452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488909847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2488909847
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/253.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1987998511
Short name T1145
Test name
Test status
Simulation time 48382496772 ps
CPU time 62.25 seconds
Started Aug 23 04:13:07 AM UTC 24
Finished Aug 23 04:14:11 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987998511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1987998511
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/254.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/255.uart_fifo_reset.172374709
Short name T244
Test name
Test status
Simulation time 11216818173 ps
CPU time 18.79 seconds
Started Aug 23 04:13:11 AM UTC 24
Finished Aug 23 04:13:31 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172374709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.172374709
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/255.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/256.uart_fifo_reset.2561240100
Short name T1136
Test name
Test status
Simulation time 38468052652 ps
CPU time 17.44 seconds
Started Aug 23 04:13:14 AM UTC 24
Finished Aug 23 04:13:33 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561240100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2561240100
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/256.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/257.uart_fifo_reset.1301512602
Short name T1138
Test name
Test status
Simulation time 51189159011 ps
CPU time 20.95 seconds
Started Aug 23 04:13:15 AM UTC 24
Finished Aug 23 04:13:37 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301512602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1301512602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/257.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/258.uart_fifo_reset.1567896208
Short name T1134
Test name
Test status
Simulation time 9203479975 ps
CPU time 12.53 seconds
Started Aug 23 04:13:15 AM UTC 24
Finished Aug 23 04:13:28 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567896208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1567896208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/258.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/259.uart_fifo_reset.324137197
Short name T1170
Test name
Test status
Simulation time 125554006963 ps
CPU time 113.29 seconds
Started Aug 23 04:13:20 AM UTC 24
Finished Aug 23 04:15:15 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324137197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.324137197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/259.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_alert_test.1251892082
Short name T581
Test name
Test status
Simulation time 92529439 ps
CPU time 0.47 seconds
Started Aug 23 03:43:15 AM UTC 24
Finished Aug 23 03:43:17 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251892082 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1251892082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_fifo_full.371259839
Short name T580
Test name
Test status
Simulation time 32832015810 ps
CPU time 44.63 seconds
Started Aug 23 03:42:30 AM UTC 24
Finished Aug 23 03:43:16 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371259839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.371259839
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.3776691251
Short name T606
Test name
Test status
Simulation time 83683887995 ps
CPU time 148.29 seconds
Started Aug 23 03:42:36 AM UTC 24
Finished Aug 23 03:45:07 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776691251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3776691251
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_fifo_reset.1988287747
Short name T414
Test name
Test status
Simulation time 105250697036 ps
CPU time 49.11 seconds
Started Aug 23 03:42:39 AM UTC 24
Finished Aug 23 03:43:30 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988287747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1988287747
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_intr.1870387256
Short name T595
Test name
Test status
Simulation time 197168573411 ps
CPU time 90.56 seconds
Started Aug 23 03:42:46 AM UTC 24
Finished Aug 23 03:44:18 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870387256 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1870387256
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.552349979
Short name T757
Test name
Test status
Simulation time 93790016085 ps
CPU time 619.34 seconds
Started Aug 23 03:43:09 AM UTC 24
Finished Aug 23 03:53:36 AM UTC 24
Peak memory 212404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552349979 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.552349979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_loopback.1354026717
Short name T576
Test name
Test status
Simulation time 3005215155 ps
CPU time 1.02 seconds
Started Aug 23 03:43:06 AM UTC 24
Finished Aug 23 03:43:08 AM UTC 24
Peak memory 206552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354026717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1354026717
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_noise_filter.2266910633
Short name T579
Test name
Test status
Simulation time 40996044908 ps
CPU time 14.73 seconds
Started Aug 23 03:42:59 AM UTC 24
Finished Aug 23 03:43:15 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266910633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2266910633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_perf.2411591185
Short name T626
Test name
Test status
Simulation time 12224564252 ps
CPU time 201.39 seconds
Started Aug 23 03:43:09 AM UTC 24
Finished Aug 23 03:46:34 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411591185 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2411591185
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_rx_oversample.3158704837
Short name T584
Test name
Test status
Simulation time 4622948846 ps
CPU time 34.49 seconds
Started Aug 23 03:42:46 AM UTC 24
Finished Aug 23 03:43:21 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158704837 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3158704837
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.3647721524
Short name T582
Test name
Test status
Simulation time 31325177772 ps
CPU time 15.31 seconds
Started Aug 23 03:43:03 AM UTC 24
Finished Aug 23 03:43:19 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647721524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3647721524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.491498946
Short name T574
Test name
Test status
Simulation time 1381509807 ps
CPU time 2.7 seconds
Started Aug 23 03:42:59 AM UTC 24
Finished Aug 23 03:43:03 AM UTC 24
Peak memory 205036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491498946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.491498946
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_smoke.460191338
Short name T572
Test name
Test status
Simulation time 10564664036 ps
CPU time 10.64 seconds
Started Aug 23 03:42:24 AM UTC 24
Finished Aug 23 03:42:36 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460191338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 26.uart_smoke.460191338
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.2436485039
Short name T89
Test name
Test status
Simulation time 14297780887 ps
CPU time 56.81 seconds
Started Aug 23 03:43:13 AM UTC 24
Finished Aug 23 03:44:12 AM UTC 24
Peak memory 221772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2436485039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all
_with_rand_reset.2436485039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.2319061136
Short name T577
Test name
Test status
Simulation time 232937850 ps
CPU time 1.02 seconds
Started Aug 23 03:43:06 AM UTC 24
Finished Aug 23 03:43:08 AM UTC 24
Peak memory 206428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319061136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2319061136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/26.uart_tx_rx.880550739
Short name T419
Test name
Test status
Simulation time 121346668495 ps
CPU time 38.5 seconds
Started Aug 23 03:42:25 AM UTC 24
Finished Aug 23 03:43:05 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880550739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.880550739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/26.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/260.uart_fifo_reset.1635736520
Short name T1137
Test name
Test status
Simulation time 33169714786 ps
CPU time 12.74 seconds
Started Aug 23 04:13:21 AM UTC 24
Finished Aug 23 04:13:35 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635736520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1635736520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/260.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/261.uart_fifo_reset.3493298497
Short name T234
Test name
Test status
Simulation time 50912055720 ps
CPU time 16.51 seconds
Started Aug 23 04:13:21 AM UTC 24
Finished Aug 23 04:13:39 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493298497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3493298497
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/261.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/262.uart_fifo_reset.559842092
Short name T1146
Test name
Test status
Simulation time 34307892829 ps
CPU time 49.63 seconds
Started Aug 23 04:13:23 AM UTC 24
Finished Aug 23 04:14:14 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559842092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.559842092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/262.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/263.uart_fifo_reset.3873723861
Short name T1178
Test name
Test status
Simulation time 152608092091 ps
CPU time 155.35 seconds
Started Aug 23 04:13:25 AM UTC 24
Finished Aug 23 04:16:03 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873723861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3873723861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/263.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/264.uart_fifo_reset.4250964972
Short name T1148
Test name
Test status
Simulation time 44068209753 ps
CPU time 50.13 seconds
Started Aug 23 04:13:25 AM UTC 24
Finished Aug 23 04:14:16 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250964972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.4250964972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/264.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/265.uart_fifo_reset.4124832964
Short name T243
Test name
Test status
Simulation time 51533804193 ps
CPU time 19.88 seconds
Started Aug 23 04:13:29 AM UTC 24
Finished Aug 23 04:13:50 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124832964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.4124832964
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/265.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/266.uart_fifo_reset.4228023386
Short name T1143
Test name
Test status
Simulation time 18058240348 ps
CPU time 27.35 seconds
Started Aug 23 04:13:29 AM UTC 24
Finished Aug 23 04:13:58 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228023386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.4228023386
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/266.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/267.uart_fifo_reset.899748991
Short name T1141
Test name
Test status
Simulation time 12454437434 ps
CPU time 16.19 seconds
Started Aug 23 04:13:32 AM UTC 24
Finished Aug 23 04:13:49 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899748991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.899748991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/267.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/268.uart_fifo_reset.1084059855
Short name T1186
Test name
Test status
Simulation time 76917720583 ps
CPU time 267.53 seconds
Started Aug 23 04:13:33 AM UTC 24
Finished Aug 23 04:18:04 AM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084059855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1084059855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/268.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_alert_test.2806905120
Short name T593
Test name
Test status
Simulation time 42354381 ps
CPU time 0.5 seconds
Started Aug 23 03:44:13 AM UTC 24
Finished Aug 23 03:44:14 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806905120 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2806905120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_fifo_full.2873156175
Short name T596
Test name
Test status
Simulation time 40154810247 ps
CPU time 57.44 seconds
Started Aug 23 03:43:20 AM UTC 24
Finished Aug 23 03:44:19 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873156175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2873156175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.1820595598
Short name T165
Test name
Test status
Simulation time 63160805174 ps
CPU time 26.67 seconds
Started Aug 23 03:43:22 AM UTC 24
Finished Aug 23 03:43:50 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820595598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1820595598
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_intr.1497154744
Short name T636
Test name
Test status
Simulation time 171081386759 ps
CPU time 206.91 seconds
Started Aug 23 03:43:30 AM UTC 24
Finished Aug 23 03:47:00 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497154744 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1497154744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.2709488175
Short name T651
Test name
Test status
Simulation time 57317632022 ps
CPU time 281.81 seconds
Started Aug 23 03:44:00 AM UTC 24
Finished Aug 23 03:48:45 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709488175 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2709488175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_loopback.3902806887
Short name T591
Test name
Test status
Simulation time 9763105864 ps
CPU time 10.48 seconds
Started Aug 23 03:43:50 AM UTC 24
Finished Aug 23 03:44:02 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902806887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3902806887
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_noise_filter.27423787
Short name T608
Test name
Test status
Simulation time 227678706991 ps
CPU time 95.44 seconds
Started Aug 23 03:43:31 AM UTC 24
Finished Aug 23 03:45:09 AM UTC 24
Peak memory 208804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27423787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.27423787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_perf.3707889422
Short name T657
Test name
Test status
Simulation time 25967724025 ps
CPU time 304.36 seconds
Started Aug 23 03:43:55 AM UTC 24
Finished Aug 23 03:49:04 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707889422 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3707889422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_rx_oversample.3700438429
Short name T588
Test name
Test status
Simulation time 5848350691 ps
CPU time 12.32 seconds
Started Aug 23 03:43:23 AM UTC 24
Finished Aug 23 03:43:36 AM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700438429 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3700438429
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.2203374148
Short name T167
Test name
Test status
Simulation time 57524505631 ps
CPU time 91.8 seconds
Started Aug 23 03:43:37 AM UTC 24
Finished Aug 23 03:45:11 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203374148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2203374148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.3395625402
Short name T598
Test name
Test status
Simulation time 39855098176 ps
CPU time 53.59 seconds
Started Aug 23 03:43:34 AM UTC 24
Finished Aug 23 03:44:29 AM UTC 24
Peak memory 205024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395625402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3395625402
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_smoke.2068904935
Short name T587
Test name
Test status
Simulation time 5717288203 ps
CPU time 14.82 seconds
Started Aug 23 03:43:18 AM UTC 24
Finished Aug 23 03:43:34 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068904935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2068904935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_stress_all.1666885061
Short name T741
Test name
Test status
Simulation time 200834382792 ps
CPU time 511.62 seconds
Started Aug 23 03:44:07 AM UTC 24
Finished Aug 23 03:52:44 AM UTC 24
Peak memory 212212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666885061 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1666885061
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.847633540
Short name T90
Test name
Test status
Simulation time 1968564942 ps
CPU time 22.01 seconds
Started Aug 23 03:44:03 AM UTC 24
Finished Aug 23 03:44:26 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=847633540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all_
with_rand_reset.847633540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.1904262829
Short name T367
Test name
Test status
Simulation time 6285245543 ps
CPU time 19.35 seconds
Started Aug 23 03:43:45 AM UTC 24
Finished Aug 23 03:44:06 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904262829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1904262829
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/27.uart_tx_rx.3703847084
Short name T621
Test name
Test status
Simulation time 94614979707 ps
CPU time 175.73 seconds
Started Aug 23 03:43:18 AM UTC 24
Finished Aug 23 03:46:16 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703847084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3703847084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/27.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1914296950
Short name T1153
Test name
Test status
Simulation time 50811165196 ps
CPU time 40.45 seconds
Started Aug 23 04:13:38 AM UTC 24
Finished Aug 23 04:14:20 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914296950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1914296950
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/271.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/272.uart_fifo_reset.814607273
Short name T218
Test name
Test status
Simulation time 20778814255 ps
CPU time 7.92 seconds
Started Aug 23 04:13:40 AM UTC 24
Finished Aug 23 04:13:49 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814607273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.814607273
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/272.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/273.uart_fifo_reset.3305334974
Short name T1158
Test name
Test status
Simulation time 133640103430 ps
CPU time 49.02 seconds
Started Aug 23 04:13:42 AM UTC 24
Finished Aug 23 04:14:32 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305334974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3305334974
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/273.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/274.uart_fifo_reset.2685737760
Short name T249
Test name
Test status
Simulation time 22119836766 ps
CPU time 22.24 seconds
Started Aug 23 04:13:49 AM UTC 24
Finished Aug 23 04:14:13 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685737760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2685737760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/274.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/275.uart_fifo_reset.4187427834
Short name T1144
Test name
Test status
Simulation time 10607581563 ps
CPU time 14.94 seconds
Started Aug 23 04:13:51 AM UTC 24
Finished Aug 23 04:14:07 AM UTC 24
Peak memory 207784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187427834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.4187427834
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/275.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/276.uart_fifo_reset.3698872746
Short name T1162
Test name
Test status
Simulation time 127592019843 ps
CPU time 55.53 seconds
Started Aug 23 04:13:51 AM UTC 24
Finished Aug 23 04:14:48 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698872746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3698872746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/276.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/277.uart_fifo_reset.1221407859
Short name T1182
Test name
Test status
Simulation time 70737107381 ps
CPU time 214.37 seconds
Started Aug 23 04:13:51 AM UTC 24
Finished Aug 23 04:17:28 AM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221407859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1221407859
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/277.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/278.uart_fifo_reset.64807289
Short name T1167
Test name
Test status
Simulation time 60250698019 ps
CPU time 70.01 seconds
Started Aug 23 04:13:53 AM UTC 24
Finished Aug 23 04:15:04 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64807289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.64807289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/278.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/279.uart_fifo_reset.4290382758
Short name T1152
Test name
Test status
Simulation time 30743358159 ps
CPU time 25.49 seconds
Started Aug 23 04:13:53 AM UTC 24
Finished Aug 23 04:14:19 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290382758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.4290382758
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/279.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_alert_test.2133367521
Short name T605
Test name
Test status
Simulation time 103806109 ps
CPU time 0.48 seconds
Started Aug 23 03:45:03 AM UTC 24
Finished Aug 23 03:45:05 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133367521 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2133367521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_fifo_full.2604805197
Short name T600
Test name
Test status
Simulation time 134502799168 ps
CPU time 29.43 seconds
Started Aug 23 03:44:15 AM UTC 24
Finished Aug 23 03:44:46 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604805197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2604805197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.2950567772
Short name T599
Test name
Test status
Simulation time 35081528514 ps
CPU time 25.37 seconds
Started Aug 23 03:44:16 AM UTC 24
Finished Aug 23 03:44:43 AM UTC 24
Peak memory 208524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950567772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2950567772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_fifo_reset.3464038706
Short name T192
Test name
Test status
Simulation time 10790551310 ps
CPU time 17.8 seconds
Started Aug 23 03:44:18 AM UTC 24
Finished Aug 23 03:44:37 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464038706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3464038706
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_intr.3260634684
Short name T667
Test name
Test status
Simulation time 219491482705 ps
CPU time 306.4 seconds
Started Aug 23 03:44:24 AM UTC 24
Finished Aug 23 03:49:34 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260634684 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3260634684
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.1334582474
Short name T713
Test name
Test status
Simulation time 112590960097 ps
CPU time 400.83 seconds
Started Aug 23 03:44:49 AM UTC 24
Finished Aug 23 03:51:35 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334582474 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1334582474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_loopback.1135774146
Short name T609
Test name
Test status
Simulation time 11950995368 ps
CPU time 23.92 seconds
Started Aug 23 03:44:47 AM UTC 24
Finished Aug 23 03:45:12 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135774146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1135774146
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_noise_filter.1090448096
Short name T410
Test name
Test status
Simulation time 155167029537 ps
CPU time 236.25 seconds
Started Aug 23 03:44:26 AM UTC 24
Finished Aug 23 03:48:26 AM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090448096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1090448096
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_perf.499775796
Short name T611
Test name
Test status
Simulation time 2196581416 ps
CPU time 31.6 seconds
Started Aug 23 03:44:47 AM UTC 24
Finished Aug 23 03:45:20 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499775796 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.499775796
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_rx_oversample.2275659015
Short name T597
Test name
Test status
Simulation time 3650548717 ps
CPU time 3.01 seconds
Started Aug 23 03:44:19 AM UTC 24
Finished Aug 23 03:44:23 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275659015 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2275659015
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.3247851256
Short name T142
Test name
Test status
Simulation time 33410743661 ps
CPU time 15.79 seconds
Started Aug 23 03:44:38 AM UTC 24
Finished Aug 23 03:44:55 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247851256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3247851256
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.3773150764
Short name T604
Test name
Test status
Simulation time 38702538459 ps
CPU time 30.67 seconds
Started Aug 23 03:44:31 AM UTC 24
Finished Aug 23 03:45:03 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773150764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3773150764
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_smoke.4075328982
Short name T594
Test name
Test status
Simulation time 505413505 ps
CPU time 1.19 seconds
Started Aug 23 03:44:13 AM UTC 24
Finished Aug 23 03:44:15 AM UTC 24
Peak memory 206340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075328982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4075328982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_stress_all.2164799426
Short name T672
Test name
Test status
Simulation time 224067423420 ps
CPU time 284.28 seconds
Started Aug 23 03:45:02 AM UTC 24
Finished Aug 23 03:49:50 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164799426 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2164799426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.3754052799
Short name T397
Test name
Test status
Simulation time 4995697729 ps
CPU time 26.95 seconds
Started Aug 23 03:44:55 AM UTC 24
Finished Aug 23 03:45:23 AM UTC 24
Peak memory 217644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3754052799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all
_with_rand_reset.3754052799
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.620045406
Short name T601
Test name
Test status
Simulation time 532374178 ps
CPU time 1.81 seconds
Started Aug 23 03:44:44 AM UTC 24
Finished Aug 23 03:44:47 AM UTC 24
Peak memory 208080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620045406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.620045406
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/28.uart_tx_rx.692265588
Short name T603
Test name
Test status
Simulation time 31689703126 ps
CPU time 44.67 seconds
Started Aug 23 03:44:15 AM UTC 24
Finished Aug 23 03:45:01 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692265588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.692265588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/28.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/280.uart_fifo_reset.1521291957
Short name T1149
Test name
Test status
Simulation time 48048636090 ps
CPU time 16.28 seconds
Started Aug 23 04:13:59 AM UTC 24
Finished Aug 23 04:14:17 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521291957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1521291957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/280.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2998374345
Short name T1159
Test name
Test status
Simulation time 19873133570 ps
CPU time 27.05 seconds
Started Aug 23 04:14:06 AM UTC 24
Finished Aug 23 04:14:34 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998374345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2998374345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/282.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/283.uart_fifo_reset.693288495
Short name T213
Test name
Test status
Simulation time 116550732768 ps
CPU time 31.66 seconds
Started Aug 23 04:14:08 AM UTC 24
Finished Aug 23 04:14:41 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693288495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.693288495
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/283.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/284.uart_fifo_reset.3976934233
Short name T1161
Test name
Test status
Simulation time 21973588666 ps
CPU time 33.84 seconds
Started Aug 23 04:14:13 AM UTC 24
Finished Aug 23 04:14:48 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976934233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3976934233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/284.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/285.uart_fifo_reset.2243902978
Short name T1179
Test name
Test status
Simulation time 83590084004 ps
CPU time 114.86 seconds
Started Aug 23 04:14:14 AM UTC 24
Finished Aug 23 04:16:11 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243902978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2243902978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/285.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/286.uart_fifo_reset.1512808931
Short name T1177
Test name
Test status
Simulation time 74788143387 ps
CPU time 101.76 seconds
Started Aug 23 04:14:16 AM UTC 24
Finished Aug 23 04:15:59 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512808931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1512808931
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/286.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/287.uart_fifo_reset.2600920229
Short name T1129
Test name
Test status
Simulation time 39165272169 ps
CPU time 26.03 seconds
Started Aug 23 04:14:16 AM UTC 24
Finished Aug 23 04:14:43 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600920229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2600920229
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/287.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/288.uart_fifo_reset.810000010
Short name T1160
Test name
Test status
Simulation time 39830078020 ps
CPU time 16.16 seconds
Started Aug 23 04:14:17 AM UTC 24
Finished Aug 23 04:14:35 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810000010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.810000010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/288.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/289.uart_fifo_reset.2891777848
Short name T1156
Test name
Test status
Simulation time 6473429664 ps
CPU time 9.29 seconds
Started Aug 23 04:14:17 AM UTC 24
Finished Aug 23 04:14:28 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891777848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2891777848
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/289.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_alert_test.178550727
Short name T619
Test name
Test status
Simulation time 15990389 ps
CPU time 0.48 seconds
Started Aug 23 03:46:03 AM UTC 24
Finished Aug 23 03:46:04 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178550727 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.178550727
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_fifo_full.2746796860
Short name T631
Test name
Test status
Simulation time 57971739446 ps
CPU time 97.9 seconds
Started Aug 23 03:45:09 AM UTC 24
Finished Aug 23 03:46:49 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746796860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2746796860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.1121542735
Short name T616
Test name
Test status
Simulation time 66824660632 ps
CPU time 26.35 seconds
Started Aug 23 03:45:09 AM UTC 24
Finished Aug 23 03:45:37 AM UTC 24
Peak memory 208648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121542735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1121542735
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_fifo_reset.1159332334
Short name T618
Test name
Test status
Simulation time 25237382939 ps
CPU time 36.42 seconds
Started Aug 23 03:45:12 AM UTC 24
Finished Aug 23 03:45:49 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159332334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1159332334
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_intr.2783313283
Short name T614
Test name
Test status
Simulation time 36167025117 ps
CPU time 15.13 seconds
Started Aug 23 03:45:16 AM UTC 24
Finished Aug 23 03:45:32 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783313283 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2783313283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.740224552
Short name T794
Test name
Test status
Simulation time 93259424218 ps
CPU time 609.61 seconds
Started Aug 23 03:45:37 AM UTC 24
Finished Aug 23 03:55:54 AM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740224552 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.740224552
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_loopback.907402703
Short name T617
Test name
Test status
Simulation time 4947723885 ps
CPU time 4.6 seconds
Started Aug 23 03:45:33 AM UTC 24
Finished Aug 23 03:45:40 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907402703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.uart_loopback.907402703
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_noise_filter.874535070
Short name T622
Test name
Test status
Simulation time 155042778493 ps
CPU time 60.44 seconds
Started Aug 23 03:45:21 AM UTC 24
Finished Aug 23 03:46:23 AM UTC 24
Peak memory 209052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874535070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.874535070
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_perf.2809046459
Short name T855
Test name
Test status
Simulation time 15293169966 ps
CPU time 817.69 seconds
Started Aug 23 03:45:35 AM UTC 24
Finished Aug 23 03:59:22 AM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809046459 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2809046459
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_rx_oversample.1451260513
Short name T610
Test name
Test status
Simulation time 1958775816 ps
CPU time 1.65 seconds
Started Aug 23 03:45:13 AM UTC 24
Finished Aug 23 03:45:15 AM UTC 24
Peak memory 206432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451260513 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1451260513
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.3480260477
Short name T645
Test name
Test status
Simulation time 134733629033 ps
CPU time 149.08 seconds
Started Aug 23 03:45:24 AM UTC 24
Finished Aug 23 03:47:55 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480260477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3480260477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.2294438486
Short name T613
Test name
Test status
Simulation time 5104724873 ps
CPU time 7.61 seconds
Started Aug 23 03:45:22 AM UTC 24
Finished Aug 23 03:45:31 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294438486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2294438486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_smoke.4211554923
Short name T607
Test name
Test status
Simulation time 872044837 ps
CPU time 1.98 seconds
Started Aug 23 03:45:05 AM UTC 24
Finished Aug 23 03:45:09 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211554923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.4211554923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_stress_all.2887726509
Short name T175
Test name
Test status
Simulation time 85822895684 ps
CPU time 186.98 seconds
Started Aug 23 03:45:50 AM UTC 24
Finished Aug 23 03:49:00 AM UTC 24
Peak memory 217576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887726509 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2887726509
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.1998094588
Short name T398
Test name
Test status
Simulation time 8022913619 ps
CPU time 20.38 seconds
Started Aug 23 03:45:40 AM UTC 24
Finished Aug 23 03:46:02 AM UTC 24
Peak memory 217664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1998094588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all
_with_rand_reset.1998094588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.3189397664
Short name T615
Test name
Test status
Simulation time 1396886741 ps
CPU time 1.48 seconds
Started Aug 23 03:45:31 AM UTC 24
Finished Aug 23 03:45:34 AM UTC 24
Peak memory 206308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189397664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3189397664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/29.uart_tx_rx.3562445623
Short name T612
Test name
Test status
Simulation time 16196519197 ps
CPU time 11.6 seconds
Started Aug 23 03:45:08 AM UTC 24
Finished Aug 23 03:45:21 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562445623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3562445623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/29.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2398793107
Short name T1174
Test name
Test status
Simulation time 104811283914 ps
CPU time 79.95 seconds
Started Aug 23 04:14:19 AM UTC 24
Finished Aug 23 04:15:40 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398793107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2398793107
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/290.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/292.uart_fifo_reset.3066316034
Short name T1185
Test name
Test status
Simulation time 130193330641 ps
CPU time 202.22 seconds
Started Aug 23 04:14:21 AM UTC 24
Finished Aug 23 04:17:46 AM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066316034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3066316034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/292.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/293.uart_fifo_reset.343559031
Short name T1184
Test name
Test status
Simulation time 268950733135 ps
CPU time 197.12 seconds
Started Aug 23 04:14:21 AM UTC 24
Finished Aug 23 04:17:41 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343559031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.343559031
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/293.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/294.uart_fifo_reset.1308519289
Short name T1175
Test name
Test status
Simulation time 122617972269 ps
CPU time 75.91 seconds
Started Aug 23 04:14:26 AM UTC 24
Finished Aug 23 04:15:44 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308519289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1308519289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/294.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/295.uart_fifo_reset.3271829840
Short name T1166
Test name
Test status
Simulation time 154788895979 ps
CPU time 33.91 seconds
Started Aug 23 04:14:28 AM UTC 24
Finished Aug 23 04:15:03 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271829840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3271829840
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/295.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/296.uart_fifo_reset.2837060077
Short name T1176
Test name
Test status
Simulation time 49008499572 ps
CPU time 82.65 seconds
Started Aug 23 04:14:29 AM UTC 24
Finished Aug 23 04:15:53 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837060077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2837060077
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/296.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/297.uart_fifo_reset.1356697458
Short name T1169
Test name
Test status
Simulation time 132279383512 ps
CPU time 41.77 seconds
Started Aug 23 04:14:31 AM UTC 24
Finished Aug 23 04:15:14 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356697458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1356697458
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/297.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/298.uart_fifo_reset.3326094940
Short name T1171
Test name
Test status
Simulation time 29886841945 ps
CPU time 44.59 seconds
Started Aug 23 04:14:34 AM UTC 24
Finished Aug 23 04:15:20 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326094940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3326094940
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/298.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/299.uart_fifo_reset.2284957615
Short name T1165
Test name
Test status
Simulation time 56099616081 ps
CPU time 21.3 seconds
Started Aug 23 04:14:35 AM UTC 24
Finished Aug 23 04:14:58 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284957615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2284957615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/299.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_alert_test.1717788536
Short name T429
Test name
Test status
Simulation time 16294747 ps
CPU time 0.48 seconds
Started Aug 23 03:24:29 AM UTC 24
Finished Aug 23 03:24:31 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717788536 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1717788536
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_fifo_full.284539539
Short name T117
Test name
Test status
Simulation time 144694738428 ps
CPU time 135.59 seconds
Started Aug 23 03:24:00 AM UTC 24
Finished Aug 23 03:26:18 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284539539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.284539539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.4276829988
Short name T115
Test name
Test status
Simulation time 36089601333 ps
CPU time 25.73 seconds
Started Aug 23 03:24:01 AM UTC 24
Finished Aug 23 03:24:28 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276829988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.4276829988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_fifo_reset.2723814527
Short name T114
Test name
Test status
Simulation time 43253627324 ps
CPU time 31.06 seconds
Started Aug 23 03:24:05 AM UTC 24
Finished Aug 23 03:24:37 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723814527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2723814527
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_intr.3854066805
Short name T291
Test name
Test status
Simulation time 61984248738 ps
CPU time 101 seconds
Started Aug 23 03:24:08 AM UTC 24
Finished Aug 23 03:25:51 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854066805 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3854066805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.2357992363
Short name T288
Test name
Test status
Simulation time 46558128522 ps
CPU time 230.81 seconds
Started Aug 23 03:24:21 AM UTC 24
Finished Aug 23 03:28:15 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357992363 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2357992363
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_loopback.102538033
Short name T428
Test name
Test status
Simulation time 11857683776 ps
CPU time 4.75 seconds
Started Aug 23 03:24:18 AM UTC 24
Finished Aug 23 03:24:24 AM UTC 24
Peak memory 208496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102538033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.uart_loopback.102538033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_perf.3010403899
Short name T273
Test name
Test status
Simulation time 13351825248 ps
CPU time 115.01 seconds
Started Aug 23 03:24:20 AM UTC 24
Finished Aug 23 03:26:17 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010403899 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3010403899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_rx_oversample.2523942263
Short name T427
Test name
Test status
Simulation time 1374745473 ps
CPU time 2.57 seconds
Started Aug 23 03:24:06 AM UTC 24
Finished Aug 23 03:24:09 AM UTC 24
Peak memory 207080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523942263 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2523942263
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.612117358
Short name T160
Test name
Test status
Simulation time 23526306680 ps
CPU time 27.06 seconds
Started Aug 23 03:24:11 AM UTC 24
Finished Aug 23 03:24:39 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612117358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.612117358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.794084904
Short name T304
Test name
Test status
Simulation time 42938737705 ps
CPU time 3.83 seconds
Started Aug 23 03:24:10 AM UTC 24
Finished Aug 23 03:24:15 AM UTC 24
Peak memory 204724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794084904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.794084904
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_sec_cm.1113577571
Short name T84
Test name
Test status
Simulation time 125852772 ps
CPU time 0.66 seconds
Started Aug 23 03:24:27 AM UTC 24
Finished Aug 23 03:24:28 AM UTC 24
Peak memory 237444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113577571 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1113577571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_smoke.583400279
Short name T286
Test name
Test status
Simulation time 450269029 ps
CPU time 1.1 seconds
Started Aug 23 03:23:57 AM UTC 24
Finished Aug 23 03:23:59 AM UTC 24
Peak memory 207040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583400279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.uart_smoke.583400279
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_stress_all.2973173427
Short name T691
Test name
Test status
Simulation time 225610547029 ps
CPU time 1551.8 seconds
Started Aug 23 03:24:25 AM UTC 24
Finished Aug 23 03:50:33 AM UTC 24
Peak memory 221104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973173427 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2973173427
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.1063677730
Short name T28
Test name
Test status
Simulation time 4805094210 ps
CPU time 29.23 seconds
Started Aug 23 03:24:23 AM UTC 24
Finished Aug 23 03:24:53 AM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1063677730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_
with_rand_reset.1063677730
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.2004266772
Short name T268
Test name
Test status
Simulation time 673769991 ps
CPU time 1.81 seconds
Started Aug 23 03:24:16 AM UTC 24
Finished Aug 23 03:24:19 AM UTC 24
Peak memory 206448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004266772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2004266772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/3.uart_tx_rx.1990478898
Short name T44
Test name
Test status
Simulation time 24926225565 ps
CPU time 34.45 seconds
Started Aug 23 03:24:00 AM UTC 24
Finished Aug 23 03:24:36 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990478898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1990478898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/3.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_alert_test.458643597
Short name T635
Test name
Test status
Simulation time 14069629 ps
CPU time 0.47 seconds
Started Aug 23 03:46:58 AM UTC 24
Finished Aug 23 03:46:59 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458643597 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.458643597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_fifo_full.2059163046
Short name T644
Test name
Test status
Simulation time 128194650599 ps
CPU time 95.97 seconds
Started Aug 23 03:46:17 AM UTC 24
Finished Aug 23 03:47:55 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059163046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2059163046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.4167312069
Short name T632
Test name
Test status
Simulation time 46248443884 ps
CPU time 24.84 seconds
Started Aug 23 03:46:24 AM UTC 24
Finished Aug 23 03:46:50 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167312069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4167312069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_fifo_reset.750209555
Short name T625
Test name
Test status
Simulation time 60636461825 ps
CPU time 6.54 seconds
Started Aug 23 03:46:24 AM UTC 24
Finished Aug 23 03:46:32 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750209555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.750209555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_intr.1093719099
Short name T629
Test name
Test status
Simulation time 27552111853 ps
CPU time 7.24 seconds
Started Aug 23 03:46:32 AM UTC 24
Finished Aug 23 03:46:40 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093719099 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1093719099
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.1927712972
Short name T737
Test name
Test status
Simulation time 68276757689 ps
CPU time 337.47 seconds
Started Aug 23 03:46:50 AM UTC 24
Finished Aug 23 03:52:31 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927712972 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1927712972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_loopback.381565293
Short name T633
Test name
Test status
Simulation time 8035326100 ps
CPU time 10.01 seconds
Started Aug 23 03:46:41 AM UTC 24
Finished Aug 23 03:46:53 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381565293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.uart_loopback.381565293
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_noise_filter.272949051
Short name T677
Test name
Test status
Simulation time 97468227833 ps
CPU time 204.67 seconds
Started Aug 23 03:46:34 AM UTC 24
Finished Aug 23 03:50:02 AM UTC 24
Peak memory 208416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272949051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.272949051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_perf.1441914386
Short name T687
Test name
Test status
Simulation time 30763935237 ps
CPU time 217.24 seconds
Started Aug 23 03:46:47 AM UTC 24
Finished Aug 23 03:50:27 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441914386 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1441914386
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_rx_oversample.4009725682
Short name T627
Test name
Test status
Simulation time 1925006995 ps
CPU time 2.37 seconds
Started Aug 23 03:46:31 AM UTC 24
Finished Aug 23 03:46:35 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009725682 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4009725682
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.4023586675
Short name T642
Test name
Test status
Simulation time 54314892193 ps
CPU time 69.58 seconds
Started Aug 23 03:46:39 AM UTC 24
Finished Aug 23 03:47:50 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023586675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.4023586675
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.2952209027
Short name T628
Test name
Test status
Simulation time 4215761123 ps
CPU time 3.35 seconds
Started Aug 23 03:46:35 AM UTC 24
Finished Aug 23 03:46:40 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952209027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2952209027
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_smoke.3490005658
Short name T623
Test name
Test status
Simulation time 6285110532 ps
CPU time 17.2 seconds
Started Aug 23 03:46:05 AM UTC 24
Finished Aug 23 03:46:23 AM UTC 24
Peak memory 208436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490005658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3490005658
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_stress_all.3795351013
Short name T146
Test name
Test status
Simulation time 248904164847 ps
CPU time 210.27 seconds
Started Aug 23 03:46:54 AM UTC 24
Finished Aug 23 03:50:27 AM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795351013 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3795351013
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.374919637
Short name T91
Test name
Test status
Simulation time 1056192866 ps
CPU time 10.81 seconds
Started Aug 23 03:46:51 AM UTC 24
Finished Aug 23 03:47:03 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=374919637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all_
with_rand_reset.374919637
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.913630633
Short name T630
Test name
Test status
Simulation time 1126957478 ps
CPU time 4.24 seconds
Started Aug 23 03:46:40 AM UTC 24
Finished Aug 23 03:46:46 AM UTC 24
Peak memory 207580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913630633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.913630633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/30.uart_tx_rx.668251819
Short name T624
Test name
Test status
Simulation time 16033651850 ps
CPU time 20.72 seconds
Started Aug 23 03:46:09 AM UTC 24
Finished Aug 23 03:46:31 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668251819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.668251819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/30.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_alert_test.2395653336
Short name T649
Test name
Test status
Simulation time 34970698 ps
CPU time 0.45 seconds
Started Aug 23 03:48:11 AM UTC 24
Finished Aug 23 03:48:13 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395653336 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2395653336
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_fifo_full.3351695541
Short name T676
Test name
Test status
Simulation time 296622055842 ps
CPU time 172.53 seconds
Started Aug 23 03:47:01 AM UTC 24
Finished Aug 23 03:49:56 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351695541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3351695541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.3585016634
Short name T652
Test name
Test status
Simulation time 81723778497 ps
CPU time 102.49 seconds
Started Aug 23 03:47:01 AM UTC 24
Finished Aug 23 03:48:45 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585016634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3585016634
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_fifo_reset.2372501818
Short name T193
Test name
Test status
Simulation time 16100366602 ps
CPU time 22.82 seconds
Started Aug 23 03:47:03 AM UTC 24
Finished Aug 23 03:47:27 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372501818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2372501818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_intr.108120652
Short name T653
Test name
Test status
Simulation time 41817344078 ps
CPU time 79.81 seconds
Started Aug 23 03:47:26 AM UTC 24
Finished Aug 23 03:48:48 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108120652 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.108120652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.2037970401
Short name T768
Test name
Test status
Simulation time 191545917761 ps
CPU time 372.99 seconds
Started Aug 23 03:47:56 AM UTC 24
Finished Aug 23 03:54:13 AM UTC 24
Peak memory 212204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037970401 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2037970401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_loopback.1170165398
Short name T646
Test name
Test status
Simulation time 4789317324 ps
CPU time 6.36 seconds
Started Aug 23 03:47:54 AM UTC 24
Finished Aug 23 03:48:01 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170165398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1170165398
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_noise_filter.1969661577
Short name T411
Test name
Test status
Simulation time 142544649701 ps
CPU time 61.81 seconds
Started Aug 23 03:47:28 AM UTC 24
Finished Aug 23 03:48:31 AM UTC 24
Peak memory 217688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969661577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1969661577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_rx_oversample.1935162260
Short name T640
Test name
Test status
Simulation time 6788685985 ps
CPU time 7.6 seconds
Started Aug 23 03:47:18 AM UTC 24
Finished Aug 23 03:47:27 AM UTC 24
Peak memory 208464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935162260 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1935162260
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.739587628
Short name T648
Test name
Test status
Simulation time 18618773047 ps
CPU time 33.43 seconds
Started Aug 23 03:47:36 AM UTC 24
Finished Aug 23 03:48:11 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739587628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.739587628
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.3154064966
Short name T641
Test name
Test status
Simulation time 2881242505 ps
CPU time 4.77 seconds
Started Aug 23 03:47:29 AM UTC 24
Finished Aug 23 03:47:34 AM UTC 24
Peak memory 205104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154064966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3154064966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_smoke.732859721
Short name T637
Test name
Test status
Simulation time 619154865 ps
CPU time 1.44 seconds
Started Aug 23 03:46:58 AM UTC 24
Finished Aug 23 03:47:00 AM UTC 24
Peak memory 206244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732859721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.uart_smoke.732859721
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_stress_all.3182117367
Short name T412
Test name
Test status
Simulation time 239333826237 ps
CPU time 109.51 seconds
Started Aug 23 03:48:06 AM UTC 24
Finished Aug 23 03:49:58 AM UTC 24
Peak memory 217844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182117367 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3182117367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.2583226627
Short name T395
Test name
Test status
Simulation time 46548354612 ps
CPU time 73.98 seconds
Started Aug 23 03:48:02 AM UTC 24
Finished Aug 23 03:49:18 AM UTC 24
Peak memory 221892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2583226627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all
_with_rand_reset.2583226627
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.2888528426
Short name T643
Test name
Test status
Simulation time 514888864 ps
CPU time 1.74 seconds
Started Aug 23 03:47:51 AM UTC 24
Finished Aug 23 03:47:54 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888528426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2888528426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/31.uart_tx_rx.3848504830
Short name T638
Test name
Test status
Simulation time 20239174663 ps
CPU time 16.81 seconds
Started Aug 23 03:47:00 AM UTC 24
Finished Aug 23 03:47:18 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848504830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3848504830
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/31.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_alert_test.5502645
Short name T664
Test name
Test status
Simulation time 13656998 ps
CPU time 0.47 seconds
Started Aug 23 03:49:17 AM UTC 24
Finished Aug 23 03:49:18 AM UTC 24
Peak memory 203912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5502645 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.5502645
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_fifo_full.2727829766
Short name T654
Test name
Test status
Simulation time 16610757481 ps
CPU time 22.99 seconds
Started Aug 23 03:48:27 AM UTC 24
Finished Aug 23 03:48:51 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727829766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2727829766
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.323778477
Short name T663
Test name
Test status
Simulation time 32808772234 ps
CPU time 43.13 seconds
Started Aug 23 03:48:32 AM UTC 24
Finished Aug 23 03:49:16 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323778477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.323778477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_fifo_reset.4162080001
Short name T662
Test name
Test status
Simulation time 57513675711 ps
CPU time 29.26 seconds
Started Aug 23 03:48:46 AM UTC 24
Finished Aug 23 03:49:16 AM UTC 24
Peak memory 208436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162080001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.4162080001
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_intr.4075879514
Short name T661
Test name
Test status
Simulation time 60405804183 ps
CPU time 21.65 seconds
Started Aug 23 03:48:49 AM UTC 24
Finished Aug 23 03:49:12 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075879514 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4075879514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.3893657089
Short name T899
Test name
Test status
Simulation time 126610402768 ps
CPU time 704.62 seconds
Started Aug 23 03:49:10 AM UTC 24
Finished Aug 23 04:01:03 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893657089 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3893657089
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_loopback.745506787
Short name T660
Test name
Test status
Simulation time 4634616527 ps
CPU time 4.06 seconds
Started Aug 23 03:49:05 AM UTC 24
Finished Aug 23 03:49:11 AM UTC 24
Peak memory 207932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745506787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.uart_loopback.745506787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_noise_filter.2006028538
Short name T659
Test name
Test status
Simulation time 35790282482 ps
CPU time 16.69 seconds
Started Aug 23 03:48:52 AM UTC 24
Finished Aug 23 03:49:10 AM UTC 24
Peak memory 208452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006028538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2006028538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_perf.2540843644
Short name T685
Test name
Test status
Simulation time 6873952161 ps
CPU time 73.4 seconds
Started Aug 23 03:49:05 AM UTC 24
Finished Aug 23 03:50:21 AM UTC 24
Peak memory 208924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540843644 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2540843644
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_rx_oversample.3820743531
Short name T655
Test name
Test status
Simulation time 4989044385 ps
CPU time 9.94 seconds
Started Aug 23 03:48:46 AM UTC 24
Finished Aug 23 03:48:57 AM UTC 24
Peak memory 207764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820743531 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3820743531
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.935016777
Short name T670
Test name
Test status
Simulation time 96763276124 ps
CPU time 41.95 seconds
Started Aug 23 03:49:01 AM UTC 24
Finished Aug 23 03:49:45 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935016777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.935016777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.3586946491
Short name T656
Test name
Test status
Simulation time 4945251313 ps
CPU time 2.28 seconds
Started Aug 23 03:48:58 AM UTC 24
Finished Aug 23 03:49:01 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586946491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3586946491
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_smoke.3057330954
Short name T650
Test name
Test status
Simulation time 445140392 ps
CPU time 1.64 seconds
Started Aug 23 03:48:13 AM UTC 24
Finished Aug 23 03:48:16 AM UTC 24
Peak memory 206248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057330954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3057330954
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_stress_all.3412164363
Short name T825
Test name
Test status
Simulation time 202060921852 ps
CPU time 493.67 seconds
Started Aug 23 03:49:13 AM UTC 24
Finished Aug 23 03:57:32 AM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412164363 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3412164363
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.1674318149
Short name T669
Test name
Test status
Simulation time 2163849042 ps
CPU time 28.83 seconds
Started Aug 23 03:49:12 AM UTC 24
Finished Aug 23 03:49:42 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1674318149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all
_with_rand_reset.1674318149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.788112633
Short name T658
Test name
Test status
Simulation time 3851146910 ps
CPU time 1.13 seconds
Started Aug 23 03:49:02 AM UTC 24
Finished Aug 23 03:49:05 AM UTC 24
Peak memory 206252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788112633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.788112633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/32.uart_tx_rx.1375112129
Short name T666
Test name
Test status
Simulation time 46822350508 ps
CPU time 71.15 seconds
Started Aug 23 03:48:16 AM UTC 24
Finished Aug 23 03:49:29 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375112129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1375112129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/32.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_alert_test.1779069465
Short name T679
Test name
Test status
Simulation time 12301633 ps
CPU time 0.47 seconds
Started Aug 23 03:50:03 AM UTC 24
Finished Aug 23 03:50:05 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779069465 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1779069465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_fifo_full.1508489977
Short name T673
Test name
Test status
Simulation time 96989645636 ps
CPU time 32 seconds
Started Aug 23 03:49:19 AM UTC 24
Finished Aug 23 03:49:52 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508489977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1508489977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.2194060417
Short name T682
Test name
Test status
Simulation time 92809285896 ps
CPU time 53.1 seconds
Started Aug 23 03:49:20 AM UTC 24
Finished Aug 23 03:50:15 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194060417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2194060417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_fifo_reset.3767889849
Short name T675
Test name
Test status
Simulation time 258734776617 ps
CPU time 22.92 seconds
Started Aug 23 03:49:30 AM UTC 24
Finished Aug 23 03:49:54 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767889849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3767889849
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_intr.1637888194
Short name T678
Test name
Test status
Simulation time 13402559617 ps
CPU time 18.45 seconds
Started Aug 23 03:49:42 AM UTC 24
Finished Aug 23 03:50:02 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637888194 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1637888194
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.2621921204
Short name T730
Test name
Test status
Simulation time 41959981253 ps
CPU time 140.48 seconds
Started Aug 23 03:49:56 AM UTC 24
Finished Aug 23 03:52:19 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621921204 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2621921204
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_loopback.1821999458
Short name T680
Test name
Test status
Simulation time 5426734278 ps
CPU time 14.49 seconds
Started Aug 23 03:49:53 AM UTC 24
Finished Aug 23 03:50:08 AM UTC 24
Peak memory 208404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821999458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1821999458
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_noise_filter.2338669814
Short name T683
Test name
Test status
Simulation time 375609274600 ps
CPU time 31.51 seconds
Started Aug 23 03:49:43 AM UTC 24
Finished Aug 23 03:50:16 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338669814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2338669814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_perf.1509312122
Short name T699
Test name
Test status
Simulation time 15851707054 ps
CPU time 63.02 seconds
Started Aug 23 03:49:55 AM UTC 24
Finished Aug 23 03:50:59 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509312122 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1509312122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_rx_oversample.104155839
Short name T668
Test name
Test status
Simulation time 3693292416 ps
CPU time 5.33 seconds
Started Aug 23 03:49:35 AM UTC 24
Finished Aug 23 03:49:41 AM UTC 24
Peak memory 207356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104155839 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.104155839
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.2021507357
Short name T684
Test name
Test status
Simulation time 14843570006 ps
CPU time 27.3 seconds
Started Aug 23 03:49:48 AM UTC 24
Finished Aug 23 03:50:17 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021507357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2021507357
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.4127651514
Short name T671
Test name
Test status
Simulation time 603420003 ps
CPU time 1.45 seconds
Started Aug 23 03:49:45 AM UTC 24
Finished Aug 23 03:49:48 AM UTC 24
Peak memory 204436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127651514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4127651514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_smoke.449306352
Short name T665
Test name
Test status
Simulation time 909399936 ps
CPU time 1.74 seconds
Started Aug 23 03:49:17 AM UTC 24
Finished Aug 23 03:49:20 AM UTC 24
Peak memory 207680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449306352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.uart_smoke.449306352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_stress_all.322415765
Short name T407
Test name
Test status
Simulation time 48123218064 ps
CPU time 72.46 seconds
Started Aug 23 03:49:59 AM UTC 24
Finished Aug 23 03:51:13 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322415765 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.322415765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.2545069593
Short name T692
Test name
Test status
Simulation time 13912397106 ps
CPU time 36.81 seconds
Started Aug 23 03:49:57 AM UTC 24
Finished Aug 23 03:50:35 AM UTC 24
Peak memory 219844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2545069593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all
_with_rand_reset.2545069593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.1220898317
Short name T674
Test name
Test status
Simulation time 693839456 ps
CPU time 2.06 seconds
Started Aug 23 03:49:51 AM UTC 24
Finished Aug 23 03:49:54 AM UTC 24
Peak memory 207932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220898317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1220898317
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/33.uart_tx_rx.2147052558
Short name T698
Test name
Test status
Simulation time 59625776731 ps
CPU time 94.96 seconds
Started Aug 23 03:49:19 AM UTC 24
Finished Aug 23 03:50:56 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147052558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2147052558
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/33.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_alert_test.3009347335
Short name T695
Test name
Test status
Simulation time 20427515 ps
CPU time 0.48 seconds
Started Aug 23 03:50:43 AM UTC 24
Finished Aug 23 03:50:44 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009347335 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3009347335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_fifo_full.2344889896
Short name T693
Test name
Test status
Simulation time 64127367353 ps
CPU time 31.94 seconds
Started Aug 23 03:50:09 AM UTC 24
Finished Aug 23 03:50:42 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344889896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2344889896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.1549660334
Short name T697
Test name
Test status
Simulation time 105553451934 ps
CPU time 32.43 seconds
Started Aug 23 03:50:15 AM UTC 24
Finished Aug 23 03:50:49 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549660334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1549660334
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_fifo_reset.3278697232
Short name T706
Test name
Test status
Simulation time 187491152690 ps
CPU time 59.45 seconds
Started Aug 23 03:50:15 AM UTC 24
Finished Aug 23 03:51:16 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278697232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3278697232
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_intr.583144593
Short name T694
Test name
Test status
Simulation time 17680206109 ps
CPU time 24.03 seconds
Started Aug 23 03:50:17 AM UTC 24
Finished Aug 23 03:50:43 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583144593 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.583144593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.2945403224
Short name T834
Test name
Test status
Simulation time 138424173706 ps
CPU time 422.65 seconds
Started Aug 23 03:50:34 AM UTC 24
Finished Aug 23 03:57:42 AM UTC 24
Peak memory 212176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945403224 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2945403224
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_loopback.591082518
Short name T690
Test name
Test status
Simulation time 735075369 ps
CPU time 0.81 seconds
Started Aug 23 03:50:31 AM UTC 24
Finished Aug 23 03:50:33 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591082518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.uart_loopback.591082518
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_noise_filter.2022939973
Short name T710
Test name
Test status
Simulation time 153860473031 ps
CPU time 61.32 seconds
Started Aug 23 03:50:22 AM UTC 24
Finished Aug 23 03:51:24 AM UTC 24
Peak memory 208412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022939973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2022939973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_perf.4241769278
Short name T775
Test name
Test status
Simulation time 24784280426 ps
CPU time 254.07 seconds
Started Aug 23 03:50:31 AM UTC 24
Finished Aug 23 03:54:48 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241769278 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4241769278
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_rx_oversample.690746521
Short name T686
Test name
Test status
Simulation time 5207653250 ps
CPU time 8.2 seconds
Started Aug 23 03:50:16 AM UTC 24
Finished Aug 23 03:50:26 AM UTC 24
Peak memory 207488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690746521 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.690746521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.2005981806
Short name T696
Test name
Test status
Simulation time 10894137223 ps
CPU time 17.13 seconds
Started Aug 23 03:50:28 AM UTC 24
Finished Aug 23 03:50:46 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005981806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2005981806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.453063091
Short name T688
Test name
Test status
Simulation time 5267231349 ps
CPU time 2.32 seconds
Started Aug 23 03:50:27 AM UTC 24
Finished Aug 23 03:50:30 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453063091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.453063091
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_smoke.3691989565
Short name T681
Test name
Test status
Simulation time 6072097535 ps
CPU time 10.41 seconds
Started Aug 23 03:50:03 AM UTC 24
Finished Aug 23 03:50:15 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691989565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3691989565
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_stress_all.397835849
Short name T742
Test name
Test status
Simulation time 379691051098 ps
CPU time 134.54 seconds
Started Aug 23 03:50:35 AM UTC 24
Finished Aug 23 03:52:52 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397835849 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.397835849
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.704010887
Short name T399
Test name
Test status
Simulation time 16371013338 ps
CPU time 26.85 seconds
Started Aug 23 03:50:34 AM UTC 24
Finished Aug 23 03:51:02 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=704010887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all_
with_rand_reset.704010887
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.158144496
Short name T689
Test name
Test status
Simulation time 5862915743 ps
CPU time 1.43 seconds
Started Aug 23 03:50:28 AM UTC 24
Finished Aug 23 03:50:30 AM UTC 24
Peak memory 207764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158144496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.158144496
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/34.uart_tx_rx.791560772
Short name T704
Test name
Test status
Simulation time 147465907012 ps
CPU time 61.65 seconds
Started Aug 23 03:50:05 AM UTC 24
Finished Aug 23 03:51:08 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791560772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.791560772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/34.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_alert_test.2385704168
Short name T708
Test name
Test status
Simulation time 24196501 ps
CPU time 0.49 seconds
Started Aug 23 03:51:17 AM UTC 24
Finished Aug 23 03:51:19 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385704168 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2385704168
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_fifo_full.697882845
Short name T143
Test name
Test status
Simulation time 36421825720 ps
CPU time 30.27 seconds
Started Aug 23 03:50:45 AM UTC 24
Finished Aug 23 03:51:17 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697882845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.697882845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.423176408
Short name T700
Test name
Test status
Simulation time 36399805798 ps
CPU time 11.04 seconds
Started Aug 23 03:50:47 AM UTC 24
Finished Aug 23 03:50:59 AM UTC 24
Peak memory 207340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423176408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.423176408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_fifo_reset.2335682928
Short name T716
Test name
Test status
Simulation time 42211620972 ps
CPU time 59.49 seconds
Started Aug 23 03:50:49 AM UTC 24
Finished Aug 23 03:51:50 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335682928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2335682928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_intr.2974358937
Short name T702
Test name
Test status
Simulation time 14417811982 ps
CPU time 2.66 seconds
Started Aug 23 03:51:00 AM UTC 24
Finished Aug 23 03:51:03 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974358937 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2974358937
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.3925766943
Short name T964
Test name
Test status
Simulation time 93989839828 ps
CPU time 807.83 seconds
Started Aug 23 03:51:12 AM UTC 24
Finished Aug 23 04:04:48 AM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925766943 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3925766943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_loopback.3262647461
Short name T707
Test name
Test status
Simulation time 5952564228 ps
CPU time 9.82 seconds
Started Aug 23 03:51:05 AM UTC 24
Finished Aug 23 03:51:17 AM UTC 24
Peak memory 207888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262647461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3262647461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_noise_filter.115444318
Short name T750
Test name
Test status
Simulation time 82349962108 ps
CPU time 124.19 seconds
Started Aug 23 03:51:01 AM UTC 24
Finished Aug 23 03:53:07 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115444318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.115444318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_perf.3360859934
Short name T764
Test name
Test status
Simulation time 7775715806 ps
CPU time 171.07 seconds
Started Aug 23 03:51:09 AM UTC 24
Finished Aug 23 03:54:03 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360859934 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3360859934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_rx_oversample.2518428500
Short name T703
Test name
Test status
Simulation time 1895525981 ps
CPU time 7.18 seconds
Started Aug 23 03:50:57 AM UTC 24
Finished Aug 23 03:51:05 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518428500 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2518428500
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.2029410901
Short name T717
Test name
Test status
Simulation time 118570179048 ps
CPU time 44.77 seconds
Started Aug 23 03:51:04 AM UTC 24
Finished Aug 23 03:51:51 AM UTC 24
Peak memory 208388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029410901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2029410901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.2960865082
Short name T712
Test name
Test status
Simulation time 32849978045 ps
CPU time 23.69 seconds
Started Aug 23 03:51:03 AM UTC 24
Finished Aug 23 03:51:28 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960865082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2960865082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_smoke.3352963039
Short name T701
Test name
Test status
Simulation time 5808312362 ps
CPU time 17.75 seconds
Started Aug 23 03:50:44 AM UTC 24
Finished Aug 23 03:51:03 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352963039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3352963039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_stress_all.1246368396
Short name T918
Test name
Test status
Simulation time 219789926868 ps
CPU time 637.26 seconds
Started Aug 23 03:51:17 AM UTC 24
Finished Aug 23 04:02:01 AM UTC 24
Peak memory 212272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246368396 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1246368396
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.2793002331
Short name T705
Test name
Test status
Simulation time 7282356100 ps
CPU time 5.92 seconds
Started Aug 23 03:51:04 AM UTC 24
Finished Aug 23 03:51:11 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793002331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2793002331
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/35.uart_tx_rx.4112453765
Short name T711
Test name
Test status
Simulation time 31825287168 ps
CPU time 41.3 seconds
Started Aug 23 03:50:44 AM UTC 24
Finished Aug 23 03:51:26 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112453765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.4112453765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/35.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_alert_test.2304272398
Short name T724
Test name
Test status
Simulation time 12236107 ps
CPU time 0.49 seconds
Started Aug 23 03:51:58 AM UTC 24
Finished Aug 23 03:52:00 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304272398 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2304272398
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_fifo_full.2472199987
Short name T721
Test name
Test status
Simulation time 156928225842 ps
CPU time 32.65 seconds
Started Aug 23 03:51:21 AM UTC 24
Finished Aug 23 03:51:55 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472199987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2472199987
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.441661543
Short name T774
Test name
Test status
Simulation time 78677053081 ps
CPU time 196.75 seconds
Started Aug 23 03:51:25 AM UTC 24
Finished Aug 23 03:54:44 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441661543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.441661543
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_fifo_reset.955003367
Short name T770
Test name
Test status
Simulation time 264555997421 ps
CPU time 176.78 seconds
Started Aug 23 03:51:27 AM UTC 24
Finished Aug 23 03:54:26 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955003367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.955003367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_intr.3559234111
Short name T728
Test name
Test status
Simulation time 56052168864 ps
CPU time 27.9 seconds
Started Aug 23 03:51:34 AM UTC 24
Finished Aug 23 03:52:04 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559234111 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3559234111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.708675336
Short name T791
Test name
Test status
Simulation time 86225728076 ps
CPU time 232.58 seconds
Started Aug 23 03:51:54 AM UTC 24
Finished Aug 23 03:55:50 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708675336 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.708675336
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_loopback.4128534714
Short name T722
Test name
Test status
Simulation time 9170574047 ps
CPU time 5.53 seconds
Started Aug 23 03:51:51 AM UTC 24
Finished Aug 23 03:51:58 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128534714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.uart_loopback.4128534714
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_noise_filter.2368853735
Short name T726
Test name
Test status
Simulation time 14635249741 ps
CPU time 25.12 seconds
Started Aug 23 03:51:36 AM UTC 24
Finished Aug 23 03:52:02 AM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368853735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2368853735
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_perf.4039377962
Short name T853
Test name
Test status
Simulation time 9419711402 ps
CPU time 432.54 seconds
Started Aug 23 03:51:52 AM UTC 24
Finished Aug 23 03:59:10 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039377962 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4039377962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_rx_oversample.2330573314
Short name T714
Test name
Test status
Simulation time 7178602405 ps
CPU time 14.18 seconds
Started Aug 23 03:51:29 AM UTC 24
Finished Aug 23 03:51:45 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330573314 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2330573314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.3987721697
Short name T727
Test name
Test status
Simulation time 30498789479 ps
CPU time 15.11 seconds
Started Aug 23 03:51:47 AM UTC 24
Finished Aug 23 03:52:03 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987721697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3987721697
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.3850154925
Short name T718
Test name
Test status
Simulation time 2742923287 ps
CPU time 4.25 seconds
Started Aug 23 03:51:46 AM UTC 24
Finished Aug 23 03:51:51 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850154925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3850154925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_smoke.3468550456
Short name T709
Test name
Test status
Simulation time 915126574 ps
CPU time 1.78 seconds
Started Aug 23 03:51:17 AM UTC 24
Finished Aug 23 03:51:20 AM UTC 24
Peak memory 206340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468550456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3468550456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_stress_all.4162049758
Short name T814
Test name
Test status
Simulation time 233569515942 ps
CPU time 311.41 seconds
Started Aug 23 03:51:56 AM UTC 24
Finished Aug 23 03:57:11 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162049758 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4162049758
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.2718215643
Short name T152
Test name
Test status
Simulation time 4264096253 ps
CPU time 20.09 seconds
Started Aug 23 03:51:56 AM UTC 24
Finished Aug 23 03:52:17 AM UTC 24
Peak memory 225332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2718215643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all
_with_rand_reset.2718215643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.3766704944
Short name T720
Test name
Test status
Simulation time 893043733 ps
CPU time 2.31 seconds
Started Aug 23 03:51:51 AM UTC 24
Finished Aug 23 03:51:55 AM UTC 24
Peak memory 207160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766704944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3766704944
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/36.uart_tx_rx.2729157543
Short name T406
Test name
Test status
Simulation time 444610489718 ps
CPU time 41.52 seconds
Started Aug 23 03:51:20 AM UTC 24
Finished Aug 23 03:52:03 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729157543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2729157543
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/36.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_alert_test.768298419
Short name T739
Test name
Test status
Simulation time 20040174 ps
CPU time 0.47 seconds
Started Aug 23 03:52:33 AM UTC 24
Finished Aug 23 03:52:34 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768298419 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.768298419
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_fifo_full.4030858606
Short name T773
Test name
Test status
Simulation time 139795862978 ps
CPU time 154.27 seconds
Started Aug 23 03:52:03 AM UTC 24
Finished Aug 23 03:54:40 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030858606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4030858606
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.2204569813
Short name T729
Test name
Test status
Simulation time 92386556933 ps
CPU time 8.04 seconds
Started Aug 23 03:52:05 AM UTC 24
Finished Aug 23 03:52:14 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204569813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2204569813
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_fifo_reset.2112817008
Short name T736
Test name
Test status
Simulation time 17255244085 ps
CPU time 25.07 seconds
Started Aug 23 03:52:05 AM UTC 24
Finished Aug 23 03:52:31 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112817008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2112817008
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_intr.2056308956
Short name T758
Test name
Test status
Simulation time 211780365221 ps
CPU time 82.18 seconds
Started Aug 23 03:52:15 AM UTC 24
Finished Aug 23 03:53:39 AM UTC 24
Peak memory 208472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056308956 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2056308956
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.3473281069
Short name T776
Test name
Test status
Simulation time 99752193322 ps
CPU time 137.66 seconds
Started Aug 23 03:52:28 AM UTC 24
Finished Aug 23 03:54:48 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473281069 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3473281069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_loopback.4284434965
Short name T735
Test name
Test status
Simulation time 2626365654 ps
CPU time 1.93 seconds
Started Aug 23 03:52:24 AM UTC 24
Finished Aug 23 03:52:27 AM UTC 24
Peak memory 206444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284434965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4284434965
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_noise_filter.2667623775
Short name T746
Test name
Test status
Simulation time 23966542207 ps
CPU time 35.91 seconds
Started Aug 23 03:52:18 AM UTC 24
Finished Aug 23 03:52:55 AM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667623775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2667623775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_perf.1690041298
Short name T789
Test name
Test status
Simulation time 9978403641 ps
CPU time 198.37 seconds
Started Aug 23 03:52:26 AM UTC 24
Finished Aug 23 03:55:47 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690041298 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1690041298
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_rx_oversample.3095820114
Short name T738
Test name
Test status
Simulation time 7000879301 ps
CPU time 26.15 seconds
Started Aug 23 03:52:05 AM UTC 24
Finished Aug 23 03:52:32 AM UTC 24
Peak memory 208232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095820114 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3095820114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.625641218
Short name T424
Test name
Test status
Simulation time 35699169389 ps
CPU time 49.02 seconds
Started Aug 23 03:52:19 AM UTC 24
Finished Aug 23 03:53:10 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625641218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.625641218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.643882997
Short name T732
Test name
Test status
Simulation time 5567484438 ps
CPU time 1.21 seconds
Started Aug 23 03:52:19 AM UTC 24
Finished Aug 23 03:52:22 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643882997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.643882997
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_smoke.839517868
Short name T733
Test name
Test status
Simulation time 5819699286 ps
CPU time 21.44 seconds
Started Aug 23 03:52:01 AM UTC 24
Finished Aug 23 03:52:23 AM UTC 24
Peak memory 207988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839517868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.uart_smoke.839517868
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_stress_all.576916296
Short name T797
Test name
Test status
Simulation time 93752217637 ps
CPU time 205.21 seconds
Started Aug 23 03:52:32 AM UTC 24
Finished Aug 23 03:56:00 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576916296 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.576916296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.21946031
Short name T744
Test name
Test status
Simulation time 1732377636 ps
CPU time 19.16 seconds
Started Aug 23 03:52:32 AM UTC 24
Finished Aug 23 03:52:52 AM UTC 24
Peak memory 219772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=21946031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all_w
ith_rand_reset.21946031
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.778349919
Short name T734
Test name
Test status
Simulation time 546380483 ps
CPU time 1.61 seconds
Started Aug 23 03:52:23 AM UTC 24
Finished Aug 23 03:52:26 AM UTC 24
Peak memory 206444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778349919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.778349919
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/37.uart_tx_rx.555057748
Short name T731
Test name
Test status
Simulation time 19893595589 ps
CPU time 16.7 seconds
Started Aug 23 03:52:01 AM UTC 24
Finished Aug 23 03:52:19 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555057748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.555057748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/37.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_alert_test.3962769978
Short name T754
Test name
Test status
Simulation time 11965956 ps
CPU time 0.47 seconds
Started Aug 23 03:53:22 AM UTC 24
Finished Aug 23 03:53:23 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962769978 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3962769978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_fifo_full.1618570171
Short name T761
Test name
Test status
Simulation time 44694469755 ps
CPU time 70.99 seconds
Started Aug 23 03:52:45 AM UTC 24
Finished Aug 23 03:53:57 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618570171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1618570171
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.3438049919
Short name T753
Test name
Test status
Simulation time 14128837476 ps
CPU time 18.31 seconds
Started Aug 23 03:52:51 AM UTC 24
Finished Aug 23 03:53:10 AM UTC 24
Peak memory 207752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438049919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3438049919
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_fifo_reset.1318290283
Short name T186
Test name
Test status
Simulation time 34307352295 ps
CPU time 26.06 seconds
Started Aug 23 03:52:53 AM UTC 24
Finished Aug 23 03:53:21 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318290283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1318290283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_intr.701956212
Short name T747
Test name
Test status
Simulation time 1807726472 ps
CPU time 3.14 seconds
Started Aug 23 03:52:55 AM UTC 24
Finished Aug 23 03:52:59 AM UTC 24
Peak memory 207080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701956212 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.701956212
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.1942392215
Short name T854
Test name
Test status
Simulation time 63835619721 ps
CPU time 362 seconds
Started Aug 23 03:53:11 AM UTC 24
Finished Aug 23 03:59:18 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942392215 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1942392215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_loopback.3764156196
Short name T752
Test name
Test status
Simulation time 1346143137 ps
CPU time 1.15 seconds
Started Aug 23 03:53:08 AM UTC 24
Finished Aug 23 03:53:10 AM UTC 24
Peak memory 207100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764156196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3764156196
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_noise_filter.3103561980
Short name T759
Test name
Test status
Simulation time 107261289629 ps
CPU time 45.51 seconds
Started Aug 23 03:52:56 AM UTC 24
Finished Aug 23 03:53:43 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103561980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3103561980
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_perf.2630471274
Short name T800
Test name
Test status
Simulation time 15134715935 ps
CPU time 170.06 seconds
Started Aug 23 03:53:09 AM UTC 24
Finished Aug 23 03:56:02 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630471274 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2630471274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_rx_oversample.2822517743
Short name T748
Test name
Test status
Simulation time 4575514116 ps
CPU time 7.02 seconds
Started Aug 23 03:52:53 AM UTC 24
Finished Aug 23 03:53:02 AM UTC 24
Peak memory 207476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822517743 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2822517743
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.3022506945
Short name T769
Test name
Test status
Simulation time 54493296756 ps
CPU time 81.53 seconds
Started Aug 23 03:53:02 AM UTC 24
Finished Aug 23 03:54:25 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022506945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3022506945
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.3361878852
Short name T749
Test name
Test status
Simulation time 5704147991 ps
CPU time 2.35 seconds
Started Aug 23 03:53:00 AM UTC 24
Finished Aug 23 03:53:03 AM UTC 24
Peak memory 205104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361878852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3361878852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_smoke.4185559189
Short name T740
Test name
Test status
Simulation time 498475354 ps
CPU time 1.12 seconds
Started Aug 23 03:52:35 AM UTC 24
Finished Aug 23 03:52:38 AM UTC 24
Peak memory 206380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185559189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4185559189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_stress_all.1175953344
Short name T1130
Test name
Test status
Simulation time 286127280117 ps
CPU time 1197.79 seconds
Started Aug 23 03:53:12 AM UTC 24
Finished Aug 23 04:13:21 AM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175953344 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1175953344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.1174745611
Short name T760
Test name
Test status
Simulation time 14875728442 ps
CPU time 34.07 seconds
Started Aug 23 03:53:12 AM UTC 24
Finished Aug 23 03:53:47 AM UTC 24
Peak memory 217948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1174745611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all
_with_rand_reset.1174745611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.60608287
Short name T751
Test name
Test status
Simulation time 1108477064 ps
CPU time 2.56 seconds
Started Aug 23 03:53:04 AM UTC 24
Finished Aug 23 03:53:08 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60608287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.60608287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/38.uart_tx_rx.3555593611
Short name T745
Test name
Test status
Simulation time 67883574661 ps
CPU time 13.56 seconds
Started Aug 23 03:52:38 AM UTC 24
Finished Aug 23 03:52:53 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555593611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3555593611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/38.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_alert_test.3183354536
Short name T771
Test name
Test status
Simulation time 14753593 ps
CPU time 0.47 seconds
Started Aug 23 03:54:27 AM UTC 24
Finished Aug 23 03:54:28 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183354536 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3183354536
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_fifo_full.1576692319
Short name T763
Test name
Test status
Simulation time 28035678604 ps
CPU time 23.25 seconds
Started Aug 23 03:53:35 AM UTC 24
Finished Aug 23 03:53:59 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576692319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1576692319
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_fifo_reset.3231375814
Short name T232
Test name
Test status
Simulation time 13678568677 ps
CPU time 21.72 seconds
Started Aug 23 03:53:40 AM UTC 24
Finished Aug 23 03:54:03 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231375814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3231375814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_intr.3778615809
Short name T767
Test name
Test status
Simulation time 48252519860 ps
CPU time 22.35 seconds
Started Aug 23 03:53:48 AM UTC 24
Finished Aug 23 03:54:12 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778615809 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3778615809
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.3717778780
Short name T792
Test name
Test status
Simulation time 205469295065 ps
CPU time 99.62 seconds
Started Aug 23 03:54:08 AM UTC 24
Finished Aug 23 03:55:50 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717778780 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3717778780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_loopback.3961750455
Short name T765
Test name
Test status
Simulation time 1843079014 ps
CPU time 0.97 seconds
Started Aug 23 03:54:04 AM UTC 24
Finished Aug 23 03:54:05 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961750455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3961750455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_noise_filter.3331107234
Short name T787
Test name
Test status
Simulation time 59768479060 ps
CPU time 98.59 seconds
Started Aug 23 03:53:59 AM UTC 24
Finished Aug 23 03:55:39 AM UTC 24
Peak memory 208412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331107234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3331107234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_perf.672700821
Short name T938
Test name
Test status
Simulation time 14254098233 ps
CPU time 545.38 seconds
Started Aug 23 03:54:07 AM UTC 24
Finished Aug 23 04:03:18 AM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672700821 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.672700821
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_rx_oversample.1104527852
Short name T762
Test name
Test status
Simulation time 6952206551 ps
CPU time 13.41 seconds
Started Aug 23 03:53:44 AM UTC 24
Finished Aug 23 03:53:59 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104527852 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1104527852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.2414611719
Short name T788
Test name
Test status
Simulation time 148531565535 ps
CPU time 100.66 seconds
Started Aug 23 03:54:00 AM UTC 24
Finished Aug 23 03:55:43 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414611719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2414611719
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.2661785591
Short name T777
Test name
Test status
Simulation time 43638043315 ps
CPU time 50.97 seconds
Started Aug 23 03:54:00 AM UTC 24
Finished Aug 23 03:54:52 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661785591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2661785591
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_smoke.3676307905
Short name T755
Test name
Test status
Simulation time 443621236 ps
CPU time 1.8 seconds
Started Aug 23 03:53:24 AM UTC 24
Finished Aug 23 03:53:27 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676307905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3676307905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_stress_all.3178364568
Short name T831
Test name
Test status
Simulation time 251380920406 ps
CPU time 203.31 seconds
Started Aug 23 03:54:14 AM UTC 24
Finished Aug 23 03:57:40 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178364568 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3178364568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.247317387
Short name T778
Test name
Test status
Simulation time 54111966886 ps
CPU time 46.42 seconds
Started Aug 23 03:54:13 AM UTC 24
Finished Aug 23 03:55:01 AM UTC 24
Peak memory 223784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=247317387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all_
with_rand_reset.247317387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1295569841
Short name T766
Test name
Test status
Simulation time 410195868 ps
CPU time 1.89 seconds
Started Aug 23 03:54:03 AM UTC 24
Finished Aug 23 03:54:06 AM UTC 24
Peak memory 206380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295569841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1295569841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/39.uart_tx_rx.361091414
Short name T756
Test name
Test status
Simulation time 3130259161 ps
CPU time 5.27 seconds
Started Aug 23 03:53:27 AM UTC 24
Finished Aug 23 03:53:34 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361091414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.361091414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/39.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_alert_test.959742252
Short name T431
Test name
Test status
Simulation time 11607482 ps
CPU time 0.47 seconds
Started Aug 23 03:25:02 AM UTC 24
Finished Aug 23 03:25:03 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959742252 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.959742252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_fifo_full.92720727
Short name T135
Test name
Test status
Simulation time 7496249692 ps
CPU time 4.39 seconds
Started Aug 23 03:24:33 AM UTC 24
Finished Aug 23 03:24:39 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92720727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.92720727
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.1608443030
Short name T47
Test name
Test status
Simulation time 215763238979 ps
CPU time 70.97 seconds
Started Aug 23 03:24:37 AM UTC 24
Finished Aug 23 03:25:50 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608443030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1608443030
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_fifo_reset.3793643846
Short name T261
Test name
Test status
Simulation time 61812033861 ps
CPU time 29.52 seconds
Started Aug 23 03:24:37 AM UTC 24
Finished Aug 23 03:25:08 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793643846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3793643846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.3693688254
Short name T294
Test name
Test status
Simulation time 39259362512 ps
CPU time 145.27 seconds
Started Aug 23 03:24:56 AM UTC 24
Finished Aug 23 03:27:24 AM UTC 24
Peak memory 208976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693688254 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3693688254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_loopback.832841157
Short name T404
Test name
Test status
Simulation time 3933206262 ps
CPU time 7.44 seconds
Started Aug 23 03:24:50 AM UTC 24
Finished Aug 23 03:24:59 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832841157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.uart_loopback.832841157
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_noise_filter.3346348708
Short name T328
Test name
Test status
Simulation time 12401520375 ps
CPU time 18.75 seconds
Started Aug 23 03:24:40 AM UTC 24
Finished Aug 23 03:25:00 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346348708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3346348708
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_perf.3817329812
Short name T634
Test name
Test status
Simulation time 24705585296 ps
CPU time 1310.82 seconds
Started Aug 23 03:24:53 AM UTC 24
Finished Aug 23 03:46:58 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817329812 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3817329812
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_rx_oversample.393482048
Short name T430
Test name
Test status
Simulation time 2012675447 ps
CPU time 8.5 seconds
Started Aug 23 03:24:38 AM UTC 24
Finished Aug 23 03:24:48 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393482048 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.393482048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.178444544
Short name T112
Test name
Test status
Simulation time 19431892786 ps
CPU time 13.42 seconds
Started Aug 23 03:24:46 AM UTC 24
Finished Aug 23 03:25:01 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178444544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.178444544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.3140375643
Short name T306
Test name
Test status
Simulation time 35841423537 ps
CPU time 12.23 seconds
Started Aug 23 03:24:42 AM UTC 24
Finished Aug 23 03:24:55 AM UTC 24
Peak memory 205024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140375643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3140375643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_sec_cm.3314545883
Short name T85
Test name
Test status
Simulation time 38000442 ps
CPU time 0.69 seconds
Started Aug 23 03:25:02 AM UTC 24
Finished Aug 23 03:25:03 AM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314545883 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3314545883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_smoke.3564615146
Short name T349
Test name
Test status
Simulation time 531805838 ps
CPU time 1.51 seconds
Started Aug 23 03:24:29 AM UTC 24
Finished Aug 23 03:24:32 AM UTC 24
Peak memory 208484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564615146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3564615146
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.3700360683
Short name T351
Test name
Test status
Simulation time 7307641768 ps
CPU time 11.32 seconds
Started Aug 23 03:24:48 AM UTC 24
Finished Aug 23 03:25:01 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700360683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3700360683
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/4.uart_tx_rx.238794343
Short name T45
Test name
Test status
Simulation time 31884224622 ps
CPU time 47.38 seconds
Started Aug 23 03:24:32 AM UTC 24
Finished Aug 23 03:25:21 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238794343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.238794343
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_alert_test.1100258714
Short name T785
Test name
Test status
Simulation time 13441365 ps
CPU time 0.46 seconds
Started Aug 23 03:55:28 AM UTC 24
Finished Aug 23 03:55:29 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100258714 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1100258714
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_fifo_full.2780034624
Short name T815
Test name
Test status
Simulation time 123901847887 ps
CPU time 159.65 seconds
Started Aug 23 03:54:32 AM UTC 24
Finished Aug 23 03:57:15 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780034624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2780034624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.98062677
Short name T780
Test name
Test status
Simulation time 53414713792 ps
CPU time 28.23 seconds
Started Aug 23 03:54:41 AM UTC 24
Finished Aug 23 03:55:10 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98062677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.98062677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_fifo_reset.1232464818
Short name T779
Test name
Test status
Simulation time 54346805262 ps
CPU time 19.53 seconds
Started Aug 23 03:54:46 AM UTC 24
Finished Aug 23 03:55:07 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232464818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1232464818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_intr.8699790
Short name T821
Test name
Test status
Simulation time 478298717973 ps
CPU time 155.37 seconds
Started Aug 23 03:54:49 AM UTC 24
Finished Aug 23 03:57:27 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8699790 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.8699790
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.3011269423
Short name T887
Test name
Test status
Simulation time 128245117942 ps
CPU time 318.51 seconds
Started Aug 23 03:55:17 AM UTC 24
Finished Aug 23 04:00:39 AM UTC 24
Peak memory 212404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011269423 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3011269423
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_loopback.1583482746
Short name T783
Test name
Test status
Simulation time 5519084649 ps
CPU time 7.87 seconds
Started Aug 23 03:55:11 AM UTC 24
Finished Aug 23 03:55:20 AM UTC 24
Peak memory 207760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583482746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1583482746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_noise_filter.1234540037
Short name T784
Test name
Test status
Simulation time 34476556208 ps
CPU time 31.89 seconds
Started Aug 23 03:54:54 AM UTC 24
Finished Aug 23 03:55:27 AM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234540037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1234540037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_perf.2369815877
Short name T868
Test name
Test status
Simulation time 11437047138 ps
CPU time 263.34 seconds
Started Aug 23 03:55:16 AM UTC 24
Finished Aug 23 03:59:42 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369815877 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2369815877
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_rx_oversample.409040131
Short name T781
Test name
Test status
Simulation time 3483029174 ps
CPU time 24.94 seconds
Started Aug 23 03:54:49 AM UTC 24
Finished Aug 23 03:55:16 AM UTC 24
Peak memory 207356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409040131 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.409040131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.3271742220
Short name T153
Test name
Test status
Simulation time 35377802453 ps
CPU time 12.02 seconds
Started Aug 23 03:55:02 AM UTC 24
Finished Aug 23 03:55:15 AM UTC 24
Peak memory 208024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271742220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3271742220
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.2546582559
Short name T793
Test name
Test status
Simulation time 40817119475 ps
CPU time 54.08 seconds
Started Aug 23 03:54:55 AM UTC 24
Finished Aug 23 03:55:50 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546582559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2546582559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_smoke.2439683360
Short name T772
Test name
Test status
Simulation time 508790231 ps
CPU time 2.37 seconds
Started Aug 23 03:54:28 AM UTC 24
Finished Aug 23 03:54:31 AM UTC 24
Peak memory 207996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439683360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2439683360
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_stress_all.2159753433
Short name T808
Test name
Test status
Simulation time 283380581018 ps
CPU time 74.35 seconds
Started Aug 23 03:55:21 AM UTC 24
Finished Aug 23 03:56:37 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159753433 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2159753433
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.589551868
Short name T107
Test name
Test status
Simulation time 31652014511 ps
CPU time 60.31 seconds
Started Aug 23 03:55:18 AM UTC 24
Finished Aug 23 03:56:20 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=589551868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all_
with_rand_reset.589551868
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.1772327182
Short name T782
Test name
Test status
Simulation time 7115506694 ps
CPU time 8.93 seconds
Started Aug 23 03:55:07 AM UTC 24
Finished Aug 23 03:55:17 AM UTC 24
Peak memory 208408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772327182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1772327182
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/40.uart_tx_rx.2681404226
Short name T804
Test name
Test status
Simulation time 84141675309 ps
CPU time 116.68 seconds
Started Aug 23 03:54:29 AM UTC 24
Finished Aug 23 03:56:28 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681404226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2681404226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/40.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_alert_test.1858853234
Short name T802
Test name
Test status
Simulation time 69645073 ps
CPU time 0.48 seconds
Started Aug 23 03:56:02 AM UTC 24
Finished Aug 23 03:56:04 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858853234 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1858853234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_fifo_full.3101981154
Short name T818
Test name
Test status
Simulation time 122897300611 ps
CPU time 96.21 seconds
Started Aug 23 03:55:40 AM UTC 24
Finished Aug 23 03:57:18 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101981154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3101981154
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.2445670931
Short name T856
Test name
Test status
Simulation time 165210347928 ps
CPU time 216.21 seconds
Started Aug 23 03:55:43 AM UTC 24
Finished Aug 23 03:59:23 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445670931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2445670931
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_intr.1069417733
Short name T798
Test name
Test status
Simulation time 9114329672 ps
CPU time 7.57 seconds
Started Aug 23 03:55:52 AM UTC 24
Finished Aug 23 03:56:00 AM UTC 24
Peak memory 208484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069417733 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1069417733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.1036721642
Short name T861
Test name
Test status
Simulation time 67321878248 ps
CPU time 205.74 seconds
Started Aug 23 03:56:01 AM UTC 24
Finished Aug 23 03:59:30 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036721642 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1036721642
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_loopback.386821996
Short name T799
Test name
Test status
Simulation time 997372919 ps
CPU time 0.91 seconds
Started Aug 23 03:55:58 AM UTC 24
Finished Aug 23 03:56:00 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386821996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.uart_loopback.386821996
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_noise_filter.977752120
Short name T842
Test name
Test status
Simulation time 197378591073 ps
CPU time 135.32 seconds
Started Aug 23 03:55:52 AM UTC 24
Finished Aug 23 03:58:09 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977752120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.977752120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_perf.797301664
Short name T846
Test name
Test status
Simulation time 13255492354 ps
CPU time 148.59 seconds
Started Aug 23 03:56:01 AM UTC 24
Finished Aug 23 03:58:32 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797301664 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.797301664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_rx_oversample.3610589339
Short name T801
Test name
Test status
Simulation time 1923568352 ps
CPU time 10.58 seconds
Started Aug 23 03:55:50 AM UTC 24
Finished Aug 23 03:56:02 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610589339 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3610589339
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.1495595855
Short name T812
Test name
Test status
Simulation time 92543710031 ps
CPU time 62.09 seconds
Started Aug 23 03:55:55 AM UTC 24
Finished Aug 23 03:56:59 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495595855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1495595855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.581796400
Short name T795
Test name
Test status
Simulation time 2613233478 ps
CPU time 1.42 seconds
Started Aug 23 03:55:52 AM UTC 24
Finished Aug 23 03:55:54 AM UTC 24
Peak memory 206424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581796400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.581796400
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_smoke.3111342249
Short name T786
Test name
Test status
Simulation time 514413868 ps
CPU time 1.25 seconds
Started Aug 23 03:55:30 AM UTC 24
Finished Aug 23 03:55:32 AM UTC 24
Peak memory 208068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111342249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3111342249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_stress_all.1935453624
Short name T898
Test name
Test status
Simulation time 439471169358 ps
CPU time 293.98 seconds
Started Aug 23 03:56:02 AM UTC 24
Finished Aug 23 04:01:00 AM UTC 24
Peak memory 219136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935453624 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1935453624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.1316035234
Short name T828
Test name
Test status
Simulation time 17578242165 ps
CPU time 93.87 seconds
Started Aug 23 03:56:01 AM UTC 24
Finished Aug 23 03:57:37 AM UTC 24
Peak memory 222044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1316035234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all
_with_rand_reset.1316035234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.2457800668
Short name T796
Test name
Test status
Simulation time 1710140654 ps
CPU time 1.75 seconds
Started Aug 23 03:55:55 AM UTC 24
Finished Aug 23 03:55:58 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457800668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2457800668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/41.uart_tx_rx.658964030
Short name T806
Test name
Test status
Simulation time 137823965080 ps
CPU time 58.39 seconds
Started Aug 23 03:55:33 AM UTC 24
Finished Aug 23 03:56:33 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658964030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.658964030
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/41.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_alert_test.3998409285
Short name T817
Test name
Test status
Simulation time 17052622 ps
CPU time 0.49 seconds
Started Aug 23 03:57:16 AM UTC 24
Finished Aug 23 03:57:18 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998409285 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3998409285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_fifo_full.1943205420
Short name T840
Test name
Test status
Simulation time 67087913799 ps
CPU time 98.59 seconds
Started Aug 23 03:56:21 AM UTC 24
Finished Aug 23 03:58:02 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943205420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1943205420
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.3091767654
Short name T813
Test name
Test status
Simulation time 45165426161 ps
CPU time 37.41 seconds
Started Aug 23 03:56:22 AM UTC 24
Finished Aug 23 03:57:01 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091767654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3091767654
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_fifo_reset.3728150346
Short name T169
Test name
Test status
Simulation time 12982825405 ps
CPU time 11.75 seconds
Started Aug 23 03:56:30 AM UTC 24
Finished Aug 23 03:56:43 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728150346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3728150346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_intr.4273359225
Short name T819
Test name
Test status
Simulation time 30499914202 ps
CPU time 47.52 seconds
Started Aug 23 03:56:34 AM UTC 24
Finished Aug 23 03:57:23 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273359225 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.4273359225
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.3868425266
Short name T978
Test name
Test status
Simulation time 117526671397 ps
CPU time 502.59 seconds
Started Aug 23 03:57:00 AM UTC 24
Finished Aug 23 04:05:28 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868425266 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3868425266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_loopback.761355905
Short name T811
Test name
Test status
Simulation time 4382149632 ps
CPU time 7.9 seconds
Started Aug 23 03:56:49 AM UTC 24
Finished Aug 23 03:56:58 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761355905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.uart_loopback.761355905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_noise_filter.1481164961
Short name T823
Test name
Test status
Simulation time 73307136593 ps
CPU time 53.9 seconds
Started Aug 23 03:56:35 AM UTC 24
Finished Aug 23 03:57:31 AM UTC 24
Peak memory 208908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481164961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1481164961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_perf.1169554079
Short name T946
Test name
Test status
Simulation time 25913073745 ps
CPU time 403.83 seconds
Started Aug 23 03:57:00 AM UTC 24
Finished Aug 23 04:03:48 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169554079 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1169554079
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_rx_oversample.3674355879
Short name T807
Test name
Test status
Simulation time 1811881744 ps
CPU time 3.2 seconds
Started Aug 23 03:56:30 AM UTC 24
Finished Aug 23 03:56:34 AM UTC 24
Peak memory 207348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674355879 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3674355879
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.1741482211
Short name T409
Test name
Test status
Simulation time 108528019772 ps
CPU time 36.26 seconds
Started Aug 23 03:56:42 AM UTC 24
Finished Aug 23 03:57:19 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741482211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1741482211
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.145742156
Short name T809
Test name
Test status
Simulation time 721948335 ps
CPU time 1.57 seconds
Started Aug 23 03:56:38 AM UTC 24
Finished Aug 23 03:56:41 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145742156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.145742156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_smoke.3190207550
Short name T803
Test name
Test status
Simulation time 5965785146 ps
CPU time 6.45 seconds
Started Aug 23 03:56:05 AM UTC 24
Finished Aug 23 03:56:12 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190207550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3190207550
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_stress_all.2879620949
Short name T858
Test name
Test status
Simulation time 12723308229 ps
CPU time 130.52 seconds
Started Aug 23 03:57:12 AM UTC 24
Finished Aug 23 03:59:25 AM UTC 24
Peak memory 208844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879620949 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2879620949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.1719197534
Short name T816
Test name
Test status
Simulation time 2821669440 ps
CPU time 13.22 seconds
Started Aug 23 03:57:02 AM UTC 24
Finished Aug 23 03:57:16 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1719197534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all
_with_rand_reset.1719197534
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.2946797633
Short name T810
Test name
Test status
Simulation time 963877954 ps
CPU time 3.66 seconds
Started Aug 23 03:56:44 AM UTC 24
Finished Aug 23 03:56:49 AM UTC 24
Peak memory 207172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946797633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2946797633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/42.uart_tx_rx.1925585900
Short name T805
Test name
Test status
Simulation time 104150565432 ps
CPU time 14.9 seconds
Started Aug 23 03:56:13 AM UTC 24
Finished Aug 23 03:56:29 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925585900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1925585900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/42.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_alert_test.3830355753
Short name T835
Test name
Test status
Simulation time 36640318 ps
CPU time 0.49 seconds
Started Aug 23 03:57:42 AM UTC 24
Finished Aug 23 03:57:44 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830355753 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3830355753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_fifo_full.1109350973
Short name T864
Test name
Test status
Simulation time 236023492378 ps
CPU time 131.41 seconds
Started Aug 23 03:57:19 AM UTC 24
Finished Aug 23 03:59:33 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109350973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1109350973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.3713590522
Short name T839
Test name
Test status
Simulation time 19541955115 ps
CPU time 38.24 seconds
Started Aug 23 03:57:20 AM UTC 24
Finished Aug 23 03:58:00 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713590522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3713590522
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_fifo_reset.286798139
Short name T240
Test name
Test status
Simulation time 84195814193 ps
CPU time 142.9 seconds
Started Aug 23 03:57:25 AM UTC 24
Finished Aug 23 03:59:50 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286798139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.286798139
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_intr.1040573277
Short name T743
Test name
Test status
Simulation time 5495822159 ps
CPU time 1.45 seconds
Started Aug 23 03:57:28 AM UTC 24
Finished Aug 23 03:57:30 AM UTC 24
Peak memory 204500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040573277 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1040573277
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.2827343844
Short name T905
Test name
Test status
Simulation time 53046814303 ps
CPU time 215.99 seconds
Started Aug 23 03:57:38 AM UTC 24
Finished Aug 23 04:01:17 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827343844 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2827343844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_loopback.1279399934
Short name T826
Test name
Test status
Simulation time 1815359889 ps
CPU time 1.47 seconds
Started Aug 23 03:57:33 AM UTC 24
Finished Aug 23 03:57:36 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279399934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1279399934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_noise_filter.1115599271
Short name T833
Test name
Test status
Simulation time 12707816598 ps
CPU time 10.91 seconds
Started Aug 23 03:57:29 AM UTC 24
Finished Aug 23 03:57:41 AM UTC 24
Peak memory 205244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115599271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1115599271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_perf.1669171610
Short name T845
Test name
Test status
Simulation time 16967035341 ps
CPU time 50.21 seconds
Started Aug 23 03:57:36 AM UTC 24
Finished Aug 23 03:58:28 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669171610 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1669171610
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_rx_oversample.4015642313
Short name T829
Test name
Test status
Simulation time 3550533242 ps
CPU time 12.29 seconds
Started Aug 23 03:57:25 AM UTC 24
Finished Aug 23 03:57:38 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015642313 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.4015642313
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.2802650883
Short name T830
Test name
Test status
Simulation time 71160578097 ps
CPU time 7.07 seconds
Started Aug 23 03:57:32 AM UTC 24
Finished Aug 23 03:57:40 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802650883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2802650883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.3111998939
Short name T832
Test name
Test status
Simulation time 4759613114 ps
CPU time 7.62 seconds
Started Aug 23 03:57:32 AM UTC 24
Finished Aug 23 03:57:40 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111998939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3111998939
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_smoke.1387896165
Short name T824
Test name
Test status
Simulation time 5740547929 ps
CPU time 13.15 seconds
Started Aug 23 03:57:18 AM UTC 24
Finished Aug 23 03:57:32 AM UTC 24
Peak memory 207644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387896165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1387896165
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_stress_all.2838157258
Short name T993
Test name
Test status
Simulation time 753817955331 ps
CPU time 506.63 seconds
Started Aug 23 03:57:39 AM UTC 24
Finished Aug 23 04:06:12 AM UTC 24
Peak memory 222512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838157258 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2838157258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.2871839024
Short name T837
Test name
Test status
Simulation time 1342574691 ps
CPU time 10.12 seconds
Started Aug 23 03:57:38 AM UTC 24
Finished Aug 23 03:57:49 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2871839024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all
_with_rand_reset.2871839024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.419672203
Short name T827
Test name
Test status
Simulation time 916922485 ps
CPU time 2.42 seconds
Started Aug 23 03:57:33 AM UTC 24
Finished Aug 23 03:57:37 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419672203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.419672203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/43.uart_tx_rx.1782280005
Short name T822
Test name
Test status
Simulation time 6028394599 ps
CPU time 8.57 seconds
Started Aug 23 03:57:19 AM UTC 24
Finished Aug 23 03:57:29 AM UTC 24
Peak memory 207280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782280005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1782280005
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/43.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_alert_test.1508165699
Short name T847
Test name
Test status
Simulation time 133921995 ps
CPU time 0.46 seconds
Started Aug 23 03:58:33 AM UTC 24
Finished Aug 23 03:58:34 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508165699 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1508165699
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_fifo_full.1489408062
Short name T869
Test name
Test status
Simulation time 80465837974 ps
CPU time 118.7 seconds
Started Aug 23 03:57:42 AM UTC 24
Finished Aug 23 03:59:43 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489408062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1489408062
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.1969511772
Short name T889
Test name
Test status
Simulation time 134921678993 ps
CPU time 173.9 seconds
Started Aug 23 03:57:43 AM UTC 24
Finished Aug 23 04:00:40 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969511772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1969511772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_fifo_reset.1530730737
Short name T202
Test name
Test status
Simulation time 30125857143 ps
CPU time 14.14 seconds
Started Aug 23 03:57:46 AM UTC 24
Finished Aug 23 03:58:01 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530730737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1530730737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_intr.4058042738
Short name T849
Test name
Test status
Simulation time 169231574189 ps
CPU time 62.37 seconds
Started Aug 23 03:57:50 AM UTC 24
Finished Aug 23 03:58:54 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058042738 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.4058042738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.188622586
Short name T914
Test name
Test status
Simulation time 182359858520 ps
CPU time 209.09 seconds
Started Aug 23 03:58:18 AM UTC 24
Finished Aug 23 04:01:50 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188622586 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.188622586
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_loopback.2611755739
Short name T843
Test name
Test status
Simulation time 5976658472 ps
CPU time 11.1 seconds
Started Aug 23 03:58:04 AM UTC 24
Finished Aug 23 03:58:17 AM UTC 24
Peak memory 207836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611755739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2611755739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_noise_filter.1861376108
Short name T870
Test name
Test status
Simulation time 66431252798 ps
CPU time 107.31 seconds
Started Aug 23 03:57:54 AM UTC 24
Finished Aug 23 03:59:44 AM UTC 24
Peak memory 217592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861376108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1861376108
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_perf.806857746
Short name T1181
Test name
Test status
Simulation time 21363410436 ps
CPU time 1082.14 seconds
Started Aug 23 03:58:10 AM UTC 24
Finished Aug 23 04:16:23 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806857746 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.806857746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_rx_oversample.3677777076
Short name T838
Test name
Test status
Simulation time 1905944060 ps
CPU time 5.79 seconds
Started Aug 23 03:57:47 AM UTC 24
Finished Aug 23 03:57:54 AM UTC 24
Peak memory 207348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677777076 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3677777076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.3639900406
Short name T852
Test name
Test status
Simulation time 225372504577 ps
CPU time 61.96 seconds
Started Aug 23 03:58:02 AM UTC 24
Finished Aug 23 03:59:06 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639900406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3639900406
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.938945216
Short name T841
Test name
Test status
Simulation time 1420219714 ps
CPU time 1.49 seconds
Started Aug 23 03:58:01 AM UTC 24
Finished Aug 23 03:58:04 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938945216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.938945216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_smoke.2039196358
Short name T836
Test name
Test status
Simulation time 534141380 ps
CPU time 1.87 seconds
Started Aug 23 03:57:42 AM UTC 24
Finished Aug 23 03:57:45 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039196358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2039196358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_stress_all.3810923051
Short name T866
Test name
Test status
Simulation time 92268159194 ps
CPU time 64.47 seconds
Started Aug 23 03:58:28 AM UTC 24
Finished Aug 23 03:59:35 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810923051 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3810923051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.3743485073
Short name T237
Test name
Test status
Simulation time 8712797643 ps
CPU time 25.19 seconds
Started Aug 23 03:58:21 AM UTC 24
Finished Aug 23 03:58:48 AM UTC 24
Peak memory 217684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3743485073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all
_with_rand_reset.3743485073
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.2430701485
Short name T844
Test name
Test status
Simulation time 6731609089 ps
CPU time 15.3 seconds
Started Aug 23 03:58:03 AM UTC 24
Finished Aug 23 03:58:20 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430701485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2430701485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/44.uart_tx_rx.1012636826
Short name T871
Test name
Test status
Simulation time 79490863403 ps
CPU time 122.49 seconds
Started Aug 23 03:57:42 AM UTC 24
Finished Aug 23 03:59:47 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012636826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1012636826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/44.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_alert_test.468101529
Short name T865
Test name
Test status
Simulation time 16987196 ps
CPU time 0.47 seconds
Started Aug 23 03:59:31 AM UTC 24
Finished Aug 23 03:59:33 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468101529 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.468101529
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_fifo_full.1091255280
Short name T857
Test name
Test status
Simulation time 30694363601 ps
CPU time 29.91 seconds
Started Aug 23 03:58:54 AM UTC 24
Finished Aug 23 03:59:25 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091255280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1091255280
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.1586287301
Short name T851
Test name
Test status
Simulation time 6477621904 ps
CPU time 9.86 seconds
Started Aug 23 03:58:55 AM UTC 24
Finished Aug 23 03:59:06 AM UTC 24
Peak memory 207848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586287301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1586287301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_intr.1222947742
Short name T862
Test name
Test status
Simulation time 56458113626 ps
CPU time 23.87 seconds
Started Aug 23 03:59:07 AM UTC 24
Finished Aug 23 03:59:32 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222947742 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1222947742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.2675055798
Short name T945
Test name
Test status
Simulation time 82096963366 ps
CPU time 250.89 seconds
Started Aug 23 03:59:27 AM UTC 24
Finished Aug 23 04:03:42 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675055798 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2675055798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_loopback.2169991357
Short name T860
Test name
Test status
Simulation time 2139462768 ps
CPU time 0.96 seconds
Started Aug 23 03:59:26 AM UTC 24
Finished Aug 23 03:59:28 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169991357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2169991357
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_noise_filter.4153862920
Short name T415
Test name
Test status
Simulation time 177222865240 ps
CPU time 16.41 seconds
Started Aug 23 03:59:11 AM UTC 24
Finished Aug 23 03:59:28 AM UTC 24
Peak memory 208024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153862920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.4153862920
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_perf.2435100713
Short name T909
Test name
Test status
Simulation time 13246463197 ps
CPU time 117.79 seconds
Started Aug 23 03:59:26 AM UTC 24
Finished Aug 23 04:01:26 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435100713 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2435100713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_rx_oversample.3993086611
Short name T874
Test name
Test status
Simulation time 6050001676 ps
CPU time 42.08 seconds
Started Aug 23 03:59:07 AM UTC 24
Finished Aug 23 03:59:50 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993086611 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3993086611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.1076895285
Short name T881
Test name
Test status
Simulation time 64177577177 ps
CPU time 49.26 seconds
Started Aug 23 03:59:22 AM UTC 24
Finished Aug 23 04:00:13 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076895285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1076895285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.2657877719
Short name T863
Test name
Test status
Simulation time 44271355497 ps
CPU time 11.31 seconds
Started Aug 23 03:59:19 AM UTC 24
Finished Aug 23 03:59:32 AM UTC 24
Peak memory 207208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657877719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2657877719
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_smoke.1034542710
Short name T848
Test name
Test status
Simulation time 10536544921 ps
CPU time 16.95 seconds
Started Aug 23 03:58:35 AM UTC 24
Finished Aug 23 03:58:53 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034542710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1034542710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_stress_all.1821027413
Short name T1001
Test name
Test status
Simulation time 291960356790 ps
CPU time 413.81 seconds
Started Aug 23 03:59:30 AM UTC 24
Finished Aug 23 04:06:28 AM UTC 24
Peak memory 212400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821027413 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1821027413
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.1861562745
Short name T877
Test name
Test status
Simulation time 8083574049 ps
CPU time 35.26 seconds
Started Aug 23 03:59:29 AM UTC 24
Finished Aug 23 04:00:05 AM UTC 24
Peak memory 219844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1861562745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all
_with_rand_reset.1861562745
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.426152479
Short name T859
Test name
Test status
Simulation time 1670445259 ps
CPU time 1.44 seconds
Started Aug 23 03:59:24 AM UTC 24
Finished Aug 23 03:59:26 AM UTC 24
Peak memory 206384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426152479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.426152479
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/45.uart_tx_rx.1973139919
Short name T850
Test name
Test status
Simulation time 25238128838 ps
CPU time 10.89 seconds
Started Aug 23 03:58:48 AM UTC 24
Finished Aug 23 03:59:00 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973139919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1973139919
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/45.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_alert_test.4216287654
Short name T879
Test name
Test status
Simulation time 42996209 ps
CPU time 0.46 seconds
Started Aug 23 04:00:08 AM UTC 24
Finished Aug 23 04:00:09 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216287654 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4216287654
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_fifo_full.2136702486
Short name T882
Test name
Test status
Simulation time 51948979070 ps
CPU time 38.79 seconds
Started Aug 23 03:59:34 AM UTC 24
Finished Aug 23 04:00:15 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136702486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2136702486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.644452689
Short name T878
Test name
Test status
Simulation time 20601863795 ps
CPU time 30.03 seconds
Started Aug 23 03:59:34 AM UTC 24
Finished Aug 23 04:00:06 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644452689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.644452689
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_fifo_reset.1203908389
Short name T156
Test name
Test status
Simulation time 42578906368 ps
CPU time 60.42 seconds
Started Aug 23 03:59:35 AM UTC 24
Finished Aug 23 04:00:38 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203908389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1203908389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_intr.1862639801
Short name T884
Test name
Test status
Simulation time 14434497326 ps
CPU time 39.39 seconds
Started Aug 23 03:59:43 AM UTC 24
Finished Aug 23 04:00:24 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862639801 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1862639801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.1517516064
Short name T921
Test name
Test status
Simulation time 157643961610 ps
CPU time 131.68 seconds
Started Aug 23 03:59:51 AM UTC 24
Finished Aug 23 04:02:05 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517516064 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1517516064
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_loopback.805881360
Short name T876
Test name
Test status
Simulation time 9652757450 ps
CPU time 5.73 seconds
Started Aug 23 03:59:49 AM UTC 24
Finished Aug 23 03:59:56 AM UTC 24
Peak memory 208536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805881360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.uart_loopback.805881360
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_noise_filter.2395356532
Short name T896
Test name
Test status
Simulation time 189372786439 ps
CPU time 68.73 seconds
Started Aug 23 03:59:44 AM UTC 24
Finished Aug 23 04:00:55 AM UTC 24
Peak memory 208964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395356532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2395356532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_perf.3866120941
Short name T1077
Test name
Test status
Simulation time 11183608209 ps
CPU time 655.56 seconds
Started Aug 23 03:59:51 AM UTC 24
Finished Aug 23 04:10:53 AM UTC 24
Peak memory 211992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866120941 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3866120941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_rx_oversample.2897958617
Short name T873
Test name
Test status
Simulation time 6700537599 ps
CPU time 4.23 seconds
Started Aug 23 03:59:43 AM UTC 24
Finished Aug 23 03:59:48 AM UTC 24
Peak memory 207612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897958617 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2897958617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.3936883534
Short name T1045
Test name
Test status
Simulation time 217999725020 ps
CPU time 547.58 seconds
Started Aug 23 03:59:48 AM UTC 24
Finished Aug 23 04:09:01 AM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936883534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3936883534
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.2149017122
Short name T894
Test name
Test status
Simulation time 45757007596 ps
CPU time 66.32 seconds
Started Aug 23 03:59:44 AM UTC 24
Finished Aug 23 04:00:52 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149017122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2149017122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_smoke.657513304
Short name T867
Test name
Test status
Simulation time 5638260800 ps
CPU time 7.53 seconds
Started Aug 23 03:59:33 AM UTC 24
Finished Aug 23 03:59:42 AM UTC 24
Peak memory 208460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657513304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.uart_smoke.657513304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_stress_all.1430739062
Short name T924
Test name
Test status
Simulation time 89436302020 ps
CPU time 129.69 seconds
Started Aug 23 03:59:57 AM UTC 24
Finished Aug 23 04:02:09 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430739062 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1430739062
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.3164207933
Short name T883
Test name
Test status
Simulation time 2508076714 ps
CPU time 25.75 seconds
Started Aug 23 03:59:53 AM UTC 24
Finished Aug 23 04:00:20 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3164207933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all
_with_rand_reset.3164207933
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.156287196
Short name T875
Test name
Test status
Simulation time 390341844 ps
CPU time 1.37 seconds
Started Aug 23 03:59:49 AM UTC 24
Finished Aug 23 03:59:52 AM UTC 24
Peak memory 206444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156287196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.156287196
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/46.uart_tx_rx.521421114
Short name T872
Test name
Test status
Simulation time 36849515549 ps
CPU time 13.31 seconds
Started Aug 23 03:59:33 AM UTC 24
Finished Aug 23 03:59:48 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521421114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.521421114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/46.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_alert_test.330505607
Short name T895
Test name
Test status
Simulation time 15716378 ps
CPU time 0.49 seconds
Started Aug 23 04:00:52 AM UTC 24
Finished Aug 23 04:00:53 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330505607 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.330505607
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_fifo_full.1294842797
Short name T893
Test name
Test status
Simulation time 55158062234 ps
CPU time 38.98 seconds
Started Aug 23 04:00:10 AM UTC 24
Finished Aug 23 04:00:50 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294842797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1294842797
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.500196080
Short name T886
Test name
Test status
Simulation time 46237444606 ps
CPU time 22.31 seconds
Started Aug 23 04:00:14 AM UTC 24
Finished Aug 23 04:00:38 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500196080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.500196080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_fifo_reset.1443790729
Short name T181
Test name
Test status
Simulation time 390972583051 ps
CPU time 58.15 seconds
Started Aug 23 04:00:16 AM UTC 24
Finished Aug 23 04:01:15 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443790729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1443790729
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_intr.1821005824
Short name T888
Test name
Test status
Simulation time 34128098922 ps
CPU time 14.79 seconds
Started Aug 23 04:00:24 AM UTC 24
Finished Aug 23 04:00:40 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821005824 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1821005824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.1646609424
Short name T915
Test name
Test status
Simulation time 39062580787 ps
CPU time 64.55 seconds
Started Aug 23 04:00:44 AM UTC 24
Finished Aug 23 04:01:50 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646609424 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1646609424
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_loopback.575018871
Short name T892
Test name
Test status
Simulation time 1675849937 ps
CPU time 5.92 seconds
Started Aug 23 04:00:42 AM UTC 24
Finished Aug 23 04:00:49 AM UTC 24
Peak memory 208360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575018871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.uart_loopback.575018871
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_noise_filter.1033427311
Short name T900
Test name
Test status
Simulation time 27345746895 ps
CPU time 39.53 seconds
Started Aug 23 04:00:26 AM UTC 24
Finished Aug 23 04:01:07 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033427311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1033427311
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_perf.4176215471
Short name T937
Test name
Test status
Simulation time 6258931305 ps
CPU time 152.55 seconds
Started Aug 23 04:00:42 AM UTC 24
Finished Aug 23 04:03:17 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176215471 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4176215471
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_rx_oversample.2795048746
Short name T885
Test name
Test status
Simulation time 2239599253 ps
CPU time 3.24 seconds
Started Aug 23 04:00:21 AM UTC 24
Finished Aug 23 04:00:25 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795048746 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2795048746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.2370631018
Short name T907
Test name
Test status
Simulation time 27003833573 ps
CPU time 41.59 seconds
Started Aug 23 04:00:39 AM UTC 24
Finished Aug 23 04:01:22 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370631018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2370631018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.2424822198
Short name T890
Test name
Test status
Simulation time 3125764161 ps
CPU time 2.95 seconds
Started Aug 23 04:00:39 AM UTC 24
Finished Aug 23 04:00:43 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424822198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2424822198
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_smoke.602594693
Short name T880
Test name
Test status
Simulation time 103938020 ps
CPU time 0.85 seconds
Started Aug 23 04:00:08 AM UTC 24
Finished Aug 23 04:00:09 AM UTC 24
Peak memory 206436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602594693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.uart_smoke.602594693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.4046082585
Short name T901
Test name
Test status
Simulation time 10728037819 ps
CPU time 22.42 seconds
Started Aug 23 04:00:44 AM UTC 24
Finished Aug 23 04:01:08 AM UTC 24
Peak memory 219964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4046082585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all
_with_rand_reset.4046082585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.3800854582
Short name T891
Test name
Test status
Simulation time 479391192 ps
CPU time 1.85 seconds
Started Aug 23 04:00:40 AM UTC 24
Finished Aug 23 04:00:43 AM UTC 24
Peak memory 207876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800854582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3800854582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/47.uart_tx_rx.4089324431
Short name T928
Test name
Test status
Simulation time 95834671825 ps
CPU time 127.43 seconds
Started Aug 23 04:00:10 AM UTC 24
Finished Aug 23 04:02:20 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089324431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.4089324431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_alert_test.1296712048
Short name T908
Test name
Test status
Simulation time 44839389 ps
CPU time 0.5 seconds
Started Aug 23 04:01:23 AM UTC 24
Finished Aug 23 04:01:25 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296712048 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1296712048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_fifo_full.3043317003
Short name T913
Test name
Test status
Simulation time 54225417117 ps
CPU time 41.78 seconds
Started Aug 23 04:00:56 AM UTC 24
Finished Aug 23 04:01:40 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043317003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3043317003
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.1450449835
Short name T916
Test name
Test status
Simulation time 272650212821 ps
CPU time 54.22 seconds
Started Aug 23 04:00:56 AM UTC 24
Finished Aug 23 04:01:52 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450449835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1450449835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_fifo_reset.3632288324
Short name T171
Test name
Test status
Simulation time 42797826348 ps
CPU time 12.51 seconds
Started Aug 23 04:00:56 AM UTC 24
Finished Aug 23 04:01:10 AM UTC 24
Peak memory 208416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632288324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3632288324
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_intr.2672458119
Short name T902
Test name
Test status
Simulation time 10145455567 ps
CPU time 8.2 seconds
Started Aug 23 04:01:03 AM UTC 24
Finished Aug 23 04:01:13 AM UTC 24
Peak memory 207208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672458119 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2672458119
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.2032282897
Short name T1065
Test name
Test status
Simulation time 61644607335 ps
CPU time 510.38 seconds
Started Aug 23 04:01:17 AM UTC 24
Finished Aug 23 04:09:54 AM UTC 24
Peak memory 212204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032282897 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2032282897
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_loopback.3827717943
Short name T911
Test name
Test status
Simulation time 6851829231 ps
CPU time 10.38 seconds
Started Aug 23 04:01:16 AM UTC 24
Finished Aug 23 04:01:28 AM UTC 24
Peak memory 208008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827717943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3827717943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_noise_filter.3998760278
Short name T932
Test name
Test status
Simulation time 72827757973 ps
CPU time 96.67 seconds
Started Aug 23 04:01:09 AM UTC 24
Finished Aug 23 04:02:48 AM UTC 24
Peak memory 208004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998760278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3998760278
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_perf.3319556740
Short name T985
Test name
Test status
Simulation time 22699671249 ps
CPU time 264.87 seconds
Started Aug 23 04:01:16 AM UTC 24
Finished Aug 23 04:05:44 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319556740 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3319556740
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_rx_oversample.3785298110
Short name T906
Test name
Test status
Simulation time 3145029225 ps
CPU time 16.5 seconds
Started Aug 23 04:01:01 AM UTC 24
Finished Aug 23 04:01:19 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785298110 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3785298110
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.19948146
Short name T939
Test name
Test status
Simulation time 102629247227 ps
CPU time 131.89 seconds
Started Aug 23 04:01:11 AM UTC 24
Finished Aug 23 04:03:26 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19948146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.19948146
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.1454078684
Short name T903
Test name
Test status
Simulation time 6508323987 ps
CPU time 5.26 seconds
Started Aug 23 04:01:09 AM UTC 24
Finished Aug 23 04:01:16 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454078684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1454078684
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_smoke.471880846
Short name T897
Test name
Test status
Simulation time 530196365 ps
CPU time 1.08 seconds
Started Aug 23 04:00:53 AM UTC 24
Finished Aug 23 04:00:55 AM UTC 24
Peak memory 206244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471880846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.uart_smoke.471880846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_stress_all.1296551269
Short name T919
Test name
Test status
Simulation time 94478986247 ps
CPU time 40.31 seconds
Started Aug 23 04:01:20 AM UTC 24
Finished Aug 23 04:02:01 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296551269 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1296551269
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.1122094544
Short name T912
Test name
Test status
Simulation time 1453566934 ps
CPU time 10.21 seconds
Started Aug 23 04:01:19 AM UTC 24
Finished Aug 23 04:01:30 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1122094544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all
_with_rand_reset.1122094544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.2801073490
Short name T904
Test name
Test status
Simulation time 1337342598 ps
CPU time 1.53 seconds
Started Aug 23 04:01:14 AM UTC 24
Finished Aug 23 04:01:16 AM UTC 24
Peak memory 207364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801073490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2801073490
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/48.uart_tx_rx.94550737
Short name T933
Test name
Test status
Simulation time 94412680831 ps
CPU time 123.51 seconds
Started Aug 23 04:00:54 AM UTC 24
Finished Aug 23 04:03:00 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94550737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.94550737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/48.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_alert_test.2804002633
Short name T925
Test name
Test status
Simulation time 14781780 ps
CPU time 0.49 seconds
Started Aug 23 04:02:10 AM UTC 24
Finished Aug 23 04:02:12 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804002633 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2804002633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_fifo_full.1179932653
Short name T987
Test name
Test status
Simulation time 112977256055 ps
CPU time 256.04 seconds
Started Aug 23 04:01:28 AM UTC 24
Finished Aug 23 04:05:47 AM UTC 24
Peak memory 207180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179932653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1179932653
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.2922200473
Short name T950
Test name
Test status
Simulation time 215199783790 ps
CPU time 151.76 seconds
Started Aug 23 04:01:29 AM UTC 24
Finished Aug 23 04:04:03 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922200473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2922200473
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_fifo_reset.2737444889
Short name T172
Test name
Test status
Simulation time 112924618333 ps
CPU time 35.33 seconds
Started Aug 23 04:01:31 AM UTC 24
Finished Aug 23 04:02:08 AM UTC 24
Peak memory 208492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737444889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2737444889
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_intr.2389934900
Short name T975
Test name
Test status
Simulation time 160408467938 ps
CPU time 200.88 seconds
Started Aug 23 04:01:51 AM UTC 24
Finished Aug 23 04:05:15 AM UTC 24
Peak memory 208432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389934900 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2389934900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.750879857
Short name T1117
Test name
Test status
Simulation time 141216200279 ps
CPU time 640.22 seconds
Started Aug 23 04:02:06 AM UTC 24
Finished Aug 23 04:12:53 AM UTC 24
Peak memory 212428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750879857 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.750879857
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_loopback.3678791524
Short name T929
Test name
Test status
Simulation time 13956342600 ps
CPU time 19.69 seconds
Started Aug 23 04:02:03 AM UTC 24
Finished Aug 23 04:02:24 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678791524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3678791524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_noise_filter.1350855896
Short name T923
Test name
Test status
Simulation time 10584269766 ps
CPU time 16.86 seconds
Started Aug 23 04:01:51 AM UTC 24
Finished Aug 23 04:02:09 AM UTC 24
Peak memory 207436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350855896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1350855896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_perf.2523363084
Short name T1011
Test name
Test status
Simulation time 6970437862 ps
CPU time 286.31 seconds
Started Aug 23 04:02:05 AM UTC 24
Finished Aug 23 04:06:56 AM UTC 24
Peak memory 208496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523363084 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2523363084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_rx_oversample.4109194363
Short name T920
Test name
Test status
Simulation time 3865941596 ps
CPU time 22.71 seconds
Started Aug 23 04:01:41 AM UTC 24
Finished Aug 23 04:02:04 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109194363 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.4109194363
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.1633167031
Short name T922
Test name
Test status
Simulation time 10998514936 ps
CPU time 8.75 seconds
Started Aug 23 04:01:58 AM UTC 24
Finished Aug 23 04:02:07 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633167031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1633167031
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.86724789
Short name T917
Test name
Test status
Simulation time 2204140491 ps
CPU time 2.11 seconds
Started Aug 23 04:01:53 AM UTC 24
Finished Aug 23 04:01:56 AM UTC 24
Peak memory 205104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86724789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.86724789
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_smoke.3774858076
Short name T910
Test name
Test status
Simulation time 113117355 ps
CPU time 0.77 seconds
Started Aug 23 04:01:25 AM UTC 24
Finished Aug 23 04:01:27 AM UTC 24
Peak memory 206428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774858076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3774858076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_stress_all.3144858405
Short name T1073
Test name
Test status
Simulation time 202461538796 ps
CPU time 500.35 seconds
Started Aug 23 04:02:09 AM UTC 24
Finished Aug 23 04:10:35 AM UTC 24
Peak memory 212464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144858405 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3144858405
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.2676134715
Short name T927
Test name
Test status
Simulation time 1940729831 ps
CPU time 7.47 seconds
Started Aug 23 04:02:09 AM UTC 24
Finished Aug 23 04:02:17 AM UTC 24
Peak memory 221980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2676134715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all
_with_rand_reset.2676134715
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.4022185480
Short name T930
Test name
Test status
Simulation time 6531971981 ps
CPU time 23.31 seconds
Started Aug 23 04:02:03 AM UTC 24
Finished Aug 23 04:02:27 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022185480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4022185480
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/49.uart_tx_rx.476062704
Short name T926
Test name
Test status
Simulation time 101097871915 ps
CPU time 46.85 seconds
Started Aug 23 04:01:28 AM UTC 24
Finished Aug 23 04:02:16 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476062704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.476062704
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/49.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_alert_test.1754506266
Short name T432
Test name
Test status
Simulation time 15327450 ps
CPU time 0.5 seconds
Started Aug 23 03:25:49 AM UTC 24
Finished Aug 23 03:25:51 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754506266 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1754506266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_fifo_full.888621229
Short name T118
Test name
Test status
Simulation time 32907264180 ps
CPU time 16.98 seconds
Started Aug 23 03:25:09 AM UTC 24
Finished Aug 23 03:25:27 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888621229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.888621229
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_fifo_reset.1793140702
Short name T162
Test name
Test status
Simulation time 62188314907 ps
CPU time 102.16 seconds
Started Aug 23 03:25:20 AM UTC 24
Finished Aug 23 03:27:04 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793140702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1793140702
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_loopback.3128940590
Short name T433
Test name
Test status
Simulation time 9021656074 ps
CPU time 15.27 seconds
Started Aug 23 03:25:35 AM UTC 24
Finished Aug 23 03:25:51 AM UTC 24
Peak memory 207884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128940590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3128940590
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_noise_filter.898929010
Short name T111
Test name
Test status
Simulation time 32445428791 ps
CPU time 24.81 seconds
Started Aug 23 03:25:23 AM UTC 24
Finished Aug 23 03:25:49 AM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898929010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.898929010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_perf.1178639010
Short name T511
Test name
Test status
Simulation time 19886885000 ps
CPU time 792.41 seconds
Started Aug 23 03:25:36 AM UTC 24
Finished Aug 23 03:38:57 AM UTC 24
Peak memory 212144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178639010 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1178639010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_rx_oversample.3518422275
Short name T403
Test name
Test status
Simulation time 5159278026 ps
CPU time 9.27 seconds
Started Aug 23 03:25:22 AM UTC 24
Finished Aug 23 03:25:32 AM UTC 24
Peak memory 207744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518422275 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3518422275
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.550211584
Short name T340
Test name
Test status
Simulation time 33437390752 ps
CPU time 14.21 seconds
Started Aug 23 03:25:26 AM UTC 24
Finished Aug 23 03:25:41 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550211584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.550211584
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_smoke.1896208138
Short name T336
Test name
Test status
Simulation time 5816212356 ps
CPU time 17.39 seconds
Started Aug 23 03:25:04 AM UTC 24
Finished Aug 23 03:25:22 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896208138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1896208138
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.1331391076
Short name T293
Test name
Test status
Simulation time 632115436 ps
CPU time 1.69 seconds
Started Aug 23 03:25:33 AM UTC 24
Finished Aug 23 03:25:36 AM UTC 24
Peak memory 207356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331391076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1331391076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/5.uart_tx_rx.733753571
Short name T269
Test name
Test status
Simulation time 80028901387 ps
CPU time 129.67 seconds
Started Aug 23 03:25:04 AM UTC 24
Finished Aug 23 03:27:15 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733753571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.733753571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.776417265
Short name T210
Test name
Test status
Simulation time 4298098522 ps
CPU time 40.95 seconds
Started Aug 23 04:02:13 AM UTC 24
Finished Aug 23 04:02:55 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=776417265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all_
with_rand_reset.776417265
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.349416069
Short name T396
Test name
Test status
Simulation time 21900697481 ps
CPU time 66.06 seconds
Started Aug 23 04:02:18 AM UTC 24
Finished Aug 23 04:03:26 AM UTC 24
Peak memory 221872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=349416069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all_
with_rand_reset.349416069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/52.uart_fifo_reset.4069329636
Short name T158
Test name
Test status
Simulation time 22581219007 ps
CPU time 30.24 seconds
Started Aug 23 04:02:21 AM UTC 24
Finished Aug 23 04:02:52 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069329636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.4069329636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/52.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.124827081
Short name T931
Test name
Test status
Simulation time 1152701672 ps
CPU time 10.62 seconds
Started Aug 23 04:02:25 AM UTC 24
Finished Aug 23 04:02:36 AM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=124827081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all_
with_rand_reset.124827081
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/53.uart_fifo_reset.2511314171
Short name T935
Test name
Test status
Simulation time 26418289978 ps
CPU time 45.59 seconds
Started Aug 23 04:02:28 AM UTC 24
Finished Aug 23 04:03:15 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511314171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2511314171
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/53.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.3388325809
Short name T941
Test name
Test status
Simulation time 14216976232 ps
CPU time 49.55 seconds
Started Aug 23 04:02:37 AM UTC 24
Finished Aug 23 04:03:28 AM UTC 24
Peak memory 217684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3388325809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all
_with_rand_reset.3388325809
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/54.uart_fifo_reset.146395391
Short name T940
Test name
Test status
Simulation time 33486926921 ps
CPU time 42.68 seconds
Started Aug 23 04:02:43 AM UTC 24
Finished Aug 23 04:03:27 AM UTC 24
Peak memory 208588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146395391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.146395391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/54.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.251689872
Short name T936
Test name
Test status
Simulation time 5256530225 ps
CPU time 24.84 seconds
Started Aug 23 04:02:49 AM UTC 24
Finished Aug 23 04:03:15 AM UTC 24
Peak memory 225280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=251689872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all_
with_rand_reset.251689872
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/55.uart_fifo_reset.1165433205
Short name T934
Test name
Test status
Simulation time 29724627861 ps
CPU time 19.16 seconds
Started Aug 23 04:02:53 AM UTC 24
Finished Aug 23 04:03:13 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165433205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1165433205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/55.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.945698524
Short name T942
Test name
Test status
Simulation time 2777851002 ps
CPU time 33.35 seconds
Started Aug 23 04:02:56 AM UTC 24
Finished Aug 23 04:03:31 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=945698524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all_
with_rand_reset.945698524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/56.uart_fifo_reset.3273832508
Short name T214
Test name
Test status
Simulation time 43046041294 ps
CPU time 66.15 seconds
Started Aug 23 04:03:01 AM UTC 24
Finished Aug 23 04:04:08 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273832508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3273832508
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/56.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.4249048949
Short name T943
Test name
Test status
Simulation time 8030392591 ps
CPU time 33.33 seconds
Started Aug 23 04:03:06 AM UTC 24
Finished Aug 23 04:03:41 AM UTC 24
Peak memory 224364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4249048949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all
_with_rand_reset.4249048949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/57.uart_fifo_reset.328734351
Short name T203
Test name
Test status
Simulation time 93789552859 ps
CPU time 33.98 seconds
Started Aug 23 04:03:14 AM UTC 24
Finished Aug 23 04:03:49 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328734351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.328734351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/57.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.3443050238
Short name T944
Test name
Test status
Simulation time 35599758110 ps
CPU time 23.03 seconds
Started Aug 23 04:03:17 AM UTC 24
Finished Aug 23 04:03:41 AM UTC 24
Peak memory 225444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3443050238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all
_with_rand_reset.3443050238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/58.uart_fifo_reset.1651715779
Short name T949
Test name
Test status
Simulation time 29025099791 ps
CPU time 44.53 seconds
Started Aug 23 04:03:17 AM UTC 24
Finished Aug 23 04:04:03 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651715779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1651715779
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/58.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.780705650
Short name T961
Test name
Test status
Simulation time 18337324542 ps
CPU time 79.47 seconds
Started Aug 23 04:03:18 AM UTC 24
Finished Aug 23 04:04:39 AM UTC 24
Peak memory 219988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=780705650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all_
with_rand_reset.780705650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/59.uart_fifo_reset.671923602
Short name T182
Test name
Test status
Simulation time 324781150802 ps
CPU time 31.15 seconds
Started Aug 23 04:03:19 AM UTC 24
Finished Aug 23 04:03:51 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671923602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.671923602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/59.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.3844570714
Short name T951
Test name
Test status
Simulation time 4882499202 ps
CPU time 37.51 seconds
Started Aug 23 04:03:27 AM UTC 24
Finished Aug 23 04:04:05 AM UTC 24
Peak memory 219784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3844570714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all
_with_rand_reset.3844570714
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_alert_test.3504462475
Short name T435
Test name
Test status
Simulation time 28255177 ps
CPU time 0.46 seconds
Started Aug 23 03:26:22 AM UTC 24
Finished Aug 23 03:26:24 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504462475 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3504462475
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_fifo_full.928448477
Short name T262
Test name
Test status
Simulation time 252780665626 ps
CPU time 26.3 seconds
Started Aug 23 03:25:51 AM UTC 24
Finished Aug 23 03:26:19 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928448477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.928448477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.3704492001
Short name T97
Test name
Test status
Simulation time 31873399354 ps
CPU time 24.59 seconds
Started Aug 23 03:25:52 AM UTC 24
Finished Aug 23 03:26:18 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704492001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3704492001
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_fifo_reset.2545091226
Short name T126
Test name
Test status
Simulation time 48206052730 ps
CPU time 37.23 seconds
Started Aug 23 03:25:53 AM UTC 24
Finished Aug 23 03:26:32 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545091226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2545091226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_intr.1893956572
Short name T72
Test name
Test status
Simulation time 14319597299 ps
CPU time 19.83 seconds
Started Aug 23 03:26:02 AM UTC 24
Finished Aug 23 03:26:23 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893956572 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1893956572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_loopback.2257943597
Short name T436
Test name
Test status
Simulation time 9437387951 ps
CPU time 4.44 seconds
Started Aug 23 03:26:18 AM UTC 24
Finished Aug 23 03:26:24 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257943597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2257943597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_noise_filter.2453732525
Short name T298
Test name
Test status
Simulation time 166447215524 ps
CPU time 58.26 seconds
Started Aug 23 03:26:04 AM UTC 24
Finished Aug 23 03:27:04 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453732525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2453732525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_rx_oversample.2866086592
Short name T434
Test name
Test status
Simulation time 7063131965 ps
CPU time 8.48 seconds
Started Aug 23 03:25:56 AM UTC 24
Finished Aug 23 03:26:06 AM UTC 24
Peak memory 207988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866086592 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2866086592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.3465553089
Short name T120
Test name
Test status
Simulation time 36030875220 ps
CPU time 45.01 seconds
Started Aug 23 03:26:08 AM UTC 24
Finished Aug 23 03:26:55 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465553089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3465553089
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.2642240976
Short name T284
Test name
Test status
Simulation time 43745301348 ps
CPU time 13.63 seconds
Started Aug 23 03:26:07 AM UTC 24
Finished Aug 23 03:26:22 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642240976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2642240976
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_smoke.3566265246
Short name T316
Test name
Test status
Simulation time 542748395 ps
CPU time 1.12 seconds
Started Aug 23 03:25:50 AM UTC 24
Finished Aug 23 03:25:52 AM UTC 24
Peak memory 206244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566265246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3566265246
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.3627833057
Short name T33
Test name
Test status
Simulation time 1172338576 ps
CPU time 41.34 seconds
Started Aug 23 03:26:19 AM UTC 24
Finished Aug 23 03:27:02 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3627833057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_
with_rand_reset.3627833057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.3892559946
Short name T359
Test name
Test status
Simulation time 1514237279 ps
CPU time 2.11 seconds
Started Aug 23 03:26:15 AM UTC 24
Finished Aug 23 03:26:19 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892559946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3892559946
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/6.uart_tx_rx.1376451563
Short name T259
Test name
Test status
Simulation time 56105015520 ps
CPU time 89.89 seconds
Started Aug 23 03:25:51 AM UTC 24
Finished Aug 23 03:27:23 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376451563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1376451563
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/6.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/60.uart_fifo_reset.1343646215
Short name T230
Test name
Test status
Simulation time 154869955641 ps
CPU time 121.99 seconds
Started Aug 23 04:03:27 AM UTC 24
Finished Aug 23 04:05:31 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343646215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1343646215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/60.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.4147698064
Short name T947
Test name
Test status
Simulation time 2083643493 ps
CPU time 19.9 seconds
Started Aug 23 04:03:28 AM UTC 24
Finished Aug 23 04:03:49 AM UTC 24
Peak memory 219648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4147698064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all
_with_rand_reset.4147698064
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/61.uart_fifo_reset.1453810362
Short name T948
Test name
Test status
Simulation time 27735434715 ps
CPU time 20.89 seconds
Started Aug 23 04:03:29 AM UTC 24
Finished Aug 23 04:03:51 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453810362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1453810362
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/61.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.2931405346
Short name T957
Test name
Test status
Simulation time 4268809280 ps
CPU time 48.1 seconds
Started Aug 23 04:03:32 AM UTC 24
Finished Aug 23 04:04:22 AM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2931405346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all
_with_rand_reset.2931405346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/62.uart_fifo_reset.2773220584
Short name T235
Test name
Test status
Simulation time 34716270861 ps
CPU time 25.67 seconds
Started Aug 23 04:03:42 AM UTC 24
Finished Aug 23 04:04:09 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773220584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2773220584
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/62.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.2762277409
Short name T958
Test name
Test status
Simulation time 17259085079 ps
CPU time 42.54 seconds
Started Aug 23 04:03:42 AM UTC 24
Finished Aug 23 04:04:26 AM UTC 24
Peak memory 219768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2762277409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all
_with_rand_reset.2762277409
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/63.uart_fifo_reset.2564122422
Short name T963
Test name
Test status
Simulation time 41672240551 ps
CPU time 56.81 seconds
Started Aug 23 04:03:43 AM UTC 24
Finished Aug 23 04:04:41 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564122422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2564122422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/63.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.4040504674
Short name T954
Test name
Test status
Simulation time 22589155277 ps
CPU time 22.95 seconds
Started Aug 23 04:03:47 AM UTC 24
Finished Aug 23 04:04:12 AM UTC 24
Peak memory 217588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4040504674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all
_with_rand_reset.4040504674
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/64.uart_fifo_reset.1265222655
Short name T956
Test name
Test status
Simulation time 17445853986 ps
CPU time 26.01 seconds
Started Aug 23 04:03:49 AM UTC 24
Finished Aug 23 04:04:16 AM UTC 24
Peak memory 207492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265222655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1265222655
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/64.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.650798742
Short name T959
Test name
Test status
Simulation time 25632810325 ps
CPU time 35.62 seconds
Started Aug 23 04:03:50 AM UTC 24
Finished Aug 23 04:04:27 AM UTC 24
Peak memory 219832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=650798742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all_
with_rand_reset.650798742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/65.uart_fifo_reset.1152532766
Short name T952
Test name
Test status
Simulation time 19035650073 ps
CPU time 15.46 seconds
Started Aug 23 04:03:50 AM UTC 24
Finished Aug 23 04:04:07 AM UTC 24
Peak memory 208868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152532766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1152532766
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/65.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.1119794635
Short name T955
Test name
Test status
Simulation time 7790612619 ps
CPU time 21.26 seconds
Started Aug 23 04:03:52 AM UTC 24
Finished Aug 23 04:04:14 AM UTC 24
Peak memory 217916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1119794635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all
_with_rand_reset.1119794635
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/66.uart_fifo_reset.761796458
Short name T953
Test name
Test status
Simulation time 8404160730 ps
CPU time 15.31 seconds
Started Aug 23 04:03:53 AM UTC 24
Finished Aug 23 04:04:09 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761796458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.761796458
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/66.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.3922683371
Short name T971
Test name
Test status
Simulation time 59490235621 ps
CPU time 58.64 seconds
Started Aug 23 04:04:03 AM UTC 24
Finished Aug 23 04:05:04 AM UTC 24
Peak memory 217588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3922683371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all
_with_rand_reset.3922683371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/67.uart_fifo_reset.3119867735
Short name T216
Test name
Test status
Simulation time 85530642435 ps
CPU time 123.83 seconds
Started Aug 23 04:04:05 AM UTC 24
Finished Aug 23 04:06:11 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119867735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3119867735
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/67.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.3767493684
Short name T960
Test name
Test status
Simulation time 2468094207 ps
CPU time 27.75 seconds
Started Aug 23 04:04:07 AM UTC 24
Finished Aug 23 04:04:36 AM UTC 24
Peak memory 209092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3767493684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all
_with_rand_reset.3767493684
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/68.uart_fifo_reset.2685663873
Short name T1017
Test name
Test status
Simulation time 97861178864 ps
CPU time 187.02 seconds
Started Aug 23 04:04:08 AM UTC 24
Finished Aug 23 04:07:18 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685663873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2685663873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/68.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.2755174373
Short name T962
Test name
Test status
Simulation time 3296511848 ps
CPU time 28.5 seconds
Started Aug 23 04:04:10 AM UTC 24
Finished Aug 23 04:04:40 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2755174373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all
_with_rand_reset.2755174373
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/69.uart_fifo_reset.842489165
Short name T966
Test name
Test status
Simulation time 151224560389 ps
CPU time 48.26 seconds
Started Aug 23 04:04:10 AM UTC 24
Finished Aug 23 04:04:59 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842489165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.842489165
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/69.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.2647105962
Short name T967
Test name
Test status
Simulation time 12849191495 ps
CPU time 47.94 seconds
Started Aug 23 04:04:11 AM UTC 24
Finished Aug 23 04:05:01 AM UTC 24
Peak memory 219784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2647105962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all
_with_rand_reset.2647105962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_alert_test.3737302495
Short name T439
Test name
Test status
Simulation time 43200794 ps
CPU time 0.53 seconds
Started Aug 23 03:27:18 AM UTC 24
Finished Aug 23 03:27:20 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737302495 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3737302495
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_fifo_full.4243389798
Short name T276
Test name
Test status
Simulation time 69874294016 ps
CPU time 85.2 seconds
Started Aug 23 03:26:25 AM UTC 24
Finished Aug 23 03:27:51 AM UTC 24
Peak memory 208844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243389798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.4243389798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2024747021
Short name T119
Test name
Test status
Simulation time 91270144213 ps
CPU time 56.78 seconds
Started Aug 23 03:26:33 AM UTC 24
Finished Aug 23 03:27:31 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024747021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2024747021
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_intr.1514807778
Short name T389
Test name
Test status
Simulation time 269826430517 ps
CPU time 85.35 seconds
Started Aug 23 03:26:50 AM UTC 24
Finished Aug 23 03:28:17 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514807778 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1514807778
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.4258663383
Short name T257
Test name
Test status
Simulation time 79953912451 ps
CPU time 135.15 seconds
Started Aug 23 03:27:03 AM UTC 24
Finished Aug 23 03:29:21 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258663383 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.4258663383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_loopback.164542672
Short name T438
Test name
Test status
Simulation time 8435837347 ps
CPU time 14.15 seconds
Started Aug 23 03:27:00 AM UTC 24
Finished Aug 23 03:27:16 AM UTC 24
Peak memory 207876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164542672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.uart_loopback.164542672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_noise_filter.1512756092
Short name T267
Test name
Test status
Simulation time 21835223874 ps
CPU time 37.37 seconds
Started Aug 23 03:26:51 AM UTC 24
Finished Aug 23 03:27:30 AM UTC 24
Peak memory 208944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512756092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1512756092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_perf.2254463540
Short name T373
Test name
Test status
Simulation time 12997679628 ps
CPU time 590.96 seconds
Started Aug 23 03:27:02 AM UTC 24
Finished Aug 23 03:37:00 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254463540 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2254463540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_rx_oversample.1013766330
Short name T437
Test name
Test status
Simulation time 4210672553 ps
CPU time 24.1 seconds
Started Aug 23 03:26:36 AM UTC 24
Finished Aug 23 03:27:01 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013766330 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1013766330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.1109172071
Short name T123
Test name
Test status
Simulation time 14139863820 ps
CPU time 24.87 seconds
Started Aug 23 03:26:54 AM UTC 24
Finished Aug 23 03:27:20 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109172071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1109172071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.767022828
Short name T309
Test name
Test status
Simulation time 3749215464 ps
CPU time 1.03 seconds
Started Aug 23 03:26:51 AM UTC 24
Finished Aug 23 03:26:53 AM UTC 24
Peak memory 204444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767022828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.767022828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_smoke.2886760192
Short name T346
Test name
Test status
Simulation time 735626143 ps
CPU time 1.46 seconds
Started Aug 23 03:26:24 AM UTC 24
Finished Aug 23 03:26:27 AM UTC 24
Peak memory 207432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886760192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2886760192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_stress_all.3000350191
Short name T423
Test name
Test status
Simulation time 120791149941 ps
CPU time 789.35 seconds
Started Aug 23 03:27:05 AM UTC 24
Finished Aug 23 03:40:22 AM UTC 24
Peak memory 211828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000350191 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3000350191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.347979420
Short name T34
Test name
Test status
Simulation time 10915342335 ps
CPU time 30.75 seconds
Started Aug 23 03:27:05 AM UTC 24
Finished Aug 23 03:27:37 AM UTC 24
Peak memory 219424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=347979420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_w
ith_rand_reset.347979420
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.1505859696
Short name T310
Test name
Test status
Simulation time 1166899860 ps
CPU time 3.36 seconds
Started Aug 23 03:26:55 AM UTC 24
Finished Aug 23 03:27:00 AM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505859696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1505859696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/7.uart_tx_rx.2769193394
Short name T388
Test name
Test status
Simulation time 18906196473 ps
CPU time 24.9 seconds
Started Aug 23 03:26:24 AM UTC 24
Finished Aug 23 03:26:51 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769193394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2769193394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/7.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/70.uart_fifo_reset.3259172682
Short name T976
Test name
Test status
Simulation time 150019581884 ps
CPU time 61.27 seconds
Started Aug 23 04:04:12 AM UTC 24
Finished Aug 23 04:05:15 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259172682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3259172682
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/70.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.3339116127
Short name T986
Test name
Test status
Simulation time 7929475490 ps
CPU time 88.59 seconds
Started Aug 23 04:04:15 AM UTC 24
Finished Aug 23 04:05:45 AM UTC 24
Peak memory 224996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3339116127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all
_with_rand_reset.3339116127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/71.uart_fifo_reset.1000633252
Short name T1023
Test name
Test status
Simulation time 110081848784 ps
CPU time 186.91 seconds
Started Aug 23 04:04:17 AM UTC 24
Finished Aug 23 04:07:27 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000633252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1000633252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/71.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.3581926393
Short name T972
Test name
Test status
Simulation time 4352995188 ps
CPU time 44.59 seconds
Started Aug 23 04:04:23 AM UTC 24
Finished Aug 23 04:05:09 AM UTC 24
Peak memory 217524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3581926393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all
_with_rand_reset.3581926393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/72.uart_fifo_reset.1474777067
Short name T188
Test name
Test status
Simulation time 125595068710 ps
CPU time 105.3 seconds
Started Aug 23 04:04:27 AM UTC 24
Finished Aug 23 04:06:14 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474777067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1474777067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/72.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.1050814109
Short name T965
Test name
Test status
Simulation time 5769373758 ps
CPU time 28.74 seconds
Started Aug 23 04:04:28 AM UTC 24
Finished Aug 23 04:04:58 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1050814109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all
_with_rand_reset.1050814109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/73.uart_fifo_reset.3442992236
Short name T973
Test name
Test status
Simulation time 64354225128 ps
CPU time 31.29 seconds
Started Aug 23 04:04:37 AM UTC 24
Finished Aug 23 04:05:10 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442992236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3442992236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/73.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.47035717
Short name T968
Test name
Test status
Simulation time 1802393986 ps
CPU time 21.7 seconds
Started Aug 23 04:04:40 AM UTC 24
Finished Aug 23 04:05:02 AM UTC 24
Peak memory 217588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=47035717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all_w
ith_rand_reset.47035717
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/74.uart_fifo_reset.284124056
Short name T1002
Test name
Test status
Simulation time 54531360640 ps
CPU time 106.13 seconds
Started Aug 23 04:04:41 AM UTC 24
Finished Aug 23 04:06:29 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284124056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.284124056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/74.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.1543199991
Short name T969
Test name
Test status
Simulation time 10085328835 ps
CPU time 20.62 seconds
Started Aug 23 04:04:42 AM UTC 24
Finished Aug 23 04:05:04 AM UTC 24
Peak memory 217744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1543199991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all
_with_rand_reset.1543199991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/75.uart_fifo_reset.21608614
Short name T191
Test name
Test status
Simulation time 104511608602 ps
CPU time 149.17 seconds
Started Aug 23 04:04:49 AM UTC 24
Finished Aug 23 04:07:21 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21608614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.21608614
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/75.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.2016563886
Short name T979
Test name
Test status
Simulation time 3175688509 ps
CPU time 28.11 seconds
Started Aug 23 04:04:59 AM UTC 24
Finished Aug 23 04:05:28 AM UTC 24
Peak memory 219988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2016563886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all
_with_rand_reset.2016563886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/76.uart_fifo_reset.558087009
Short name T974
Test name
Test status
Simulation time 30260062713 ps
CPU time 11.66 seconds
Started Aug 23 04:05:00 AM UTC 24
Finished Aug 23 04:05:13 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558087009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.558087009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/76.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.2852879280
Short name T977
Test name
Test status
Simulation time 1215821151 ps
CPU time 12.63 seconds
Started Aug 23 04:05:01 AM UTC 24
Finished Aug 23 04:05:15 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2852879280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all
_with_rand_reset.2852879280
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/77.uart_fifo_reset.3261442614
Short name T980
Test name
Test status
Simulation time 19208117151 ps
CPU time 24.28 seconds
Started Aug 23 04:05:04 AM UTC 24
Finished Aug 23 04:05:29 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261442614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3261442614
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/77.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.2671158002
Short name T981
Test name
Test status
Simulation time 6599304196 ps
CPU time 22.96 seconds
Started Aug 23 04:05:05 AM UTC 24
Finished Aug 23 04:05:30 AM UTC 24
Peak memory 217684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2671158002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all
_with_rand_reset.2671158002
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/78.uart_fifo_reset.2852923151
Short name T1019
Test name
Test status
Simulation time 97947529445 ps
CPU time 133.84 seconds
Started Aug 23 04:05:05 AM UTC 24
Finished Aug 23 04:07:22 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852923151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2852923151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/78.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.1350114859
Short name T1000
Test name
Test status
Simulation time 4706205156 ps
CPU time 75.37 seconds
Started Aug 23 04:05:11 AM UTC 24
Finished Aug 23 04:06:28 AM UTC 24
Peak memory 217744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1350114859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all
_with_rand_reset.1350114859
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/79.uart_fifo_reset.3592721410
Short name T221
Test name
Test status
Simulation time 28969992577 ps
CPU time 11.67 seconds
Started Aug 23 04:05:11 AM UTC 24
Finished Aug 23 04:05:24 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592721410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3592721410
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/79.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.1640709582
Short name T1006
Test name
Test status
Simulation time 18249207538 ps
CPU time 79.71 seconds
Started Aug 23 04:05:13 AM UTC 24
Finished Aug 23 04:06:35 AM UTC 24
Peak memory 217684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1640709582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all
_with_rand_reset.1640709582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_alert_test.1799653751
Short name T440
Test name
Test status
Simulation time 34557862 ps
CPU time 0.46 seconds
Started Aug 23 03:27:52 AM UTC 24
Finished Aug 23 03:27:54 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799653751 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1799653751
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_fifo_full.2419368079
Short name T319
Test name
Test status
Simulation time 20529694834 ps
CPU time 15.53 seconds
Started Aug 23 03:27:21 AM UTC 24
Finished Aug 23 03:27:38 AM UTC 24
Peak memory 208800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419368079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2419368079
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1006443078
Short name T130
Test name
Test status
Simulation time 59856737928 ps
CPU time 46.38 seconds
Started Aug 23 03:27:21 AM UTC 24
Finished Aug 23 03:28:09 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006443078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1006443078
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_fifo_reset.441861549
Short name T177
Test name
Test status
Simulation time 13966070183 ps
CPU time 21.6 seconds
Started Aug 23 03:27:23 AM UTC 24
Finished Aug 23 03:27:46 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441861549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.441861549
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_intr.2588458756
Short name T299
Test name
Test status
Simulation time 22329418508 ps
CPU time 30.58 seconds
Started Aug 23 03:27:31 AM UTC 24
Finished Aug 23 03:28:03 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588458756 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2588458756
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.2439956290
Short name T521
Test name
Test status
Simulation time 94734053643 ps
CPU time 690.64 seconds
Started Aug 23 03:27:44 AM UTC 24
Finished Aug 23 03:39:22 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439956290 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2439956290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_loopback.1422732608
Short name T402
Test name
Test status
Simulation time 4446649675 ps
CPU time 5.18 seconds
Started Aug 23 03:27:38 AM UTC 24
Finished Aug 23 03:27:44 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422732608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1422732608
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_noise_filter.2206992407
Short name T318
Test name
Test status
Simulation time 169348326530 ps
CPU time 39.72 seconds
Started Aug 23 03:27:31 AM UTC 24
Finished Aug 23 03:28:13 AM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206992407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2206992407
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_perf.3664456166
Short name T301
Test name
Test status
Simulation time 11059468454 ps
CPU time 141.07 seconds
Started Aug 23 03:27:40 AM UTC 24
Finished Aug 23 03:30:03 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664456166 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3664456166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_rx_oversample.785344951
Short name T441
Test name
Test status
Simulation time 6512527847 ps
CPU time 50.08 seconds
Started Aug 23 03:27:25 AM UTC 24
Finished Aug 23 03:28:17 AM UTC 24
Peak memory 208144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785344951 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.785344951
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.1567485035
Short name T297
Test name
Test status
Simulation time 3918220982 ps
CPU time 3.28 seconds
Started Aug 23 03:27:31 AM UTC 24
Finished Aug 23 03:27:36 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567485035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1567485035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_smoke.3874535316
Short name T295
Test name
Test status
Simulation time 91709527 ps
CPU time 0.79 seconds
Started Aug 23 03:27:18 AM UTC 24
Finished Aug 23 03:27:20 AM UTC 24
Peak memory 207036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874535316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3874535316
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.1804266313
Short name T323
Test name
Test status
Simulation time 6595910654 ps
CPU time 18.27 seconds
Started Aug 23 03:27:38 AM UTC 24
Finished Aug 23 03:27:57 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804266313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1804266313
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/8.uart_tx_rx.3250309776
Short name T274
Test name
Test status
Simulation time 218239697553 ps
CPU time 19.4 seconds
Started Aug 23 03:27:21 AM UTC 24
Finished Aug 23 03:27:42 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250309776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3250309776
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/8.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/80.uart_fifo_reset.450654871
Short name T170
Test name
Test status
Simulation time 48597726449 ps
CPU time 18.89 seconds
Started Aug 23 04:05:16 AM UTC 24
Finished Aug 23 04:05:36 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450654871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.450654871
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/80.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2562872105
Short name T988
Test name
Test status
Simulation time 2779893913 ps
CPU time 34.7 seconds
Started Aug 23 04:05:16 AM UTC 24
Finished Aug 23 04:05:52 AM UTC 24
Peak memory 217660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2562872105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all
_with_rand_reset.2562872105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.17842083
Short name T1012
Test name
Test status
Simulation time 8108092178 ps
CPU time 90.07 seconds
Started Aug 23 04:05:25 AM UTC 24
Finished Aug 23 04:06:57 AM UTC 24
Peak memory 225172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=17842083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all_w
ith_rand_reset.17842083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/82.uart_fifo_reset.1035634842
Short name T982
Test name
Test status
Simulation time 14974461192 ps
CPU time 6.1 seconds
Started Aug 23 04:05:29 AM UTC 24
Finished Aug 23 04:05:37 AM UTC 24
Peak memory 208352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035634842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1035634842
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/82.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.4096050051
Short name T992
Test name
Test status
Simulation time 17599634981 ps
CPU time 38.69 seconds
Started Aug 23 04:05:29 AM UTC 24
Finished Aug 23 04:06:09 AM UTC 24
Peak memory 219708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4096050051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all
_with_rand_reset.4096050051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/83.uart_fifo_reset.324453788
Short name T984
Test name
Test status
Simulation time 15460955900 ps
CPU time 11.51 seconds
Started Aug 23 04:05:31 AM UTC 24
Finished Aug 23 04:05:44 AM UTC 24
Peak memory 208860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324453788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.324453788
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/83.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.2066163048
Short name T989
Test name
Test status
Simulation time 8325759562 ps
CPU time 24.52 seconds
Started Aug 23 04:05:31 AM UTC 24
Finished Aug 23 04:05:57 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2066163048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all
_with_rand_reset.2066163048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/84.uart_fifo_reset.1833004436
Short name T983
Test name
Test status
Simulation time 36556136343 ps
CPU time 5.29 seconds
Started Aug 23 04:05:32 AM UTC 24
Finished Aug 23 04:05:39 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833004436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1833004436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/84.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.2669981902
Short name T996
Test name
Test status
Simulation time 4238760193 ps
CPU time 39.33 seconds
Started Aug 23 04:05:38 AM UTC 24
Finished Aug 23 04:06:19 AM UTC 24
Peak memory 224728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2669981902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all
_with_rand_reset.2669981902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/85.uart_fifo_reset.3751033248
Short name T1003
Test name
Test status
Simulation time 37795712304 ps
CPU time 52.45 seconds
Started Aug 23 04:05:38 AM UTC 24
Finished Aug 23 04:06:32 AM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751033248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3751033248
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/85.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.857013023
Short name T990
Test name
Test status
Simulation time 1627709021 ps
CPU time 17.6 seconds
Started Aug 23 04:05:40 AM UTC 24
Finished Aug 23 04:05:59 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=857013023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all_
with_rand_reset.857013023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/86.uart_fifo_reset.2020131776
Short name T174
Test name
Test status
Simulation time 7070789836 ps
CPU time 12.32 seconds
Started Aug 23 04:05:45 AM UTC 24
Finished Aug 23 04:05:58 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020131776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2020131776
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/86.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.192900267
Short name T1009
Test name
Test status
Simulation time 5946587029 ps
CPU time 63.34 seconds
Started Aug 23 04:05:46 AM UTC 24
Finished Aug 23 04:06:52 AM UTC 24
Peak memory 217844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=192900267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all_
with_rand_reset.192900267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/87.uart_fifo_reset.61923729
Short name T991
Test name
Test status
Simulation time 49642261702 ps
CPU time 21.59 seconds
Started Aug 23 04:05:46 AM UTC 24
Finished Aug 23 04:06:09 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61923729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.61923729
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/87.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.3725061389
Short name T999
Test name
Test status
Simulation time 11279752373 ps
CPU time 36.71 seconds
Started Aug 23 04:05:48 AM UTC 24
Finished Aug 23 04:06:26 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3725061389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all
_with_rand_reset.3725061389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/88.uart_fifo_reset.3230544497
Short name T1040
Test name
Test status
Simulation time 105019376199 ps
CPU time 162.1 seconds
Started Aug 23 04:05:53 AM UTC 24
Finished Aug 23 04:08:38 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230544497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3230544497
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/88.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.3315254760
Short name T997
Test name
Test status
Simulation time 2301487500 ps
CPU time 21.45 seconds
Started Aug 23 04:05:59 AM UTC 24
Finished Aug 23 04:06:22 AM UTC 24
Peak memory 222020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3315254760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all
_with_rand_reset.3315254760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2049775309
Short name T184
Test name
Test status
Simulation time 30230797185 ps
CPU time 45.75 seconds
Started Aug 23 04:05:59 AM UTC 24
Finished Aug 23 04:06:46 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049775309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2049775309
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/89.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.3195830562
Short name T994
Test name
Test status
Simulation time 1772661437 ps
CPU time 15.16 seconds
Started Aug 23 04:05:59 AM UTC 24
Finished Aug 23 04:06:15 AM UTC 24
Peak memory 208968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3195830562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all
_with_rand_reset.3195830562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_alert_test.204102106
Short name T443
Test name
Test status
Simulation time 40079217 ps
CPU time 0.45 seconds
Started Aug 23 03:28:29 AM UTC 24
Finished Aug 23 03:28:30 AM UTC 24
Peak memory 204312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204102106 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.204102106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.240793693
Short name T121
Test name
Test status
Simulation time 77707829578 ps
CPU time 108.5 seconds
Started Aug 23 03:28:04 AM UTC 24
Finished Aug 23 03:29:55 AM UTC 24
Peak memory 208520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240793693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.240793693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_fifo_reset.3228853155
Short name T211
Test name
Test status
Simulation time 11691109253 ps
CPU time 29.42 seconds
Started Aug 23 03:28:05 AM UTC 24
Finished Aug 23 03:28:36 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228853155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3228853155
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_intr.2671184442
Short name T270
Test name
Test status
Simulation time 31236235471 ps
CPU time 30.09 seconds
Started Aug 23 03:28:07 AM UTC 24
Finished Aug 23 03:28:39 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671184442 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2671184442
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.470391164
Short name T283
Test name
Test status
Simulation time 50562251227 ps
CPU time 262.75 seconds
Started Aug 23 03:28:23 AM UTC 24
Finished Aug 23 03:32:49 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470391164 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.470391164
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_loopback.923418346
Short name T442
Test name
Test status
Simulation time 2521040629 ps
CPU time 2.85 seconds
Started Aug 23 03:28:18 AM UTC 24
Finished Aug 23 03:28:21 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923418346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.uart_loopback.923418346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_noise_filter.552389771
Short name T277
Test name
Test status
Simulation time 94527240179 ps
CPU time 69.54 seconds
Started Aug 23 03:28:09 AM UTC 24
Finished Aug 23 03:29:20 AM UTC 24
Peak memory 208504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552389771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.552389771
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_perf.2315041881
Short name T279
Test name
Test status
Simulation time 11728086254 ps
CPU time 501.33 seconds
Started Aug 23 03:28:23 AM UTC 24
Finished Aug 23 03:36:50 AM UTC 24
Peak memory 212108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315041881 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2315041881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_rx_oversample.4205599480
Short name T444
Test name
Test status
Simulation time 5846391852 ps
CPU time 48.25 seconds
Started Aug 23 03:28:07 AM UTC 24
Finished Aug 23 03:28:57 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205599480 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4205599480
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.3850772656
Short name T150
Test name
Test status
Simulation time 67798534201 ps
CPU time 183.37 seconds
Started Aug 23 03:28:17 AM UTC 24
Finished Aug 23 03:31:24 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850772656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3850772656
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.3328232304
Short name T390
Test name
Test status
Simulation time 4211235354 ps
CPU time 6.95 seconds
Started Aug 23 03:28:13 AM UTC 24
Finished Aug 23 03:28:21 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328232304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3328232304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_smoke.3460179006
Short name T331
Test name
Test status
Simulation time 475740362 ps
CPU time 1.87 seconds
Started Aug 23 03:27:54 AM UTC 24
Finished Aug 23 03:27:57 AM UTC 24
Peak memory 207932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460179006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3460179006
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_stress_all.3837601218
Short name T364
Test name
Test status
Simulation time 3430645720 ps
CPU time 4.27 seconds
Started Aug 23 03:28:23 AM UTC 24
Finished Aug 23 03:28:28 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837601218 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3837601218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3389293560
Short name T36
Test name
Test status
Simulation time 2477033104 ps
CPU time 57.12 seconds
Started Aug 23 03:28:23 AM UTC 24
Finished Aug 23 03:29:21 AM UTC 24
Peak memory 221824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3389293560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_
with_rand_reset.3389293560
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1301010745
Short name T358
Test name
Test status
Simulation time 7001476936 ps
CPU time 13.61 seconds
Started Aug 23 03:28:17 AM UTC 24
Finished Aug 23 03:28:32 AM UTC 24
Peak memory 208436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301010745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1301010745
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/9.uart_tx_rx.3215841150
Short name T256
Test name
Test status
Simulation time 72684023771 ps
CPU time 6.35 seconds
Started Aug 23 03:27:58 AM UTC 24
Finished Aug 23 03:28:06 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215841150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3215841150
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/9.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/90.uart_fifo_reset.1464359448
Short name T995
Test name
Test status
Simulation time 19366876842 ps
CPU time 14.13 seconds
Started Aug 23 04:06:00 AM UTC 24
Finished Aug 23 04:06:15 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464359448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1464359448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/90.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.230971149
Short name T247
Test name
Test status
Simulation time 8770541122 ps
CPU time 19.2 seconds
Started Aug 23 04:06:11 AM UTC 24
Finished Aug 23 04:06:31 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=230971149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all_
with_rand_reset.230971149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/91.uart_fifo_reset.3147327005
Short name T173
Test name
Test status
Simulation time 36327597015 ps
CPU time 68.26 seconds
Started Aug 23 04:06:11 AM UTC 24
Finished Aug 23 04:07:21 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147327005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3147327005
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/91.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.3466057787
Short name T1005
Test name
Test status
Simulation time 4705824055 ps
CPU time 19.47 seconds
Started Aug 23 04:06:12 AM UTC 24
Finished Aug 23 04:06:33 AM UTC 24
Peak memory 209040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3466057787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all
_with_rand_reset.3466057787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/92.uart_fifo_reset.1364353145
Short name T176
Test name
Test status
Simulation time 44955492451 ps
CPU time 21.54 seconds
Started Aug 23 04:06:13 AM UTC 24
Finished Aug 23 04:06:35 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364353145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1364353145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/92.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.1812825863
Short name T998
Test name
Test status
Simulation time 548582546 ps
CPU time 7.81 seconds
Started Aug 23 04:06:15 AM UTC 24
Finished Aug 23 04:06:24 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1812825863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all
_with_rand_reset.1812825863
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/93.uart_fifo_reset.46383140
Short name T1037
Test name
Test status
Simulation time 384318920034 ps
CPU time 121.64 seconds
Started Aug 23 04:06:16 AM UTC 24
Finished Aug 23 04:08:20 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46383140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.46383140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/93.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.2369328124
Short name T1004
Test name
Test status
Simulation time 3591143449 ps
CPU time 15.48 seconds
Started Aug 23 04:06:17 AM UTC 24
Finished Aug 23 04:06:33 AM UTC 24
Peak memory 221768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2369328124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all
_with_rand_reset.2369328124
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/94.uart_fifo_reset.2977885696
Short name T1013
Test name
Test status
Simulation time 54977340178 ps
CPU time 39.84 seconds
Started Aug 23 04:06:20 AM UTC 24
Finished Aug 23 04:07:01 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977885696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2977885696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/94.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.2851828221
Short name T1007
Test name
Test status
Simulation time 30022872612 ps
CPU time 23.5 seconds
Started Aug 23 04:06:22 AM UTC 24
Finished Aug 23 04:06:47 AM UTC 24
Peak memory 219868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2851828221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all
_with_rand_reset.2851828221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/95.uart_fifo_reset.399993436
Short name T1051
Test name
Test status
Simulation time 116495020768 ps
CPU time 164.55 seconds
Started Aug 23 04:06:24 AM UTC 24
Finished Aug 23 04:09:11 AM UTC 24
Peak memory 208584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399993436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.399993436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/95.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.3672107801
Short name T1008
Test name
Test status
Simulation time 1926140517 ps
CPU time 20.42 seconds
Started Aug 23 04:06:27 AM UTC 24
Finished Aug 23 04:06:48 AM UTC 24
Peak memory 217588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3672107801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all
_with_rand_reset.3672107801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/96.uart_fifo_reset.1420935037
Short name T206
Test name
Test status
Simulation time 27482071241 ps
CPU time 22.45 seconds
Started Aug 23 04:06:29 AM UTC 24
Finished Aug 23 04:06:53 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420935037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1420935037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/96.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.3867454412
Short name T1021
Test name
Test status
Simulation time 34311470954 ps
CPU time 51.49 seconds
Started Aug 23 04:06:29 AM UTC 24
Finished Aug 23 04:07:22 AM UTC 24
Peak memory 224560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3867454412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all
_with_rand_reset.3867454412
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/97.uart_fifo_reset.1483351646
Short name T1035
Test name
Test status
Simulation time 258581798659 ps
CPU time 99.6 seconds
Started Aug 23 04:06:31 AM UTC 24
Finished Aug 23 04:08:12 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483351646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1483351646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/97.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2314814045
Short name T1022
Test name
Test status
Simulation time 12371331124 ps
CPU time 49.51 seconds
Started Aug 23 04:06:32 AM UTC 24
Finished Aug 23 04:07:23 AM UTC 24
Peak memory 225332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2314814045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all
_with_rand_reset.2314814045
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/98.uart_fifo_reset.201304690
Short name T725
Test name
Test status
Simulation time 44247269052 ps
CPU time 82.07 seconds
Started Aug 23 04:06:34 AM UTC 24
Finished Aug 23 04:07:58 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201304690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.201304690
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/98.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.1244874794
Short name T1010
Test name
Test status
Simulation time 5567770433 ps
CPU time 16.68 seconds
Started Aug 23 04:06:34 AM UTC 24
Finished Aug 23 04:06:52 AM UTC 24
Peak memory 217916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1244874794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all
_with_rand_reset.1244874794
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/99.uart_fifo_reset.619128977
Short name T1059
Test name
Test status
Simulation time 132745928481 ps
CPU time 188.34 seconds
Started Aug 23 04:06:34 AM UTC 24
Finished Aug 23 04:09:45 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619128977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.619128977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/99.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.1003332204
Short name T1014
Test name
Test status
Simulation time 4628406011 ps
CPU time 26.78 seconds
Started Aug 23 04:06:37 AM UTC 24
Finished Aug 23 04:07:05 AM UTC 24
Peak memory 217748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1003332204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all
_with_rand_reset.1003332204
Directory /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest
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