| T258 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/153.uart_fifo_reset.1847931658 |
|
|
Aug 25 04:02:54 AM UTC 24 |
Aug 25 04:05:03 AM UTC 24 |
34295689545 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/104.uart_fifo_reset.3189025839 |
|
|
Aug 25 04:01:46 AM UTC 24 |
Aug 25 04:05:03 AM UTC 24 |
275453468450 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/194.uart_fifo_reset.333031040 |
|
|
Aug 25 04:03:52 AM UTC 24 |
Aug 25 04:05:03 AM UTC 24 |
98618447490 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/121.uart_fifo_reset.1224066776 |
|
|
Aug 25 04:02:14 AM UTC 24 |
Aug 25 04:05:06 AM UTC 24 |
78702982590 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.3820792642 |
|
|
Aug 25 03:56:01 AM UTC 24 |
Aug 25 04:05:08 AM UTC 24 |
202755804803 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2219319545 |
|
|
Aug 25 04:04:25 AM UTC 24 |
Aug 25 04:05:10 AM UTC 24 |
37270829945 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/208.uart_fifo_reset.1366070167 |
|
|
Aug 25 04:04:12 AM UTC 24 |
Aug 25 04:05:11 AM UTC 24 |
27374418008 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/184.uart_fifo_reset.1012737837 |
|
|
Aug 25 04:03:36 AM UTC 24 |
Aug 25 04:05:11 AM UTC 24 |
22712863427 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/183.uart_fifo_reset.2882590239 |
|
|
Aug 25 04:03:27 AM UTC 24 |
Aug 25 04:05:12 AM UTC 24 |
127728158650 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/133.uart_fifo_reset.1518280467 |
|
|
Aug 25 04:02:26 AM UTC 24 |
Aug 25 04:05:12 AM UTC 24 |
150512943446 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/221.uart_fifo_reset.2100900063 |
|
|
Aug 25 04:04:32 AM UTC 24 |
Aug 25 04:05:14 AM UTC 24 |
33445182276 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/189.uart_fifo_reset.1503862855 |
|
|
Aug 25 04:03:46 AM UTC 24 |
Aug 25 04:05:14 AM UTC 24 |
65134097189 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/146.uart_fifo_reset.1739252826 |
|
|
Aug 25 04:02:44 AM UTC 24 |
Aug 25 04:05:15 AM UTC 24 |
122519051426 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/199.uart_fifo_reset.633624364 |
|
|
Aug 25 04:03:57 AM UTC 24 |
Aug 25 04:05:16 AM UTC 24 |
49535408588 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2501831372 |
|
|
Aug 25 04:04:02 AM UTC 24 |
Aug 25 04:05:19 AM UTC 24 |
19634037344 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/228.uart_fifo_reset.4110874509 |
|
|
Aug 25 04:04:46 AM UTC 24 |
Aug 25 04:05:20 AM UTC 24 |
61205480453 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/188.uart_fifo_reset.21501426 |
|
|
Aug 25 04:03:43 AM UTC 24 |
Aug 25 04:05:20 AM UTC 24 |
133462230402 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/108.uart_fifo_reset.144538643 |
|
|
Aug 25 04:01:51 AM UTC 24 |
Aug 25 04:05:20 AM UTC 24 |
135002306984 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/125.uart_fifo_reset.3754995110 |
|
|
Aug 25 04:02:17 AM UTC 24 |
Aug 25 04:05:24 AM UTC 24 |
304958686807 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3449244749 |
|
|
Aug 25 04:04:15 AM UTC 24 |
Aug 25 04:05:26 AM UTC 24 |
90114456392 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/94.uart_fifo_reset.944463729 |
|
|
Aug 25 04:01:20 AM UTC 24 |
Aug 25 04:05:27 AM UTC 24 |
109306209502 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/139.uart_fifo_reset.1427890860 |
|
|
Aug 25 04:02:35 AM UTC 24 |
Aug 25 04:05:27 AM UTC 24 |
135014339395 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/155.uart_fifo_reset.782489227 |
|
|
Aug 25 04:02:54 AM UTC 24 |
Aug 25 04:05:28 AM UTC 24 |
146785767768 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/200.uart_fifo_reset.1141062449 |
|
|
Aug 25 04:04:00 AM UTC 24 |
Aug 25 04:05:34 AM UTC 24 |
28158669462 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/224.uart_fifo_reset.1846229370 |
|
|
Aug 25 04:04:38 AM UTC 24 |
Aug 25 04:05:42 AM UTC 24 |
108810040576 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/190.uart_fifo_reset.128188118 |
|
|
Aug 25 04:03:48 AM UTC 24 |
Aug 25 04:05:42 AM UTC 24 |
31716745095 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/234.uart_fifo_reset.1357530299 |
|
|
Aug 25 04:05:00 AM UTC 24 |
Aug 25 04:05:42 AM UTC 24 |
24200013910 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1238103291 |
|
|
Aug 25 04:04:29 AM UTC 24 |
Aug 25 04:05:44 AM UTC 24 |
53753664481 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/154.uart_fifo_reset.2449090886 |
|
|
Aug 25 04:02:54 AM UTC 24 |
Aug 25 04:05:45 AM UTC 24 |
71098548108 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3230775527 |
|
|
Aug 25 04:05:15 AM UTC 24 |
Aug 25 04:05:52 AM UTC 24 |
12551556482 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/222.uart_fifo_reset.1123615045 |
|
|
Aug 25 04:04:35 AM UTC 24 |
Aug 25 04:05:52 AM UTC 24 |
94679073758 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/209.uart_fifo_reset.1158000723 |
|
|
Aug 25 04:04:14 AM UTC 24 |
Aug 25 04:05:55 AM UTC 24 |
51788057175 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/253.uart_fifo_reset.2550299657 |
|
|
Aug 25 04:05:20 AM UTC 24 |
Aug 25 04:05:55 AM UTC 24 |
23448017273 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/202.uart_fifo_reset.302816551 |
|
|
Aug 25 04:04:01 AM UTC 24 |
Aug 25 04:05:57 AM UTC 24 |
180952171626 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_perf.1916321280 |
|
|
Aug 25 03:52:47 AM UTC 24 |
Aug 25 04:05:59 AM UTC 24 |
11559883520 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/231.uart_fifo_reset.2440516229 |
|
|
Aug 25 04:04:51 AM UTC 24 |
Aug 25 04:06:00 AM UTC 24 |
18889616650 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.2580430597 |
|
|
Aug 25 03:58:10 AM UTC 24 |
Aug 25 04:06:02 AM UTC 24 |
42141541595 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/118.uart_fifo_reset.3382749548 |
|
|
Aug 25 04:02:12 AM UTC 24 |
Aug 25 04:06:03 AM UTC 24 |
73751946803 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1229701572 |
|
|
Aug 25 04:05:12 AM UTC 24 |
Aug 25 04:06:03 AM UTC 24 |
118916300460 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.4156303902 |
|
|
Aug 25 03:43:15 AM UTC 24 |
Aug 25 04:06:03 AM UTC 24 |
138073847767 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/249.uart_fifo_reset.3510664685 |
|
|
Aug 25 04:05:16 AM UTC 24 |
Aug 25 04:06:07 AM UTC 24 |
28483020151 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/246.uart_fifo_reset.2594909408 |
|
|
Aug 25 04:05:13 AM UTC 24 |
Aug 25 04:06:10 AM UTC 24 |
36749527455 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3632402265 |
|
|
Aug 25 04:04:49 AM UTC 24 |
Aug 25 04:06:15 AM UTC 24 |
25420239329 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1227617420 |
|
|
Aug 25 04:05:21 AM UTC 24 |
Aug 25 04:06:21 AM UTC 24 |
146334621528 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_stress_all.2555207107 |
|
|
Aug 25 03:57:40 AM UTC 24 |
Aug 25 04:06:22 AM UTC 24 |
163307865041 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/141.uart_fifo_reset.1534496372 |
|
|
Aug 25 04:02:41 AM UTC 24 |
Aug 25 04:06:22 AM UTC 24 |
132528003761 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/241.uart_fifo_reset.4205035715 |
|
|
Aug 25 04:05:10 AM UTC 24 |
Aug 25 04:06:22 AM UTC 24 |
116422959936 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/185.uart_fifo_reset.1398848432 |
|
|
Aug 25 04:03:38 AM UTC 24 |
Aug 25 04:06:23 AM UTC 24 |
285799420152 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/148.uart_fifo_reset.2467739374 |
|
|
Aug 25 04:02:46 AM UTC 24 |
Aug 25 04:06:25 AM UTC 24 |
82673130058 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/177.uart_fifo_reset.1125979485 |
|
|
Aug 25 04:03:22 AM UTC 24 |
Aug 25 04:06:25 AM UTC 24 |
139401073826 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/277.uart_fifo_reset.1182500097 |
|
|
Aug 25 04:06:04 AM UTC 24 |
Aug 25 04:06:27 AM UTC 24 |
25851484196 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3346819096 |
|
|
Aug 25 04:05:15 AM UTC 24 |
Aug 25 04:06:30 AM UTC 24 |
111072334593 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/214.uart_fifo_reset.4073724939 |
|
|
Aug 25 04:04:22 AM UTC 24 |
Aug 25 04:06:30 AM UTC 24 |
153810070621 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/237.uart_fifo_reset.3277528975 |
|
|
Aug 25 04:05:03 AM UTC 24 |
Aug 25 04:06:30 AM UTC 24 |
27431403338 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/225.uart_fifo_reset.2006550983 |
|
|
Aug 25 04:04:39 AM UTC 24 |
Aug 25 04:06:32 AM UTC 24 |
59065330604 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/262.uart_fifo_reset.3310181021 |
|
|
Aug 25 04:05:43 AM UTC 24 |
Aug 25 04:06:35 AM UTC 24 |
17871555261 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/251.uart_fifo_reset.3943300690 |
|
|
Aug 25 04:05:20 AM UTC 24 |
Aug 25 04:06:36 AM UTC 24 |
99895060403 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/227.uart_fifo_reset.2762000280 |
|
|
Aug 25 04:04:44 AM UTC 24 |
Aug 25 04:06:37 AM UTC 24 |
225742161109 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/279.uart_fifo_reset.151307795 |
|
|
Aug 25 04:06:04 AM UTC 24 |
Aug 25 04:06:40 AM UTC 24 |
12022044124 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/281.uart_fifo_reset.106506048 |
|
|
Aug 25 04:06:10 AM UTC 24 |
Aug 25 04:06:42 AM UTC 24 |
19502261654 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/116.uart_fifo_reset.3880050141 |
|
|
Aug 25 04:02:06 AM UTC 24 |
Aug 25 04:06:43 AM UTC 24 |
75607515570 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2907390625 |
|
|
Aug 25 04:04:56 AM UTC 24 |
Aug 25 04:06:46 AM UTC 24 |
99588052287 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/245.uart_fifo_reset.2569153351 |
|
|
Aug 25 04:05:13 AM UTC 24 |
Aug 25 04:06:47 AM UTC 24 |
52073967950 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/129.uart_fifo_reset.2537767334 |
|
|
Aug 25 04:02:22 AM UTC 24 |
Aug 25 04:06:51 AM UTC 24 |
86457033018 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/198.uart_fifo_reset.2070433971 |
|
|
Aug 25 04:03:55 AM UTC 24 |
Aug 25 04:06:52 AM UTC 24 |
72737509922 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2423027695 |
|
|
Aug 25 04:06:28 AM UTC 24 |
Aug 25 04:06:53 AM UTC 24 |
25855145451 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/258.uart_fifo_reset.2500968098 |
|
|
Aug 25 04:05:28 AM UTC 24 |
Aug 25 04:06:55 AM UTC 24 |
299617772919 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/284.uart_fifo_reset.3856841416 |
|
|
Aug 25 04:06:23 AM UTC 24 |
Aug 25 04:06:55 AM UTC 24 |
19999994937 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/275.uart_fifo_reset.2187632135 |
|
|
Aug 25 04:06:03 AM UTC 24 |
Aug 25 04:06:59 AM UTC 24 |
91584614580 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/256.uart_fifo_reset.1105612124 |
|
|
Aug 25 04:05:28 AM UTC 24 |
Aug 25 04:07:00 AM UTC 24 |
26519783612 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/265.uart_fifo_reset.2449132713 |
|
|
Aug 25 04:05:46 AM UTC 24 |
Aug 25 04:07:00 AM UTC 24 |
96206683349 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.907687466 |
|
|
Aug 25 03:49:36 AM UTC 24 |
Aug 25 04:07:04 AM UTC 24 |
138170504068 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/250.uart_fifo_reset.3683250255 |
|
|
Aug 25 04:05:17 AM UTC 24 |
Aug 25 04:07:04 AM UTC 24 |
133957139312 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/297.uart_fifo_reset.2491796420 |
|
|
Aug 25 04:06:38 AM UTC 24 |
Aug 25 04:07:05 AM UTC 24 |
20705355678 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/212.uart_fifo_reset.1639109151 |
|
|
Aug 25 04:04:16 AM UTC 24 |
Aug 25 04:07:08 AM UTC 24 |
64460428592 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/285.uart_fifo_reset.3864580003 |
|
|
Aug 25 04:06:23 AM UTC 24 |
Aug 25 04:07:11 AM UTC 24 |
20825741913 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/191.uart_fifo_reset.4137711678 |
|
|
Aug 25 04:03:49 AM UTC 24 |
Aug 25 04:07:12 AM UTC 24 |
180180328281 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_intr.3457446997 |
|
|
Aug 25 03:55:53 AM UTC 24 |
Aug 25 04:07:15 AM UTC 24 |
216560445296 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/242.uart_fifo_reset.417822619 |
|
|
Aug 25 04:05:11 AM UTC 24 |
Aug 25 04:07:17 AM UTC 24 |
36745118145 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_stress_all.3718997224 |
|
|
Aug 25 03:53:09 AM UTC 24 |
Aug 25 04:07:21 AM UTC 24 |
280283130626 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/299.uart_fifo_reset.1077412940 |
|
|
Aug 25 04:06:44 AM UTC 24 |
Aug 25 04:07:22 AM UTC 24 |
46255154251 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/238.uart_fifo_reset.126814965 |
|
|
Aug 25 04:05:04 AM UTC 24 |
Aug 25 04:07:24 AM UTC 24 |
43226836655 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/280.uart_fifo_reset.3540348246 |
|
|
Aug 25 04:06:08 AM UTC 24 |
Aug 25 04:07:25 AM UTC 24 |
22858115689 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/296.uart_fifo_reset.1582243007 |
|
|
Aug 25 04:06:37 AM UTC 24 |
Aug 25 04:07:27 AM UTC 24 |
203663256057 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/223.uart_fifo_reset.2659286126 |
|
|
Aug 25 04:04:35 AM UTC 24 |
Aug 25 04:07:29 AM UTC 24 |
69121713275 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_stress_all.794189308 |
|
|
Aug 25 03:55:33 AM UTC 24 |
Aug 25 04:07:29 AM UTC 24 |
254567692758 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3057021107 |
|
|
Aug 25 04:04:15 AM UTC 24 |
Aug 25 04:07:31 AM UTC 24 |
104278354755 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/261.uart_fifo_reset.972654819 |
|
|
Aug 25 04:05:43 AM UTC 24 |
Aug 25 04:07:32 AM UTC 24 |
149206368683 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/260.uart_fifo_reset.3425096263 |
|
|
Aug 25 04:05:35 AM UTC 24 |
Aug 25 04:07:33 AM UTC 24 |
85703236588 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/298.uart_fifo_reset.990594887 |
|
|
Aug 25 04:06:41 AM UTC 24 |
Aug 25 04:07:34 AM UTC 24 |
112622772745 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/295.uart_fifo_reset.1573053701 |
|
|
Aug 25 04:06:36 AM UTC 24 |
Aug 25 04:07:37 AM UTC 24 |
16781854674 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/272.uart_fifo_reset.371885085 |
|
|
Aug 25 04:06:01 AM UTC 24 |
Aug 25 04:07:40 AM UTC 24 |
42294440387 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/270.uart_fifo_reset.3006073619 |
|
|
Aug 25 04:05:58 AM UTC 24 |
Aug 25 04:07:42 AM UTC 24 |
41799832151 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/263.uart_fifo_reset.1824926948 |
|
|
Aug 25 04:05:43 AM UTC 24 |
Aug 25 04:07:42 AM UTC 24 |
48256683564 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1057428469 |
|
|
Aug 25 04:05:53 AM UTC 24 |
Aug 25 04:07:48 AM UTC 24 |
80875337063 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.203315594 |
|
|
Aug 25 03:46:58 AM UTC 24 |
Aug 25 04:07:48 AM UTC 24 |
99244597524 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/166.uart_fifo_reset.819979149 |
|
|
Aug 25 04:03:11 AM UTC 24 |
Aug 25 04:07:51 AM UTC 24 |
110982249875 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/257.uart_fifo_reset.613135726 |
|
|
Aug 25 04:05:28 AM UTC 24 |
Aug 25 04:07:57 AM UTC 24 |
62487378908 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/274.uart_fifo_reset.3331685647 |
|
|
Aug 25 04:06:02 AM UTC 24 |
Aug 25 04:07:57 AM UTC 24 |
153597806705 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/236.uart_fifo_reset.2907928376 |
|
|
Aug 25 04:05:01 AM UTC 24 |
Aug 25 04:07:58 AM UTC 24 |
130668360842 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/276.uart_fifo_reset.2943861499 |
|
|
Aug 25 04:06:03 AM UTC 24 |
Aug 25 04:08:03 AM UTC 24 |
38395488627 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/269.uart_fifo_reset.3166658462 |
|
|
Aug 25 04:05:56 AM UTC 24 |
Aug 25 04:08:04 AM UTC 24 |
207464388657 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/292.uart_fifo_reset.4274426740 |
|
|
Aug 25 04:06:30 AM UTC 24 |
Aug 25 04:08:10 AM UTC 24 |
28026461181 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/294.uart_fifo_reset.3126252802 |
|
|
Aug 25 04:06:33 AM UTC 24 |
Aug 25 04:08:10 AM UTC 24 |
66412419190 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/207.uart_fifo_reset.1050560766 |
|
|
Aug 25 04:04:12 AM UTC 24 |
Aug 25 04:08:25 AM UTC 24 |
193574932475 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/168.uart_fifo_reset.1345671968 |
|
|
Aug 25 04:03:13 AM UTC 24 |
Aug 25 04:08:26 AM UTC 24 |
117359637970 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/278.uart_fifo_reset.497865786 |
|
|
Aug 25 04:06:04 AM UTC 24 |
Aug 25 04:08:29 AM UTC 24 |
65858316765 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/264.uart_fifo_reset.1776602583 |
|
|
Aug 25 04:05:45 AM UTC 24 |
Aug 25 04:08:33 AM UTC 24 |
58125897255 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/288.uart_fifo_reset.1828233017 |
|
|
Aug 25 04:06:26 AM UTC 24 |
Aug 25 04:08:33 AM UTC 24 |
82900280973 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_perf.1760448247 |
|
|
Aug 25 03:51:03 AM UTC 24 |
Aug 25 04:08:37 AM UTC 24 |
12165874106 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/266.uart_fifo_reset.518552237 |
|
|
Aug 25 04:05:53 AM UTC 24 |
Aug 25 04:08:39 AM UTC 24 |
63684725202 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/273.uart_fifo_reset.2413937363 |
|
|
Aug 25 04:06:01 AM UTC 24 |
Aug 25 04:08:41 AM UTC 24 |
55808438778 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/271.uart_fifo_reset.2014568675 |
|
|
Aug 25 04:06:00 AM UTC 24 |
Aug 25 04:08:41 AM UTC 24 |
81000230764 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.2509395037 |
|
|
Aug 25 03:49:27 AM UTC 24 |
Aug 25 04:08:46 AM UTC 24 |
85486934370 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/244.uart_fifo_reset.2773757620 |
|
|
Aug 25 04:05:12 AM UTC 24 |
Aug 25 04:08:56 AM UTC 24 |
80452015119 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/216.uart_fifo_reset.275722303 |
|
|
Aug 25 04:04:28 AM UTC 24 |
Aug 25 04:08:57 AM UTC 24 |
110433190562 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1322828666 |
|
|
Aug 25 04:04:32 AM UTC 24 |
Aug 25 04:08:58 AM UTC 24 |
112586994562 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.4124558000 |
|
|
Aug 25 03:41:27 AM UTC 24 |
Aug 25 04:09:04 AM UTC 24 |
120697855315 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_fifo_full.2253225002 |
|
|
Aug 25 03:57:26 AM UTC 24 |
Aug 25 04:09:06 AM UTC 24 |
189028568094 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/226.uart_fifo_reset.2948396884 |
|
|
Aug 25 04:04:42 AM UTC 24 |
Aug 25 04:09:08 AM UTC 24 |
67634455084 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3725808530 |
|
|
Aug 25 04:06:24 AM UTC 24 |
Aug 25 04:09:08 AM UTC 24 |
74992337971 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_intr.3619529543 |
|
|
Aug 25 03:53:44 AM UTC 24 |
Aug 25 04:09:12 AM UTC 24 |
405226565518 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1766295648 |
|
|
Aug 25 04:05:04 AM UTC 24 |
Aug 25 04:09:16 AM UTC 24 |
178692473582 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_intr.3975845491 |
|
|
Aug 25 03:56:52 AM UTC 24 |
Aug 25 04:09:18 AM UTC 24 |
273686146575 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/178.uart_fifo_reset.4190595449 |
|
|
Aug 25 04:03:23 AM UTC 24 |
Aug 25 04:09:21 AM UTC 24 |
154272907624 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1028920777 |
|
|
Aug 25 04:06:30 AM UTC 24 |
Aug 25 04:09:30 AM UTC 24 |
97583595316 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/255.uart_fifo_reset.2865979765 |
|
|
Aug 25 04:05:25 AM UTC 24 |
Aug 25 04:09:38 AM UTC 24 |
104521083924 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/293.uart_fifo_reset.1561327295 |
|
|
Aug 25 04:06:31 AM UTC 24 |
Aug 25 04:09:39 AM UTC 24 |
194156731341 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_perf.243012890 |
|
|
Aug 25 03:54:45 AM UTC 24 |
Aug 25 04:09:41 AM UTC 24 |
11032428207 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/283.uart_fifo_reset.2658097493 |
|
|
Aug 25 04:06:23 AM UTC 24 |
Aug 25 04:09:41 AM UTC 24 |
81563048543 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2677798789 |
|
|
Aug 25 04:04:29 AM UTC 24 |
Aug 25 04:09:47 AM UTC 24 |
141456240295 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/235.uart_fifo_reset.1867335214 |
|
|
Aug 25 04:05:00 AM UTC 24 |
Aug 25 04:09:50 AM UTC 24 |
97069107362 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/192.uart_fifo_reset.406821512 |
|
|
Aug 25 04:03:51 AM UTC 24 |
Aug 25 04:09:55 AM UTC 24 |
126532589921 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/81.uart_fifo_reset.2103301710 |
|
|
Aug 25 04:00:40 AM UTC 24 |
Aug 25 04:10:04 AM UTC 24 |
245386338022 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/240.uart_fifo_reset.3211266474 |
|
|
Aug 25 04:05:06 AM UTC 24 |
Aug 25 04:10:11 AM UTC 24 |
159410700392 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2256897063 |
|
|
Aug 25 04:06:15 AM UTC 24 |
Aug 25 04:10:12 AM UTC 24 |
117728102841 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/127.uart_fifo_reset.2469325669 |
|
|
Aug 25 04:02:18 AM UTC 24 |
Aug 25 04:10:30 AM UTC 24 |
235636747121 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/229.uart_fifo_reset.3424269805 |
|
|
Aug 25 04:04:47 AM UTC 24 |
Aug 25 04:10:32 AM UTC 24 |
105027935827 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.3147600376 |
|
|
Aug 25 03:55:28 AM UTC 24 |
Aug 25 04:10:36 AM UTC 24 |
117030548692 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.122958058 |
|
|
Aug 25 03:58:36 AM UTC 24 |
Aug 25 04:10:41 AM UTC 24 |
162573935353 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/259.uart_fifo_reset.2780163559 |
|
|
Aug 25 04:05:29 AM UTC 24 |
Aug 25 04:10:50 AM UTC 24 |
148901364112 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/268.uart_fifo_reset.685746332 |
|
|
Aug 25 04:05:56 AM UTC 24 |
Aug 25 04:10:59 AM UTC 24 |
152910310508 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_stress_all.4284575092 |
|
|
Aug 25 03:58:38 AM UTC 24 |
Aug 25 04:11:01 AM UTC 24 |
125895880261 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_perf.3820273497 |
|
|
Aug 25 03:33:37 AM UTC 24 |
Aug 25 04:11:23 AM UTC 24 |
32599816986 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_perf.409978644 |
|
|
Aug 25 03:44:53 AM UTC 24 |
Aug 25 04:11:35 AM UTC 24 |
18468092713 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_stress_all.1013623965 |
|
|
Aug 25 03:50:36 AM UTC 24 |
Aug 25 04:15:04 AM UTC 24 |
280530055277 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.1982492615 |
|
|
Aug 25 03:52:22 AM UTC 24 |
Aug 25 04:15:09 AM UTC 24 |
135524274657 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/289.uart_fifo_reset.1033759526 |
|
|
Aug 25 04:06:26 AM UTC 24 |
Aug 25 04:15:24 AM UTC 24 |
124541769683 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.3062054683 |
|
|
Aug 25 03:51:03 AM UTC 24 |
Aug 25 04:22:38 AM UTC 24 |
139699275457 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_stress_all.2869229819 |
|
|
Aug 25 03:53:33 AM UTC 24 |
Aug 25 04:30:00 AM UTC 24 |
225296693803 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_stress_all.230230292 |
|
|
Aug 25 03:34:29 AM UTC 24 |
Aug 25 04:31:36 AM UTC 24 |
375819104858 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.3310103787 |
|
|
Aug 25 04:06:44 AM UTC 24 |
Aug 25 04:06:48 AM UTC 24 |
126991717 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.797495310 |
|
|
Aug 25 04:06:48 AM UTC 24 |
Aug 25 04:06:50 AM UTC 24 |
12484000 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.2000438654 |
|
|
Aug 25 04:06:47 AM UTC 24 |
Aug 25 04:06:50 AM UTC 24 |
249876989 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.3063485774 |
|
|
Aug 25 04:06:49 AM UTC 24 |
Aug 25 04:06:51 AM UTC 24 |
14964545 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.3378343600 |
|
|
Aug 25 04:06:50 AM UTC 24 |
Aug 25 04:06:52 AM UTC 24 |
34603303 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.4023388993 |
|
|
Aug 25 04:06:51 AM UTC 24 |
Aug 25 04:06:53 AM UTC 24 |
153268113 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.4141417505 |
|
|
Aug 25 04:06:51 AM UTC 24 |
Aug 25 04:06:53 AM UTC 24 |
262517997 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3030037266 |
|
|
Aug 25 04:06:52 AM UTC 24 |
Aug 25 04:06:55 AM UTC 24 |
21285487 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1604246714 |
|
|
Aug 25 04:06:51 AM UTC 24 |
Aug 25 04:06:56 AM UTC 24 |
688921704 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3705596893 |
|
|
Aug 25 04:06:54 AM UTC 24 |
Aug 25 04:06:56 AM UTC 24 |
67832670 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.2316130012 |
|
|
Aug 25 04:06:54 AM UTC 24 |
Aug 25 04:06:56 AM UTC 24 |
225772701 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1709625306 |
|
|
Aug 25 04:06:53 AM UTC 24 |
Aug 25 04:06:57 AM UTC 24 |
272578003 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2769032168 |
|
|
Aug 25 04:06:54 AM UTC 24 |
Aug 25 04:06:57 AM UTC 24 |
88164009 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.88990186 |
|
|
Aug 25 04:06:56 AM UTC 24 |
Aug 25 04:06:57 AM UTC 24 |
42070211 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.3111119516 |
|
|
Aug 25 04:06:57 AM UTC 24 |
Aug 25 04:06:59 AM UTC 24 |
161089642 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.2538010511 |
|
|
Aug 25 04:06:57 AM UTC 24 |
Aug 25 04:06:59 AM UTC 24 |
100376648 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3838670992 |
|
|
Aug 25 04:06:57 AM UTC 24 |
Aug 25 04:07:00 AM UTC 24 |
25935722 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3799484138 |
|
|
Aug 25 04:06:56 AM UTC 24 |
Aug 25 04:07:00 AM UTC 24 |
108796219 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.2035725418 |
|
|
Aug 25 04:06:57 AM UTC 24 |
Aug 25 04:07:00 AM UTC 24 |
27694196 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2121509551 |
|
|
Aug 25 04:06:58 AM UTC 24 |
Aug 25 04:07:00 AM UTC 24 |
33440534 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.3493881668 |
|
|
Aug 25 04:06:58 AM UTC 24 |
Aug 25 04:07:00 AM UTC 24 |
74421642 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.3739651294 |
|
|
Aug 25 04:06:58 AM UTC 24 |
Aug 25 04:07:00 AM UTC 24 |
463616431 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.894191821 |
|
|
Aug 25 04:07:00 AM UTC 24 |
Aug 25 04:07:02 AM UTC 24 |
29762912 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3930324137 |
|
|
Aug 25 04:07:00 AM UTC 24 |
Aug 25 04:07:02 AM UTC 24 |
58071795 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3030418690 |
|
|
Aug 25 04:07:00 AM UTC 24 |
Aug 25 04:07:03 AM UTC 24 |
59742565 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.1508462284 |
|
|
Aug 25 04:07:01 AM UTC 24 |
Aug 25 04:07:03 AM UTC 24 |
21098958 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2514838235 |
|
|
Aug 25 04:07:00 AM UTC 24 |
Aug 25 04:07:03 AM UTC 24 |
19371687 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.422247545 |
|
|
Aug 25 04:07:01 AM UTC 24 |
Aug 25 04:07:03 AM UTC 24 |
163928390 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2971226833 |
|
|
Aug 25 04:07:02 AM UTC 24 |
Aug 25 04:07:04 AM UTC 24 |
38626468 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.1670520953 |
|
|
Aug 25 04:07:00 AM UTC 24 |
Aug 25 04:07:04 AM UTC 24 |
1411009315 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2858165128 |
|
|
Aug 25 04:07:02 AM UTC 24 |
Aug 25 04:07:04 AM UTC 24 |
23813677 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.2720800102 |
|
|
Aug 25 04:07:01 AM UTC 24 |
Aug 25 04:07:04 AM UTC 24 |
281123929 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.209697776 |
|
|
Aug 25 04:07:03 AM UTC 24 |
Aug 25 04:07:05 AM UTC 24 |
20975740 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2908427220 |
|
|
Aug 25 04:07:03 AM UTC 24 |
Aug 25 04:07:05 AM UTC 24 |
21898439 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.875353342 |
|
|
Aug 25 04:07:02 AM UTC 24 |
Aug 25 04:07:05 AM UTC 24 |
535151514 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3139381465 |
|
|
Aug 25 04:07:03 AM UTC 24 |
Aug 25 04:07:05 AM UTC 24 |
19962028 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.2065501099 |
|
|
Aug 25 04:07:03 AM UTC 24 |
Aug 25 04:07:06 AM UTC 24 |
21534514 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.311990651 |
|
|
Aug 25 04:07:04 AM UTC 24 |
Aug 25 04:07:06 AM UTC 24 |
14088297 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.2708094304 |
|
|
Aug 25 04:07:04 AM UTC 24 |
Aug 25 04:07:06 AM UTC 24 |
25820110 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.1728141726 |
|
|
Aug 25 04:07:05 AM UTC 24 |
Aug 25 04:07:06 AM UTC 24 |
33115459 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.1018231071 |
|
|
Aug 25 04:07:05 AM UTC 24 |
Aug 25 04:07:07 AM UTC 24 |
25031824 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3125753999 |
|
|
Aug 25 04:07:05 AM UTC 24 |
Aug 25 04:07:07 AM UTC 24 |
98451206 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.3729297895 |
|
|
Aug 25 04:07:04 AM UTC 24 |
Aug 25 04:07:07 AM UTC 24 |
361910441 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3179227883 |
|
|
Aug 25 04:07:05 AM UTC 24 |
Aug 25 04:07:08 AM UTC 24 |
544199910 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.306855093 |
|
|
Aug 25 04:07:06 AM UTC 24 |
Aug 25 04:07:08 AM UTC 24 |
27728097 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.636993221 |
|
|
Aug 25 04:07:06 AM UTC 24 |
Aug 25 04:07:08 AM UTC 24 |
39768680 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.438452114 |
|
|
Aug 25 04:07:06 AM UTC 24 |
Aug 25 04:07:08 AM UTC 24 |
50952120 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1145811359 |
|
|
Aug 25 04:07:06 AM UTC 24 |
Aug 25 04:07:08 AM UTC 24 |
28308238 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.2538166443 |
|
|
Aug 25 04:07:06 AM UTC 24 |
Aug 25 04:07:09 AM UTC 24 |
241585262 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.2691246505 |
|
|
Aug 25 04:07:06 AM UTC 24 |
Aug 25 04:07:09 AM UTC 24 |
248134450 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.678007448 |
|
|
Aug 25 04:07:07 AM UTC 24 |
Aug 25 04:07:09 AM UTC 24 |
15080461 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1539250306 |
|
|
Aug 25 04:07:07 AM UTC 24 |
Aug 25 04:07:09 AM UTC 24 |
14833994 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.2205362741 |
|
|
Aug 25 04:07:07 AM UTC 24 |
Aug 25 04:07:10 AM UTC 24 |
102337493 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3522304207 |
|
|
Aug 25 04:07:07 AM UTC 24 |
Aug 25 04:07:10 AM UTC 24 |
33604861 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2256237229 |
|
|
Aug 25 04:07:07 AM UTC 24 |
Aug 25 04:07:10 AM UTC 24 |
71313428 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.1648727386 |
|
|
Aug 25 04:07:07 AM UTC 24 |
Aug 25 04:07:10 AM UTC 24 |
135038434 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.100745831 |
|
|
Aug 25 04:07:09 AM UTC 24 |
Aug 25 04:07:11 AM UTC 24 |
14067559 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3315031986 |
|
|
Aug 25 04:07:09 AM UTC 24 |
Aug 25 04:07:11 AM UTC 24 |
130304496 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.4169873159 |
|
|
Aug 25 04:07:09 AM UTC 24 |
Aug 25 04:07:11 AM UTC 24 |
54409694 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.2519459484 |
|
|
Aug 25 04:07:09 AM UTC 24 |
Aug 25 04:07:11 AM UTC 24 |
116521256 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3153488075 |
|
|
Aug 25 04:07:09 AM UTC 24 |
Aug 25 04:07:11 AM UTC 24 |
89988590 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.1065384389 |
|
|
Aug 25 04:07:09 AM UTC 24 |
Aug 25 04:07:12 AM UTC 24 |
110248194 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1336303933 |
|
|
Aug 25 04:07:12 AM UTC 24 |
Aug 25 04:07:14 AM UTC 24 |
63201267 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.1160923531 |
|
|
Aug 25 04:07:10 AM UTC 24 |
Aug 25 04:07:12 AM UTC 24 |
101857813 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.531526343 |
|
|
Aug 25 04:07:09 AM UTC 24 |
Aug 25 04:07:12 AM UTC 24 |
326024111 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.349739046 |
|
|
Aug 25 04:07:10 AM UTC 24 |
Aug 25 04:07:12 AM UTC 24 |
21870997 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.1486464617 |
|
|
Aug 25 04:07:10 AM UTC 24 |
Aug 25 04:07:12 AM UTC 24 |
98272752 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.203328145 |
|
|
Aug 25 04:07:10 AM UTC 24 |
Aug 25 04:07:13 AM UTC 24 |
89870092 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4251963055 |
|
|
Aug 25 04:07:10 AM UTC 24 |
Aug 25 04:07:13 AM UTC 24 |
31821395 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.1260561811 |
|
|
Aug 25 04:07:10 AM UTC 24 |
Aug 25 04:07:13 AM UTC 24 |
133774012 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.1647524230 |
|
|
Aug 25 04:07:12 AM UTC 24 |
Aug 25 04:07:13 AM UTC 24 |
14780128 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.1859796489 |
|
|
Aug 25 04:07:12 AM UTC 24 |
Aug 25 04:07:14 AM UTC 24 |
44705999 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.1456001957 |
|
|
Aug 25 04:07:12 AM UTC 24 |
Aug 25 04:07:14 AM UTC 24 |
46187802 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.2784922799 |
|
|
Aug 25 04:07:12 AM UTC 24 |
Aug 25 04:07:14 AM UTC 24 |
153577466 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.587005202 |
|
|
Aug 25 04:07:12 AM UTC 24 |
Aug 25 04:07:15 AM UTC 24 |
802329655 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1723542912 |
|
|
Aug 25 04:07:13 AM UTC 24 |
Aug 25 04:07:16 AM UTC 24 |
177179244 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.108020256 |
|
|
Aug 25 04:07:13 AM UTC 24 |
Aug 25 04:07:15 AM UTC 24 |
12813235 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.1889510964 |
|
|
Aug 25 04:07:15 AM UTC 24 |
Aug 25 04:07:17 AM UTC 24 |
23515987 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1865221076 |
|
|
Aug 25 04:07:13 AM UTC 24 |
Aug 25 04:07:15 AM UTC 24 |
15833269 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.3850448377 |
|
|
Aug 25 04:07:13 AM UTC 24 |
Aug 25 04:07:15 AM UTC 24 |
43556277 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.1389525270 |
|
|
Aug 25 04:07:13 AM UTC 24 |
Aug 25 04:07:15 AM UTC 24 |
43571909 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3086474228 |
|
|
Aug 25 04:07:13 AM UTC 24 |
Aug 25 04:07:15 AM UTC 24 |
134226976 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.3810680250 |
|
|
Aug 25 04:07:13 AM UTC 24 |
Aug 25 04:07:15 AM UTC 24 |
16480637 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.4244299629 |
|
|
Aug 25 04:07:13 AM UTC 24 |
Aug 25 04:07:16 AM UTC 24 |
70634376 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.2763698667 |
|
|
Aug 25 04:07:13 AM UTC 24 |
Aug 25 04:07:16 AM UTC 24 |
46613286 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.2434215278 |
|
|
Aug 25 04:07:13 AM UTC 24 |
Aug 25 04:07:16 AM UTC 24 |
171784858 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.636048656 |
|
|
Aug 25 04:07:15 AM UTC 24 |
Aug 25 04:07:17 AM UTC 24 |
47420417 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3675849427 |
|
|
Aug 25 04:07:15 AM UTC 24 |
Aug 25 04:07:17 AM UTC 24 |
67262203 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.1412298179 |
|
|
Aug 25 04:07:15 AM UTC 24 |
Aug 25 04:07:17 AM UTC 24 |
44262490 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.301216467 |
|
|
Aug 25 04:07:15 AM UTC 24 |
Aug 25 04:07:18 AM UTC 24 |
154956990 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1462838943 |
|
|
Aug 25 04:07:16 AM UTC 24 |
Aug 25 04:07:18 AM UTC 24 |
64506735 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.626857981 |
|
|
Aug 25 04:07:16 AM UTC 24 |
Aug 25 04:07:18 AM UTC 24 |
133951622 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2673000769 |
|
|
Aug 25 04:07:16 AM UTC 24 |
Aug 25 04:07:18 AM UTC 24 |
68224476 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.604115537 |
|
|
Aug 25 04:07:16 AM UTC 24 |
Aug 25 04:07:18 AM UTC 24 |
25192734 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1511528432 |
|
|
Aug 25 04:07:16 AM UTC 24 |
Aug 25 04:07:18 AM UTC 24 |
16941863 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.4132083394 |
|
|
Aug 25 04:07:16 AM UTC 24 |
Aug 25 04:07:19 AM UTC 24 |
47971728 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.154677099 |
|
|
Aug 25 04:07:15 AM UTC 24 |
Aug 25 04:07:19 AM UTC 24 |
89840000 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.2727404013 |
|
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