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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.62


Total test records in report: 1316
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T1255 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2933002937 Aug 25 04:07:17 AM UTC 24 Aug 25 04:07:20 AM UTC 24 231363925 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.2040747269 Aug 25 04:07:18 AM UTC 24 Aug 25 04:07:20 AM UTC 24 13406333 ps
T1256 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1931499835 Aug 25 04:07:18 AM UTC 24 Aug 25 04:07:20 AM UTC 24 27400653 ps
T1257 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.1278915265 Aug 25 04:07:18 AM UTC 24 Aug 25 04:07:20 AM UTC 24 33447450 ps
T1258 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1475682132 Aug 25 04:07:18 AM UTC 24 Aug 25 04:07:20 AM UTC 24 21161701 ps
T1259 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2818529826 Aug 25 04:07:18 AM UTC 24 Aug 25 04:07:20 AM UTC 24 99203941 ps
T1260 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.1486825794 Aug 25 04:07:17 AM UTC 24 Aug 25 04:07:21 AM UTC 24 465611478 ps
T1261 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.2474079585 Aug 25 04:07:18 AM UTC 24 Aug 25 04:07:21 AM UTC 24 367423916 ps
T1262 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.4161081013 Aug 25 04:07:19 AM UTC 24 Aug 25 04:07:21 AM UTC 24 16067679 ps
T1263 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.2461976660 Aug 25 04:07:20 AM UTC 24 Aug 25 04:07:21 AM UTC 24 25810772 ps
T1264 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1435655106 Aug 25 04:07:19 AM UTC 24 Aug 25 04:07:22 AM UTC 24 26965426 ps
T1265 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.4098383945 Aug 25 04:07:20 AM UTC 24 Aug 25 04:07:22 AM UTC 24 53196584 ps
T1266 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.3487651771 Aug 25 04:07:19 AM UTC 24 Aug 25 04:07:22 AM UTC 24 141723797 ps
T1267 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.3899766188 Aug 25 04:07:18 AM UTC 24 Aug 25 04:07:22 AM UTC 24 47789580 ps
T1268 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3815167545 Aug 25 04:07:20 AM UTC 24 Aug 25 04:07:22 AM UTC 24 386307090 ps
T1269 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2501638577 Aug 25 04:07:19 AM UTC 24 Aug 25 04:07:23 AM UTC 24 95388045 ps
T1270 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.2387784416 Aug 25 04:07:21 AM UTC 24 Aug 25 04:07:23 AM UTC 24 68507983 ps
T1271 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.3210679978 Aug 25 04:07:21 AM UTC 24 Aug 25 04:07:23 AM UTC 24 16918035 ps
T1272 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.4069392299 Aug 25 04:07:21 AM UTC 24 Aug 25 04:07:23 AM UTC 24 24571780 ps
T1273 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2514216298 Aug 25 04:07:21 AM UTC 24 Aug 25 04:07:23 AM UTC 24 21336905 ps
T1274 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3579201970 Aug 25 04:07:21 AM UTC 24 Aug 25 04:07:23 AM UTC 24 46314779 ps
T1275 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.2312538768 Aug 25 04:07:21 AM UTC 24 Aug 25 04:07:23 AM UTC 24 54837694 ps
T1276 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.724576065 Aug 25 04:07:21 AM UTC 24 Aug 25 04:07:24 AM UTC 24 31051868 ps
T1277 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3901344354 Aug 25 04:07:21 AM UTC 24 Aug 25 04:07:24 AM UTC 24 193766199 ps
T1278 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.1671359423 Aug 25 04:07:21 AM UTC 24 Aug 25 04:07:25 AM UTC 24 200097114 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.1630457250 Aug 25 04:07:23 AM UTC 24 Aug 25 04:07:25 AM UTC 24 14048465 ps
T1279 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.1713803330 Aug 25 04:07:23 AM UTC 24 Aug 25 04:07:25 AM UTC 24 13511887 ps
T1280 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.3167627181 Aug 25 04:07:23 AM UTC 24 Aug 25 04:07:25 AM UTC 24 31228515 ps
T1281 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2821244672 Aug 25 04:07:23 AM UTC 24 Aug 25 04:07:26 AM UTC 24 44913017 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.1954096805 Aug 25 04:07:23 AM UTC 24 Aug 25 04:07:26 AM UTC 24 14495299 ps
T1282 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1060938929 Aug 25 04:07:23 AM UTC 24 Aug 25 04:07:26 AM UTC 24 28130108 ps
T1283 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.3741405622 Aug 25 04:07:23 AM UTC 24 Aug 25 04:07:26 AM UTC 24 52839127 ps
T1284 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.920638177 Aug 25 04:07:23 AM UTC 24 Aug 25 04:07:26 AM UTC 24 159450285 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3140284991 Aug 25 04:07:23 AM UTC 24 Aug 25 04:07:26 AM UTC 24 210275115 ps
T1285 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2434786659 Aug 25 04:07:24 AM UTC 24 Aug 25 04:07:26 AM UTC 24 26328641 ps
T1286 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.4021742443 Aug 25 04:07:24 AM UTC 24 Aug 25 04:07:26 AM UTC 24 13523202 ps
T1287 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.2165162309 Aug 25 04:07:24 AM UTC 24 Aug 25 04:07:26 AM UTC 24 122239533 ps
T1288 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.3262353533 Aug 25 04:07:24 AM UTC 24 Aug 25 04:07:27 AM UTC 24 26139009 ps
T1289 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.1787764936 Aug 25 04:07:25 AM UTC 24 Aug 25 04:07:27 AM UTC 24 20137070 ps
T1290 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.588042607 Aug 25 04:07:25 AM UTC 24 Aug 25 04:07:27 AM UTC 24 18981486 ps
T1291 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2575739097 Aug 25 04:07:23 AM UTC 24 Aug 25 04:07:27 AM UTC 24 28376369 ps
T1292 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3063827537 Aug 25 04:07:25 AM UTC 24 Aug 25 04:07:27 AM UTC 24 33676549 ps
T1293 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2505271709 Aug 25 04:07:25 AM UTC 24 Aug 25 04:07:27 AM UTC 24 20359552 ps
T1294 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.3256035098 Aug 25 04:07:25 AM UTC 24 Aug 25 04:07:27 AM UTC 24 48300951 ps
T1295 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3540346524 Aug 25 04:07:24 AM UTC 24 Aug 25 04:07:27 AM UTC 24 82551179 ps
T1296 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.416725809 Aug 25 04:07:26 AM UTC 24 Aug 25 04:07:28 AM UTC 24 38741455 ps
T1297 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1549212354 Aug 25 04:07:26 AM UTC 24 Aug 25 04:07:28 AM UTC 24 34515285 ps
T1298 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.1539220246 Aug 25 04:07:26 AM UTC 24 Aug 25 04:07:28 AM UTC 24 48301287 ps
T1299 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.2776470070 Aug 25 04:07:26 AM UTC 24 Aug 25 04:07:28 AM UTC 24 30669111 ps
T1300 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.3685117234 Aug 25 04:07:26 AM UTC 24 Aug 25 04:07:28 AM UTC 24 13874598 ps
T1301 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2791555971 Aug 25 04:07:26 AM UTC 24 Aug 25 04:07:28 AM UTC 24 51526093 ps
T1302 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.1980972747 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:30 AM UTC 24 105459480 ps
T1303 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.1705708811 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:30 AM UTC 24 13035155 ps
T1304 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.3840053240 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 11515664 ps
T1305 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.3509651194 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 12945135 ps
T1306 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.942579757 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 13166287 ps
T1307 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.450809396 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 14597697 ps
T1308 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.2454194038 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 16925392 ps
T1309 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.2723975611 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 20869353 ps
T1310 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.2677036770 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 12389038 ps
T1311 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.636827589 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 34047457 ps
T1312 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1006373976 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 25074676 ps
T1313 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2721181669 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 45888608 ps
T1314 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.1894072228 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 11773543 ps
T1315 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1544875916 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 31133214 ps
T1316 /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.2731633000 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:31 AM UTC 24 41330395 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_noise_filter.3333605904
Short name T10
Test name
Test status
Simulation time 8118787528 ps
CPU time 11.09 seconds
Started Aug 25 03:33:23 AM UTC 24
Finished Aug 25 03:33:36 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333605904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3333605904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.1008397457
Short name T21
Test name
Test status
Simulation time 9259951069 ps
CPU time 89.02 seconds
Started Aug 25 03:33:13 AM UTC 24
Finished Aug 25 03:34:44 AM UTC 24
Peak memory 225472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1008397457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_
with_rand_reset.1008397457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_fifo_full.3326116369
Short name T12
Test name
Test status
Simulation time 50031312686 ps
CPU time 30.86 seconds
Started Aug 25 03:33:18 AM UTC 24
Finished Aug 25 03:33:50 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326116369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3326116369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_stress_all.417247497
Short name T177
Test name
Test status
Simulation time 219740088096 ps
CPU time 209.98 seconds
Started Aug 25 03:33:47 AM UTC 24
Finished Aug 25 03:37:21 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417247497 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.417247497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_stress_all.3679439136
Short name T103
Test name
Test status
Simulation time 691146077355 ps
CPU time 414.49 seconds
Started Aug 25 03:35:10 AM UTC 24
Finished Aug 25 03:42:10 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679439136 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3679439136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.2887289598
Short name T333
Test name
Test status
Simulation time 101288618681 ps
CPU time 282.85 seconds
Started Aug 25 03:35:04 AM UTC 24
Finished Aug 25 03:39:51 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887289598 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2887289598
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.2206182640
Short name T293
Test name
Test status
Simulation time 73619732892 ps
CPU time 463.35 seconds
Started Aug 25 03:34:47 AM UTC 24
Finished Aug 25 03:42:38 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206182640 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2206182640
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.1430271510
Short name T3
Test name
Test status
Simulation time 1391302991 ps
CPU time 2.56 seconds
Started Aug 25 03:33:08 AM UTC 24
Finished Aug 25 03:33:12 AM UTC 24
Peak memory 207532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430271510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1430271510
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_intr.1008021201
Short name T25
Test name
Test status
Simulation time 56446057725 ps
CPU time 18.7 seconds
Started Aug 25 03:34:57 AM UTC 24
Finished Aug 25 03:35:18 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008021201 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1008021201
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_stress_all.2873360946
Short name T148
Test name
Test status
Simulation time 200848046867 ps
CPU time 314.54 seconds
Started Aug 25 03:36:09 AM UTC 24
Finished Aug 25 03:41:28 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873360946 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2873360946
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.3220551027
Short name T138
Test name
Test status
Simulation time 192547896313 ps
CPU time 150.07 seconds
Started Aug 25 03:38:04 AM UTC 24
Finished Aug 25 03:40:37 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220551027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3220551027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_sec_cm.2456013611
Short name T31
Test name
Test status
Simulation time 83022215 ps
CPU time 1.14 seconds
Started Aug 25 03:33:48 AM UTC 24
Finished Aug 25 03:33:50 AM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456013611 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2456013611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_fifo_full.2133241885
Short name T101
Test name
Test status
Simulation time 57142032571 ps
CPU time 62.92 seconds
Started Aug 25 03:34:10 AM UTC 24
Finished Aug 25 03:35:14 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133241885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2133241885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_intr.15228816
Short name T19
Test name
Test status
Simulation time 52221531516 ps
CPU time 94.07 seconds
Started Aug 25 03:33:04 AM UTC 24
Finished Aug 25 03:34:41 AM UTC 24
Peak memory 208844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15228816 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.15228816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.3405974165
Short name T28
Test name
Test status
Simulation time 6159717341 ps
CPU time 50.26 seconds
Started Aug 25 03:34:06 AM UTC 24
Finished Aug 25 03:34:58 AM UTC 24
Peak memory 224788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3405974165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_
with_rand_reset.3405974165
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2858165128
Short name T62
Test name
Test status
Simulation time 23813677 ps
CPU time 0.9 seconds
Started Aug 25 04:07:02 AM UTC 24
Finished Aug 25 04:07:04 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858165128 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2858165128
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_fifo_full.2825149752
Short name T157
Test name
Test status
Simulation time 209865075330 ps
CPU time 177.23 seconds
Started Aug 25 03:36:14 AM UTC 24
Finished Aug 25 03:39:14 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825149752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2825149752
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_perf.3846855129
Short name T310
Test name
Test status
Simulation time 25295781127 ps
CPU time 255.39 seconds
Started Aug 25 03:35:48 AM UTC 24
Finished Aug 25 03:40:08 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846855129 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3846855129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.1477787032
Short name T110
Test name
Test status
Simulation time 138712380154 ps
CPU time 236.6 seconds
Started Aug 25 03:33:02 AM UTC 24
Finished Aug 25 03:37:02 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477787032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1477787032
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_fifo_reset.561601715
Short name T145
Test name
Test status
Simulation time 107579850421 ps
CPU time 231.35 seconds
Started Aug 25 03:35:56 AM UTC 24
Finished Aug 25 03:39:51 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561601715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.561601715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.2246868686
Short name T358
Test name
Test status
Simulation time 41219770782 ps
CPU time 276.6 seconds
Started Aug 25 03:38:45 AM UTC 24
Finished Aug 25 03:43:27 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246868686 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2246868686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_noise_filter.1193760953
Short name T55
Test name
Test status
Simulation time 141799627290 ps
CPU time 142.35 seconds
Started Aug 25 03:33:53 AM UTC 24
Finished Aug 25 03:36:17 AM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193760953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1193760953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_fifo_full.2280996206
Short name T317
Test name
Test status
Simulation time 246739387816 ps
CPU time 210.24 seconds
Started Aug 25 03:37:08 AM UTC 24
Finished Aug 25 03:40:42 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280996206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2280996206
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_fifo_reset.3023049756
Short name T188
Test name
Test status
Simulation time 79009182775 ps
CPU time 429.61 seconds
Started Aug 25 03:36:40 AM UTC 24
Finished Aug 25 03:43:57 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023049756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3023049756
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.587005202
Short name T85
Test name
Test status
Simulation time 802329655 ps
CPU time 1.96 seconds
Started Aug 25 04:07:12 AM UTC 24
Finished Aug 25 04:07:15 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587005202 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.587005202
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.557211980
Short name T314
Test name
Test status
Simulation time 167633413421 ps
CPU time 289.39 seconds
Started Aug 25 03:35:36 AM UTC 24
Finished Aug 25 03:40:30 AM UTC 24
Peak memory 208648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557211980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.557211980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.1111907341
Short name T273
Test name
Test status
Simulation time 237894483575 ps
CPU time 309.88 seconds
Started Aug 25 03:33:37 AM UTC 24
Finished Aug 25 03:38:52 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111907341 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1111907341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_fifo_full.3186558106
Short name T142
Test name
Test status
Simulation time 53592028643 ps
CPU time 33.19 seconds
Started Aug 25 03:34:55 AM UTC 24
Finished Aug 25 03:35:29 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186558106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3186558106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_alert_test.497641308
Short name T6
Test name
Test status
Simulation time 23816888 ps
CPU time 0.8 seconds
Started Aug 25 03:33:16 AM UTC 24
Finished Aug 25 03:33:18 AM UTC 24
Peak memory 204312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497641308 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.497641308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_fifo_reset.1450063549
Short name T114
Test name
Test status
Simulation time 81658835951 ps
CPU time 138.22 seconds
Started Aug 25 03:33:50 AM UTC 24
Finished Aug 25 03:36:11 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450063549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1450063549
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_fifo_reset.3681795058
Short name T150
Test name
Test status
Simulation time 139844252804 ps
CPU time 149.51 seconds
Started Aug 25 03:37:10 AM UTC 24
Finished Aug 25 03:39:43 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681795058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3681795058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_fifo_reset.4116163464
Short name T168
Test name
Test status
Simulation time 17976275842 ps
CPU time 104.3 seconds
Started Aug 25 03:38:29 AM UTC 24
Finished Aug 25 03:40:15 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116163464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.4116163464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.2127861121
Short name T143
Test name
Test status
Simulation time 127609537860 ps
CPU time 62.73 seconds
Started Aug 25 03:40:16 AM UTC 24
Finished Aug 25 03:41:21 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127861121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2127861121
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.1983656573
Short name T18
Test name
Test status
Simulation time 146784697881 ps
CPU time 27.23 seconds
Started Aug 25 03:34:01 AM UTC 24
Finished Aug 25 03:34:29 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983656573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1983656573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.136272727
Short name T22
Test name
Test status
Simulation time 4275390046 ps
CPU time 89.16 seconds
Started Aug 25 03:33:45 AM UTC 24
Finished Aug 25 03:35:17 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=136272727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_w
ith_rand_reset.136272727
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_fifo_reset.3054132216
Short name T144
Test name
Test status
Simulation time 102391046210 ps
CPU time 170.53 seconds
Started Aug 25 03:41:10 AM UTC 24
Finished Aug 25 03:44:03 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054132216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3054132216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_tx_rx.3565205706
Short name T48
Test name
Test status
Simulation time 114019650396 ps
CPU time 45.19 seconds
Started Aug 25 03:34:08 AM UTC 24
Finished Aug 25 03:34:55 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565205706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3565205706
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.301216467
Short name T81
Test name
Test status
Simulation time 154956990 ps
CPU time 1.95 seconds
Started Aug 25 04:07:15 AM UTC 24
Finished Aug 25 04:07:18 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301216467 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.301216467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_stress_all.4157096508
Short name T189
Test name
Test status
Simulation time 319165654662 ps
CPU time 281.79 seconds
Started Aug 25 03:40:30 AM UTC 24
Finished Aug 25 03:45:16 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157096508 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.4157096508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_stress_all.590714669
Short name T167
Test name
Test status
Simulation time 701688723596 ps
CPU time 520.79 seconds
Started Aug 25 03:39:55 AM UTC 24
Finished Aug 25 03:48:43 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590714669 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.590714669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_tx_rx.1039504413
Short name T17
Test name
Test status
Simulation time 30586159831 ps
CPU time 47.45 seconds
Started Aug 25 03:33:01 AM UTC 24
Finished Aug 25 03:33:50 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039504413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1039504413
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_stress_all.274276658
Short name T367
Test name
Test status
Simulation time 101507521738 ps
CPU time 149.13 seconds
Started Aug 25 03:45:01 AM UTC 24
Finished Aug 25 03:47:33 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274276658 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.274276658
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.118374406
Short name T294
Test name
Test status
Simulation time 167113659805 ps
CPU time 249.78 seconds
Started Aug 25 03:34:55 AM UTC 24
Finished Aug 25 03:39:09 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118374406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.118374406
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_stress_all.1912853800
Short name T401
Test name
Test status
Simulation time 603754621472 ps
CPU time 763.87 seconds
Started Aug 25 03:33:14 AM UTC 24
Finished Aug 25 03:46:07 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912853800 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1912853800
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.1106447278
Short name T307
Test name
Test status
Simulation time 62597148346 ps
CPU time 118.55 seconds
Started Aug 25 03:37:22 AM UTC 24
Finished Aug 25 03:39:23 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106447278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1106447278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.1883745868
Short name T170
Test name
Test status
Simulation time 36668205716 ps
CPU time 74.27 seconds
Started Aug 25 03:43:07 AM UTC 24
Finished Aug 25 03:44:24 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883745868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1883745868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_tx_rx.43495587
Short name T316
Test name
Test status
Simulation time 50722571287 ps
CPU time 198.53 seconds
Started Aug 25 03:34:31 AM UTC 24
Finished Aug 25 03:37:52 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43495587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.43495587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/174.uart_fifo_reset.217579498
Short name T215
Test name
Test status
Simulation time 15880567869 ps
CPU time 64.8 seconds
Started Aug 25 04:03:21 AM UTC 24
Finished Aug 25 04:04:27 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217579498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.217579498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/174.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/224.uart_fifo_reset.1846229370
Short name T231
Test name
Test status
Simulation time 108810040576 ps
CPU time 61.89 seconds
Started Aug 25 04:04:38 AM UTC 24
Finished Aug 25 04:05:42 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846229370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1846229370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/224.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_perf.1627614548
Short name T498
Test name
Test status
Simulation time 19289709416 ps
CPU time 273.02 seconds
Started Aug 25 03:39:18 AM UTC 24
Finished Aug 25 03:43:55 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627614548 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1627614548
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_fifo_reset.4250856755
Short name T172
Test name
Test status
Simulation time 53627614194 ps
CPU time 83.95 seconds
Started Aug 25 03:46:47 AM UTC 24
Finished Aug 25 03:48:13 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250856755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4250856755
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.2540251273
Short name T128
Test name
Test status
Simulation time 32259392735 ps
CPU time 58.71 seconds
Started Aug 25 03:34:22 AM UTC 24
Finished Aug 25 03:35:22 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540251273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2540251273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_stress_all.2793739547
Short name T102
Test name
Test status
Simulation time 102982623023 ps
CPU time 270.7 seconds
Started Aug 25 03:34:50 AM UTC 24
Finished Aug 25 03:39:24 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793739547 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2793739547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.706454082
Short name T30
Test name
Test status
Simulation time 46408123072 ps
CPU time 38.89 seconds
Started Aug 25 03:33:24 AM UTC 24
Finished Aug 25 03:34:05 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706454082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.706454082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_tx_rx.3721591567
Short name T326
Test name
Test status
Simulation time 105936513270 ps
CPU time 84.67 seconds
Started Aug 25 03:37:08 AM UTC 24
Finished Aug 25 03:38:35 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721591567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3721591567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/176.uart_fifo_reset.462790469
Short name T243
Test name
Test status
Simulation time 48903950858 ps
CPU time 53.19 seconds
Started Aug 25 04:03:21 AM UTC 24
Finished Aug 25 04:04:16 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462790469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.462790469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/176.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_fifo_reset.1486412256
Short name T174
Test name
Test status
Simulation time 159918245283 ps
CPU time 218.37 seconds
Started Aug 25 03:45:16 AM UTC 24
Finished Aug 25 03:48:58 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486412256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1486412256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_fifo_reset.1051975702
Short name T159
Test name
Test status
Simulation time 57385004593 ps
CPU time 81.57 seconds
Started Aug 25 03:46:24 AM UTC 24
Finished Aug 25 03:47:48 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051975702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1051975702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/104.uart_fifo_reset.3189025839
Short name T1066
Test name
Test status
Simulation time 275453468450 ps
CPU time 194.1 seconds
Started Aug 25 04:01:46 AM UTC 24
Finished Aug 25 04:05:03 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189025839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3189025839
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/104.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/110.uart_fifo_reset.1198619037
Short name T208
Test name
Test status
Simulation time 33508131402 ps
CPU time 55.21 seconds
Started Aug 25 04:01:55 AM UTC 24
Finished Aug 25 04:02:52 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198619037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1198619037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/110.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/134.uart_fifo_reset.3603785959
Short name T236
Test name
Test status
Simulation time 53918592377 ps
CPU time 17.99 seconds
Started Aug 25 04:02:26 AM UTC 24
Finished Aug 25 04:02:45 AM UTC 24
Peak memory 208360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603785959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3603785959
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/134.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.346254671
Short name T186
Test name
Test status
Simulation time 60731619761 ps
CPU time 84.8 seconds
Started Aug 25 03:39:48 AM UTC 24
Finished Aug 25 03:41:14 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346254671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.346254671
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.1235988364
Short name T274
Test name
Test status
Simulation time 2882483775 ps
CPU time 45.14 seconds
Started Aug 25 03:39:54 AM UTC 24
Finished Aug 25 03:40:41 AM UTC 24
Peak memory 221908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1235988364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all
_with_rand_reset.1235988364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_tx_rx.3950793804
Short name T376
Test name
Test status
Simulation time 97285405293 ps
CPU time 132.54 seconds
Started Aug 25 03:40:00 AM UTC 24
Finished Aug 25 03:42:16 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950793804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3950793804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/185.uart_fifo_reset.1398848432
Short name T226
Test name
Test status
Simulation time 285799420152 ps
CPU time 162.96 seconds
Started Aug 25 04:03:38 AM UTC 24
Finished Aug 25 04:06:23 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398848432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1398848432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/185.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_tx_rx.394616681
Short name T315
Test name
Test status
Simulation time 62379810839 ps
CPU time 44.91 seconds
Started Aug 25 03:42:17 AM UTC 24
Finished Aug 25 03:43:04 AM UTC 24
Peak memory 208924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394616681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.394616681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3449244749
Short name T183
Test name
Test status
Simulation time 90114456392 ps
CPU time 68 seconds
Started Aug 25 04:04:15 AM UTC 24
Finished Aug 25 04:05:26 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449244749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3449244749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/211.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/237.uart_fifo_reset.3277528975
Short name T248
Test name
Test status
Simulation time 27431403338 ps
CPU time 84.92 seconds
Started Aug 25 04:05:03 AM UTC 24
Finished Aug 25 04:06:30 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277528975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3277528975
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/237.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/298.uart_fifo_reset.990594887
Short name T228
Test name
Test status
Simulation time 112622772745 ps
CPU time 51.61 seconds
Started Aug 25 04:06:41 AM UTC 24
Finished Aug 25 04:07:34 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990594887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.990594887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/298.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_perf.4004720132
Short name T271
Test name
Test status
Simulation time 15990236982 ps
CPU time 237.59 seconds
Started Aug 25 03:33:11 AM UTC 24
Finished Aug 25 03:37:12 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004720132 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.4004720132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.1081730356
Short name T107
Test name
Test status
Simulation time 35426477779 ps
CPU time 58.59 seconds
Started Aug 25 03:33:19 AM UTC 24
Finished Aug 25 03:34:19 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081730356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1081730356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/100.uart_fifo_reset.3328002037
Short name T254
Test name
Test status
Simulation time 120430477338 ps
CPU time 136.32 seconds
Started Aug 25 04:01:39 AM UTC 24
Finished Aug 25 04:03:58 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328002037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3328002037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/100.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/119.uart_fifo_reset.1171324244
Short name T232
Test name
Test status
Simulation time 14843961542 ps
CPU time 47 seconds
Started Aug 25 04:02:12 AM UTC 24
Finished Aug 25 04:03:00 AM UTC 24
Peak memory 208432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171324244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1171324244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/119.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/125.uart_fifo_reset.3754995110
Short name T252
Test name
Test status
Simulation time 304958686807 ps
CPU time 183.78 seconds
Started Aug 25 04:02:17 AM UTC 24
Finished Aug 25 04:05:24 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754995110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3754995110
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/125.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/128.uart_fifo_reset.2246918130
Short name T240
Test name
Test status
Simulation time 116111799207 ps
CPU time 75.67 seconds
Started Aug 25 04:02:20 AM UTC 24
Finished Aug 25 04:03:37 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246918130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2246918130
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/128.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/131.uart_fifo_reset.1250701071
Short name T255
Test name
Test status
Simulation time 84931248508 ps
CPU time 71.39 seconds
Started Aug 25 04:02:25 AM UTC 24
Finished Aug 25 04:03:38 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250701071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1250701071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/131.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/133.uart_fifo_reset.1518280467
Short name T238
Test name
Test status
Simulation time 150512943446 ps
CPU time 163.36 seconds
Started Aug 25 04:02:26 AM UTC 24
Finished Aug 25 04:05:12 AM UTC 24
Peak memory 208236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518280467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1518280467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/133.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/140.uart_fifo_reset.1491349153
Short name T1041
Test name
Test status
Simulation time 143399966762 ps
CPU time 81.75 seconds
Started Aug 25 04:02:38 AM UTC 24
Finished Aug 25 04:04:02 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491349153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1491349153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/140.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/143.uart_fifo_reset.254948659
Short name T260
Test name
Test status
Simulation time 43446528154 ps
CPU time 136.65 seconds
Started Aug 25 04:02:41 AM UTC 24
Finished Aug 25 04:05:00 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254948659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.254948659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/143.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/152.uart_fifo_reset.2291078684
Short name T428
Test name
Test status
Simulation time 54103810395 ps
CPU time 26.76 seconds
Started Aug 25 04:02:52 AM UTC 24
Finished Aug 25 04:03:20 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291078684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2291078684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/152.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_fifo_reset.1444406220
Short name T146
Test name
Test status
Simulation time 40637554584 ps
CPU time 30.41 seconds
Started Aug 25 03:40:38 AM UTC 24
Finished Aug 25 03:41:09 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444406220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1444406220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/177.uart_fifo_reset.1125979485
Short name T233
Test name
Test status
Simulation time 139401073826 ps
CPU time 179.85 seconds
Started Aug 25 04:03:22 AM UTC 24
Finished Aug 25 04:06:25 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125979485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1125979485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/177.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/184.uart_fifo_reset.1012737837
Short name T245
Test name
Test status
Simulation time 22712863427 ps
CPU time 92.29 seconds
Started Aug 25 04:03:36 AM UTC 24
Finished Aug 25 04:05:11 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012737837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1012737837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/184.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_intr.21866768
Short name T921
Test name
Test status
Simulation time 334604163497 ps
CPU time 1044.21 seconds
Started Aug 25 03:43:03 AM UTC 24
Finished Aug 25 04:00:39 AM UTC 24
Peak memory 212204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21866768 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.21866768
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/214.uart_fifo_reset.4073724939
Short name T256
Test name
Test status
Simulation time 153810070621 ps
CPU time 125.33 seconds
Started Aug 25 04:04:22 AM UTC 24
Finished Aug 25 04:06:30 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073724939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4073724939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/214.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1322828666
Short name T249
Test name
Test status
Simulation time 112586994562 ps
CPU time 261.58 seconds
Started Aug 25 04:04:32 AM UTC 24
Finished Aug 25 04:08:58 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322828666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1322828666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/220.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/252.uart_fifo_reset.507753286
Short name T262
Test name
Test status
Simulation time 191904887244 ps
CPU time 38.77 seconds
Started Aug 25 04:05:20 AM UTC 24
Finished Aug 25 04:06:00 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507753286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.507753286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/252.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/268.uart_fifo_reset.685746332
Short name T259
Test name
Test status
Simulation time 152910310508 ps
CPU time 298.82 seconds
Started Aug 25 04:05:56 AM UTC 24
Finished Aug 25 04:10:59 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685746332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.685746332
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/268.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/280.uart_fifo_reset.3540348246
Short name T251
Test name
Test status
Simulation time 22858115689 ps
CPU time 74.12 seconds
Started Aug 25 04:06:08 AM UTC 24
Finished Aug 25 04:07:25 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540348246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3540348246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/280.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/284.uart_fifo_reset.3856841416
Short name T264
Test name
Test status
Simulation time 19999994937 ps
CPU time 31.42 seconds
Started Aug 25 04:06:23 AM UTC 24
Finished Aug 25 04:06:55 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856841416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3856841416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/284.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_fifo_reset.390854919
Short name T135
Test name
Test status
Simulation time 103562671022 ps
CPU time 64.14 seconds
Started Aug 25 03:34:56 AM UTC 24
Finished Aug 25 03:36:02 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390854919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.390854919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/61.uart_fifo_reset.551374555
Short name T160
Test name
Test status
Simulation time 15245471103 ps
CPU time 14.15 seconds
Started Aug 25 03:59:32 AM UTC 24
Finished Aug 25 03:59:48 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551374555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.551374555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/61.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/66.uart_fifo_reset.2965485325
Short name T230
Test name
Test status
Simulation time 19774197883 ps
CPU time 27 seconds
Started Aug 25 03:59:46 AM UTC 24
Finished Aug 25 04:00:14 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965485325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2965485325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/66.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.4141417505
Short name T56
Test name
Test status
Simulation time 262517997 ps
CPU time 1.16 seconds
Started Aug 25 04:06:51 AM UTC 24
Finished Aug 25 04:06:53 AM UTC 24
Peak memory 201760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141417505 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.4141417505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1604246714
Short name T1189
Test name
Test status
Simulation time 688921704 ps
CPU time 3.55 seconds
Started Aug 25 04:06:51 AM UTC 24
Finished Aug 25 04:06:56 AM UTC 24
Peak memory 202760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604246714 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1604246714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.3063485774
Short name T1187
Test name
Test status
Simulation time 14964545 ps
CPU time 0.87 seconds
Started Aug 25 04:06:49 AM UTC 24
Finished Aug 25 04:06:51 AM UTC 24
Peak memory 201760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063485774 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3063485774
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3030037266
Short name T1188
Test name
Test status
Simulation time 21285487 ps
CPU time 1.35 seconds
Started Aug 25 04:06:52 AM UTC 24
Finished Aug 25 04:06:55 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3030037266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r
eset.3030037266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.3378343600
Short name T70
Test name
Test status
Simulation time 34603303 ps
CPU time 0.84 seconds
Started Aug 25 04:06:50 AM UTC 24
Finished Aug 25 04:06:52 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378343600 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3378343600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.797495310
Short name T1186
Test name
Test status
Simulation time 12484000 ps
CPU time 0.81 seconds
Started Aug 25 04:06:48 AM UTC 24
Finished Aug 25 04:06:50 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797495310 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.797495310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.4023388993
Short name T71
Test name
Test status
Simulation time 153268113 ps
CPU time 1.09 seconds
Started Aug 25 04:06:51 AM UTC 24
Finished Aug 25 04:06:53 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023388993 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.4023388993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.3310103787
Short name T1185
Test name
Test status
Simulation time 126991717 ps
CPU time 3.1 seconds
Started Aug 25 04:06:44 AM UTC 24
Finished Aug 25 04:06:48 AM UTC 24
Peak memory 204848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310103787 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3310103787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.2000438654
Short name T76
Test name
Test status
Simulation time 249876989 ps
CPU time 2.35 seconds
Started Aug 25 04:06:47 AM UTC 24
Finished Aug 25 04:06:50 AM UTC 24
Peak memory 202756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000438654 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2000438654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.2538010511
Short name T58
Test name
Test status
Simulation time 100376648 ps
CPU time 1.12 seconds
Started Aug 25 04:06:57 AM UTC 24
Finished Aug 25 04:06:59 AM UTC 24
Peak memory 201760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538010511 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2538010511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3799484138
Short name T1194
Test name
Test status
Simulation time 108796219 ps
CPU time 3.05 seconds
Started Aug 25 04:06:56 AM UTC 24
Finished Aug 25 04:07:00 AM UTC 24
Peak memory 202888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799484138 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3799484138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.2316130012
Short name T1191
Test name
Test status
Simulation time 225772701 ps
CPU time 0.86 seconds
Started Aug 25 04:06:54 AM UTC 24
Finished Aug 25 04:06:56 AM UTC 24
Peak memory 201760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316130012 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2316130012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3838670992
Short name T1193
Test name
Test status
Simulation time 25935722 ps
CPU time 1.75 seconds
Started Aug 25 04:06:57 AM UTC 24
Finished Aug 25 04:07:00 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3838670992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_r
eset.3838670992
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.88990186
Short name T57
Test name
Test status
Simulation time 42070211 ps
CPU time 0.9 seconds
Started Aug 25 04:06:56 AM UTC 24
Finished Aug 25 04:06:57 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88990186 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.88990186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3705596893
Short name T1190
Test name
Test status
Simulation time 67832670 ps
CPU time 0.82 seconds
Started Aug 25 04:06:54 AM UTC 24
Finished Aug 25 04:06:56 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705596893 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3705596893
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.3111119516
Short name T72
Test name
Test status
Simulation time 161089642 ps
CPU time 1.08 seconds
Started Aug 25 04:06:57 AM UTC 24
Finished Aug 25 04:06:59 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111119516 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.3111119516
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1709625306
Short name T1192
Test name
Test status
Simulation time 272578003 ps
CPU time 2.19 seconds
Started Aug 25 04:06:53 AM UTC 24
Finished Aug 25 04:06:57 AM UTC 24
Peak memory 202620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709625306 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1709625306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2769032168
Short name T77
Test name
Test status
Simulation time 88164009 ps
CPU time 2.03 seconds
Started Aug 25 04:06:54 AM UTC 24
Finished Aug 25 04:06:57 AM UTC 24
Peak memory 202884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769032168 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2769032168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3086474228
Short name T1240
Test name
Test status
Simulation time 134226976 ps
CPU time 1.21 seconds
Started Aug 25 04:07:13 AM UTC 24
Finished Aug 25 04:07:15 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3086474228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_
reset.3086474228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1865221076
Short name T1237
Test name
Test status
Simulation time 15833269 ps
CPU time 0.91 seconds
Started Aug 25 04:07:13 AM UTC 24
Finished Aug 25 04:07:15 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865221076 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1865221076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.108020256
Short name T1235
Test name
Test status
Simulation time 12813235 ps
CPU time 0.85 seconds
Started Aug 25 04:07:13 AM UTC 24
Finished Aug 25 04:07:15 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108020256 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.108020256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.1389525270
Short name T1239
Test name
Test status
Simulation time 43571909 ps
CPU time 0.94 seconds
Started Aug 25 04:07:13 AM UTC 24
Finished Aug 25 04:07:15 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389525270 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.1389525270
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1723542912
Short name T1234
Test name
Test status
Simulation time 177179244 ps
CPU time 1.98 seconds
Started Aug 25 04:07:13 AM UTC 24
Finished Aug 25 04:07:16 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723542912 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1723542912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.2434215278
Short name T86
Test name
Test status
Simulation time 171784858 ps
CPU time 1.9 seconds
Started Aug 25 04:07:13 AM UTC 24
Finished Aug 25 04:07:16 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434215278 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2434215278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3675849427
Short name T1245
Test name
Test status
Simulation time 67262203 ps
CPU time 0.94 seconds
Started Aug 25 04:07:15 AM UTC 24
Finished Aug 25 04:07:17 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3675849427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_
reset.3675849427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.3810680250
Short name T1241
Test name
Test status
Simulation time 16480637 ps
CPU time 0.89 seconds
Started Aug 25 04:07:13 AM UTC 24
Finished Aug 25 04:07:15 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810680250 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3810680250
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.3850448377
Short name T1238
Test name
Test status
Simulation time 43556277 ps
CPU time 0.81 seconds
Started Aug 25 04:07:13 AM UTC 24
Finished Aug 25 04:07:15 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850448377 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3850448377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.636048656
Short name T1244
Test name
Test status
Simulation time 47420417 ps
CPU time 0.98 seconds
Started Aug 25 04:07:15 AM UTC 24
Finished Aug 25 04:07:17 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636048656 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.636048656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.4244299629
Short name T1242
Test name
Test status
Simulation time 70634376 ps
CPU time 1.3 seconds
Started Aug 25 04:07:13 AM UTC 24
Finished Aug 25 04:07:16 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244299629 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.4244299629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.2763698667
Short name T1243
Test name
Test status
Simulation time 46613286 ps
CPU time 1.37 seconds
Started Aug 25 04:07:13 AM UTC 24
Finished Aug 25 04:07:16 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763698667 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2763698667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2673000769
Short name T1249
Test name
Test status
Simulation time 68224476 ps
CPU time 0.98 seconds
Started Aug 25 04:07:16 AM UTC 24
Finished Aug 25 04:07:18 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2673000769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_
reset.2673000769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.1412298179
Short name T1246
Test name
Test status
Simulation time 44262490 ps
CPU time 0.84 seconds
Started Aug 25 04:07:15 AM UTC 24
Finished Aug 25 04:07:17 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412298179 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1412298179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.1889510964
Short name T1236
Test name
Test status
Simulation time 23515987 ps
CPU time 0.84 seconds
Started Aug 25 04:07:15 AM UTC 24
Finished Aug 25 04:07:17 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889510964 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1889510964
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.626857981
Short name T1248
Test name
Test status
Simulation time 133951622 ps
CPU time 0.91 seconds
Started Aug 25 04:07:16 AM UTC 24
Finished Aug 25 04:07:18 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626857981 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.626857981
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.154677099
Short name T1252
Test name
Test status
Simulation time 89840000 ps
CPU time 3.26 seconds
Started Aug 25 04:07:15 AM UTC 24
Finished Aug 25 04:07:19 AM UTC 24
Peak memory 202692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154677099 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.154677099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2933002937
Short name T1255
Test name
Test status
Simulation time 231363925 ps
CPU time 2.13 seconds
Started Aug 25 04:07:17 AM UTC 24
Finished Aug 25 04:07:20 AM UTC 24
Peak memory 204876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2933002937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_
reset.2933002937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.604115537
Short name T1250
Test name
Test status
Simulation time 25192734 ps
CPU time 0.87 seconds
Started Aug 25 04:07:16 AM UTC 24
Finished Aug 25 04:07:18 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604115537 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.604115537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1462838943
Short name T1247
Test name
Test status
Simulation time 64506735 ps
CPU time 0.87 seconds
Started Aug 25 04:07:16 AM UTC 24
Finished Aug 25 04:07:18 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462838943 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1462838943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1511528432
Short name T1251
Test name
Test status
Simulation time 16941863 ps
CPU time 1.02 seconds
Started Aug 25 04:07:16 AM UTC 24
Finished Aug 25 04:07:18 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511528432 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.1511528432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.2727404013
Short name T1253
Test name
Test status
Simulation time 30773935 ps
CPU time 2.14 seconds
Started Aug 25 04:07:16 AM UTC 24
Finished Aug 25 04:07:20 AM UTC 24
Peak memory 204808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727404013 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2727404013
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.4132083394
Short name T122
Test name
Test status
Simulation time 47971728 ps
CPU time 1.34 seconds
Started Aug 25 04:07:16 AM UTC 24
Finished Aug 25 04:07:19 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132083394 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.4132083394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1475682132
Short name T1258
Test name
Test status
Simulation time 21161701 ps
CPU time 1.04 seconds
Started Aug 25 04:07:18 AM UTC 24
Finished Aug 25 04:07:20 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1475682132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_
reset.1475682132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.2040747269
Short name T65
Test name
Test status
Simulation time 13406333 ps
CPU time 0.85 seconds
Started Aug 25 04:07:18 AM UTC 24
Finished Aug 25 04:07:20 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040747269 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2040747269
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1931499835
Short name T1256
Test name
Test status
Simulation time 27400653 ps
CPU time 0.88 seconds
Started Aug 25 04:07:18 AM UTC 24
Finished Aug 25 04:07:20 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931499835 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1931499835
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2818529826
Short name T1259
Test name
Test status
Simulation time 99203941 ps
CPU time 1.08 seconds
Started Aug 25 04:07:18 AM UTC 24
Finished Aug 25 04:07:20 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818529826 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.2818529826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.1486825794
Short name T1260
Test name
Test status
Simulation time 465611478 ps
CPU time 3.08 seconds
Started Aug 25 04:07:17 AM UTC 24
Finished Aug 25 04:07:21 AM UTC 24
Peak memory 202280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486825794 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1486825794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.264930897
Short name T1254
Test name
Test status
Simulation time 80908748 ps
CPU time 1.85 seconds
Started Aug 25 04:07:17 AM UTC 24
Finished Aug 25 04:07:20 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264930897 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.264930897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1435655106
Short name T1264
Test name
Test status
Simulation time 26965426 ps
CPU time 1.16 seconds
Started Aug 25 04:07:19 AM UTC 24
Finished Aug 25 04:07:22 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1435655106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_
reset.1435655106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.4161081013
Short name T1262
Test name
Test status
Simulation time 16067679 ps
CPU time 0.91 seconds
Started Aug 25 04:07:19 AM UTC 24
Finished Aug 25 04:07:21 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161081013 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.4161081013
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.1278915265
Short name T1257
Test name
Test status
Simulation time 33447450 ps
CPU time 0.84 seconds
Started Aug 25 04:07:18 AM UTC 24
Finished Aug 25 04:07:20 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278915265 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1278915265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.3487651771
Short name T1266
Test name
Test status
Simulation time 141723797 ps
CPU time 1.13 seconds
Started Aug 25 04:07:19 AM UTC 24
Finished Aug 25 04:07:22 AM UTC 24
Peak memory 205788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487651771 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.3487651771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.3899766188
Short name T1267
Test name
Test status
Simulation time 47789580 ps
CPU time 2.81 seconds
Started Aug 25 04:07:18 AM UTC 24
Finished Aug 25 04:07:22 AM UTC 24
Peak memory 202820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899766188 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3899766188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.2474079585
Short name T1261
Test name
Test status
Simulation time 367423916 ps
CPU time 1.98 seconds
Started Aug 25 04:07:18 AM UTC 24
Finished Aug 25 04:07:21 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474079585 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2474079585
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2514216298
Short name T1273
Test name
Test status
Simulation time 21336905 ps
CPU time 1.42 seconds
Started Aug 25 04:07:21 AM UTC 24
Finished Aug 25 04:07:23 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2514216298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_
reset.2514216298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.4098383945
Short name T1265
Test name
Test status
Simulation time 53196584 ps
CPU time 0.9 seconds
Started Aug 25 04:07:20 AM UTC 24
Finished Aug 25 04:07:22 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098383945 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4098383945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.2461976660
Short name T1263
Test name
Test status
Simulation time 25810772 ps
CPU time 0.83 seconds
Started Aug 25 04:07:20 AM UTC 24
Finished Aug 25 04:07:21 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461976660 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2461976660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.2387784416
Short name T1270
Test name
Test status
Simulation time 68507983 ps
CPU time 1.06 seconds
Started Aug 25 04:07:21 AM UTC 24
Finished Aug 25 04:07:23 AM UTC 24
Peak memory 205788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387784416 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.2387784416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2501638577
Short name T1269
Test name
Test status
Simulation time 95388045 ps
CPU time 2.06 seconds
Started Aug 25 04:07:19 AM UTC 24
Finished Aug 25 04:07:23 AM UTC 24
Peak memory 204740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501638577 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2501638577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3815167545
Short name T1268
Test name
Test status
Simulation time 386307090 ps
CPU time 1.83 seconds
Started Aug 25 04:07:20 AM UTC 24
Finished Aug 25 04:07:22 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815167545 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3815167545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.724576065
Short name T1276
Test name
Test status
Simulation time 31051868 ps
CPU time 1.19 seconds
Started Aug 25 04:07:21 AM UTC 24
Finished Aug 25 04:07:24 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=724576065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_r
eset.724576065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.3210679978
Short name T1271
Test name
Test status
Simulation time 16918035 ps
CPU time 0.91 seconds
Started Aug 25 04:07:21 AM UTC 24
Finished Aug 25 04:07:23 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210679978 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3210679978
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.4069392299
Short name T1272
Test name
Test status
Simulation time 24571780 ps
CPU time 0.88 seconds
Started Aug 25 04:07:21 AM UTC 24
Finished Aug 25 04:07:23 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069392299 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4069392299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3579201970
Short name T1274
Test name
Test status
Simulation time 46314779 ps
CPU time 0.99 seconds
Started Aug 25 04:07:21 AM UTC 24
Finished Aug 25 04:07:23 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579201970 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.3579201970
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3901344354
Short name T1277
Test name
Test status
Simulation time 193766199 ps
CPU time 1.72 seconds
Started Aug 25 04:07:21 AM UTC 24
Finished Aug 25 04:07:24 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901344354 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3901344354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.2312538768
Short name T1275
Test name
Test status
Simulation time 54837694 ps
CPU time 1.33 seconds
Started Aug 25 04:07:21 AM UTC 24
Finished Aug 25 04:07:23 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312538768 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2312538768
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1060938929
Short name T1282
Test name
Test status
Simulation time 28130108 ps
CPU time 1.24 seconds
Started Aug 25 04:07:23 AM UTC 24
Finished Aug 25 04:07:26 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1060938929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_
reset.1060938929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.1630457250
Short name T68
Test name
Test status
Simulation time 14048465 ps
CPU time 0.87 seconds
Started Aug 25 04:07:23 AM UTC 24
Finished Aug 25 04:07:25 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630457250 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1630457250
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.1713803330
Short name T1279
Test name
Test status
Simulation time 13511887 ps
CPU time 0.87 seconds
Started Aug 25 04:07:23 AM UTC 24
Finished Aug 25 04:07:25 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713803330 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1713803330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.3167627181
Short name T1280
Test name
Test status
Simulation time 31228515 ps
CPU time 0.96 seconds
Started Aug 25 04:07:23 AM UTC 24
Finished Aug 25 04:07:25 AM UTC 24
Peak memory 203804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167627181 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.3167627181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.1671359423
Short name T1278
Test name
Test status
Simulation time 200097114 ps
CPU time 2.64 seconds
Started Aug 25 04:07:21 AM UTC 24
Finished Aug 25 04:07:25 AM UTC 24
Peak memory 204664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671359423 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1671359423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.920638177
Short name T1284
Test name
Test status
Simulation time 159450285 ps
CPU time 1.39 seconds
Started Aug 25 04:07:23 AM UTC 24
Finished Aug 25 04:07:26 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920638177 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.920638177
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3540346524
Short name T1295
Test name
Test status
Simulation time 82551179 ps
CPU time 1.57 seconds
Started Aug 25 04:07:24 AM UTC 24
Finished Aug 25 04:07:27 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3540346524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_
reset.3540346524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.1954096805
Short name T69
Test name
Test status
Simulation time 14495299 ps
CPU time 0.94 seconds
Started Aug 25 04:07:23 AM UTC 24
Finished Aug 25 04:07:26 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954096805 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1954096805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2821244672
Short name T1281
Test name
Test status
Simulation time 44913017 ps
CPU time 0.86 seconds
Started Aug 25 04:07:23 AM UTC 24
Finished Aug 25 04:07:26 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821244672 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2821244672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.3741405622
Short name T1283
Test name
Test status
Simulation time 52839127 ps
CPU time 0.98 seconds
Started Aug 25 04:07:23 AM UTC 24
Finished Aug 25 04:07:26 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741405622 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.3741405622
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2575739097
Short name T1291
Test name
Test status
Simulation time 28376369 ps
CPU time 2 seconds
Started Aug 25 04:07:23 AM UTC 24
Finished Aug 25 04:07:27 AM UTC 24
Peak memory 201580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575739097 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2575739097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3140284991
Short name T82
Test name
Test status
Simulation time 210275115 ps
CPU time 1.43 seconds
Started Aug 25 04:07:23 AM UTC 24
Finished Aug 25 04:07:26 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140284991 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3140284991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3030418690
Short name T61
Test name
Test status
Simulation time 59742565 ps
CPU time 1.15 seconds
Started Aug 25 04:07:00 AM UTC 24
Finished Aug 25 04:07:03 AM UTC 24
Peak memory 201760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030418690 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3030418690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.1670520953
Short name T66
Test name
Test status
Simulation time 1411009315 ps
CPU time 2.21 seconds
Started Aug 25 04:07:00 AM UTC 24
Finished Aug 25 04:07:04 AM UTC 24
Peak memory 202824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670520953 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1670520953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.3493881668
Short name T59
Test name
Test status
Simulation time 74421642 ps
CPU time 0.87 seconds
Started Aug 25 04:06:58 AM UTC 24
Finished Aug 25 04:07:00 AM UTC 24
Peak memory 201760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493881668 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3493881668
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2514838235
Short name T1198
Test name
Test status
Simulation time 19371687 ps
CPU time 1.25 seconds
Started Aug 25 04:07:00 AM UTC 24
Finished Aug 25 04:07:03 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2514838235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_r
eset.2514838235
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.894191821
Short name T60
Test name
Test status
Simulation time 29762912 ps
CPU time 0.93 seconds
Started Aug 25 04:07:00 AM UTC 24
Finished Aug 25 04:07:02 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894191821 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.894191821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2121509551
Short name T1196
Test name
Test status
Simulation time 33440534 ps
CPU time 0.82 seconds
Started Aug 25 04:06:58 AM UTC 24
Finished Aug 25 04:07:00 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121509551 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2121509551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3930324137
Short name T73
Test name
Test status
Simulation time 58071795 ps
CPU time 1 seconds
Started Aug 25 04:07:00 AM UTC 24
Finished Aug 25 04:07:02 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930324137 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.3930324137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.2035725418
Short name T1195
Test name
Test status
Simulation time 27694196 ps
CPU time 1.92 seconds
Started Aug 25 04:06:57 AM UTC 24
Finished Aug 25 04:07:00 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035725418 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2035725418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.3739651294
Short name T78
Test name
Test status
Simulation time 463616431 ps
CPU time 1.39 seconds
Started Aug 25 04:06:58 AM UTC 24
Finished Aug 25 04:07:00 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739651294 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3739651294
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2434786659
Short name T1285
Test name
Test status
Simulation time 26328641 ps
CPU time 0.83 seconds
Started Aug 25 04:07:24 AM UTC 24
Finished Aug 25 04:07:26 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434786659 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2434786659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.4021742443
Short name T1286
Test name
Test status
Simulation time 13523202 ps
CPU time 0.83 seconds
Started Aug 25 04:07:24 AM UTC 24
Finished Aug 25 04:07:26 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021742443 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.4021742443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.2165162309
Short name T1287
Test name
Test status
Simulation time 122239533 ps
CPU time 0.84 seconds
Started Aug 25 04:07:24 AM UTC 24
Finished Aug 25 04:07:26 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165162309 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2165162309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.3262353533
Short name T1288
Test name
Test status
Simulation time 26139009 ps
CPU time 0.81 seconds
Started Aug 25 04:07:24 AM UTC 24
Finished Aug 25 04:07:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262353533 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3262353533
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.1787764936
Short name T1289
Test name
Test status
Simulation time 20137070 ps
CPU time 0.85 seconds
Started Aug 25 04:07:25 AM UTC 24
Finished Aug 25 04:07:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787764936 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1787764936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2505271709
Short name T1293
Test name
Test status
Simulation time 20359552 ps
CPU time 0.84 seconds
Started Aug 25 04:07:25 AM UTC 24
Finished Aug 25 04:07:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505271709 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2505271709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3063827537
Short name T1292
Test name
Test status
Simulation time 33676549 ps
CPU time 0.83 seconds
Started Aug 25 04:07:25 AM UTC 24
Finished Aug 25 04:07:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063827537 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3063827537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.588042607
Short name T1290
Test name
Test status
Simulation time 18981486 ps
CPU time 0.83 seconds
Started Aug 25 04:07:25 AM UTC 24
Finished Aug 25 04:07:27 AM UTC 24
Peak memory 201616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588042607 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.588042607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.3256035098
Short name T1294
Test name
Test status
Simulation time 48300951 ps
CPU time 0.81 seconds
Started Aug 25 04:07:25 AM UTC 24
Finished Aug 25 04:07:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256035098 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3256035098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.1539220246
Short name T1298
Test name
Test status
Simulation time 48301287 ps
CPU time 0.85 seconds
Started Aug 25 04:07:26 AM UTC 24
Finished Aug 25 04:07:28 AM UTC 24
Peak memory 201240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539220246 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1539220246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2908427220
Short name T1201
Test name
Test status
Simulation time 21898439 ps
CPU time 1.01 seconds
Started Aug 25 04:07:03 AM UTC 24
Finished Aug 25 04:07:05 AM UTC 24
Peak memory 201760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908427220 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2908427220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.875353342
Short name T1202
Test name
Test status
Simulation time 535151514 ps
CPU time 2.33 seconds
Started Aug 25 04:07:02 AM UTC 24
Finished Aug 25 04:07:05 AM UTC 24
Peak memory 202696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875353342 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.875353342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2971226833
Short name T1199
Test name
Test status
Simulation time 38626468 ps
CPU time 0.84 seconds
Started Aug 25 04:07:02 AM UTC 24
Finished Aug 25 04:07:04 AM UTC 24
Peak memory 201760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971226833 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2971226833
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3139381465
Short name T1203
Test name
Test status
Simulation time 19962028 ps
CPU time 1.35 seconds
Started Aug 25 04:07:03 AM UTC 24
Finished Aug 25 04:07:05 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3139381465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r
eset.3139381465
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.1508462284
Short name T1197
Test name
Test status
Simulation time 21098958 ps
CPU time 0.84 seconds
Started Aug 25 04:07:01 AM UTC 24
Finished Aug 25 04:07:03 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508462284 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1508462284
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.209697776
Short name T74
Test name
Test status
Simulation time 20975740 ps
CPU time 0.94 seconds
Started Aug 25 04:07:03 AM UTC 24
Finished Aug 25 04:07:05 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209697776 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.209697776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.2720800102
Short name T1200
Test name
Test status
Simulation time 281123929 ps
CPU time 2.2 seconds
Started Aug 25 04:07:01 AM UTC 24
Finished Aug 25 04:07:04 AM UTC 24
Peak memory 202672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720800102 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2720800102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.422247545
Short name T121
Test name
Test status
Simulation time 163928390 ps
CPU time 1.39 seconds
Started Aug 25 04:07:01 AM UTC 24
Finished Aug 25 04:07:03 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422247545 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.422247545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1549212354
Short name T1297
Test name
Test status
Simulation time 34515285 ps
CPU time 0.86 seconds
Started Aug 25 04:07:26 AM UTC 24
Finished Aug 25 04:07:28 AM UTC 24
Peak memory 201260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549212354 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1549212354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.416725809
Short name T1296
Test name
Test status
Simulation time 38741455 ps
CPU time 0.83 seconds
Started Aug 25 04:07:26 AM UTC 24
Finished Aug 25 04:07:28 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416725809 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.416725809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2791555971
Short name T1301
Test name
Test status
Simulation time 51526093 ps
CPU time 0.87 seconds
Started Aug 25 04:07:26 AM UTC 24
Finished Aug 25 04:07:28 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791555971 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2791555971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.3685117234
Short name T1300
Test name
Test status
Simulation time 13874598 ps
CPU time 0.83 seconds
Started Aug 25 04:07:26 AM UTC 24
Finished Aug 25 04:07:28 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685117234 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3685117234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.2776470070
Short name T1299
Test name
Test status
Simulation time 30669111 ps
CPU time 0.81 seconds
Started Aug 25 04:07:26 AM UTC 24
Finished Aug 25 04:07:28 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776470070 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2776470070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.1980972747
Short name T1302
Test name
Test status
Simulation time 105459480 ps
CPU time 0.8 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:30 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980972747 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1980972747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.3840053240
Short name T1304
Test name
Test status
Simulation time 11515664 ps
CPU time 0.84 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840053240 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3840053240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.1705708811
Short name T1303
Test name
Test status
Simulation time 13035155 ps
CPU time 0.84 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:30 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705708811 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1705708811
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.450809396
Short name T1307
Test name
Test status
Simulation time 14597697 ps
CPU time 0.87 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450809396 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.450809396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.942579757
Short name T1306
Test name
Test status
Simulation time 13166287 ps
CPU time 0.86 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942579757 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.942579757
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.1018231071
Short name T1207
Test name
Test status
Simulation time 25031824 ps
CPU time 1.03 seconds
Started Aug 25 04:07:05 AM UTC 24
Finished Aug 25 04:07:07 AM UTC 24
Peak memory 201760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018231071 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1018231071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3179227883
Short name T1208
Test name
Test status
Simulation time 544199910 ps
CPU time 2.25 seconds
Started Aug 25 04:07:05 AM UTC 24
Finished Aug 25 04:07:08 AM UTC 24
Peak memory 202684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179227883 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3179227883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.2708094304
Short name T1206
Test name
Test status
Simulation time 25820110 ps
CPU time 0.89 seconds
Started Aug 25 04:07:04 AM UTC 24
Finished Aug 25 04:07:06 AM UTC 24
Peak memory 201760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708094304 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2708094304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.438452114
Short name T1210
Test name
Test status
Simulation time 50952120 ps
CPU time 1.21 seconds
Started Aug 25 04:07:06 AM UTC 24
Finished Aug 25 04:07:08 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=438452114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_re
set.438452114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.1728141726
Short name T63
Test name
Test status
Simulation time 33115459 ps
CPU time 0.84 seconds
Started Aug 25 04:07:05 AM UTC 24
Finished Aug 25 04:07:06 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728141726 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1728141726
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.311990651
Short name T1205
Test name
Test status
Simulation time 14088297 ps
CPU time 0.83 seconds
Started Aug 25 04:07:04 AM UTC 24
Finished Aug 25 04:07:06 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311990651 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.311990651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3125753999
Short name T75
Test name
Test status
Simulation time 98451206 ps
CPU time 1.05 seconds
Started Aug 25 04:07:05 AM UTC 24
Finished Aug 25 04:07:07 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125753999 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.3125753999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.2065501099
Short name T1204
Test name
Test status
Simulation time 21534514 ps
CPU time 1.59 seconds
Started Aug 25 04:07:03 AM UTC 24
Finished Aug 25 04:07:06 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065501099 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2065501099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.3729297895
Short name T84
Test name
Test status
Simulation time 361910441 ps
CPU time 1.91 seconds
Started Aug 25 04:07:04 AM UTC 24
Finished Aug 25 04:07:07 AM UTC 24
Peak memory 201712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729297895 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3729297895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.2677036770
Short name T1310
Test name
Test status
Simulation time 12389038 ps
CPU time 0.84 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677036770 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2677036770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.636827589
Short name T1311
Test name
Test status
Simulation time 34047457 ps
CPU time 0.85 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636827589 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.636827589
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.2723975611
Short name T1309
Test name
Test status
Simulation time 20869353 ps
CPU time 0.85 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723975611 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2723975611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.2731633000
Short name T1316
Test name
Test status
Simulation time 41330395 ps
CPU time 0.83 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731633000 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2731633000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1544875916
Short name T1315
Test name
Test status
Simulation time 31133214 ps
CPU time 0.84 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544875916 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1544875916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1006373976
Short name T1312
Test name
Test status
Simulation time 25074676 ps
CPU time 0.85 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006373976 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1006373976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.3509651194
Short name T1305
Test name
Test status
Simulation time 12945135 ps
CPU time 0.84 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509651194 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3509651194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.1894072228
Short name T1314
Test name
Test status
Simulation time 11773543 ps
CPU time 0.88 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894072228 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1894072228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2721181669
Short name T1313
Test name
Test status
Simulation time 45888608 ps
CPU time 0.84 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721181669 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2721181669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.2454194038
Short name T1308
Test name
Test status
Simulation time 16925392 ps
CPU time 0.88 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454194038 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2454194038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3522304207
Short name T1216
Test name
Test status
Simulation time 33604861 ps
CPU time 1.32 seconds
Started Aug 25 04:07:07 AM UTC 24
Finished Aug 25 04:07:10 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3522304207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r
eset.3522304207
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.636993221
Short name T67
Test name
Test status
Simulation time 39768680 ps
CPU time 0.86 seconds
Started Aug 25 04:07:06 AM UTC 24
Finished Aug 25 04:07:08 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636993221 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.636993221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.306855093
Short name T1209
Test name
Test status
Simulation time 27728097 ps
CPU time 0.8 seconds
Started Aug 25 04:07:06 AM UTC 24
Finished Aug 25 04:07:08 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306855093 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.306855093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1145811359
Short name T1211
Test name
Test status
Simulation time 28308238 ps
CPU time 1.08 seconds
Started Aug 25 04:07:06 AM UTC 24
Finished Aug 25 04:07:08 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145811359 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.1145811359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.2538166443
Short name T1212
Test name
Test status
Simulation time 241585262 ps
CPU time 1.72 seconds
Started Aug 25 04:07:06 AM UTC 24
Finished Aug 25 04:07:09 AM UTC 24
Peak memory 203676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538166443 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2538166443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.2691246505
Short name T80
Test name
Test status
Simulation time 248134450 ps
CPU time 1.93 seconds
Started Aug 25 04:07:06 AM UTC 24
Finished Aug 25 04:07:09 AM UTC 24
Peak memory 201712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691246505 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2691246505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3315031986
Short name T1219
Test name
Test status
Simulation time 130304496 ps
CPU time 1.06 seconds
Started Aug 25 04:07:09 AM UTC 24
Finished Aug 25 04:07:11 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3315031986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_r
eset.3315031986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1539250306
Short name T1214
Test name
Test status
Simulation time 14833994 ps
CPU time 0.89 seconds
Started Aug 25 04:07:07 AM UTC 24
Finished Aug 25 04:07:09 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539250306 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1539250306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.678007448
Short name T1213
Test name
Test status
Simulation time 15080461 ps
CPU time 0.88 seconds
Started Aug 25 04:07:07 AM UTC 24
Finished Aug 25 04:07:09 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678007448 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.678007448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.2205362741
Short name T1215
Test name
Test status
Simulation time 102337493 ps
CPU time 0.97 seconds
Started Aug 25 04:07:07 AM UTC 24
Finished Aug 25 04:07:10 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205362741 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.2205362741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2256237229
Short name T1217
Test name
Test status
Simulation time 71313428 ps
CPU time 1.96 seconds
Started Aug 25 04:07:07 AM UTC 24
Finished Aug 25 04:07:10 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256237229 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2256237229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.1648727386
Short name T79
Test name
Test status
Simulation time 135038434 ps
CPU time 2.06 seconds
Started Aug 25 04:07:07 AM UTC 24
Finished Aug 25 04:07:10 AM UTC 24
Peak memory 202884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648727386 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1648727386
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3153488075
Short name T1222
Test name
Test status
Simulation time 89988590 ps
CPU time 1.16 seconds
Started Aug 25 04:07:09 AM UTC 24
Finished Aug 25 04:07:11 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3153488075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_r
eset.3153488075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.4169873159
Short name T1220
Test name
Test status
Simulation time 54409694 ps
CPU time 0.9 seconds
Started Aug 25 04:07:09 AM UTC 24
Finished Aug 25 04:07:11 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169873159 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4169873159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.100745831
Short name T1218
Test name
Test status
Simulation time 14067559 ps
CPU time 0.71 seconds
Started Aug 25 04:07:09 AM UTC 24
Finished Aug 25 04:07:11 AM UTC 24
Peak memory 201568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100745831 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.100745831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.2519459484
Short name T1221
Test name
Test status
Simulation time 116521256 ps
CPU time 1.12 seconds
Started Aug 25 04:07:09 AM UTC 24
Finished Aug 25 04:07:11 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519459484 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.2519459484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.1065384389
Short name T1223
Test name
Test status
Simulation time 110248194 ps
CPU time 1.96 seconds
Started Aug 25 04:07:09 AM UTC 24
Finished Aug 25 04:07:12 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065384389 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1065384389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.531526343
Short name T83
Test name
Test status
Simulation time 326024111 ps
CPU time 1.97 seconds
Started Aug 25 04:07:09 AM UTC 24
Finished Aug 25 04:07:12 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531526343 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.531526343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4251963055
Short name T1229
Test name
Test status
Simulation time 31821395 ps
CPU time 1.25 seconds
Started Aug 25 04:07:10 AM UTC 24
Finished Aug 25 04:07:13 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4251963055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r
eset.4251963055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.349739046
Short name T1226
Test name
Test status
Simulation time 21870997 ps
CPU time 0.82 seconds
Started Aug 25 04:07:10 AM UTC 24
Finished Aug 25 04:07:12 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349739046 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.349739046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.1160923531
Short name T1225
Test name
Test status
Simulation time 101857813 ps
CPU time 0.84 seconds
Started Aug 25 04:07:10 AM UTC 24
Finished Aug 25 04:07:12 AM UTC 24
Peak memory 200800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160923531 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1160923531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.1486464617
Short name T1227
Test name
Test status
Simulation time 98272752 ps
CPU time 1.06 seconds
Started Aug 25 04:07:10 AM UTC 24
Finished Aug 25 04:07:12 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486464617 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.1486464617
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.203328145
Short name T1228
Test name
Test status
Simulation time 89870092 ps
CPU time 1.33 seconds
Started Aug 25 04:07:10 AM UTC 24
Finished Aug 25 04:07:13 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203328145 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.203328145
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.1260561811
Short name T1230
Test name
Test status
Simulation time 133774012 ps
CPU time 1.87 seconds
Started Aug 25 04:07:10 AM UTC 24
Finished Aug 25 04:07:13 AM UTC 24
Peak memory 201712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260561811 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1260561811
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1336303933
Short name T1224
Test name
Test status
Simulation time 63201267 ps
CPU time 0.9 seconds
Started Aug 25 04:07:12 AM UTC 24
Finished Aug 25 04:07:14 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1336303933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r
eset.1336303933
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.1859796489
Short name T64
Test name
Test status
Simulation time 44705999 ps
CPU time 0.92 seconds
Started Aug 25 04:07:12 AM UTC 24
Finished Aug 25 04:07:14 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859796489 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1859796489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.1647524230
Short name T1231
Test name
Test status
Simulation time 14780128 ps
CPU time 0.86 seconds
Started Aug 25 04:07:12 AM UTC 24
Finished Aug 25 04:07:13 AM UTC 24
Peak memory 201660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647524230 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1647524230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.1456001957
Short name T1232
Test name
Test status
Simulation time 46187802 ps
CPU time 1.04 seconds
Started Aug 25 04:07:12 AM UTC 24
Finished Aug 25 04:07:14 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456001957 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.1456001957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.2784922799
Short name T1233
Test name
Test status
Simulation time 153577466 ps
CPU time 1.64 seconds
Started Aug 25 04:07:12 AM UTC 24
Finished Aug 25 04:07:14 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784922799 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2784922799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_fifo_full.2580564489
Short name T11
Test name
Test status
Simulation time 36889214169 ps
CPU time 33.63 seconds
Started Aug 25 03:33:01 AM UTC 24
Finished Aug 25 03:33:36 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580564489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2580564489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2104250325
Short name T106
Test name
Test status
Simulation time 82626641906 ps
CPU time 73.8 seconds
Started Aug 25 03:33:02 AM UTC 24
Finished Aug 25 03:34:18 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104250325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2104250325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.2642198470
Short name T272
Test name
Test status
Simulation time 155281202533 ps
CPU time 212.91 seconds
Started Aug 25 03:33:13 AM UTC 24
Finished Aug 25 03:36:49 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642198470 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2642198470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_loopback.2993469239
Short name T4
Test name
Test status
Simulation time 1871602388 ps
CPU time 5.66 seconds
Started Aug 25 03:33:08 AM UTC 24
Finished Aug 25 03:33:15 AM UTC 24
Peak memory 207500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993469239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2993469239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_noise_filter.3288641967
Short name T46
Test name
Test status
Simulation time 84224590604 ps
CPU time 106.58 seconds
Started Aug 25 03:33:05 AM UTC 24
Finished Aug 25 03:34:54 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288641967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3288641967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_rx_oversample.2340883224
Short name T7
Test name
Test status
Simulation time 1796425117 ps
CPU time 12.66 seconds
Started Aug 25 03:33:04 AM UTC 24
Finished Aug 25 03:33:18 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340883224 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2340883224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.1303252063
Short name T343
Test name
Test status
Simulation time 108248363259 ps
CPU time 319.09 seconds
Started Aug 25 03:33:07 AM UTC 24
Finished Aug 25 03:38:31 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303252063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1303252063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.430373316
Short name T2
Test name
Test status
Simulation time 3519483204 ps
CPU time 4.42 seconds
Started Aug 25 03:33:06 AM UTC 24
Finished Aug 25 03:33:12 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430373316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.430373316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_sec_cm.394620860
Short name T5
Test name
Test status
Simulation time 70831747 ps
CPU time 1.26 seconds
Started Aug 25 03:33:15 AM UTC 24
Finished Aug 25 03:33:17 AM UTC 24
Peak memory 240132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394620860 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.394620860
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/0.uart_smoke.3933300822
Short name T1
Test name
Test status
Simulation time 860694181 ps
CPU time 3.29 seconds
Started Aug 25 03:33:00 AM UTC 24
Finished Aug 25 03:33:04 AM UTC 24
Peak memory 207572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933300822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3933300822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/0.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_alert_test.969902635
Short name T33
Test name
Test status
Simulation time 11815087 ps
CPU time 0.81 seconds
Started Aug 25 03:33:48 AM UTC 24
Finished Aug 25 03:33:50 AM UTC 24
Peak memory 202328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969902635 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.969902635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_fifo_reset.176304298
Short name T392
Test name
Test status
Simulation time 99313041567 ps
CPU time 155.83 seconds
Started Aug 25 03:33:19 AM UTC 24
Finished Aug 25 03:35:58 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176304298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.176304298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_intr.1500428711
Short name T9
Test name
Test status
Simulation time 7147505003 ps
CPU time 2.37 seconds
Started Aug 25 03:33:20 AM UTC 24
Finished Aug 25 03:33:24 AM UTC 24
Peak memory 207340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500428711 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1500428711
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_loopback.4154494125
Short name T16
Test name
Test status
Simulation time 8458268858 ps
CPU time 10.62 seconds
Started Aug 25 03:33:37 AM UTC 24
Finished Aug 25 03:33:49 AM UTC 24
Peak memory 207944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154494125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.4154494125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_perf.3820273497
Short name T1178
Test name
Test status
Simulation time 32599816986 ps
CPU time 2239.34 seconds
Started Aug 25 03:33:37 AM UTC 24
Finished Aug 25 04:11:23 AM UTC 24
Peak memory 212148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820273497 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3820273497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_rx_oversample.2891641240
Short name T14
Test name
Test status
Simulation time 4126869312 ps
CPU time 26.47 seconds
Started Aug 25 03:33:20 AM UTC 24
Finished Aug 25 03:33:48 AM UTC 24
Peak memory 207348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891641240 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2891641240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2501144914
Short name T23
Test name
Test status
Simulation time 22430522391 ps
CPU time 58.92 seconds
Started Aug 25 03:33:27 AM UTC 24
Finished Aug 25 03:34:27 AM UTC 24
Peak memory 208324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501144914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2501144914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_smoke.2034981917
Short name T8
Test name
Test status
Simulation time 691100609 ps
CPU time 5.24 seconds
Started Aug 25 03:33:16 AM UTC 24
Finished Aug 25 03:33:22 AM UTC 24
Peak memory 208168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034981917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2034981917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.793869374
Short name T15
Test name
Test status
Simulation time 9317280586 ps
CPU time 13.17 seconds
Started Aug 25 03:33:34 AM UTC 24
Finished Aug 25 03:33:48 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793869374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.793869374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/1.uart_tx_rx.2045283177
Short name T98
Test name
Test status
Simulation time 69825746204 ps
CPU time 105.38 seconds
Started Aug 25 03:33:18 AM UTC 24
Finished Aug 25 03:35:06 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045283177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2045283177
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/1.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_alert_test.3253963543
Short name T442
Test name
Test status
Simulation time 11314418 ps
CPU time 0.79 seconds
Started Aug 25 03:37:05 AM UTC 24
Finished Aug 25 03:37:07 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253963543 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3253963543
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_fifo_full.1184010899
Short name T268
Test name
Test status
Simulation time 123338726689 ps
CPU time 100.87 seconds
Started Aug 25 03:36:33 AM UTC 24
Finished Aug 25 03:38:16 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184010899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1184010899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.3070598016
Short name T127
Test name
Test status
Simulation time 12956566576 ps
CPU time 13.32 seconds
Started Aug 25 03:36:35 AM UTC 24
Finished Aug 25 03:36:50 AM UTC 24
Peak memory 208532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070598016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3070598016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_intr.780880747
Short name T116
Test name
Test status
Simulation time 209021532779 ps
CPU time 314.1 seconds
Started Aug 25 03:36:44 AM UTC 24
Finished Aug 25 03:42:03 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780880747 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.780880747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.15411106
Short name T522
Test name
Test status
Simulation time 165117721416 ps
CPU time 508.12 seconds
Started Aug 25 03:37:02 AM UTC 24
Finished Aug 25 03:45:39 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15411106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.15411106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_loopback.2471718808
Short name T447
Test name
Test status
Simulation time 13312981766 ps
CPU time 48.3 seconds
Started Aug 25 03:37:00 AM UTC 24
Finished Aug 25 03:37:50 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471718808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2471718808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_noise_filter.4012910618
Short name T278
Test name
Test status
Simulation time 42992911723 ps
CPU time 51.07 seconds
Started Aug 25 03:36:51 AM UTC 24
Finished Aug 25 03:37:43 AM UTC 24
Peak memory 207788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012910618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.4012910618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_perf.2550076013
Short name T474
Test name
Test status
Simulation time 9994992100 ps
CPU time 313.06 seconds
Started Aug 25 03:37:00 AM UTC 24
Finished Aug 25 03:42:18 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550076013 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2550076013
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_rx_oversample.2775494259
Short name T443
Test name
Test status
Simulation time 2510188668 ps
CPU time 21.09 seconds
Started Aug 25 03:36:44 AM UTC 24
Finished Aug 25 03:37:07 AM UTC 24
Peak memory 207700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775494259 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2775494259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.3977857368
Short name T134
Test name
Test status
Simulation time 10403682806 ps
CPU time 16.58 seconds
Started Aug 25 03:36:56 AM UTC 24
Finished Aug 25 03:37:14 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977857368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3977857368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.1516199868
Short name T365
Test name
Test status
Simulation time 709388614 ps
CPU time 3.43 seconds
Started Aug 25 03:36:51 AM UTC 24
Finished Aug 25 03:36:55 AM UTC 24
Peak memory 205160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516199868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1516199868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_smoke.1477117322
Short name T350
Test name
Test status
Simulation time 254753148 ps
CPU time 1.72 seconds
Started Aug 25 03:36:32 AM UTC 24
Finished Aug 25 03:36:35 AM UTC 24
Peak memory 206380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477117322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1477117322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_stress_all.1575861825
Short name T298
Test name
Test status
Simulation time 369651117392 ps
CPU time 440.45 seconds
Started Aug 25 03:37:04 AM UTC 24
Finished Aug 25 03:44:30 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575861825 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1575861825
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.2422344929
Short name T120
Test name
Test status
Simulation time 7068724221 ps
CPU time 52.99 seconds
Started Aug 25 03:37:03 AM UTC 24
Finished Aug 25 03:37:58 AM UTC 24
Peak memory 217980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2422344929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all
_with_rand_reset.2422344929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.2968989210
Short name T366
Test name
Test status
Simulation time 1275069671 ps
CPU time 2.35 seconds
Started Aug 25 03:36:58 AM UTC 24
Finished Aug 25 03:37:01 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968989210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2968989210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/10.uart_tx_rx.1129905578
Short name T291
Test name
Test status
Simulation time 53356917596 ps
CPU time 197.24 seconds
Started Aug 25 03:36:33 AM UTC 24
Finished Aug 25 03:39:54 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129905578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1129905578
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/10.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/101.uart_fifo_reset.3872503756
Short name T984
Test name
Test status
Simulation time 68743614293 ps
CPU time 48.56 seconds
Started Aug 25 04:01:40 AM UTC 24
Finished Aug 25 04:02:31 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872503756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3872503756
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/101.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/102.uart_fifo_reset.3156615044
Short name T967
Test name
Test status
Simulation time 29912235815 ps
CPU time 22.74 seconds
Started Aug 25 04:01:40 AM UTC 24
Finished Aug 25 04:02:04 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156615044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3156615044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/102.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/103.uart_fifo_reset.2537503973
Short name T996
Test name
Test status
Simulation time 21797978400 ps
CPU time 67.2 seconds
Started Aug 25 04:01:45 AM UTC 24
Finished Aug 25 04:02:53 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537503973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2537503973
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/103.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/105.uart_fifo_reset.2787583770
Short name T966
Test name
Test status
Simulation time 69634361154 ps
CPU time 17.22 seconds
Started Aug 25 04:01:46 AM UTC 24
Finished Aug 25 04:02:04 AM UTC 24
Peak memory 208492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787583770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2787583770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/105.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/106.uart_fifo_reset.3499251582
Short name T1003
Test name
Test status
Simulation time 19413888455 ps
CPU time 69.62 seconds
Started Aug 25 04:01:48 AM UTC 24
Finished Aug 25 04:03:00 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499251582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3499251582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/106.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/107.uart_fifo_reset.3161999470
Short name T1004
Test name
Test status
Simulation time 20654647168 ps
CPU time 70.16 seconds
Started Aug 25 04:01:49 AM UTC 24
Finished Aug 25 04:03:01 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161999470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3161999470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/107.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/108.uart_fifo_reset.144538643
Short name T1079
Test name
Test status
Simulation time 135002306984 ps
CPU time 206.14 seconds
Started Aug 25 04:01:51 AM UTC 24
Finished Aug 25 04:05:20 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144538643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.144538643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/108.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/109.uart_fifo_reset.2070015912
Short name T211
Test name
Test status
Simulation time 88162890448 ps
CPU time 35.26 seconds
Started Aug 25 04:01:54 AM UTC 24
Finished Aug 25 04:02:31 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070015912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2070015912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/109.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_alert_test.4220772453
Short name T446
Test name
Test status
Simulation time 25429987 ps
CPU time 0.84 seconds
Started Aug 25 03:37:32 AM UTC 24
Finished Aug 25 03:37:34 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220772453 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4220772453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.1478563051
Short name T280
Test name
Test status
Simulation time 24495753016 ps
CPU time 19.69 seconds
Started Aug 25 03:37:10 AM UTC 24
Finished Aug 25 03:37:31 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478563051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1478563051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_intr.1959157324
Short name T389
Test name
Test status
Simulation time 20901245999 ps
CPU time 15.38 seconds
Started Aug 25 03:37:15 AM UTC 24
Finished Aug 25 03:37:31 AM UTC 24
Peak memory 207076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959157324 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1959157324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.573248937
Short name T744
Test name
Test status
Simulation time 113000583529 ps
CPU time 951.31 seconds
Started Aug 25 03:37:30 AM UTC 24
Finished Aug 25 03:53:34 AM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573248937 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.573248937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_loopback.2992386031
Short name T445
Test name
Test status
Simulation time 108759833 ps
CPU time 1.16 seconds
Started Aug 25 03:37:27 AM UTC 24
Finished Aug 25 03:37:29 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992386031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2992386031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_noise_filter.957281033
Short name T305
Test name
Test status
Simulation time 67659950231 ps
CPU time 82.95 seconds
Started Aug 25 03:37:15 AM UTC 24
Finished Aug 25 03:38:40 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957281033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.957281033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_perf.203912860
Short name T491
Test name
Test status
Simulation time 4177957208 ps
CPU time 345.84 seconds
Started Aug 25 03:37:27 AM UTC 24
Finished Aug 25 03:43:18 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203912860 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.203912860
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_rx_oversample.3410092790
Short name T444
Test name
Test status
Simulation time 4663017347 ps
CPU time 12.73 seconds
Started Aug 25 03:37:12 AM UTC 24
Finished Aug 25 03:37:26 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410092790 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3410092790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.1619602013
Short name T295
Test name
Test status
Simulation time 3260541012 ps
CPU time 3.85 seconds
Started Aug 25 03:37:16 AM UTC 24
Finished Aug 25 03:37:21 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619602013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1619602013
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_smoke.3884502143
Short name T364
Test name
Test status
Simulation time 499653640 ps
CPU time 2.11 seconds
Started Aug 25 03:37:06 AM UTC 24
Finished Aug 25 03:37:09 AM UTC 24
Peak memory 207424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884502143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3884502143
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_stress_all.2029014267
Short name T829
Test name
Test status
Simulation time 74612696459 ps
CPU time 1182.65 seconds
Started Aug 25 03:37:32 AM UTC 24
Finished Aug 25 03:57:30 AM UTC 24
Peak memory 212360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029014267 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2029014267
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.3815669426
Short name T89
Test name
Test status
Simulation time 5516703573 ps
CPU time 87.41 seconds
Started Aug 25 03:37:32 AM UTC 24
Finished Aug 25 03:39:02 AM UTC 24
Peak memory 221964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3815669426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all
_with_rand_reset.3815669426
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.2021647031
Short name T360
Test name
Test status
Simulation time 535132169 ps
CPU time 3.4 seconds
Started Aug 25 03:37:22 AM UTC 24
Finished Aug 25 03:37:26 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021647031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2021647031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/11.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/111.uart_fifo_reset.1970474432
Short name T1002
Test name
Test status
Simulation time 18154119042 ps
CPU time 61.78 seconds
Started Aug 25 04:01:56 AM UTC 24
Finished Aug 25 04:03:00 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970474432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1970474432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/111.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/112.uart_fifo_reset.618587005
Short name T986
Test name
Test status
Simulation time 37580186916 ps
CPU time 36.65 seconds
Started Aug 25 04:01:56 AM UTC 24
Finished Aug 25 04:02:34 AM UTC 24
Peak memory 208940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618587005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.618587005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/112.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/113.uart_fifo_reset.2633644581
Short name T257
Test name
Test status
Simulation time 70118218118 ps
CPU time 59.27 seconds
Started Aug 25 04:01:58 AM UTC 24
Finished Aug 25 04:02:59 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633644581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2633644581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/113.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/114.uart_fifo_reset.962920064
Short name T1040
Test name
Test status
Simulation time 73906640374 ps
CPU time 118.08 seconds
Started Aug 25 04:02:00 AM UTC 24
Finished Aug 25 04:04:01 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962920064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.962920064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/114.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/115.uart_fifo_reset.1380605080
Short name T1035
Test name
Test status
Simulation time 36262948875 ps
CPU time 109.7 seconds
Started Aug 25 04:02:04 AM UTC 24
Finished Aug 25 04:03:56 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380605080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1380605080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/115.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/116.uart_fifo_reset.3880050141
Short name T1109
Test name
Test status
Simulation time 75607515570 ps
CPU time 273.33 seconds
Started Aug 25 04:02:06 AM UTC 24
Finished Aug 25 04:06:43 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880050141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3880050141
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/116.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/117.uart_fifo_reset.3297797096
Short name T1025
Test name
Test status
Simulation time 100696139386 ps
CPU time 85.33 seconds
Started Aug 25 04:02:11 AM UTC 24
Finished Aug 25 04:03:38 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297797096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3297797096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/117.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/118.uart_fifo_reset.3382749548
Short name T1096
Test name
Test status
Simulation time 73751946803 ps
CPU time 227.66 seconds
Started Aug 25 04:02:12 AM UTC 24
Finished Aug 25 04:06:03 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382749548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3382749548
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/118.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_alert_test.1547396043
Short name T449
Test name
Test status
Simulation time 11174383 ps
CPU time 0.81 seconds
Started Aug 25 03:38:18 AM UTC 24
Finished Aug 25 03:38:21 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547396043 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1547396043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_fifo_full.1047318884
Short name T130
Test name
Test status
Simulation time 29175792836 ps
CPU time 102.82 seconds
Started Aug 25 03:37:45 AM UTC 24
Finished Aug 25 03:39:29 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047318884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1047318884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.1897135168
Short name T285
Test name
Test status
Simulation time 94845483917 ps
CPU time 158.22 seconds
Started Aug 25 03:37:51 AM UTC 24
Finished Aug 25 03:40:32 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897135168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1897135168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_fifo_reset.3411303176
Short name T201
Test name
Test status
Simulation time 10513760560 ps
CPU time 30.8 seconds
Started Aug 25 03:37:53 AM UTC 24
Finished Aug 25 03:38:25 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411303176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3411303176
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_intr.397242652
Short name T332
Test name
Test status
Simulation time 164758310696 ps
CPU time 194.58 seconds
Started Aug 25 03:37:56 AM UTC 24
Finished Aug 25 03:41:14 AM UTC 24
Peak memory 208592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397242652 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.397242652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.1834513199
Short name T670
Test name
Test status
Simulation time 83000756435 ps
CPU time 747.55 seconds
Started Aug 25 03:38:15 AM UTC 24
Finished Aug 25 03:50:53 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834513199 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1834513199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_loopback.2252918916
Short name T448
Test name
Test status
Simulation time 3325493507 ps
CPU time 6.27 seconds
Started Aug 25 03:38:07 AM UTC 24
Finished Aug 25 03:38:14 AM UTC 24
Peak memory 208512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252918916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2252918916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_noise_filter.594314467
Short name T286
Test name
Test status
Simulation time 66485928563 ps
CPU time 197.39 seconds
Started Aug 25 03:37:59 AM UTC 24
Finished Aug 25 03:41:19 AM UTC 24
Peak memory 217424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594314467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.594314467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_perf.3812573579
Short name T673
Test name
Test status
Simulation time 8850670631 ps
CPU time 754.63 seconds
Started Aug 25 03:38:13 AM UTC 24
Finished Aug 25 03:50:57 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812573579 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3812573579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_rx_oversample.361498351
Short name T453
Test name
Test status
Simulation time 5754590754 ps
CPU time 62.32 seconds
Started Aug 25 03:37:55 AM UTC 24
Finished Aug 25 03:38:59 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361498351 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.361498351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.3114864203
Short name T371
Test name
Test status
Simulation time 3105656081 ps
CPU time 6.41 seconds
Started Aug 25 03:37:59 AM UTC 24
Finished Aug 25 03:38:06 AM UTC 24
Peak memory 205028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114864203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3114864203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_smoke.3727808933
Short name T370
Test name
Test status
Simulation time 649989064 ps
CPU time 3.64 seconds
Started Aug 25 03:37:35 AM UTC 24
Finished Aug 25 03:37:40 AM UTC 24
Peak memory 208104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727808933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3727808933
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_stress_all.753860271
Short name T176
Test name
Test status
Simulation time 90964794446 ps
CPU time 260.76 seconds
Started Aug 25 03:38:17 AM UTC 24
Finished Aug 25 03:42:42 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753860271 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.753860271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.688236928
Short name T311
Test name
Test status
Simulation time 6352719509 ps
CPU time 93.2 seconds
Started Aug 25 03:38:17 AM UTC 24
Finished Aug 25 03:39:53 AM UTC 24
Peak memory 217940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=688236928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all_
with_rand_reset.688236928
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.304591020
Short name T289
Test name
Test status
Simulation time 7301320523 ps
CPU time 21.5 seconds
Started Aug 25 03:38:05 AM UTC 24
Finished Aug 25 03:38:28 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304591020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.304591020
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/12.uart_tx_rx.164597517
Short name T306
Test name
Test status
Simulation time 202531314366 ps
CPU time 61.25 seconds
Started Aug 25 03:37:40 AM UTC 24
Finished Aug 25 03:38:43 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164597517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.164597517
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/12.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/120.uart_fifo_reset.444862403
Short name T995
Test name
Test status
Simulation time 43444259473 ps
CPU time 36.13 seconds
Started Aug 25 04:02:14 AM UTC 24
Finished Aug 25 04:02:52 AM UTC 24
Peak memory 208532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444862403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.444862403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/120.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/121.uart_fifo_reset.1224066776
Short name T1068
Test name
Test status
Simulation time 78702982590 ps
CPU time 168.83 seconds
Started Aug 25 04:02:14 AM UTC 24
Finished Aug 25 04:05:06 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224066776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1224066776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/121.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/122.uart_fifo_reset.170523557
Short name T1014
Test name
Test status
Simulation time 142153606151 ps
CPU time 63.34 seconds
Started Aug 25 04:02:14 AM UTC 24
Finished Aug 25 04:03:19 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170523557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.170523557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/122.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/123.uart_fifo_reset.831256725
Short name T987
Test name
Test status
Simulation time 53654592488 ps
CPU time 20.84 seconds
Started Aug 25 04:02:15 AM UTC 24
Finished Aug 25 04:02:37 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831256725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.831256725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/123.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/124.uart_fifo_reset.3119622446
Short name T1012
Test name
Test status
Simulation time 21141352203 ps
CPU time 58.97 seconds
Started Aug 25 04:02:16 AM UTC 24
Finished Aug 25 04:03:17 AM UTC 24
Peak memory 208864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119622446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3119622446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/124.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/126.uart_fifo_reset.720412664
Short name T998
Test name
Test status
Simulation time 16231417542 ps
CPU time 33.93 seconds
Started Aug 25 04:02:18 AM UTC 24
Finished Aug 25 04:02:54 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720412664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.720412664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/126.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/127.uart_fifo_reset.2469325669
Short name T1172
Test name
Test status
Simulation time 235636747121 ps
CPU time 485.43 seconds
Started Aug 25 04:02:18 AM UTC 24
Finished Aug 25 04:10:30 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469325669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2469325669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/127.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/129.uart_fifo_reset.2537767334
Short name T1112
Test name
Test status
Simulation time 86457033018 ps
CPU time 265.42 seconds
Started Aug 25 04:02:22 AM UTC 24
Finished Aug 25 04:06:51 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537767334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2537767334
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/129.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_alert_test.2307613892
Short name T452
Test name
Test status
Simulation time 13812834 ps
CPU time 0.79 seconds
Started Aug 25 03:38:53 AM UTC 24
Finished Aug 25 03:38:55 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307613892 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2307613892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_fifo_full.3997271654
Short name T313
Test name
Test status
Simulation time 17717926578 ps
CPU time 67.95 seconds
Started Aug 25 03:38:26 AM UTC 24
Finished Aug 25 03:39:36 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997271654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3997271654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.1375311737
Short name T701
Test name
Test status
Simulation time 218023634953 ps
CPU time 812.32 seconds
Started Aug 25 03:38:29 AM UTC 24
Finished Aug 25 03:52:12 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375311737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1375311737
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_intr.2699883965
Short name T113
Test name
Test status
Simulation time 31696662498 ps
CPU time 21.58 seconds
Started Aug 25 03:38:34 AM UTC 24
Finished Aug 25 03:38:57 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699883965 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2699883965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_loopback.1153643384
Short name T451
Test name
Test status
Simulation time 7421430676 ps
CPU time 6.91 seconds
Started Aug 25 03:38:42 AM UTC 24
Finished Aug 25 03:38:50 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153643384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1153643384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_noise_filter.3663998396
Short name T385
Test name
Test status
Simulation time 28924708882 ps
CPU time 97.53 seconds
Started Aug 25 03:38:36 AM UTC 24
Finished Aug 25 03:40:16 AM UTC 24
Peak memory 209016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663998396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3663998396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_perf.2280254681
Short name T628
Test name
Test status
Simulation time 6693247093 ps
CPU time 624.17 seconds
Started Aug 25 03:38:44 AM UTC 24
Finished Aug 25 03:49:17 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280254681 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2280254681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_rx_oversample.492287668
Short name T450
Test name
Test status
Simulation time 3573865937 ps
CPU time 8.53 seconds
Started Aug 25 03:38:32 AM UTC 24
Finished Aug 25 03:38:42 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492287668 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.492287668
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.1159739994
Short name T129
Test name
Test status
Simulation time 10754610313 ps
CPU time 41.3 seconds
Started Aug 25 03:38:40 AM UTC 24
Finished Aug 25 03:39:23 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159739994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1159739994
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.985125957
Short name T327
Test name
Test status
Simulation time 1622997368 ps
CPU time 6.32 seconds
Started Aug 25 03:38:37 AM UTC 24
Finished Aug 25 03:38:45 AM UTC 24
Peak memory 204960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985125957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.985125957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_smoke.339486909
Short name T342
Test name
Test status
Simulation time 6275090883 ps
CPU time 14.4 seconds
Started Aug 25 03:38:21 AM UTC 24
Finished Aug 25 03:38:36 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339486909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 13.uart_smoke.339486909
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_stress_all.3046812111
Short name T104
Test name
Test status
Simulation time 162732244967 ps
CPU time 238.39 seconds
Started Aug 25 03:38:52 AM UTC 24
Finished Aug 25 03:42:54 AM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046812111 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3046812111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.980161751
Short name T375
Test name
Test status
Simulation time 2369907747 ps
CPU time 22.64 seconds
Started Aug 25 03:38:52 AM UTC 24
Finished Aug 25 03:39:15 AM UTC 24
Peak memory 223936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=980161751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all_
with_rand_reset.980161751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.392505179
Short name T321
Test name
Test status
Simulation time 9603661317 ps
CPU time 7.82 seconds
Started Aug 25 03:38:42 AM UTC 24
Finished Aug 25 03:38:51 AM UTC 24
Peak memory 208288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392505179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.392505179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/13.uart_tx_rx.718217763
Short name T349
Test name
Test status
Simulation time 30778432990 ps
CPU time 95.91 seconds
Started Aug 25 03:38:22 AM UTC 24
Finished Aug 25 03:40:00 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718217763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.718217763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/13.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/130.uart_fifo_reset.1181133070
Short name T1015
Test name
Test status
Simulation time 101577259802 ps
CPU time 56.6 seconds
Started Aug 25 04:02:22 AM UTC 24
Finished Aug 25 04:03:20 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181133070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1181133070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/130.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/132.uart_fifo_reset.2575760728
Short name T1009
Test name
Test status
Simulation time 19107426150 ps
CPU time 46.35 seconds
Started Aug 25 04:02:25 AM UTC 24
Finished Aug 25 04:03:13 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575760728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2575760728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/132.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/135.uart_fifo_reset.673011234
Short name T1006
Test name
Test status
Simulation time 25796873751 ps
CPU time 38.22 seconds
Started Aug 25 04:02:30 AM UTC 24
Finished Aug 25 04:03:10 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673011234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.673011234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/135.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/136.uart_fifo_reset.1656518894
Short name T1010
Test name
Test status
Simulation time 92477180585 ps
CPU time 40.62 seconds
Started Aug 25 04:02:31 AM UTC 24
Finished Aug 25 04:03:13 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656518894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1656518894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/136.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/137.uart_fifo_reset.2416149899
Short name T999
Test name
Test status
Simulation time 35031408767 ps
CPU time 22.06 seconds
Started Aug 25 04:02:32 AM UTC 24
Finished Aug 25 04:02:55 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416149899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2416149899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/137.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/138.uart_fifo_reset.4187995974
Short name T206
Test name
Test status
Simulation time 128334425864 ps
CPU time 124.94 seconds
Started Aug 25 04:02:35 AM UTC 24
Finished Aug 25 04:04:42 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187995974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.4187995974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/138.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/139.uart_fifo_reset.1427890860
Short name T1081
Test name
Test status
Simulation time 135014339395 ps
CPU time 168.83 seconds
Started Aug 25 04:02:35 AM UTC 24
Finished Aug 25 04:05:27 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427890860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1427890860
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/139.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_alert_test.1632311526
Short name T454
Test name
Test status
Simulation time 192339042 ps
CPU time 0.79 seconds
Started Aug 25 03:39:24 AM UTC 24
Finished Aug 25 03:39:26 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632311526 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1632311526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_fifo_full.2223893849
Short name T147
Test name
Test status
Simulation time 100213513192 ps
CPU time 96.51 seconds
Started Aug 25 03:39:00 AM UTC 24
Finished Aug 25 03:40:39 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223893849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2223893849
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.3418511358
Short name T300
Test name
Test status
Simulation time 55558022916 ps
CPU time 45.67 seconds
Started Aug 25 03:39:00 AM UTC 24
Finished Aug 25 03:39:47 AM UTC 24
Peak memory 208408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418511358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3418511358
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_fifo_reset.2584442888
Short name T151
Test name
Test status
Simulation time 60288924344 ps
CPU time 180.5 seconds
Started Aug 25 03:39:03 AM UTC 24
Finished Aug 25 03:42:07 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584442888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2584442888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_intr.2959021855
Short name T115
Test name
Test status
Simulation time 281264260812 ps
CPU time 170.19 seconds
Started Aug 25 03:39:09 AM UTC 24
Finished Aug 25 03:42:03 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959021855 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2959021855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.2163835995
Short name T814
Test name
Test status
Simulation time 129439808659 ps
CPU time 1042.48 seconds
Started Aug 25 03:39:20 AM UTC 24
Finished Aug 25 03:56:56 AM UTC 24
Peak memory 212428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163835995 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2163835995
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_loopback.3190421479
Short name T456
Test name
Test status
Simulation time 6862061270 ps
CPU time 21.45 seconds
Started Aug 25 03:39:17 AM UTC 24
Finished Aug 25 03:39:39 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190421479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3190421479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_noise_filter.1791841229
Short name T324
Test name
Test status
Simulation time 35521711060 ps
CPU time 40.88 seconds
Started Aug 25 03:39:09 AM UTC 24
Finished Aug 25 03:39:52 AM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791841229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1791841229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_rx_oversample.978936912
Short name T455
Test name
Test status
Simulation time 5294043572 ps
CPU time 22.4 seconds
Started Aug 25 03:39:06 AM UTC 24
Finished Aug 25 03:39:30 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978936912 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.978936912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.2515509439
Short name T149
Test name
Test status
Simulation time 46069012067 ps
CPU time 160.03 seconds
Started Aug 25 03:39:10 AM UTC 24
Finished Aug 25 03:41:53 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515509439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2515509439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.3847150553
Short name T302
Test name
Test status
Simulation time 4602223411 ps
CPU time 8.46 seconds
Started Aug 25 03:39:09 AM UTC 24
Finished Aug 25 03:39:19 AM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847150553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3847150553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_smoke.3509569227
Short name T378
Test name
Test status
Simulation time 513054820 ps
CPU time 2.18 seconds
Started Aug 25 03:38:56 AM UTC 24
Finished Aug 25 03:38:59 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509569227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3509569227
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_stress_all.2982953875
Short name T667
Test name
Test status
Simulation time 345232344767 ps
CPU time 671.45 seconds
Started Aug 25 03:39:24 AM UTC 24
Finished Aug 25 03:50:45 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982953875 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2982953875
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.2762243732
Short name T330
Test name
Test status
Simulation time 3006907188 ps
CPU time 50.1 seconds
Started Aug 25 03:39:21 AM UTC 24
Finished Aug 25 03:40:13 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2762243732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all
_with_rand_reset.2762243732
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.4211727795
Short name T362
Test name
Test status
Simulation time 1402198277 ps
CPU time 3.07 seconds
Started Aug 25 03:39:16 AM UTC 24
Finished Aug 25 03:39:20 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211727795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4211727795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/14.uart_tx_rx.303623015
Short name T312
Test name
Test status
Simulation time 74996906855 ps
CPU time 243.87 seconds
Started Aug 25 03:38:58 AM UTC 24
Finished Aug 25 03:43:05 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303623015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.303623015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/14.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/141.uart_fifo_reset.1534496372
Short name T1101
Test name
Test status
Simulation time 132528003761 ps
CPU time 218.02 seconds
Started Aug 25 04:02:41 AM UTC 24
Finished Aug 25 04:06:22 AM UTC 24
Peak memory 208356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534496372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1534496372
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/141.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/142.uart_fifo_reset.533904366
Short name T1038
Test name
Test status
Simulation time 53060139278 ps
CPU time 78.25 seconds
Started Aug 25 04:02:41 AM UTC 24
Finished Aug 25 04:04:00 AM UTC 24
Peak memory 208396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533904366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.533904366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/142.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/144.uart_fifo_reset.1793518750
Short name T1007
Test name
Test status
Simulation time 16622784894 ps
CPU time 27.42 seconds
Started Aug 25 04:02:42 AM UTC 24
Finished Aug 25 04:03:10 AM UTC 24
Peak memory 208092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793518750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1793518750
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/144.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/145.uart_fifo_reset.234144216
Short name T1046
Test name
Test status
Simulation time 53055836529 ps
CPU time 89.5 seconds
Started Aug 25 04:02:43 AM UTC 24
Finished Aug 25 04:04:15 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234144216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.234144216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/145.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/146.uart_fifo_reset.1739252826
Short name T1075
Test name
Test status
Simulation time 122519051426 ps
CPU time 148.99 seconds
Started Aug 25 04:02:44 AM UTC 24
Finished Aug 25 04:05:15 AM UTC 24
Peak memory 208736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739252826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1739252826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/146.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/147.uart_fifo_reset.4125980751
Short name T1062
Test name
Test status
Simulation time 54480583871 ps
CPU time 127.1 seconds
Started Aug 25 04:02:44 AM UTC 24
Finished Aug 25 04:04:53 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125980751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.4125980751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/147.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/148.uart_fifo_reset.2467739374
Short name T1103
Test name
Test status
Simulation time 82673130058 ps
CPU time 215.51 seconds
Started Aug 25 04:02:46 AM UTC 24
Finished Aug 25 04:06:25 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467739374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2467739374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/148.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/149.uart_fifo_reset.2033492687
Short name T1021
Test name
Test status
Simulation time 30359091671 ps
CPU time 33.78 seconds
Started Aug 25 04:02:48 AM UTC 24
Finished Aug 25 04:03:24 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033492687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2033492687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/149.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_alert_test.4005046667
Short name T457
Test name
Test status
Simulation time 83860295 ps
CPU time 0.82 seconds
Started Aug 25 03:39:57 AM UTC 24
Finished Aug 25 03:39:59 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005046667 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4005046667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_fifo_full.3522907260
Short name T297
Test name
Test status
Simulation time 24357452541 ps
CPU time 70.68 seconds
Started Aug 25 03:39:30 AM UTC 24
Finished Aug 25 03:40:43 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522907260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3522907260
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.85886173
Short name T131
Test name
Test status
Simulation time 26742332310 ps
CPU time 33.81 seconds
Started Aug 25 03:39:30 AM UTC 24
Finished Aug 25 03:40:05 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85886173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.85886173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_fifo_reset.851828777
Short name T155
Test name
Test status
Simulation time 25634336812 ps
CPU time 78.84 seconds
Started Aug 25 03:39:33 AM UTC 24
Finished Aug 25 03:40:54 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851828777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.851828777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_intr.3971700301
Short name T566
Test name
Test status
Simulation time 132316911224 ps
CPU time 437.15 seconds
Started Aug 25 03:39:36 AM UTC 24
Finished Aug 25 03:47:00 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971700301 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3971700301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.1560459389
Short name T521
Test name
Test status
Simulation time 66927283245 ps
CPU time 336.77 seconds
Started Aug 25 03:39:53 AM UTC 24
Finished Aug 25 03:45:34 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560459389 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1560459389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_loopback.2654306726
Short name T458
Test name
Test status
Simulation time 9536545514 ps
CPU time 14.61 seconds
Started Aug 25 03:39:52 AM UTC 24
Finished Aug 25 03:40:08 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654306726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2654306726
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_noise_filter.2010508682
Short name T383
Test name
Test status
Simulation time 34695692181 ps
CPU time 37.37 seconds
Started Aug 25 03:39:41 AM UTC 24
Finished Aug 25 03:40:19 AM UTC 24
Peak memory 208844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010508682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2010508682
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_perf.2198593498
Short name T860
Test name
Test status
Simulation time 18675528420 ps
CPU time 1097.77 seconds
Started Aug 25 03:39:53 AM UTC 24
Finished Aug 25 03:58:25 AM UTC 24
Peak memory 212308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198593498 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2198593498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_rx_oversample.3962681997
Short name T459
Test name
Test status
Simulation time 6799367955 ps
CPU time 39.96 seconds
Started Aug 25 03:39:34 AM UTC 24
Finished Aug 25 03:40:16 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962681997 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3962681997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.2470403612
Short name T377
Test name
Test status
Simulation time 3974436329 ps
CPU time 14.48 seconds
Started Aug 25 03:39:44 AM UTC 24
Finished Aug 25 03:39:59 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470403612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2470403612
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_smoke.2216116145
Short name T384
Test name
Test status
Simulation time 649952332 ps
CPU time 6.26 seconds
Started Aug 25 03:39:25 AM UTC 24
Finished Aug 25 03:39:32 AM UTC 24
Peak memory 208568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216116145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2216116145
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.1456997053
Short name T374
Test name
Test status
Simulation time 579719252 ps
CPU time 3.05 seconds
Started Aug 25 03:39:52 AM UTC 24
Finished Aug 25 03:39:56 AM UTC 24
Peak memory 207012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456997053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1456997053
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/15.uart_tx_rx.781870455
Short name T418
Test name
Test status
Simulation time 29021865526 ps
CPU time 24.4 seconds
Started Aug 25 03:39:26 AM UTC 24
Finished Aug 25 03:39:52 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781870455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.781870455
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/15.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/150.uart_fifo_reset.1469178118
Short name T225
Test name
Test status
Simulation time 35982106290 ps
CPU time 31.43 seconds
Started Aug 25 04:02:51 AM UTC 24
Finished Aug 25 04:03:24 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469178118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1469178118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/150.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/151.uart_fifo_reset.2385713622
Short name T1043
Test name
Test status
Simulation time 21316112099 ps
CPU time 77.43 seconds
Started Aug 25 04:02:52 AM UTC 24
Finished Aug 25 04:04:11 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385713622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2385713622
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/151.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/153.uart_fifo_reset.1847931658
Short name T258
Test name
Test status
Simulation time 34295689545 ps
CPU time 126.23 seconds
Started Aug 25 04:02:54 AM UTC 24
Finished Aug 25 04:05:03 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847931658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1847931658
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/153.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/154.uart_fifo_reset.2449090886
Short name T1087
Test name
Test status
Simulation time 71098548108 ps
CPU time 168.1 seconds
Started Aug 25 04:02:54 AM UTC 24
Finished Aug 25 04:05:45 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449090886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2449090886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/154.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/155.uart_fifo_reset.782489227
Short name T1082
Test name
Test status
Simulation time 146785767768 ps
CPU time 150.97 seconds
Started Aug 25 04:02:54 AM UTC 24
Finished Aug 25 04:05:28 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782489227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.782489227
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/155.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/156.uart_fifo_reset.3718431450
Short name T1022
Test name
Test status
Simulation time 13401378701 ps
CPU time 26.81 seconds
Started Aug 25 04:02:56 AM UTC 24
Finished Aug 25 04:03:25 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718431450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3718431450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/156.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/157.uart_fifo_reset.3795076108
Short name T1059
Test name
Test status
Simulation time 17949682508 ps
CPU time 104.65 seconds
Started Aug 25 04:02:58 AM UTC 24
Finished Aug 25 04:04:45 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795076108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3795076108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/157.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/158.uart_fifo_reset.766159629
Short name T1032
Test name
Test status
Simulation time 18516352499 ps
CPU time 52.66 seconds
Started Aug 25 04:03:00 AM UTC 24
Finished Aug 25 04:03:54 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766159629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.766159629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/158.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/159.uart_fifo_reset.3296078430
Short name T1036
Test name
Test status
Simulation time 19876017309 ps
CPU time 57.09 seconds
Started Aug 25 04:03:00 AM UTC 24
Finished Aug 25 04:03:59 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296078430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3296078430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/159.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_alert_test.2940327798
Short name T462
Test name
Test status
Simulation time 32361199 ps
CPU time 0.81 seconds
Started Aug 25 03:40:32 AM UTC 24
Finished Aug 25 03:40:34 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940327798 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2940327798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_fifo_full.1227221824
Short name T666
Test name
Test status
Simulation time 202425141602 ps
CPU time 635 seconds
Started Aug 25 03:40:00 AM UTC 24
Finished Aug 25 03:50:44 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227221824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1227221824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.1274228349
Short name T133
Test name
Test status
Simulation time 49671469715 ps
CPU time 38.02 seconds
Started Aug 25 03:40:03 AM UTC 24
Finished Aug 25 03:40:43 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274228349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1274228349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_fifo_reset.201764141
Short name T187
Test name
Test status
Simulation time 37054180351 ps
CPU time 41.59 seconds
Started Aug 25 03:40:05 AM UTC 24
Finished Aug 25 03:40:49 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201764141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.201764141
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_intr.1447285915
Short name T382
Test name
Test status
Simulation time 101844338768 ps
CPU time 348.16 seconds
Started Aug 25 03:40:09 AM UTC 24
Finished Aug 25 03:46:02 AM UTC 24
Peak memory 208484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447285915 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1447285915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.262013490
Short name T554
Test name
Test status
Simulation time 118336437948 ps
CPU time 377.01 seconds
Started Aug 25 03:40:22 AM UTC 24
Finished Aug 25 03:46:44 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262013490 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.262013490
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_loopback.2059850491
Short name T461
Test name
Test status
Simulation time 6880590051 ps
CPU time 15.08 seconds
Started Aug 25 03:40:17 AM UTC 24
Finished Aug 25 03:40:33 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059850491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2059850491
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_noise_filter.3653480323
Short name T304
Test name
Test status
Simulation time 78275895273 ps
CPU time 72.03 seconds
Started Aug 25 03:40:09 AM UTC 24
Finished Aug 25 03:41:23 AM UTC 24
Peak memory 208972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653480323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3653480323
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_perf.69310560
Short name T626
Test name
Test status
Simulation time 28336887672 ps
CPU time 526.72 seconds
Started Aug 25 03:40:20 AM UTC 24
Finished Aug 25 03:49:14 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69310560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.69310560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_rx_oversample.541564506
Short name T460
Test name
Test status
Simulation time 4595376597 ps
CPU time 24.42 seconds
Started Aug 25 03:40:06 AM UTC 24
Finished Aug 25 03:40:32 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541564506 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.541564506
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.3349944672
Short name T380
Test name
Test status
Simulation time 45718534883 ps
CPU time 66.64 seconds
Started Aug 25 03:40:14 AM UTC 24
Finished Aug 25 03:41:22 AM UTC 24
Peak memory 205288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349944672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3349944672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_smoke.2309470460
Short name T359
Test name
Test status
Simulation time 273406276 ps
CPU time 2.18 seconds
Started Aug 25 03:40:00 AM UTC 24
Finished Aug 25 03:40:04 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309470460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2309470460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.617538898
Short name T276
Test name
Test status
Simulation time 6120816970 ps
CPU time 27 seconds
Started Aug 25 03:40:27 AM UTC 24
Finished Aug 25 03:40:55 AM UTC 24
Peak memory 217940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=617538898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all_
with_rand_reset.617538898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.3232475173
Short name T348
Test name
Test status
Simulation time 2925261514 ps
CPU time 2.95 seconds
Started Aug 25 03:40:17 AM UTC 24
Finished Aug 25 03:40:21 AM UTC 24
Peak memory 207668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232475173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3232475173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/16.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/160.uart_fifo_reset.2853294014
Short name T1039
Test name
Test status
Simulation time 66304939848 ps
CPU time 57.92 seconds
Started Aug 25 04:03:01 AM UTC 24
Finished Aug 25 04:04:01 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853294014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2853294014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/160.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/161.uart_fifo_reset.2587829223
Short name T205
Test name
Test status
Simulation time 25127841642 ps
CPU time 24.06 seconds
Started Aug 25 04:03:01 AM UTC 24
Finished Aug 25 04:03:26 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587829223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2587829223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/161.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/162.uart_fifo_reset.3653692612
Short name T1063
Test name
Test status
Simulation time 161086399834 ps
CPU time 111.62 seconds
Started Aug 25 04:03:01 AM UTC 24
Finished Aug 25 04:04:55 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653692612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3653692612
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/162.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/163.uart_fifo_reset.373706855
Short name T1047
Test name
Test status
Simulation time 184325479625 ps
CPU time 71.75 seconds
Started Aug 25 04:03:02 AM UTC 24
Finished Aug 25 04:04:16 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373706855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.373706855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/163.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/164.uart_fifo_reset.1839599863
Short name T237
Test name
Test status
Simulation time 95195990904 ps
CPU time 45.14 seconds
Started Aug 25 04:03:04 AM UTC 24
Finished Aug 25 04:03:51 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839599863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1839599863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/164.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/165.uart_fifo_reset.1500235296
Short name T1034
Test name
Test status
Simulation time 70572447184 ps
CPU time 42.79 seconds
Started Aug 25 04:03:10 AM UTC 24
Finished Aug 25 04:03:54 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500235296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1500235296
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/165.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/166.uart_fifo_reset.819979149
Short name T1138
Test name
Test status
Simulation time 110982249875 ps
CPU time 275.7 seconds
Started Aug 25 04:03:11 AM UTC 24
Finished Aug 25 04:07:51 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819979149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.819979149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/166.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/167.uart_fifo_reset.238100371
Short name T1044
Test name
Test status
Simulation time 106485221878 ps
CPU time 59.34 seconds
Started Aug 25 04:03:12 AM UTC 24
Finished Aug 25 04:04:13 AM UTC 24
Peak memory 208424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238100371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.238100371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/167.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/168.uart_fifo_reset.1345671968
Short name T1146
Test name
Test status
Simulation time 117359637970 ps
CPU time 307.94 seconds
Started Aug 25 04:03:13 AM UTC 24
Finished Aug 25 04:08:26 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345671968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1345671968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/168.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/169.uart_fifo_reset.1972399618
Short name T1052
Test name
Test status
Simulation time 44783951935 ps
CPU time 71.7 seconds
Started Aug 25 04:03:14 AM UTC 24
Finished Aug 25 04:04:28 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972399618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1972399618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/169.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_alert_test.2112571644
Short name T466
Test name
Test status
Simulation time 14375760 ps
CPU time 0.8 seconds
Started Aug 25 03:40:58 AM UTC 24
Finished Aug 25 03:41:00 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112571644 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2112571644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_fifo_full.1831421670
Short name T139
Test name
Test status
Simulation time 102247077978 ps
CPU time 25.08 seconds
Started Aug 25 03:40:35 AM UTC 24
Finished Aug 25 03:41:02 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831421670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1831421670
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.3687499097
Short name T154
Test name
Test status
Simulation time 52339762632 ps
CPU time 82.59 seconds
Started Aug 25 03:40:37 AM UTC 24
Finished Aug 25 03:42:01 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687499097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3687499097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_intr.3169534799
Short name T397
Test name
Test status
Simulation time 9248487020 ps
CPU time 33.39 seconds
Started Aug 25 03:40:40 AM UTC 24
Finished Aug 25 03:41:15 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169534799 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3169534799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.371974336
Short name T831
Test name
Test status
Simulation time 116722468691 ps
CPU time 983.98 seconds
Started Aug 25 03:40:55 AM UTC 24
Finished Aug 25 03:57:32 AM UTC 24
Peak memory 212224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371974336 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.371974336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_loopback.3655758446
Short name T464
Test name
Test status
Simulation time 6762792453 ps
CPU time 7.18 seconds
Started Aug 25 03:40:49 AM UTC 24
Finished Aug 25 03:40:57 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655758446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3655758446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_noise_filter.257033522
Short name T526
Test name
Test status
Simulation time 87964239141 ps
CPU time 299.17 seconds
Started Aug 25 03:40:42 AM UTC 24
Finished Aug 25 03:45:45 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257033522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.257033522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_perf.3412591743
Short name T497
Test name
Test status
Simulation time 8069160599 ps
CPU time 182.1 seconds
Started Aug 25 03:40:49 AM UTC 24
Finished Aug 25 03:43:55 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412591743 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3412591743
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_rx_oversample.806351703
Short name T465
Test name
Test status
Simulation time 6681019248 ps
CPU time 17.87 seconds
Started Aug 25 03:40:40 AM UTC 24
Finished Aug 25 03:40:59 AM UTC 24
Peak memory 207348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806351703 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.806351703
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.47187120
Short name T153
Test name
Test status
Simulation time 15277004657 ps
CPU time 57.58 seconds
Started Aug 25 03:40:44 AM UTC 24
Finished Aug 25 03:41:43 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47187120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.47187120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.2570299889
Short name T463
Test name
Test status
Simulation time 1497601189 ps
CPU time 4.77 seconds
Started Aug 25 03:40:43 AM UTC 24
Finished Aug 25 03:40:49 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570299889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2570299889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_smoke.3130683217
Short name T387
Test name
Test status
Simulation time 487740956 ps
CPU time 1.56 seconds
Started Aug 25 03:40:33 AM UTC 24
Finished Aug 25 03:40:36 AM UTC 24
Peak memory 207996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130683217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3130683217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_stress_all.3287901233
Short name T105
Test name
Test status
Simulation time 66866059976 ps
CPU time 203.42 seconds
Started Aug 25 03:40:58 AM UTC 24
Finished Aug 25 03:44:25 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287901233 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3287901233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.3789834181
Short name T90
Test name
Test status
Simulation time 2616138587 ps
CPU time 37.02 seconds
Started Aug 25 03:40:56 AM UTC 24
Finished Aug 25 03:41:35 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3789834181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all
_with_rand_reset.3789834181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.1489218779
Short name T388
Test name
Test status
Simulation time 8527235532 ps
CPU time 15.32 seconds
Started Aug 25 03:40:44 AM UTC 24
Finished Aug 25 03:41:01 AM UTC 24
Peak memory 208336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489218779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1489218779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/17.uart_tx_rx.489468036
Short name T309
Test name
Test status
Simulation time 128199775823 ps
CPU time 92.02 seconds
Started Aug 25 03:40:34 AM UTC 24
Finished Aug 25 03:42:08 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489468036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.489468036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/17.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/170.uart_fifo_reset.1850605727
Short name T1031
Test name
Test status
Simulation time 13242947691 ps
CPU time 35.91 seconds
Started Aug 25 04:03:16 AM UTC 24
Finished Aug 25 04:03:53 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850605727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1850605727
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/170.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/171.uart_fifo_reset.2796957185
Short name T1054
Test name
Test status
Simulation time 72595419621 ps
CPU time 74.92 seconds
Started Aug 25 04:03:18 AM UTC 24
Finished Aug 25 04:04:34 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796957185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2796957185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/171.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/172.uart_fifo_reset.2729934209
Short name T1053
Test name
Test status
Simulation time 27982459044 ps
CPU time 70.67 seconds
Started Aug 25 04:03:19 AM UTC 24
Finished Aug 25 04:04:31 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729934209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2729934209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/172.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/173.uart_fifo_reset.412057743
Short name T1030
Test name
Test status
Simulation time 42149841022 ps
CPU time 29.48 seconds
Started Aug 25 04:03:20 AM UTC 24
Finished Aug 25 04:03:51 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412057743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.412057743
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/173.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/175.uart_fifo_reset.3309110287
Short name T1028
Test name
Test status
Simulation time 12129905731 ps
CPU time 26.15 seconds
Started Aug 25 04:03:21 AM UTC 24
Finished Aug 25 04:03:48 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309110287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3309110287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/175.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/178.uart_fifo_reset.4190595449
Short name T1162
Test name
Test status
Simulation time 154272907624 ps
CPU time 353.06 seconds
Started Aug 25 04:03:23 AM UTC 24
Finished Aug 25 04:09:21 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190595449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4190595449
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/178.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/179.uart_fifo_reset.2773298976
Short name T1016
Test name
Test status
Simulation time 54975755289 ps
CPU time 155.06 seconds
Started Aug 25 04:03:24 AM UTC 24
Finished Aug 25 04:06:02 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773298976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2773298976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/179.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_alert_test.2908618856
Short name T468
Test name
Test status
Simulation time 40457114 ps
CPU time 0.78 seconds
Started Aug 25 03:41:36 AM UTC 24
Finished Aug 25 03:41:38 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908618856 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2908618856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_fifo_full.1779908755
Short name T169
Test name
Test status
Simulation time 55162390134 ps
CPU time 41.01 seconds
Started Aug 25 03:41:02 AM UTC 24
Finished Aug 25 03:41:44 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779908755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1779908755
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.505836757
Short name T156
Test name
Test status
Simulation time 134853836303 ps
CPU time 143.33 seconds
Started Aug 25 03:41:03 AM UTC 24
Finished Aug 25 03:43:29 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505836757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.505836757
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_intr.2542803597
Short name T393
Test name
Test status
Simulation time 223614129319 ps
CPU time 166.23 seconds
Started Aug 25 03:41:15 AM UTC 24
Finished Aug 25 03:44:04 AM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542803597 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2542803597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.4124558000
Short name T1156
Test name
Test status
Simulation time 120697855315 ps
CPU time 1635.96 seconds
Started Aug 25 03:41:27 AM UTC 24
Finished Aug 25 04:09:04 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124558000 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4124558000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_loopback.334610915
Short name T469
Test name
Test status
Simulation time 8961932281 ps
CPU time 16.87 seconds
Started Aug 25 03:41:23 AM UTC 24
Finished Aug 25 03:41:41 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334610915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.uart_loopback.334610915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_noise_filter.2530347247
Short name T319
Test name
Test status
Simulation time 182980105132 ps
CPU time 150.63 seconds
Started Aug 25 03:41:15 AM UTC 24
Finished Aug 25 03:43:48 AM UTC 24
Peak memory 217560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530347247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2530347247
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_perf.1325558784
Short name T940
Test name
Test status
Simulation time 14938954058 ps
CPU time 1176.79 seconds
Started Aug 25 03:41:25 AM UTC 24
Finished Aug 25 04:01:17 AM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325558784 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1325558784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1260658436
Short name T480
Test name
Test status
Simulation time 8019456855 ps
CPU time 96.9 seconds
Started Aug 25 03:41:15 AM UTC 24
Finished Aug 25 03:42:54 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260658436 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1260658436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.3193487806
Short name T490
Test name
Test status
Simulation time 38048890145 ps
CPU time 114.02 seconds
Started Aug 25 03:41:21 AM UTC 24
Finished Aug 25 03:43:17 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193487806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3193487806
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.2554760632
Short name T335
Test name
Test status
Simulation time 3451373130 ps
CPU time 3.91 seconds
Started Aug 25 03:41:20 AM UTC 24
Finished Aug 25 03:41:25 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554760632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2554760632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_smoke.11997329
Short name T381
Test name
Test status
Simulation time 6051329228 ps
CPU time 29.94 seconds
Started Aug 25 03:40:59 AM UTC 24
Finished Aug 25 03:41:31 AM UTC 24
Peak memory 208392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11997329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_smoke.11997329
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_stress_all.2166058397
Short name T344
Test name
Test status
Simulation time 205265091521 ps
CPU time 137.8 seconds
Started Aug 25 03:41:32 AM UTC 24
Finished Aug 25 03:43:52 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166058397 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2166058397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.3161751904
Short name T485
Test name
Test status
Simulation time 2410016065 ps
CPU time 91.19 seconds
Started Aug 25 03:41:28 AM UTC 24
Finished Aug 25 03:43:02 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3161751904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all
_with_rand_reset.3161751904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.667455337
Short name T467
Test name
Test status
Simulation time 1314111707 ps
CPU time 2.48 seconds
Started Aug 25 03:41:23 AM UTC 24
Finished Aug 25 03:41:27 AM UTC 24
Peak memory 207180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667455337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.667455337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/18.uart_tx_rx.3641877127
Short name T345
Test name
Test status
Simulation time 71584178660 ps
CPU time 89.08 seconds
Started Aug 25 03:41:01 AM UTC 24
Finished Aug 25 03:42:32 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641877127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3641877127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/18.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/180.uart_fifo_reset.3160522468
Short name T1029
Test name
Test status
Simulation time 97629613278 ps
CPU time 23.83 seconds
Started Aug 25 04:03:25 AM UTC 24
Finished Aug 25 04:03:50 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160522468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3160522468
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/180.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/181.uart_fifo_reset.512471857
Short name T424
Test name
Test status
Simulation time 11096992504 ps
CPU time 18.42 seconds
Started Aug 25 04:03:25 AM UTC 24
Finished Aug 25 04:03:45 AM UTC 24
Peak memory 208496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512471857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.512471857
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/181.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/182.uart_fifo_reset.270242407
Short name T1037
Test name
Test status
Simulation time 38505874639 ps
CPU time 31.93 seconds
Started Aug 25 04:03:26 AM UTC 24
Finished Aug 25 04:04:00 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270242407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.270242407
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/182.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/183.uart_fifo_reset.2882590239
Short name T1072
Test name
Test status
Simulation time 127728158650 ps
CPU time 102.38 seconds
Started Aug 25 04:03:27 AM UTC 24
Finished Aug 25 04:05:12 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882590239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2882590239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/183.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/186.uart_fifo_reset.1747267700
Short name T1056
Test name
Test status
Simulation time 24520686480 ps
CPU time 57.64 seconds
Started Aug 25 04:03:39 AM UTC 24
Finished Aug 25 04:04:38 AM UTC 24
Peak memory 208504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747267700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1747267700
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/186.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/187.uart_fifo_reset.608943647
Short name T1050
Test name
Test status
Simulation time 13064151569 ps
CPU time 47.17 seconds
Started Aug 25 04:03:39 AM UTC 24
Finished Aug 25 04:04:27 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608943647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.608943647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/187.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/188.uart_fifo_reset.21501426
Short name T1078
Test name
Test status
Simulation time 133462230402 ps
CPU time 94.98 seconds
Started Aug 25 04:03:43 AM UTC 24
Finished Aug 25 04:05:20 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21501426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.21501426
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/188.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/189.uart_fifo_reset.1503862855
Short name T1074
Test name
Test status
Simulation time 65134097189 ps
CPU time 86.71 seconds
Started Aug 25 04:03:46 AM UTC 24
Finished Aug 25 04:05:14 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503862855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1503862855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/189.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_alert_test.3433616051
Short name T473
Test name
Test status
Simulation time 16388108 ps
CPU time 0.84 seconds
Started Aug 25 03:42:11 AM UTC 24
Finished Aug 25 03:42:13 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433616051 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3433616051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_fifo_full.1319291425
Short name T531
Test name
Test status
Simulation time 87808582413 ps
CPU time 250.71 seconds
Started Aug 25 03:41:40 AM UTC 24
Finished Aug 25 03:45:55 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319291425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1319291425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.3352898555
Short name T520
Test name
Test status
Simulation time 127801407483 ps
CPU time 226.07 seconds
Started Aug 25 03:41:42 AM UTC 24
Finished Aug 25 03:45:32 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352898555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3352898555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_fifo_reset.197093098
Short name T427
Test name
Test status
Simulation time 43540993072 ps
CPU time 36.71 seconds
Started Aug 25 03:41:44 AM UTC 24
Finished Aug 25 03:42:22 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197093098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.197093098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_intr.825722621
Short name T400
Test name
Test status
Simulation time 41163309078 ps
CPU time 74.56 seconds
Started Aug 25 03:41:50 AM UTC 24
Finished Aug 25 03:43:07 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825722621 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.825722621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.3657492907
Short name T647
Test name
Test status
Simulation time 73492677058 ps
CPU time 465.69 seconds
Started Aug 25 03:42:09 AM UTC 24
Finished Aug 25 03:50:01 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657492907 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3657492907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_loopback.2749023115
Short name T477
Test name
Test status
Simulation time 10424753594 ps
CPU time 33.21 seconds
Started Aug 25 03:42:05 AM UTC 24
Finished Aug 25 03:42:39 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749023115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2749023115
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_noise_filter.411710790
Short name T425
Test name
Test status
Simulation time 57386710488 ps
CPU time 202.43 seconds
Started Aug 25 03:41:54 AM UTC 24
Finished Aug 25 03:45:20 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411710790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.411710790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_perf.3149263131
Short name T417
Test name
Test status
Simulation time 14056767249 ps
CPU time 252.03 seconds
Started Aug 25 03:42:08 AM UTC 24
Finished Aug 25 03:46:24 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149263131 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3149263131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_rx_oversample.1218854837
Short name T478
Test name
Test status
Simulation time 5164405017 ps
CPU time 55.89 seconds
Started Aug 25 03:41:45 AM UTC 24
Finished Aug 25 03:42:43 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218854837 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1218854837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.2445806172
Short name T482
Test name
Test status
Simulation time 66152749451 ps
CPU time 50.24 seconds
Started Aug 25 03:42:03 AM UTC 24
Finished Aug 25 03:42:55 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445806172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2445806172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.3280273067
Short name T470
Test name
Test status
Simulation time 533273841 ps
CPU time 1.3 seconds
Started Aug 25 03:42:01 AM UTC 24
Finished Aug 25 03:42:04 AM UTC 24
Peak memory 204432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280273067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3280273067
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_smoke.3927278066
Short name T352
Test name
Test status
Simulation time 285386741 ps
CPU time 2.36 seconds
Started Aug 25 03:41:36 AM UTC 24
Finished Aug 25 03:41:40 AM UTC 24
Peak memory 207424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927278066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3927278066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_stress_all.589445812
Short name T279
Test name
Test status
Simulation time 446172708384 ps
CPU time 119 seconds
Started Aug 25 03:42:10 AM UTC 24
Finished Aug 25 03:44:12 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589445812 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.589445812
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.370463614
Short name T91
Test name
Test status
Simulation time 4065825124 ps
CPU time 16.82 seconds
Started Aug 25 03:42:09 AM UTC 24
Finished Aug 25 03:42:27 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=370463614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all_
with_rand_reset.370463614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.3684178576
Short name T471
Test name
Test status
Simulation time 2288432025 ps
CPU time 2.64 seconds
Started Aug 25 03:42:05 AM UTC 24
Finished Aug 25 03:42:08 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684178576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3684178576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/19.uart_tx_rx.383767490
Short name T472
Test name
Test status
Simulation time 8586309230 ps
CPU time 28.6 seconds
Started Aug 25 03:41:39 AM UTC 24
Finished Aug 25 03:42:09 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383767490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.383767490
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/19.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/190.uart_fifo_reset.128188118
Short name T1084
Test name
Test status
Simulation time 31716745095 ps
CPU time 111.99 seconds
Started Aug 25 04:03:48 AM UTC 24
Finished Aug 25 04:05:42 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128188118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.128188118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/190.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/191.uart_fifo_reset.4137711678
Short name T1123
Test name
Test status
Simulation time 180180328281 ps
CPU time 199.23 seconds
Started Aug 25 04:03:49 AM UTC 24
Finished Aug 25 04:07:12 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137711678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4137711678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/191.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/192.uart_fifo_reset.406821512
Short name T1168
Test name
Test status
Simulation time 126532589921 ps
CPU time 358.48 seconds
Started Aug 25 04:03:51 AM UTC 24
Finished Aug 25 04:09:55 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406821512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.406821512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/192.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3876541611
Short name T241
Test name
Test status
Simulation time 12090788985 ps
CPU time 38.65 seconds
Started Aug 25 04:03:51 AM UTC 24
Finished Aug 25 04:04:31 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876541611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3876541611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/193.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/194.uart_fifo_reset.333031040
Short name T1067
Test name
Test status
Simulation time 98618447490 ps
CPU time 69.33 seconds
Started Aug 25 04:03:52 AM UTC 24
Finished Aug 25 04:05:03 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333031040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.333031040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/194.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/195.uart_fifo_reset.3156352717
Short name T1055
Test name
Test status
Simulation time 56700930352 ps
CPU time 39.91 seconds
Started Aug 25 04:03:53 AM UTC 24
Finished Aug 25 04:04:34 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156352717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3156352717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/195.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/196.uart_fifo_reset.1863851266
Short name T1045
Test name
Test status
Simulation time 44081530514 ps
CPU time 18.79 seconds
Started Aug 25 04:03:54 AM UTC 24
Finished Aug 25 04:04:14 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863851266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1863851266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/196.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/197.uart_fifo_reset.4190855782
Short name T223
Test name
Test status
Simulation time 249308198462 ps
CPU time 52.79 seconds
Started Aug 25 04:03:55 AM UTC 24
Finished Aug 25 04:04:50 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190855782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.4190855782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/197.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/198.uart_fifo_reset.2070433971
Short name T1113
Test name
Test status
Simulation time 72737509922 ps
CPU time 173.85 seconds
Started Aug 25 04:03:55 AM UTC 24
Finished Aug 25 04:06:52 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070433971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2070433971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/198.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/199.uart_fifo_reset.633624364
Short name T1076
Test name
Test status
Simulation time 49535408588 ps
CPU time 77.63 seconds
Started Aug 25 04:03:57 AM UTC 24
Finished Aug 25 04:05:16 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633624364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.633624364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/199.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_alert_test.1332190095
Short name T34
Test name
Test status
Simulation time 20827813 ps
CPU time 0.8 seconds
Started Aug 25 03:34:07 AM UTC 24
Finished Aug 25 03:34:09 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332190095 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1332190095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_fifo_full.815524471
Short name T283
Test name
Test status
Simulation time 16406262185 ps
CPU time 30.34 seconds
Started Aug 25 03:33:49 AM UTC 24
Finished Aug 25 03:34:21 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815524471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.815524471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.1996309861
Short name T13
Test name
Test status
Simulation time 9730040005 ps
CPU time 16.51 seconds
Started Aug 25 03:33:50 AM UTC 24
Finished Aug 25 03:34:08 AM UTC 24
Peak memory 207960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996309861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1996309861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_intr.1836764987
Short name T386
Test name
Test status
Simulation time 232818348558 ps
CPU time 619.57 seconds
Started Aug 25 03:33:52 AM UTC 24
Finished Aug 25 03:44:19 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836764987 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1836764987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.506738437
Short name T373
Test name
Test status
Simulation time 75805286509 ps
CPU time 547.75 seconds
Started Aug 25 03:34:03 AM UTC 24
Finished Aug 25 03:43:18 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506738437 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.506738437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_loopback.2270152913
Short name T27
Test name
Test status
Simulation time 2510124849 ps
CPU time 2.43 seconds
Started Aug 25 03:34:02 AM UTC 24
Finished Aug 25 03:34:05 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270152913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2270152913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_perf.2504555821
Short name T292
Test name
Test status
Simulation time 12772892786 ps
CPU time 390.44 seconds
Started Aug 25 03:34:03 AM UTC 24
Finished Aug 25 03:40:39 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504555821 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2504555821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_rx_oversample.2248895156
Short name T41
Test name
Test status
Simulation time 5015158605 ps
CPU time 55.6 seconds
Started Aug 25 03:33:51 AM UTC 24
Finished Aug 25 03:34:49 AM UTC 24
Peak memory 207484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248895156 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2248895156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.2830287634
Short name T275
Test name
Test status
Simulation time 44053683894 ps
CPU time 35.39 seconds
Started Aug 25 03:34:00 AM UTC 24
Finished Aug 25 03:34:37 AM UTC 24
Peak memory 205104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830287634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2830287634
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_sec_cm.1397390537
Short name T32
Test name
Test status
Simulation time 130438203 ps
CPU time 1.27 seconds
Started Aug 25 03:34:06 AM UTC 24
Finished Aug 25 03:34:09 AM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397390537 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1397390537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_smoke.734110810
Short name T49
Test name
Test status
Simulation time 89981844 ps
CPU time 1.09 seconds
Started Aug 25 03:33:49 AM UTC 24
Finished Aug 25 03:33:52 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734110810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.uart_smoke.734110810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_stress_all.2609665537
Short name T583
Test name
Test status
Simulation time 148952268909 ps
CPU time 801.66 seconds
Started Aug 25 03:34:06 AM UTC 24
Finished Aug 25 03:47:38 AM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609665537 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2609665537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.3467416297
Short name T24
Test name
Test status
Simulation time 1976691389 ps
CPU time 3.3 seconds
Started Aug 25 03:34:02 AM UTC 24
Finished Aug 25 03:34:06 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467416297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3467416297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/2.uart_tx_rx.3621348706
Short name T50
Test name
Test status
Simulation time 25108926354 ps
CPU time 16.72 seconds
Started Aug 25 03:33:49 AM UTC 24
Finished Aug 25 03:34:08 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621348706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3621348706
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/2.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_alert_test.3001467230
Short name T483
Test name
Test status
Simulation time 12356281 ps
CPU time 0.83 seconds
Started Aug 25 03:42:55 AM UTC 24
Finished Aug 25 03:42:56 AM UTC 24
Peak memory 204284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001467230 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3001467230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_fifo_full.3224901958
Short name T152
Test name
Test status
Simulation time 52904466236 ps
CPU time 41.5 seconds
Started Aug 25 03:42:18 AM UTC 24
Finished Aug 25 03:43:01 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224901958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3224901958
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.285170692
Short name T369
Test name
Test status
Simulation time 65570486482 ps
CPU time 106.98 seconds
Started Aug 25 03:42:19 AM UTC 24
Finished Aug 25 03:44:09 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285170692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.285170692
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_fifo_reset.3936675703
Short name T355
Test name
Test status
Simulation time 153736532167 ps
CPU time 76.34 seconds
Started Aug 25 03:42:21 AM UTC 24
Finished Aug 25 03:43:40 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936675703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3936675703
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.170656440
Short name T658
Test name
Test status
Simulation time 53966848332 ps
CPU time 460.82 seconds
Started Aug 25 03:42:45 AM UTC 24
Finished Aug 25 03:50:33 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170656440 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.170656440
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_loopback.1898063537
Short name T486
Test name
Test status
Simulation time 5496723273 ps
CPU time 22.04 seconds
Started Aug 25 03:42:43 AM UTC 24
Finished Aug 25 03:43:06 AM UTC 24
Peak memory 208436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898063537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1898063537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_noise_filter.2220428471
Short name T555
Test name
Test status
Simulation time 75149713610 ps
CPU time 249.75 seconds
Started Aug 25 03:42:33 AM UTC 24
Finished Aug 25 03:46:46 AM UTC 24
Peak memory 217588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220428471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2220428471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_perf.3528480237
Short name T991
Test name
Test status
Simulation time 13326901707 ps
CPU time 1182.86 seconds
Started Aug 25 03:42:44 AM UTC 24
Finished Aug 25 04:02:43 AM UTC 24
Peak memory 212204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528480237 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3528480237
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_rx_oversample.2365629042
Short name T476
Test name
Test status
Simulation time 2313133178 ps
CPU time 10.2 seconds
Started Aug 25 03:42:23 AM UTC 24
Finished Aug 25 03:42:34 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365629042 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2365629042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.1947872824
Short name T481
Test name
Test status
Simulation time 12114978274 ps
CPU time 14.19 seconds
Started Aug 25 03:42:39 AM UTC 24
Finished Aug 25 03:42:54 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947872824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1947872824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.2586337897
Short name T479
Test name
Test status
Simulation time 2951636306 ps
CPU time 10.78 seconds
Started Aug 25 03:42:35 AM UTC 24
Finished Aug 25 03:42:47 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586337897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2586337897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_smoke.2590980674
Short name T475
Test name
Test status
Simulation time 544481757 ps
CPU time 2.89 seconds
Started Aug 25 03:42:14 AM UTC 24
Finished Aug 25 03:42:18 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590980674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2590980674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_stress_all.1952821781
Short name T691
Test name
Test status
Simulation time 382052696200 ps
CPU time 533.02 seconds
Started Aug 25 03:42:47 AM UTC 24
Finished Aug 25 03:51:48 AM UTC 24
Peak memory 217640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952821781 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1952821781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.2005389994
Short name T92
Test name
Test status
Simulation time 5669929399 ps
CPU time 40.09 seconds
Started Aug 25 03:42:45 AM UTC 24
Finished Aug 25 03:43:27 AM UTC 24
Peak memory 223912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2005389994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all
_with_rand_reset.2005389994
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.3669944428
Short name T363
Test name
Test status
Simulation time 7138973892 ps
CPU time 38.28 seconds
Started Aug 25 03:42:40 AM UTC 24
Finished Aug 25 03:43:20 AM UTC 24
Peak memory 208552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669944428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3669944428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/200.uart_fifo_reset.1141062449
Short name T1083
Test name
Test status
Simulation time 28158669462 ps
CPU time 92.55 seconds
Started Aug 25 04:04:00 AM UTC 24
Finished Aug 25 04:05:34 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141062449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1141062449
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/200.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/201.uart_fifo_reset.3452670878
Short name T1042
Test name
Test status
Simulation time 17644122214 ps
CPU time 10.51 seconds
Started Aug 25 04:04:00 AM UTC 24
Finished Aug 25 04:04:11 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452670878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3452670878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/201.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/202.uart_fifo_reset.302816551
Short name T1092
Test name
Test status
Simulation time 180952171626 ps
CPU time 113.66 seconds
Started Aug 25 04:04:01 AM UTC 24
Finished Aug 25 04:05:57 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302816551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.302816551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/202.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2501831372
Short name T221
Test name
Test status
Simulation time 19634037344 ps
CPU time 75.66 seconds
Started Aug 25 04:04:02 AM UTC 24
Finished Aug 25 04:05:19 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501831372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2501831372
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/203.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/204.uart_fifo_reset.856793317
Short name T1051
Test name
Test status
Simulation time 16789162113 ps
CPU time 24.73 seconds
Started Aug 25 04:04:02 AM UTC 24
Finished Aug 25 04:04:28 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856793317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.856793317
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/204.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/205.uart_fifo_reset.3763473517
Short name T1065
Test name
Test status
Simulation time 92989829294 ps
CPU time 56.84 seconds
Started Aug 25 04:04:02 AM UTC 24
Finished Aug 25 04:05:00 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763473517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3763473517
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/205.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/206.uart_fifo_reset.1272295159
Short name T1058
Test name
Test status
Simulation time 23314818193 ps
CPU time 37.19 seconds
Started Aug 25 04:04:03 AM UTC 24
Finished Aug 25 04:04:42 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272295159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1272295159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/206.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/207.uart_fifo_reset.1050560766
Short name T1145
Test name
Test status
Simulation time 193574932475 ps
CPU time 249.52 seconds
Started Aug 25 04:04:12 AM UTC 24
Finished Aug 25 04:08:25 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050560766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1050560766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/207.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/208.uart_fifo_reset.1366070167
Short name T1071
Test name
Test status
Simulation time 27374418008 ps
CPU time 56.44 seconds
Started Aug 25 04:04:12 AM UTC 24
Finished Aug 25 04:05:11 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366070167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1366070167
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/208.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/209.uart_fifo_reset.1158000723
Short name T1090
Test name
Test status
Simulation time 51788057175 ps
CPU time 98.75 seconds
Started Aug 25 04:04:14 AM UTC 24
Finished Aug 25 04:05:55 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158000723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1158000723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/209.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_alert_test.1800036831
Short name T493
Test name
Test status
Simulation time 17662381 ps
CPU time 0.8 seconds
Started Aug 25 03:43:19 AM UTC 24
Finished Aug 25 03:43:21 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800036831 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1800036831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_fifo_full.2813389171
Short name T690
Test name
Test status
Simulation time 117499619999 ps
CPU time 523.36 seconds
Started Aug 25 03:42:56 AM UTC 24
Finished Aug 25 03:51:46 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813389171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2813389171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.3168042065
Short name T421
Test name
Test status
Simulation time 25068431087 ps
CPU time 23.81 seconds
Started Aug 25 03:42:57 AM UTC 24
Finished Aug 25 03:43:22 AM UTC 24
Peak memory 208428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168042065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3168042065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_fifo_reset.4279157522
Short name T198
Test name
Test status
Simulation time 56435149108 ps
CPU time 146.47 seconds
Started Aug 25 03:42:59 AM UTC 24
Finished Aug 25 03:45:28 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279157522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4279157522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.4156303902
Short name T1097
Test name
Test status
Simulation time 138073847767 ps
CPU time 1350.97 seconds
Started Aug 25 03:43:15 AM UTC 24
Finished Aug 25 04:06:03 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156303902 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.4156303902
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_loopback.471922766
Short name T492
Test name
Test status
Simulation time 3792642790 ps
CPU time 6.32 seconds
Started Aug 25 03:43:10 AM UTC 24
Finished Aug 25 03:43:18 AM UTC 24
Peak memory 207744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471922766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.uart_loopback.471922766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_noise_filter.1838600408
Short name T515
Test name
Test status
Simulation time 142028913538 ps
CPU time 108.9 seconds
Started Aug 25 03:43:04 AM UTC 24
Finished Aug 25 03:44:55 AM UTC 24
Peak memory 217564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838600408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1838600408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_perf.3420067159
Short name T379
Test name
Test status
Simulation time 17266331780 ps
CPU time 137.46 seconds
Started Aug 25 03:43:13 AM UTC 24
Finished Aug 25 03:45:33 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420067159 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3420067159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_rx_oversample.1616161675
Short name T487
Test name
Test status
Simulation time 4994809949 ps
CPU time 6.91 seconds
Started Aug 25 03:43:02 AM UTC 24
Finished Aug 25 03:43:10 AM UTC 24
Peak memory 207620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616161675 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1616161675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.2936741471
Short name T503
Test name
Test status
Simulation time 35470715188 ps
CPU time 65.36 seconds
Started Aug 25 03:43:06 AM UTC 24
Finished Aug 25 03:44:13 AM UTC 24
Peak memory 205020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936741471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2936741471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_smoke.2331699769
Short name T484
Test name
Test status
Simulation time 724985157 ps
CPU time 2.48 seconds
Started Aug 25 03:42:55 AM UTC 24
Finished Aug 25 03:42:58 AM UTC 24
Peak memory 208396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331699769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2331699769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_stress_all.2563080092
Short name T416
Test name
Test status
Simulation time 142449678123 ps
CPU time 505.47 seconds
Started Aug 25 03:43:19 AM UTC 24
Finished Aug 25 03:51:51 AM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563080092 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2563080092
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.2667830804
Short name T158
Test name
Test status
Simulation time 67038841512 ps
CPU time 132.39 seconds
Started Aug 25 03:43:19 AM UTC 24
Finished Aug 25 03:45:34 AM UTC 24
Peak memory 223932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2667830804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all
_with_rand_reset.2667830804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.4269336240
Short name T488
Test name
Test status
Simulation time 2326239539 ps
CPU time 2.91 seconds
Started Aug 25 03:43:07 AM UTC 24
Finished Aug 25 03:43:12 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269336240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4269336240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/21.uart_tx_rx.2312546630
Short name T560
Test name
Test status
Simulation time 58317503567 ps
CPU time 235.64 seconds
Started Aug 25 03:42:56 AM UTC 24
Finished Aug 25 03:46:55 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312546630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2312546630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/21.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3057021107
Short name T1130
Test name
Test status
Simulation time 104278354755 ps
CPU time 192.74 seconds
Started Aug 25 04:04:15 AM UTC 24
Finished Aug 25 04:07:31 AM UTC 24
Peak memory 208324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057021107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3057021107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/210.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/212.uart_fifo_reset.1639109151
Short name T1121
Test name
Test status
Simulation time 64460428592 ps
CPU time 168.82 seconds
Started Aug 25 04:04:16 AM UTC 24
Finished Aug 25 04:07:08 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639109151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1639109151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/212.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/213.uart_fifo_reset.3613820382
Short name T1057
Test name
Test status
Simulation time 7570034481 ps
CPU time 20.23 seconds
Started Aug 25 04:04:16 AM UTC 24
Finished Aug 25 04:04:38 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613820382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3613820382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/213.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2219319545
Short name T1070
Test name
Test status
Simulation time 37270829945 ps
CPU time 43.69 seconds
Started Aug 25 04:04:25 AM UTC 24
Finished Aug 25 04:05:10 AM UTC 24
Peak memory 208488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219319545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2219319545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/215.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/216.uart_fifo_reset.275722303
Short name T1155
Test name
Test status
Simulation time 110433190562 ps
CPU time 265.21 seconds
Started Aug 25 04:04:28 AM UTC 24
Finished Aug 25 04:08:57 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275722303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.275722303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/216.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/217.uart_fifo_reset.674211435
Short name T1064
Test name
Test status
Simulation time 10084457400 ps
CPU time 28.65 seconds
Started Aug 25 04:04:29 AM UTC 24
Finished Aug 25 04:04:59 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674211435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.674211435
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/217.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1238103291
Short name T1086
Test name
Test status
Simulation time 53753664481 ps
CPU time 73.53 seconds
Started Aug 25 04:04:29 AM UTC 24
Finished Aug 25 04:05:44 AM UTC 24
Peak memory 208908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238103291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1238103291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/218.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2677798789
Short name T229
Test name
Test status
Simulation time 141456240295 ps
CPU time 313.25 seconds
Started Aug 25 04:04:29 AM UTC 24
Finished Aug 25 04:09:47 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677798789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2677798789
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/219.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_alert_test.1226249274
Short name T499
Test name
Test status
Simulation time 14088833 ps
CPU time 0.83 seconds
Started Aug 25 03:43:56 AM UTC 24
Finished Aug 25 03:43:58 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226249274 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1226249274
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_fifo_full.193346073
Short name T556
Test name
Test status
Simulation time 71329258566 ps
CPU time 203.73 seconds
Started Aug 25 03:43:21 AM UTC 24
Finished Aug 25 03:46:48 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193346073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.193346073
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.1947963330
Short name T509
Test name
Test status
Simulation time 61883796396 ps
CPU time 66.45 seconds
Started Aug 25 03:43:23 AM UTC 24
Finished Aug 25 03:44:31 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947963330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1947963330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_fifo_reset.2458399887
Short name T534
Test name
Test status
Simulation time 170268005543 ps
CPU time 153.74 seconds
Started Aug 25 03:43:26 AM UTC 24
Finished Aug 25 03:46:03 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458399887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2458399887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_intr.2039671254
Short name T502
Test name
Test status
Simulation time 10094289136 ps
CPU time 37.83 seconds
Started Aug 25 03:43:28 AM UTC 24
Finished Aug 25 03:44:08 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039671254 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2039671254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.3309689172
Short name T751
Test name
Test status
Simulation time 96478298965 ps
CPU time 586.35 seconds
Started Aug 25 03:43:53 AM UTC 24
Finished Aug 25 03:53:48 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309689172 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3309689172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_loopback.33602821
Short name T506
Test name
Test status
Simulation time 11558288112 ps
CPU time 36.89 seconds
Started Aug 25 03:43:46 AM UTC 24
Finished Aug 25 03:44:24 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33602821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.uart_loopback.33602821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_noise_filter.3851844616
Short name T574
Test name
Test status
Simulation time 71851875303 ps
CPU time 225.52 seconds
Started Aug 25 03:43:29 AM UTC 24
Finished Aug 25 03:47:19 AM UTC 24
Peak memory 217472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851844616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3851844616
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_perf.3056379086
Short name T612
Test name
Test status
Simulation time 18559352212 ps
CPU time 299.51 seconds
Started Aug 25 03:43:49 AM UTC 24
Finished Aug 25 03:48:53 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056379086 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3056379086
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_rx_oversample.3294700143
Short name T504
Test name
Test status
Simulation time 4848881382 ps
CPU time 52.47 seconds
Started Aug 25 03:43:27 AM UTC 24
Finished Aug 25 03:44:22 AM UTC 24
Peak memory 207968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294700143 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3294700143
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.709301579
Short name T507
Test name
Test status
Simulation time 33781246137 ps
CPU time 45.7 seconds
Started Aug 25 03:43:40 AM UTC 24
Finished Aug 25 03:44:27 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709301579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.709301579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.3301218361
Short name T495
Test name
Test status
Simulation time 5098372829 ps
CPU time 2.8 seconds
Started Aug 25 03:43:35 AM UTC 24
Finished Aug 25 03:43:39 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301218361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3301218361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_smoke.3913767485
Short name T494
Test name
Test status
Simulation time 693500180 ps
CPU time 5.04 seconds
Started Aug 25 03:43:19 AM UTC 24
Finished Aug 25 03:43:25 AM UTC 24
Peak memory 207356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913767485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3913767485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_stress_all.1846309673
Short name T356
Test name
Test status
Simulation time 1165353178921 ps
CPU time 227.68 seconds
Started Aug 25 03:43:55 AM UTC 24
Finished Aug 25 03:47:46 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846309673 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1846309673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.2912478663
Short name T93
Test name
Test status
Simulation time 5462246139 ps
CPU time 39.35 seconds
Started Aug 25 03:43:55 AM UTC 24
Finished Aug 25 03:44:36 AM UTC 24
Peak memory 219640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2912478663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all
_with_rand_reset.2912478663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.1173806313
Short name T496
Test name
Test status
Simulation time 771883247 ps
CPU time 3.42 seconds
Started Aug 25 03:43:41 AM UTC 24
Finished Aug 25 03:43:45 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173806313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1173806313
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/22.uart_tx_rx.1542393993
Short name T372
Test name
Test status
Simulation time 78999431514 ps
CPU time 129.66 seconds
Started Aug 25 03:43:21 AM UTC 24
Finished Aug 25 03:45:33 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542393993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1542393993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/22.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/221.uart_fifo_reset.2100900063
Short name T1073
Test name
Test status
Simulation time 33445182276 ps
CPU time 40.32 seconds
Started Aug 25 04:04:32 AM UTC 24
Finished Aug 25 04:05:14 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100900063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2100900063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/221.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/222.uart_fifo_reset.1123615045
Short name T1089
Test name
Test status
Simulation time 94679073758 ps
CPU time 75.2 seconds
Started Aug 25 04:04:35 AM UTC 24
Finished Aug 25 04:05:52 AM UTC 24
Peak memory 208500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123615045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1123615045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/222.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/223.uart_fifo_reset.2659286126
Short name T1128
Test name
Test status
Simulation time 69121713275 ps
CPU time 170.56 seconds
Started Aug 25 04:04:35 AM UTC 24
Finished Aug 25 04:07:29 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659286126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2659286126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/223.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/225.uart_fifo_reset.2006550983
Short name T1105
Test name
Test status
Simulation time 59065330604 ps
CPU time 110.78 seconds
Started Aug 25 04:04:39 AM UTC 24
Finished Aug 25 04:06:32 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006550983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2006550983
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/225.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/226.uart_fifo_reset.2948396884
Short name T222
Test name
Test status
Simulation time 67634455084 ps
CPU time 261.34 seconds
Started Aug 25 04:04:42 AM UTC 24
Finished Aug 25 04:09:08 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948396884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2948396884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/226.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/227.uart_fifo_reset.2762000280
Short name T227
Test name
Test status
Simulation time 225742161109 ps
CPU time 111.47 seconds
Started Aug 25 04:04:44 AM UTC 24
Finished Aug 25 04:06:37 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762000280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2762000280
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/227.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/228.uart_fifo_reset.4110874509
Short name T1077
Test name
Test status
Simulation time 61205480453 ps
CPU time 32.75 seconds
Started Aug 25 04:04:46 AM UTC 24
Finished Aug 25 04:05:20 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110874509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4110874509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/228.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/229.uart_fifo_reset.3424269805
Short name T1173
Test name
Test status
Simulation time 105027935827 ps
CPU time 340.57 seconds
Started Aug 25 04:04:47 AM UTC 24
Finished Aug 25 04:10:32 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424269805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3424269805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/229.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_alert_test.503825394
Short name T510
Test name
Test status
Simulation time 11747934 ps
CPU time 0.84 seconds
Started Aug 25 03:44:30 AM UTC 24
Finished Aug 25 03:44:32 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503825394 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.503825394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_fifo_full.4069294951
Short name T606
Test name
Test status
Simulation time 186330617434 ps
CPU time 273.05 seconds
Started Aug 25 03:44:01 AM UTC 24
Finished Aug 25 03:48:39 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069294951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.4069294951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.4038723885
Short name T171
Test name
Test status
Simulation time 51060954729 ps
CPU time 46.59 seconds
Started Aug 25 03:44:03 AM UTC 24
Finished Aug 25 03:44:52 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038723885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4038723885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_fifo_reset.541091742
Short name T202
Test name
Test status
Simulation time 45596422868 ps
CPU time 67.73 seconds
Started Aug 25 03:44:05 AM UTC 24
Finished Aug 25 03:45:14 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541091742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.541091742
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_intr.2512332129
Short name T118
Test name
Test status
Simulation time 288449374256 ps
CPU time 207.01 seconds
Started Aug 25 03:44:10 AM UTC 24
Finished Aug 25 03:47:40 AM UTC 24
Peak memory 208592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512332129 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2512332129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.1106624126
Short name T899
Test name
Test status
Simulation time 107606935037 ps
CPU time 913.62 seconds
Started Aug 25 03:44:25 AM UTC 24
Finished Aug 25 03:59:51 AM UTC 24
Peak memory 212124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106624126 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1106624126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_loopback.3191637708
Short name T512
Test name
Test status
Simulation time 3819952712 ps
CPU time 14.67 seconds
Started Aug 25 03:44:24 AM UTC 24
Finished Aug 25 03:44:40 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191637708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3191637708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_noise_filter.2598012989
Short name T414
Test name
Test status
Simulation time 19404461724 ps
CPU time 22.5 seconds
Started Aug 25 03:44:13 AM UTC 24
Finished Aug 25 03:44:37 AM UTC 24
Peak memory 205372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598012989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2598012989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_perf.2755796433
Short name T938
Test name
Test status
Simulation time 15437707114 ps
CPU time 990.94 seconds
Started Aug 25 03:44:25 AM UTC 24
Finished Aug 25 04:01:09 AM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755796433 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2755796433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_rx_oversample.2183311291
Short name T505
Test name
Test status
Simulation time 1803410080 ps
CPU time 13.35 seconds
Started Aug 25 03:44:09 AM UTC 24
Finished Aug 25 03:44:23 AM UTC 24
Peak memory 207956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183311291 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2183311291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.3753525384
Short name T541
Test name
Test status
Simulation time 36210622380 ps
CPU time 120.5 seconds
Started Aug 25 03:44:20 AM UTC 24
Finished Aug 25 03:46:23 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753525384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3753525384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.1495695281
Short name T514
Test name
Test status
Simulation time 32990353610 ps
CPU time 36.74 seconds
Started Aug 25 03:44:14 AM UTC 24
Finished Aug 25 03:44:52 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495695281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1495695281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_smoke.904042854
Short name T500
Test name
Test status
Simulation time 471043911 ps
CPU time 1.89 seconds
Started Aug 25 03:43:57 AM UTC 24
Finished Aug 25 03:44:00 AM UTC 24
Peak memory 207880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904042854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 23.uart_smoke.904042854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_stress_all.329624747
Short name T195
Test name
Test status
Simulation time 178912687373 ps
CPU time 300.44 seconds
Started Aug 25 03:44:27 AM UTC 24
Finished Aug 25 03:49:33 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329624747 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.329624747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.4087681823
Short name T190
Test name
Test status
Simulation time 2304168075 ps
CPU time 39.07 seconds
Started Aug 25 03:44:25 AM UTC 24
Finished Aug 25 03:45:06 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4087681823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all
_with_rand_reset.4087681823
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.2479331421
Short name T508
Test name
Test status
Simulation time 874437972 ps
CPU time 4.19 seconds
Started Aug 25 03:44:23 AM UTC 24
Finished Aug 25 03:44:28 AM UTC 24
Peak memory 207812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479331421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2479331421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/23.uart_tx_rx.45767181
Short name T533
Test name
Test status
Simulation time 90200563019 ps
CPU time 118.26 seconds
Started Aug 25 03:43:58 AM UTC 24
Finished Aug 25 03:45:59 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45767181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.45767181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/23.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3632402265
Short name T239
Test name
Test status
Simulation time 25420239329 ps
CPU time 83.99 seconds
Started Aug 25 04:04:49 AM UTC 24
Finished Aug 25 04:06:15 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632402265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3632402265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/230.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/231.uart_fifo_reset.2440516229
Short name T1094
Test name
Test status
Simulation time 18889616650 ps
CPU time 67.3 seconds
Started Aug 25 04:04:51 AM UTC 24
Finished Aug 25 04:06:00 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440516229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2440516229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/231.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/232.uart_fifo_reset.338739987
Short name T1019
Test name
Test status
Simulation time 153054499362 ps
CPU time 65.78 seconds
Started Aug 25 04:04:54 AM UTC 24
Finished Aug 25 04:06:01 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338739987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.338739987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/232.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2907390625
Short name T1110
Test name
Test status
Simulation time 99588052287 ps
CPU time 107.9 seconds
Started Aug 25 04:04:56 AM UTC 24
Finished Aug 25 04:06:46 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907390625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2907390625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/233.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/234.uart_fifo_reset.1357530299
Short name T1085
Test name
Test status
Simulation time 24200013910 ps
CPU time 40.84 seconds
Started Aug 25 04:05:00 AM UTC 24
Finished Aug 25 04:05:42 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357530299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1357530299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/234.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/235.uart_fifo_reset.1867335214
Short name T1167
Test name
Test status
Simulation time 97069107362 ps
CPU time 285.45 seconds
Started Aug 25 04:05:00 AM UTC 24
Finished Aug 25 04:09:50 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867335214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1867335214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/235.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/236.uart_fifo_reset.2907928376
Short name T1140
Test name
Test status
Simulation time 130668360842 ps
CPU time 173.72 seconds
Started Aug 25 04:05:01 AM UTC 24
Finished Aug 25 04:07:58 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907928376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2907928376
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/236.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/238.uart_fifo_reset.126814965
Short name T235
Test name
Test status
Simulation time 43226836655 ps
CPU time 137.2 seconds
Started Aug 25 04:05:04 AM UTC 24
Finished Aug 25 04:07:24 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126814965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.126814965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/238.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1766295648
Short name T1160
Test name
Test status
Simulation time 178692473582 ps
CPU time 248.41 seconds
Started Aug 25 04:05:04 AM UTC 24
Finished Aug 25 04:09:16 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766295648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1766295648
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/239.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_alert_test.573638127
Short name T518
Test name
Test status
Simulation time 42766908 ps
CPU time 0.83 seconds
Started Aug 25 03:45:04 AM UTC 24
Finished Aug 25 03:45:06 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573638127 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.573638127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_fifo_full.1094853721
Short name T530
Test name
Test status
Simulation time 33184069745 ps
CPU time 77.57 seconds
Started Aug 25 03:44:31 AM UTC 24
Finished Aug 25 03:45:50 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094853721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1094853721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.1472880786
Short name T698
Test name
Test status
Simulation time 144754437460 ps
CPU time 439.92 seconds
Started Aug 25 03:44:32 AM UTC 24
Finished Aug 25 03:51:58 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472880786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1472880786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_fifo_reset.247567588
Short name T194
Test name
Test status
Simulation time 175020301253 ps
CPU time 499.18 seconds
Started Aug 25 03:44:33 AM UTC 24
Finished Aug 25 03:52:59 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247567588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.247567588
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_intr.379661268
Short name T117
Test name
Test status
Simulation time 8863917578 ps
CPU time 25.13 seconds
Started Aug 25 03:44:37 AM UTC 24
Finished Aug 25 03:45:04 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379661268 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.379661268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.1776694148
Short name T739
Test name
Test status
Simulation time 134978620951 ps
CPU time 498.46 seconds
Started Aug 25 03:44:56 AM UTC 24
Finished Aug 25 03:53:21 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776694148 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1776694148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_loopback.2715964214
Short name T517
Test name
Test status
Simulation time 7552458897 ps
CPU time 6.12 seconds
Started Aug 25 03:44:53 AM UTC 24
Finished Aug 25 03:45:00 AM UTC 24
Peak memory 208196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715964214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2715964214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_noise_filter.1324096855
Short name T410
Test name
Test status
Simulation time 85089165198 ps
CPU time 245.69 seconds
Started Aug 25 03:44:37 AM UTC 24
Finished Aug 25 03:48:47 AM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324096855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1324096855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_perf.409978644
Short name T1179
Test name
Test status
Simulation time 18468092713 ps
CPU time 1581.74 seconds
Started Aug 25 03:44:53 AM UTC 24
Finished Aug 25 04:11:35 AM UTC 24
Peak memory 212368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409978644 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.409978644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_rx_oversample.1014358982
Short name T519
Test name
Test status
Simulation time 4937234661 ps
CPU time 32.75 seconds
Started Aug 25 03:44:36 AM UTC 24
Finished Aug 25 03:45:10 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014358982 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1014358982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.3410473087
Short name T161
Test name
Test status
Simulation time 55196264646 ps
CPU time 72.24 seconds
Started Aug 25 03:44:50 AM UTC 24
Finished Aug 25 03:46:05 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410473087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3410473087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.2093375384
Short name T513
Test name
Test status
Simulation time 3934888434 ps
CPU time 7.17 seconds
Started Aug 25 03:44:41 AM UTC 24
Finished Aug 25 03:44:49 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093375384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2093375384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_smoke.1565050027
Short name T511
Test name
Test status
Simulation time 646962635 ps
CPU time 4.05 seconds
Started Aug 25 03:44:30 AM UTC 24
Finished Aug 25 03:44:35 AM UTC 24
Peak memory 208196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565050027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1565050027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.3597115184
Short name T94
Test name
Test status
Simulation time 1541607384 ps
CPU time 21.83 seconds
Started Aug 25 03:44:58 AM UTC 24
Finished Aug 25 03:45:21 AM UTC 24
Peak memory 217464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3597115184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all
_with_rand_reset.3597115184
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.2423676200
Short name T516
Test name
Test status
Simulation time 868408416 ps
CPU time 4.57 seconds
Started Aug 25 03:44:51 AM UTC 24
Finished Aug 25 03:44:57 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423676200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2423676200
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/24.uart_tx_rx.403646645
Short name T501
Test name
Test status
Simulation time 17179748711 ps
CPU time 45.36 seconds
Started Aug 25 03:44:30 AM UTC 24
Finished Aug 25 03:45:17 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403646645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.403646645
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/24.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/240.uart_fifo_reset.3211266474
Short name T1170
Test name
Test status
Simulation time 159410700392 ps
CPU time 300.45 seconds
Started Aug 25 04:05:06 AM UTC 24
Finished Aug 25 04:10:11 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211266474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3211266474
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/240.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/241.uart_fifo_reset.4205035715
Short name T1102
Test name
Test status
Simulation time 116422959936 ps
CPU time 70.85 seconds
Started Aug 25 04:05:10 AM UTC 24
Finished Aug 25 04:06:22 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205035715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.4205035715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/241.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/242.uart_fifo_reset.417822619
Short name T1125
Test name
Test status
Simulation time 36745118145 ps
CPU time 124.09 seconds
Started Aug 25 04:05:11 AM UTC 24
Finished Aug 25 04:07:17 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417822619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.417822619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/242.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1229701572
Short name T244
Test name
Test status
Simulation time 118916300460 ps
CPU time 49.86 seconds
Started Aug 25 04:05:12 AM UTC 24
Finished Aug 25 04:06:03 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229701572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1229701572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/243.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/244.uart_fifo_reset.2773757620
Short name T1154
Test name
Test status
Simulation time 80452015119 ps
CPU time 221.19 seconds
Started Aug 25 04:05:12 AM UTC 24
Finished Aug 25 04:08:56 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773757620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2773757620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/244.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/245.uart_fifo_reset.2569153351
Short name T1111
Test name
Test status
Simulation time 52073967950 ps
CPU time 91.81 seconds
Started Aug 25 04:05:13 AM UTC 24
Finished Aug 25 04:06:47 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569153351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2569153351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/245.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/246.uart_fifo_reset.2594909408
Short name T246
Test name
Test status
Simulation time 36749527455 ps
CPU time 55.4 seconds
Started Aug 25 04:05:13 AM UTC 24
Finished Aug 25 04:06:10 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594909408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2594909408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/246.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3230775527
Short name T1088
Test name
Test status
Simulation time 12551556482 ps
CPU time 35.57 seconds
Started Aug 25 04:05:15 AM UTC 24
Finished Aug 25 04:05:52 AM UTC 24
Peak memory 207428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230775527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3230775527
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/247.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3346819096
Short name T1104
Test name
Test status
Simulation time 111072334593 ps
CPU time 72.85 seconds
Started Aug 25 04:05:15 AM UTC 24
Finished Aug 25 04:06:30 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346819096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3346819096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/248.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/249.uart_fifo_reset.3510664685
Short name T1098
Test name
Test status
Simulation time 28483020151 ps
CPU time 49.73 seconds
Started Aug 25 04:05:16 AM UTC 24
Finished Aug 25 04:06:07 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510664685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3510664685
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/249.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_alert_test.3023871035
Short name T525
Test name
Test status
Simulation time 11116373 ps
CPU time 0.82 seconds
Started Aug 25 03:45:40 AM UTC 24
Finished Aug 25 03:45:42 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023871035 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3023871035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_fifo_full.3497147239
Short name T633
Test name
Test status
Simulation time 276676685515 ps
CPU time 252.43 seconds
Started Aug 25 03:45:11 AM UTC 24
Finished Aug 25 03:49:27 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497147239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3497147239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.4219137520
Short name T422
Test name
Test status
Simulation time 92088626189 ps
CPU time 120.07 seconds
Started Aug 25 03:45:15 AM UTC 24
Finished Aug 25 03:47:18 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219137520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.4219137520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_intr.3553428041
Short name T544
Test name
Test status
Simulation time 38847737169 ps
CPU time 60.51 seconds
Started Aug 25 03:45:22 AM UTC 24
Finished Aug 25 03:46:24 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553428041 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3553428041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.2491573769
Short name T600
Test name
Test status
Simulation time 42280862307 ps
CPU time 164.31 seconds
Started Aug 25 03:45:35 AM UTC 24
Finished Aug 25 03:48:22 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491573769 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2491573769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_loopback.4051063737
Short name T529
Test name
Test status
Simulation time 7333205167 ps
CPU time 12.43 seconds
Started Aug 25 03:45:34 AM UTC 24
Finished Aug 25 03:45:48 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051063737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.uart_loopback.4051063737
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_noise_filter.2350634103
Short name T545
Test name
Test status
Simulation time 16548327198 ps
CPU time 64.47 seconds
Started Aug 25 03:45:22 AM UTC 24
Finished Aug 25 03:46:28 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350634103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2350634103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_perf.3094534343
Short name T765
Test name
Test status
Simulation time 5798533693 ps
CPU time 515.45 seconds
Started Aug 25 03:45:34 AM UTC 24
Finished Aug 25 03:54:17 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094534343 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3094534343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_rx_oversample.1762845019
Short name T524
Test name
Test status
Simulation time 7659772501 ps
CPU time 22.18 seconds
Started Aug 25 03:45:17 AM UTC 24
Finished Aug 25 03:45:41 AM UTC 24
Peak memory 207808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762845019 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1762845019
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.3549692510
Short name T561
Test name
Test status
Simulation time 49383196289 ps
CPU time 85.29 seconds
Started Aug 25 03:45:29 AM UTC 24
Finished Aug 25 03:46:56 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549692510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3549692510
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.57501871
Short name T565
Test name
Test status
Simulation time 34045281554 ps
CPU time 94.55 seconds
Started Aug 25 03:45:23 AM UTC 24
Finished Aug 25 03:46:59 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57501871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.57501871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_smoke.1981219309
Short name T527
Test name
Test status
Simulation time 5904432305 ps
CPU time 37.71 seconds
Started Aug 25 03:45:07 AM UTC 24
Finished Aug 25 03:45:46 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981219309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1981219309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_stress_all.3316433890
Short name T563
Test name
Test status
Simulation time 19013246587 ps
CPU time 75.78 seconds
Started Aug 25 03:45:39 AM UTC 24
Finished Aug 25 03:46:57 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316433890 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3316433890
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.1642253716
Short name T557
Test name
Test status
Simulation time 14471926236 ps
CPU time 73.84 seconds
Started Aug 25 03:45:35 AM UTC 24
Finished Aug 25 03:46:51 AM UTC 24
Peak memory 219776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1642253716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all
_with_rand_reset.1642253716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.1129572534
Short name T523
Test name
Test status
Simulation time 787208467 ps
CPU time 5.53 seconds
Started Aug 25 03:45:33 AM UTC 24
Finished Aug 25 03:45:40 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129572534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1129572534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/25.uart_tx_rx.3215813164
Short name T528
Test name
Test status
Simulation time 94563505496 ps
CPU time 38.39 seconds
Started Aug 25 03:45:07 AM UTC 24
Finished Aug 25 03:45:47 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215813164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3215813164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/25.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/250.uart_fifo_reset.3683250255
Short name T1119
Test name
Test status
Simulation time 133957139312 ps
CPU time 105.05 seconds
Started Aug 25 04:05:17 AM UTC 24
Finished Aug 25 04:07:04 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683250255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3683250255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/250.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/251.uart_fifo_reset.3943300690
Short name T1107
Test name
Test status
Simulation time 99895060403 ps
CPU time 74.03 seconds
Started Aug 25 04:05:20 AM UTC 24
Finished Aug 25 04:06:36 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943300690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3943300690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/251.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/253.uart_fifo_reset.2550299657
Short name T1091
Test name
Test status
Simulation time 23448017273 ps
CPU time 33.31 seconds
Started Aug 25 04:05:20 AM UTC 24
Finished Aug 25 04:05:55 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550299657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2550299657
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/253.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1227617420
Short name T1099
Test name
Test status
Simulation time 146334621528 ps
CPU time 58.31 seconds
Started Aug 25 04:05:21 AM UTC 24
Finished Aug 25 04:06:21 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227617420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1227617420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/254.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/255.uart_fifo_reset.2865979765
Short name T1164
Test name
Test status
Simulation time 104521083924 ps
CPU time 249.46 seconds
Started Aug 25 04:05:25 AM UTC 24
Finished Aug 25 04:09:38 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865979765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2865979765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/255.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/256.uart_fifo_reset.1105612124
Short name T1116
Test name
Test status
Simulation time 26519783612 ps
CPU time 90.36 seconds
Started Aug 25 04:05:28 AM UTC 24
Finished Aug 25 04:07:00 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105612124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1105612124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/256.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/257.uart_fifo_reset.613135726
Short name T1139
Test name
Test status
Simulation time 62487378908 ps
CPU time 146.71 seconds
Started Aug 25 04:05:28 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613135726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.613135726
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/257.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/258.uart_fifo_reset.2500968098
Short name T1114
Test name
Test status
Simulation time 299617772919 ps
CPU time 84.83 seconds
Started Aug 25 04:05:28 AM UTC 24
Finished Aug 25 04:06:55 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500968098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2500968098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/258.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/259.uart_fifo_reset.2780163559
Short name T1176
Test name
Test status
Simulation time 148901364112 ps
CPU time 309.34 seconds
Started Aug 25 04:05:29 AM UTC 24
Finished Aug 25 04:10:50 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780163559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2780163559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/259.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_alert_test.4084877763
Short name T538
Test name
Test status
Simulation time 68062668 ps
CPU time 0.82 seconds
Started Aug 25 03:46:13 AM UTC 24
Finished Aug 25 03:46:15 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084877763 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4084877763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_fifo_full.3236009402
Short name T590
Test name
Test status
Simulation time 33062303898 ps
CPU time 130.29 seconds
Started Aug 25 03:45:46 AM UTC 24
Finished Aug 25 03:47:58 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236009402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3236009402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.2061433855
Short name T592
Test name
Test status
Simulation time 44155938359 ps
CPU time 131.45 seconds
Started Aug 25 03:45:47 AM UTC 24
Finished Aug 25 03:48:01 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061433855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2061433855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_fifo_reset.2598680945
Short name T558
Test name
Test status
Simulation time 84142278214 ps
CPU time 61.36 seconds
Started Aug 25 03:45:48 AM UTC 24
Finished Aug 25 03:46:51 AM UTC 24
Peak memory 208080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598680945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2598680945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_intr.2952833413
Short name T539
Test name
Test status
Simulation time 16716715573 ps
CPU time 22.61 seconds
Started Aug 25 03:45:51 AM UTC 24
Finished Aug 25 03:46:15 AM UTC 24
Peak memory 207700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952833413 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2952833413
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.4110695562
Short name T848
Test name
Test status
Simulation time 177981439260 ps
CPU time 710.02 seconds
Started Aug 25 03:46:07 AM UTC 24
Finished Aug 25 03:58:08 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110695562 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4110695562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_loopback.1711787209
Short name T537
Test name
Test status
Simulation time 6887034852 ps
CPU time 6.27 seconds
Started Aug 25 03:46:04 AM UTC 24
Finished Aug 25 03:46:12 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711787209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1711787209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_noise_filter.1284555934
Short name T535
Test name
Test status
Simulation time 5295242809 ps
CPU time 10.79 seconds
Started Aug 25 03:45:56 AM UTC 24
Finished Aug 25 03:46:08 AM UTC 24
Peak memory 209032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284555934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1284555934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_perf.2678770922
Short name T685
Test name
Test status
Simulation time 15357047327 ps
CPU time 314.41 seconds
Started Aug 25 03:46:05 AM UTC 24
Finished Aug 25 03:51:25 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678770922 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2678770922
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_rx_oversample.3033884319
Short name T547
Test name
Test status
Simulation time 6830389482 ps
CPU time 41.11 seconds
Started Aug 25 03:45:49 AM UTC 24
Finished Aug 25 03:46:32 AM UTC 24
Peak memory 207916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033884319 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3033884319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.1491165220
Short name T542
Test name
Test status
Simulation time 7781538828 ps
CPU time 21.83 seconds
Started Aug 25 03:46:00 AM UTC 24
Finished Aug 25 03:46:23 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491165220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1491165220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.1692332292
Short name T536
Test name
Test status
Simulation time 3659105769 ps
CPU time 11.72 seconds
Started Aug 25 03:45:57 AM UTC 24
Finished Aug 25 03:46:10 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692332292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1692332292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_smoke.3990970925
Short name T532
Test name
Test status
Simulation time 5485654016 ps
CPU time 13.51 seconds
Started Aug 25 03:45:41 AM UTC 24
Finished Aug 25 03:45:56 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990970925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3990970925
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_stress_all.4121133884
Short name T870
Test name
Test status
Simulation time 240392342289 ps
CPU time 741.23 seconds
Started Aug 25 03:46:11 AM UTC 24
Finished Aug 25 03:58:41 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121133884 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.4121133884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.2367761831
Short name T95
Test name
Test status
Simulation time 1739068249 ps
CPU time 15.15 seconds
Started Aug 25 03:46:08 AM UTC 24
Finished Aug 25 03:46:25 AM UTC 24
Peak memory 208964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2367761831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all
_with_rand_reset.2367761831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.4024814995
Short name T548
Test name
Test status
Simulation time 6514412901 ps
CPU time 28.6 seconds
Started Aug 25 03:46:02 AM UTC 24
Finished Aug 25 03:46:32 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024814995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4024814995
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/26.uart_tx_rx.2446039730
Short name T540
Test name
Test status
Simulation time 65386831568 ps
CPU time 33.56 seconds
Started Aug 25 03:45:42 AM UTC 24
Finished Aug 25 03:46:17 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446039730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2446039730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/26.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/260.uart_fifo_reset.3425096263
Short name T1132
Test name
Test status
Simulation time 85703236588 ps
CPU time 116.3 seconds
Started Aug 25 04:05:35 AM UTC 24
Finished Aug 25 04:07:33 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425096263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3425096263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/260.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/261.uart_fifo_reset.972654819
Short name T1131
Test name
Test status
Simulation time 149206368683 ps
CPU time 106.88 seconds
Started Aug 25 04:05:43 AM UTC 24
Finished Aug 25 04:07:32 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972654819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.972654819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/261.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/262.uart_fifo_reset.3310181021
Short name T1106
Test name
Test status
Simulation time 17871555261 ps
CPU time 50.52 seconds
Started Aug 25 04:05:43 AM UTC 24
Finished Aug 25 04:06:35 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310181021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3310181021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/262.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/263.uart_fifo_reset.1824926948
Short name T1135
Test name
Test status
Simulation time 48256683564 ps
CPU time 116.96 seconds
Started Aug 25 04:05:43 AM UTC 24
Finished Aug 25 04:07:42 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824926948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1824926948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/263.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/264.uart_fifo_reset.1776602583
Short name T1148
Test name
Test status
Simulation time 58125897255 ps
CPU time 164.36 seconds
Started Aug 25 04:05:45 AM UTC 24
Finished Aug 25 04:08:33 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776602583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1776602583
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/264.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/265.uart_fifo_reset.2449132713
Short name T1117
Test name
Test status
Simulation time 96206683349 ps
CPU time 71.85 seconds
Started Aug 25 04:05:46 AM UTC 24
Finished Aug 25 04:07:00 AM UTC 24
Peak memory 208976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449132713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2449132713
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/265.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/266.uart_fifo_reset.518552237
Short name T1151
Test name
Test status
Simulation time 63684725202 ps
CPU time 162.59 seconds
Started Aug 25 04:05:53 AM UTC 24
Finished Aug 25 04:08:39 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518552237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.518552237
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/266.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1057428469
Short name T1136
Test name
Test status
Simulation time 80875337063 ps
CPU time 111.56 seconds
Started Aug 25 04:05:53 AM UTC 24
Finished Aug 25 04:07:48 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057428469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1057428469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/267.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/269.uart_fifo_reset.3166658462
Short name T1142
Test name
Test status
Simulation time 207464388657 ps
CPU time 126.07 seconds
Started Aug 25 04:05:56 AM UTC 24
Finished Aug 25 04:08:04 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166658462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3166658462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/269.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_alert_test.1295749621
Short name T552
Test name
Test status
Simulation time 20271950 ps
CPU time 0.81 seconds
Started Aug 25 03:46:40 AM UTC 24
Finished Aug 25 03:46:42 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295749621 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1295749621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_fifo_full.868185495
Short name T579
Test name
Test status
Simulation time 72894614516 ps
CPU time 65.88 seconds
Started Aug 25 03:46:18 AM UTC 24
Finished Aug 25 03:47:26 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868185495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.868185495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.1084747336
Short name T585
Test name
Test status
Simulation time 46697431917 ps
CPU time 75.27 seconds
Started Aug 25 03:46:24 AM UTC 24
Finished Aug 25 03:47:41 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084747336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1084747336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_intr.3384996512
Short name T551
Test name
Test status
Simulation time 8318526526 ps
CPU time 13.01 seconds
Started Aug 25 03:46:25 AM UTC 24
Finished Aug 25 03:46:39 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384996512 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3384996512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.2469331778
Short name T660
Test name
Test status
Simulation time 79897205426 ps
CPU time 237.23 seconds
Started Aug 25 03:46:33 AM UTC 24
Finished Aug 25 03:50:34 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469331778 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2469331778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_loopback.2710979195
Short name T553
Test name
Test status
Simulation time 8484779324 ps
CPU time 10.74 seconds
Started Aug 25 03:46:30 AM UTC 24
Finished Aug 25 03:46:43 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710979195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2710979195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_noise_filter.545803266
Short name T406
Test name
Test status
Simulation time 42442742233 ps
CPU time 25.22 seconds
Started Aug 25 03:46:25 AM UTC 24
Finished Aug 25 03:46:52 AM UTC 24
Peak memory 205236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545803266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.545803266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_perf.2354733356
Short name T970
Test name
Test status
Simulation time 16099858024 ps
CPU time 926.78 seconds
Started Aug 25 03:46:33 AM UTC 24
Finished Aug 25 04:02:11 AM UTC 24
Peak memory 212248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354733356 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2354733356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_rx_oversample.2249813108
Short name T584
Test name
Test status
Simulation time 6113547500 ps
CPU time 73.62 seconds
Started Aug 25 03:46:24 AM UTC 24
Finished Aug 25 03:47:40 AM UTC 24
Peak memory 207976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249813108 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2249813108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.3286253473
Short name T845
Test name
Test status
Simulation time 258404840553 ps
CPU time 682.39 seconds
Started Aug 25 03:46:28 AM UTC 24
Finished Aug 25 03:58:00 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286253473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3286253473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.1123474136
Short name T546
Test name
Test status
Simulation time 575464083 ps
CPU time 1.79 seconds
Started Aug 25 03:46:26 AM UTC 24
Finished Aug 25 03:46:29 AM UTC 24
Peak memory 204432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123474136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1123474136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_smoke.3824962414
Short name T550
Test name
Test status
Simulation time 5886722143 ps
CPU time 20.19 seconds
Started Aug 25 03:46:16 AM UTC 24
Finished Aug 25 03:46:37 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824962414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3824962414
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_stress_all.3534909829
Short name T745
Test name
Test status
Simulation time 53802654622 ps
CPU time 410.93 seconds
Started Aug 25 03:46:38 AM UTC 24
Finished Aug 25 03:53:35 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534909829 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3534909829
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.2070878121
Short name T597
Test name
Test status
Simulation time 4327428546 ps
CPU time 93.57 seconds
Started Aug 25 03:46:37 AM UTC 24
Finished Aug 25 03:48:13 AM UTC 24
Peak memory 217980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2070878121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all
_with_rand_reset.2070878121
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.229135427
Short name T573
Test name
Test status
Simulation time 7113517239 ps
CPU time 46.16 seconds
Started Aug 25 03:46:29 AM UTC 24
Finished Aug 25 03:47:17 AM UTC 24
Peak memory 208556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229135427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.229135427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/27.uart_tx_rx.877621751
Short name T407
Test name
Test status
Simulation time 63142612536 ps
CPU time 46.93 seconds
Started Aug 25 03:46:16 AM UTC 24
Finished Aug 25 03:47:04 AM UTC 24
Peak memory 208392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877621751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.877621751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/27.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/270.uart_fifo_reset.3006073619
Short name T217
Test name
Test status
Simulation time 41799832151 ps
CPU time 102.2 seconds
Started Aug 25 04:05:58 AM UTC 24
Finished Aug 25 04:07:42 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006073619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3006073619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/270.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/271.uart_fifo_reset.2014568675
Short name T1152
Test name
Test status
Simulation time 81000230764 ps
CPU time 158.64 seconds
Started Aug 25 04:06:00 AM UTC 24
Finished Aug 25 04:08:41 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014568675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2014568675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/271.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/272.uart_fifo_reset.371885085
Short name T1134
Test name
Test status
Simulation time 42294440387 ps
CPU time 97.46 seconds
Started Aug 25 04:06:01 AM UTC 24
Finished Aug 25 04:07:40 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371885085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.371885085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/272.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/273.uart_fifo_reset.2413937363
Short name T253
Test name
Test status
Simulation time 55808438778 ps
CPU time 157.16 seconds
Started Aug 25 04:06:01 AM UTC 24
Finished Aug 25 04:08:41 AM UTC 24
Peak memory 208588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413937363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2413937363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/273.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/274.uart_fifo_reset.3331685647
Short name T263
Test name
Test status
Simulation time 153597806705 ps
CPU time 112.77 seconds
Started Aug 25 04:06:02 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331685647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3331685647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/274.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/275.uart_fifo_reset.2187632135
Short name T1115
Test name
Test status
Simulation time 91584614580 ps
CPU time 54.51 seconds
Started Aug 25 04:06:03 AM UTC 24
Finished Aug 25 04:06:59 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187632135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2187632135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/275.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/276.uart_fifo_reset.2943861499
Short name T1141
Test name
Test status
Simulation time 38395488627 ps
CPU time 117.16 seconds
Started Aug 25 04:06:03 AM UTC 24
Finished Aug 25 04:08:03 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943861499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2943861499
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/276.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/277.uart_fifo_reset.1182500097
Short name T242
Test name
Test status
Simulation time 25851484196 ps
CPU time 21.15 seconds
Started Aug 25 04:06:04 AM UTC 24
Finished Aug 25 04:06:27 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182500097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1182500097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/277.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/278.uart_fifo_reset.497865786
Short name T1147
Test name
Test status
Simulation time 65858316765 ps
CPU time 141.73 seconds
Started Aug 25 04:06:04 AM UTC 24
Finished Aug 25 04:08:29 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497865786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.497865786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/278.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/279.uart_fifo_reset.151307795
Short name T1108
Test name
Test status
Simulation time 12022044124 ps
CPU time 34.22 seconds
Started Aug 25 04:06:04 AM UTC 24
Finished Aug 25 04:06:40 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151307795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.151307795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/279.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_alert_test.2193263739
Short name T568
Test name
Test status
Simulation time 29967826 ps
CPU time 0.81 seconds
Started Aug 25 03:47:00 AM UTC 24
Finished Aug 25 03:47:02 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193263739 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2193263739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_fifo_full.297165520
Short name T616
Test name
Test status
Simulation time 236658214819 ps
CPU time 134.84 seconds
Started Aug 25 03:46:43 AM UTC 24
Finished Aug 25 03:49:00 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297165520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.297165520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.2864005238
Short name T629
Test name
Test status
Simulation time 155183917623 ps
CPU time 149.26 seconds
Started Aug 25 03:46:45 AM UTC 24
Finished Aug 25 03:49:17 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864005238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2864005238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_intr.298108810
Short name T570
Test name
Test status
Simulation time 67032650839 ps
CPU time 16.85 seconds
Started Aug 25 03:46:51 AM UTC 24
Finished Aug 25 03:47:09 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298108810 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.298108810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.203315594
Short name T1137
Test name
Test status
Simulation time 99244597524 ps
CPU time 1234.36 seconds
Started Aug 25 03:46:58 AM UTC 24
Finished Aug 25 04:07:48 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203315594 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.203315594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_loopback.2520591703
Short name T582
Test name
Test status
Simulation time 11381094354 ps
CPU time 38.94 seconds
Started Aug 25 03:46:57 AM UTC 24
Finished Aug 25 03:47:37 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520591703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2520591703
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_noise_filter.1208480753
Short name T575
Test name
Test status
Simulation time 33251975255 ps
CPU time 28.2 seconds
Started Aug 25 03:46:52 AM UTC 24
Finished Aug 25 03:47:21 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208480753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1208480753
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_perf.3570470346
Short name T604
Test name
Test status
Simulation time 22380850729 ps
CPU time 95.77 seconds
Started Aug 25 03:46:57 AM UTC 24
Finished Aug 25 03:48:35 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570470346 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3570470346
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_rx_oversample.3659707454
Short name T571
Test name
Test status
Simulation time 3899379149 ps
CPU time 22.94 seconds
Started Aug 25 03:46:49 AM UTC 24
Finished Aug 25 03:47:14 AM UTC 24
Peak memory 208520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659707454 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3659707454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.422949799
Short name T640
Test name
Test status
Simulation time 47055601558 ps
CPU time 164.78 seconds
Started Aug 25 03:46:55 AM UTC 24
Finished Aug 25 03:49:42 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422949799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.422949799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.3786326733
Short name T562
Test name
Test status
Simulation time 5687691671 ps
CPU time 2.84 seconds
Started Aug 25 03:46:53 AM UTC 24
Finished Aug 25 03:46:56 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786326733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3786326733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_smoke.2134296856
Short name T564
Test name
Test status
Simulation time 6206601830 ps
CPU time 15.76 seconds
Started Aug 25 03:46:40 AM UTC 24
Finished Aug 25 03:46:57 AM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134296856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2134296856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_stress_all.397035308
Short name T840
Test name
Test status
Simulation time 148970150743 ps
CPU time 637.82 seconds
Started Aug 25 03:47:00 AM UTC 24
Finished Aug 25 03:57:46 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397035308 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.397035308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.3842984316
Short name T567
Test name
Test status
Simulation time 4014429335 ps
CPU time 3.33 seconds
Started Aug 25 03:46:56 AM UTC 24
Finished Aug 25 03:47:00 AM UTC 24
Peak memory 207532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842984316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3842984316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/28.uart_tx_rx.3762745448
Short name T618
Test name
Test status
Simulation time 189643380816 ps
CPU time 141.79 seconds
Started Aug 25 03:46:43 AM UTC 24
Finished Aug 25 03:49:07 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762745448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3762745448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/281.uart_fifo_reset.106506048
Short name T234
Test name
Test status
Simulation time 19502261654 ps
CPU time 30.42 seconds
Started Aug 25 04:06:10 AM UTC 24
Finished Aug 25 04:06:42 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106506048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.106506048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/281.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2256897063
Short name T1171
Test name
Test status
Simulation time 117728102841 ps
CPU time 232.99 seconds
Started Aug 25 04:06:15 AM UTC 24
Finished Aug 25 04:10:12 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256897063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2256897063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/282.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/283.uart_fifo_reset.2658097493
Short name T1166
Test name
Test status
Simulation time 81563048543 ps
CPU time 195.54 seconds
Started Aug 25 04:06:23 AM UTC 24
Finished Aug 25 04:09:41 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658097493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2658097493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/283.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/285.uart_fifo_reset.3864580003
Short name T1122
Test name
Test status
Simulation time 20825741913 ps
CPU time 46.55 seconds
Started Aug 25 04:06:23 AM UTC 24
Finished Aug 25 04:07:11 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864580003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3864580003
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/285.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3725808530
Short name T1158
Test name
Test status
Simulation time 74992337971 ps
CPU time 161.39 seconds
Started Aug 25 04:06:24 AM UTC 24
Finished Aug 25 04:09:08 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725808530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3725808530
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/287.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/288.uart_fifo_reset.1828233017
Short name T1149
Test name
Test status
Simulation time 82900280973 ps
CPU time 125.2 seconds
Started Aug 25 04:06:26 AM UTC 24
Finished Aug 25 04:08:33 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828233017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1828233017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/288.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/289.uart_fifo_reset.1033759526
Short name T214
Test name
Test status
Simulation time 124541769683 ps
CPU time 531.51 seconds
Started Aug 25 04:06:26 AM UTC 24
Finished Aug 25 04:15:24 AM UTC 24
Peak memory 212212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033759526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1033759526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/289.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_alert_test.2168428761
Short name T581
Test name
Test status
Simulation time 16430349 ps
CPU time 0.82 seconds
Started Aug 25 03:47:28 AM UTC 24
Finished Aug 25 03:47:31 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168428761 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2168428761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_fifo_full.1337263211
Short name T599
Test name
Test status
Simulation time 51463318709 ps
CPU time 71.36 seconds
Started Aug 25 03:47:05 AM UTC 24
Finished Aug 25 03:48:19 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337263211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1337263211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.931953564
Short name T607
Test name
Test status
Simulation time 121423181072 ps
CPU time 89.03 seconds
Started Aug 25 03:47:08 AM UTC 24
Finished Aug 25 03:48:40 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931953564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.931953564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_fifo_reset.4196976392
Short name T204
Test name
Test status
Simulation time 104480914627 ps
CPU time 340.23 seconds
Started Aug 25 03:47:12 AM UTC 24
Finished Aug 25 03:52:57 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196976392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.4196976392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_intr.1979051257
Short name T402
Test name
Test status
Simulation time 11783360288 ps
CPU time 42.76 seconds
Started Aug 25 03:47:16 AM UTC 24
Finished Aug 25 03:48:00 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979051257 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1979051257
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.2274930748
Short name T648
Test name
Test status
Simulation time 45136702405 ps
CPU time 155.44 seconds
Started Aug 25 03:47:24 AM UTC 24
Finished Aug 25 03:50:03 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274930748 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2274930748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_loopback.3137555797
Short name T580
Test name
Test status
Simulation time 3032477292 ps
CPU time 4.8 seconds
Started Aug 25 03:47:22 AM UTC 24
Finished Aug 25 03:47:28 AM UTC 24
Peak memory 207700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137555797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3137555797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_noise_filter.3710724367
Short name T645
Test name
Test status
Simulation time 79565286153 ps
CPU time 157.57 seconds
Started Aug 25 03:47:17 AM UTC 24
Finished Aug 25 03:49:57 AM UTC 24
Peak memory 208528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710724367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3710724367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_perf.2321333449
Short name T718
Test name
Test status
Simulation time 6925756389 ps
CPU time 318.86 seconds
Started Aug 25 03:47:22 AM UTC 24
Finished Aug 25 03:52:46 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321333449 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2321333449
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_rx_oversample.3853643303
Short name T594
Test name
Test status
Simulation time 4313863302 ps
CPU time 47 seconds
Started Aug 25 03:47:15 AM UTC 24
Finished Aug 25 03:48:04 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853643303 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3853643303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.332964001
Short name T596
Test name
Test status
Simulation time 12782465844 ps
CPU time 46.69 seconds
Started Aug 25 03:47:19 AM UTC 24
Finished Aug 25 03:48:07 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332964001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.332964001
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.477614960
Short name T578
Test name
Test status
Simulation time 2824128163 ps
CPU time 5.22 seconds
Started Aug 25 03:47:18 AM UTC 24
Finished Aug 25 03:47:24 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477614960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.477614960
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_smoke.2841893756
Short name T569
Test name
Test status
Simulation time 536994017 ps
CPU time 5.35 seconds
Started Aug 25 03:47:01 AM UTC 24
Finished Aug 25 03:47:08 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841893756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2841893756
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_stress_all.2548174411
Short name T185
Test name
Test status
Simulation time 228212036039 ps
CPU time 185.71 seconds
Started Aug 25 03:47:26 AM UTC 24
Finished Aug 25 03:50:35 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548174411 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2548174411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.1018606349
Short name T602
Test name
Test status
Simulation time 14914221982 ps
CPU time 63.13 seconds
Started Aug 25 03:47:25 AM UTC 24
Finished Aug 25 03:48:30 AM UTC 24
Peak memory 221824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1018606349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all
_with_rand_reset.1018606349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.2900542312
Short name T577
Test name
Test status
Simulation time 1207659722 ps
CPU time 2.04 seconds
Started Aug 25 03:47:20 AM UTC 24
Finished Aug 25 03:47:23 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900542312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2900542312
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/29.uart_tx_rx.580565801
Short name T572
Test name
Test status
Simulation time 13774143476 ps
CPU time 12.46 seconds
Started Aug 25 03:47:02 AM UTC 24
Finished Aug 25 03:47:16 AM UTC 24
Peak memory 207280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580565801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.580565801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/29.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2423027695
Short name T265
Test name
Test status
Simulation time 25855145451 ps
CPU time 24.19 seconds
Started Aug 25 04:06:28 AM UTC 24
Finished Aug 25 04:06:53 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423027695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2423027695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/290.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1028920777
Short name T1163
Test name
Test status
Simulation time 97583595316 ps
CPU time 176.73 seconds
Started Aug 25 04:06:30 AM UTC 24
Finished Aug 25 04:09:30 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028920777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1028920777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/291.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/292.uart_fifo_reset.4274426740
Short name T1143
Test name
Test status
Simulation time 28026461181 ps
CPU time 97.55 seconds
Started Aug 25 04:06:30 AM UTC 24
Finished Aug 25 04:08:10 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274426740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4274426740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/292.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/293.uart_fifo_reset.1561327295
Short name T250
Test name
Test status
Simulation time 194156731341 ps
CPU time 184.59 seconds
Started Aug 25 04:06:31 AM UTC 24
Finished Aug 25 04:09:39 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561327295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1561327295
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/293.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/294.uart_fifo_reset.3126252802
Short name T1144
Test name
Test status
Simulation time 66412419190 ps
CPU time 95.06 seconds
Started Aug 25 04:06:33 AM UTC 24
Finished Aug 25 04:08:10 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126252802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3126252802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/294.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/295.uart_fifo_reset.1573053701
Short name T1133
Test name
Test status
Simulation time 16781854674 ps
CPU time 58.82 seconds
Started Aug 25 04:06:36 AM UTC 24
Finished Aug 25 04:07:37 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573053701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1573053701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/295.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/296.uart_fifo_reset.1582243007
Short name T1127
Test name
Test status
Simulation time 203663256057 ps
CPU time 47.78 seconds
Started Aug 25 04:06:37 AM UTC 24
Finished Aug 25 04:07:27 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582243007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1582243007
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/296.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/297.uart_fifo_reset.2491796420
Short name T1120
Test name
Test status
Simulation time 20705355678 ps
CPU time 24.77 seconds
Started Aug 25 04:06:38 AM UTC 24
Finished Aug 25 04:07:05 AM UTC 24
Peak memory 208496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491796420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2491796420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/297.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/299.uart_fifo_reset.1077412940
Short name T216
Test name
Test status
Simulation time 46255154251 ps
CPU time 36.65 seconds
Started Aug 25 04:06:44 AM UTC 24
Finished Aug 25 04:07:22 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077412940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1077412940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/299.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_alert_test.3788314248
Short name T87
Test name
Test status
Simulation time 79567317 ps
CPU time 0.81 seconds
Started Aug 25 03:34:30 AM UTC 24
Finished Aug 25 03:34:32 AM UTC 24
Peak memory 204424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788314248 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3788314248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.4220016041
Short name T40
Test name
Test status
Simulation time 39202118280 ps
CPU time 33.25 seconds
Started Aug 25 03:34:10 AM UTC 24
Finished Aug 25 03:34:44 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220016041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.4220016041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_fifo_reset.2616363336
Short name T47
Test name
Test status
Simulation time 136988397030 ps
CPU time 43.11 seconds
Started Aug 25 03:34:10 AM UTC 24
Finished Aug 25 03:34:54 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616363336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2616363336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_intr.2795458493
Short name T489
Test name
Test status
Simulation time 393209859603 ps
CPU time 528.67 seconds
Started Aug 25 03:34:19 AM UTC 24
Finished Aug 25 03:43:14 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795458493 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2795458493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.533495526
Short name T390
Test name
Test status
Simulation time 83716124293 ps
CPU time 224.64 seconds
Started Aug 25 03:34:28 AM UTC 24
Finished Aug 25 03:38:17 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533495526 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.533495526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_loopback.3465432162
Short name T108
Test name
Test status
Simulation time 758870725 ps
CPU time 1.6 seconds
Started Aug 25 03:34:24 AM UTC 24
Finished Aug 25 03:34:27 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465432162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3465432162
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_noise_filter.4238447763
Short name T267
Test name
Test status
Simulation time 59745263360 ps
CPU time 214.71 seconds
Started Aug 25 03:34:20 AM UTC 24
Finished Aug 25 03:37:58 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238447763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.4238447763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_perf.1516485290
Short name T52
Test name
Test status
Simulation time 1633168595 ps
CPU time 44.93 seconds
Started Aug 25 03:34:27 AM UTC 24
Finished Aug 25 03:35:14 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516485290 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1516485290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_rx_oversample.3808689163
Short name T20
Test name
Test status
Simulation time 6547094278 ps
CPU time 18.59 seconds
Started Aug 25 03:34:17 AM UTC 24
Finished Aug 25 03:34:37 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808689163 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3808689163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.290759207
Short name T337
Test name
Test status
Simulation time 1713616242 ps
CPU time 6.25 seconds
Started Aug 25 03:34:22 AM UTC 24
Finished Aug 25 03:34:29 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290759207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.290759207
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_sec_cm.282439635
Short name T88
Test name
Test status
Simulation time 39658417 ps
CPU time 1.17 seconds
Started Aug 25 03:34:30 AM UTC 24
Finished Aug 25 03:34:33 AM UTC 24
Peak memory 240132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282439635 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.282439635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_smoke.3448418515
Short name T266
Test name
Test status
Simulation time 5542952677 ps
CPU time 13.12 seconds
Started Aug 25 03:34:07 AM UTC 24
Finished Aug 25 03:34:22 AM UTC 24
Peak memory 208928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448418515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3448418515
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_stress_all.230230292
Short name T1184
Test name
Test status
Simulation time 375819104858 ps
CPU time 3384.16 seconds
Started Aug 25 03:34:29 AM UTC 24
Finished Aug 25 04:31:36 AM UTC 24
Peak memory 221224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230230292 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.230230292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.2276675871
Short name T29
Test name
Test status
Simulation time 2118927522 ps
CPU time 38.29 seconds
Started Aug 25 03:34:29 AM UTC 24
Finished Aug 25 03:35:09 AM UTC 24
Peak memory 208964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2276675871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_
with_rand_reset.2276675871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.1635071304
Short name T51
Test name
Test status
Simulation time 1002100312 ps
CPU time 4.71 seconds
Started Aug 25 03:34:23 AM UTC 24
Finished Aug 25 03:34:29 AM UTC 24
Peak memory 207788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635071304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1635071304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/3.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_alert_test.1837227610
Short name T595
Test name
Test status
Simulation time 56165423 ps
CPU time 0.83 seconds
Started Aug 25 03:48:02 AM UTC 24
Finished Aug 25 03:48:04 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837227610 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1837227610
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_fifo_full.681518700
Short name T164
Test name
Test status
Simulation time 212332467408 ps
CPU time 97.74 seconds
Started Aug 25 03:47:38 AM UTC 24
Finished Aug 25 03:49:18 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681518700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.681518700
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.959405808
Short name T588
Test name
Test status
Simulation time 48413155077 ps
CPU time 16.89 seconds
Started Aug 25 03:47:39 AM UTC 24
Finished Aug 25 03:47:57 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959405808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.959405808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_fifo_reset.2655319126
Short name T638
Test name
Test status
Simulation time 34184304872 ps
CPU time 112.56 seconds
Started Aug 25 03:47:41 AM UTC 24
Finished Aug 25 03:49:36 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655319126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2655319126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_intr.3527573569
Short name T591
Test name
Test status
Simulation time 6228723663 ps
CPU time 16.9 seconds
Started Aug 25 03:47:42 AM UTC 24
Finished Aug 25 03:48:00 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527573569 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3527573569
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.1521387033
Short name T733
Test name
Test status
Simulation time 158075945361 ps
CPU time 309.56 seconds
Started Aug 25 03:48:00 AM UTC 24
Finished Aug 25 03:53:14 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521387033 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1521387033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_loopback.3873223429
Short name T598
Test name
Test status
Simulation time 6276180698 ps
CPU time 14.82 seconds
Started Aug 25 03:47:57 AM UTC 24
Finished Aug 25 03:48:13 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873223429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3873223429
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_noise_filter.418113290
Short name T625
Test name
Test status
Simulation time 46750044822 ps
CPU time 84.54 seconds
Started Aug 25 03:47:47 AM UTC 24
Finished Aug 25 03:49:14 AM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418113290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.418113290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_perf.1928942302
Short name T1049
Test name
Test status
Simulation time 18085689091 ps
CPU time 974.07 seconds
Started Aug 25 03:47:58 AM UTC 24
Finished Aug 25 04:04:24 AM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928942302 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1928942302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_rx_oversample.2707628687
Short name T586
Test name
Test status
Simulation time 3032341154 ps
CPU time 8.74 seconds
Started Aug 25 03:47:41 AM UTC 24
Finished Aug 25 03:47:51 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707628687 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2707628687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.2811450910
Short name T772
Test name
Test status
Simulation time 156454556778 ps
CPU time 412.73 seconds
Started Aug 25 03:47:51 AM UTC 24
Finished Aug 25 03:54:49 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811450910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2811450910
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.2194209883
Short name T610
Test name
Test status
Simulation time 35999742383 ps
CPU time 55.36 seconds
Started Aug 25 03:47:48 AM UTC 24
Finished Aug 25 03:48:45 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194209883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2194209883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_smoke.3266383832
Short name T587
Test name
Test status
Simulation time 5350148512 ps
CPU time 19.99 seconds
Started Aug 25 03:47:32 AM UTC 24
Finished Aug 25 03:47:53 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266383832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3266383832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_stress_all.4247965547
Short name T639
Test name
Test status
Simulation time 178799220881 ps
CPU time 95.91 seconds
Started Aug 25 03:48:01 AM UTC 24
Finished Aug 25 03:49:39 AM UTC 24
Peak memory 217608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247965547 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.4247965547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.3529267529
Short name T96
Test name
Test status
Simulation time 1427917168 ps
CPU time 22.35 seconds
Started Aug 25 03:48:01 AM UTC 24
Finished Aug 25 03:48:24 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3529267529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all
_with_rand_reset.3529267529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.2891285536
Short name T589
Test name
Test status
Simulation time 700064053 ps
CPU time 2.62 seconds
Started Aug 25 03:47:53 AM UTC 24
Finished Aug 25 03:47:57 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891285536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2891285536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/30.uart_tx_rx.2096561205
Short name T641
Test name
Test status
Simulation time 129734820054 ps
CPU time 133.63 seconds
Started Aug 25 03:47:34 AM UTC 24
Finished Aug 25 03:49:50 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096561205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2096561205
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/30.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_alert_test.1396800590
Short name T609
Test name
Test status
Simulation time 20108348 ps
CPU time 0.8 seconds
Started Aug 25 03:48:40 AM UTC 24
Finished Aug 25 03:48:42 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396800590 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1396800590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_fifo_full.2212095688
Short name T621
Test name
Test status
Simulation time 37894284777 ps
CPU time 63.75 seconds
Started Aug 25 03:48:04 AM UTC 24
Finished Aug 25 03:49:10 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212095688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2212095688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.2634440377
Short name T659
Test name
Test status
Simulation time 45495013047 ps
CPU time 141.85 seconds
Started Aug 25 03:48:08 AM UTC 24
Finished Aug 25 03:50:33 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634440377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2634440377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_fifo_reset.3200912476
Short name T191
Test name
Test status
Simulation time 15043065723 ps
CPU time 53.37 seconds
Started Aug 25 03:48:13 AM UTC 24
Finished Aug 25 03:49:08 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200912476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3200912476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_intr.1191865984
Short name T611
Test name
Test status
Simulation time 37930765191 ps
CPU time 33.07 seconds
Started Aug 25 03:48:14 AM UTC 24
Finished Aug 25 03:48:49 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191865984 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1191865984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.1987089068
Short name T827
Test name
Test status
Simulation time 128180076505 ps
CPU time 526.27 seconds
Started Aug 25 03:48:32 AM UTC 24
Finished Aug 25 03:57:26 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987089068 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1987089068
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_loopback.2693810042
Short name T608
Test name
Test status
Simulation time 7363826467 ps
CPU time 10.59 seconds
Started Aug 25 03:48:29 AM UTC 24
Finished Aug 25 03:48:41 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693810042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2693810042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_noise_filter.2396120822
Short name T704
Test name
Test status
Simulation time 73198250600 ps
CPU time 239.72 seconds
Started Aug 25 03:48:20 AM UTC 24
Finished Aug 25 03:52:23 AM UTC 24
Peak memory 209040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396120822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2396120822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_perf.4178282361
Short name T709
Test name
Test status
Simulation time 9355789172 ps
CPU time 236.21 seconds
Started Aug 25 03:48:31 AM UTC 24
Finished Aug 25 03:52:31 AM UTC 24
Peak memory 208432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178282361 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.4178282361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_rx_oversample.3814728555
Short name T603
Test name
Test status
Simulation time 5895475496 ps
CPU time 16.02 seconds
Started Aug 25 03:48:14 AM UTC 24
Finished Aug 25 03:48:31 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814728555 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3814728555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.1279251939
Short name T165
Test name
Test status
Simulation time 71438428416 ps
CPU time 247.37 seconds
Started Aug 25 03:48:24 AM UTC 24
Finished Aug 25 03:52:35 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279251939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1279251939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.3809211557
Short name T614
Test name
Test status
Simulation time 47613320723 ps
CPU time 32.9 seconds
Started Aug 25 03:48:23 AM UTC 24
Finished Aug 25 03:48:57 AM UTC 24
Peak memory 205024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809211557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3809211557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_smoke.2999426682
Short name T605
Test name
Test status
Simulation time 11058293566 ps
CPU time 33.72 seconds
Started Aug 25 03:48:03 AM UTC 24
Finished Aug 25 03:48:38 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999426682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2999426682
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_stress_all.3555887638
Short name T1008
Test name
Test status
Simulation time 328422183790 ps
CPU time 861.61 seconds
Started Aug 25 03:48:39 AM UTC 24
Finished Aug 25 04:03:12 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555887638 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3555887638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.3642306970
Short name T398
Test name
Test status
Simulation time 13253994927 ps
CPU time 49.85 seconds
Started Aug 25 03:48:35 AM UTC 24
Finished Aug 25 03:49:27 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3642306970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all
_with_rand_reset.3642306970
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.1169689310
Short name T601
Test name
Test status
Simulation time 838438197 ps
CPU time 2.72 seconds
Started Aug 25 03:48:25 AM UTC 24
Finished Aug 25 03:48:28 AM UTC 24
Peak memory 207820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169689310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1169689310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/31.uart_tx_rx.3469142265
Short name T408
Test name
Test status
Simulation time 100758404698 ps
CPU time 393.9 seconds
Started Aug 25 03:48:04 AM UTC 24
Finished Aug 25 03:54:44 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469142265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3469142265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/31.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_alert_test.2436240320
Short name T622
Test name
Test status
Simulation time 53671897 ps
CPU time 0.82 seconds
Started Aug 25 03:49:10 AM UTC 24
Finished Aug 25 03:49:11 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436240320 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2436240320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_fifo_full.1390963790
Short name T847
Test name
Test status
Simulation time 153918385156 ps
CPU time 557.33 seconds
Started Aug 25 03:48:43 AM UTC 24
Finished Aug 25 03:58:08 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390963790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1390963790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.2656694726
Short name T682
Test name
Test status
Simulation time 138472807405 ps
CPU time 142.39 seconds
Started Aug 25 03:48:45 AM UTC 24
Finished Aug 25 03:51:10 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656694726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2656694726
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_fifo_reset.2651400541
Short name T623
Test name
Test status
Simulation time 6927675476 ps
CPU time 25.04 seconds
Started Aug 25 03:48:46 AM UTC 24
Finished Aug 25 03:49:12 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651400541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2651400541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_intr.2715109008
Short name T634
Test name
Test status
Simulation time 46750511852 ps
CPU time 39.75 seconds
Started Aug 25 03:48:50 AM UTC 24
Finished Aug 25 03:49:31 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715109008 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2715109008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.3490237313
Short name T877
Test name
Test status
Simulation time 92641826237 ps
CPU time 582.39 seconds
Started Aug 25 03:49:06 AM UTC 24
Finished Aug 25 03:58:57 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490237313 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3490237313
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_loopback.850159651
Short name T617
Test name
Test status
Simulation time 5687611644 ps
CPU time 4.92 seconds
Started Aug 25 03:48:59 AM UTC 24
Finished Aug 25 03:49:05 AM UTC 24
Peak memory 208192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850159651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.uart_loopback.850159651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_noise_filter.234801941
Short name T661
Test name
Test status
Simulation time 197066894373 ps
CPU time 100.78 seconds
Started Aug 25 03:48:54 AM UTC 24
Finished Aug 25 03:50:37 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234801941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.234801941
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_perf.992242882
Short name T800
Test name
Test status
Simulation time 22302992175 ps
CPU time 413.91 seconds
Started Aug 25 03:49:01 AM UTC 24
Finished Aug 25 03:56:01 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992242882 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.992242882
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_rx_oversample.2155136818
Short name T619
Test name
Test status
Simulation time 2208049037 ps
CPU time 18.87 seconds
Started Aug 25 03:48:48 AM UTC 24
Finished Aug 25 03:49:08 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155136818 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2155136818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.820927404
Short name T654
Test name
Test status
Simulation time 26714153779 ps
CPU time 79.13 seconds
Started Aug 25 03:48:58 AM UTC 24
Finished Aug 25 03:50:19 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820927404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.820927404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.2827388923
Short name T615
Test name
Test status
Simulation time 1831915016 ps
CPU time 2.59 seconds
Started Aug 25 03:48:54 AM UTC 24
Finished Aug 25 03:48:58 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827388923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2827388923
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_smoke.19609126
Short name T613
Test name
Test status
Simulation time 6065891228 ps
CPU time 10.8 seconds
Started Aug 25 03:48:41 AM UTC 24
Finished Aug 25 03:48:53 AM UTC 24
Peak memory 208360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19609126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_smoke.19609126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_stress_all.2321248770
Short name T420
Test name
Test status
Simulation time 117064253461 ps
CPU time 164.23 seconds
Started Aug 25 03:49:08 AM UTC 24
Finished Aug 25 03:51:56 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321248770 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2321248770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.2480629539
Short name T642
Test name
Test status
Simulation time 12083930739 ps
CPU time 41.7 seconds
Started Aug 25 03:49:08 AM UTC 24
Finished Aug 25 03:49:52 AM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2480629539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all
_with_rand_reset.2480629539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.2789063918
Short name T624
Test name
Test status
Simulation time 7538762318 ps
CPU time 11.73 seconds
Started Aug 25 03:48:59 AM UTC 24
Finished Aug 25 03:49:12 AM UTC 24
Peak memory 208168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789063918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2789063918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/32.uart_tx_rx.307388566
Short name T620
Test name
Test status
Simulation time 30023919476 ps
CPU time 26.3 seconds
Started Aug 25 03:48:41 AM UTC 24
Finished Aug 25 03:49:09 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307388566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.307388566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/32.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_alert_test.2836492413
Short name T636
Test name
Test status
Simulation time 40831768 ps
CPU time 0.78 seconds
Started Aug 25 03:49:32 AM UTC 24
Finished Aug 25 03:49:34 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836492413 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2836492413
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_fifo_full.723638950
Short name T163
Test name
Test status
Simulation time 96640817193 ps
CPU time 71.2 seconds
Started Aug 25 03:49:12 AM UTC 24
Finished Aug 25 03:50:25 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723638950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.723638950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.2390266016
Short name T429
Test name
Test status
Simulation time 81453767154 ps
CPU time 65.87 seconds
Started Aug 25 03:49:13 AM UTC 24
Finished Aug 25 03:50:21 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390266016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2390266016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_fifo_reset.1312672790
Short name T671
Test name
Test status
Simulation time 136817258879 ps
CPU time 100.53 seconds
Started Aug 25 03:49:13 AM UTC 24
Finished Aug 25 03:50:55 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312672790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1312672790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_intr.430510367
Short name T635
Test name
Test status
Simulation time 8249080673 ps
CPU time 15.99 seconds
Started Aug 25 03:49:15 AM UTC 24
Finished Aug 25 03:49:32 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430510367 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.430510367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.2509395037
Short name T1153
Test name
Test status
Simulation time 85486934370 ps
CPU time 1144.71 seconds
Started Aug 25 03:49:27 AM UTC 24
Finished Aug 25 04:08:46 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509395037 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2509395037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_loopback.3046596891
Short name T643
Test name
Test status
Simulation time 6266878869 ps
CPU time 31.86 seconds
Started Aug 25 03:49:21 AM UTC 24
Finished Aug 25 03:49:55 AM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046596891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3046596891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_noise_filter.4281923232
Short name T655
Test name
Test status
Simulation time 21398090493 ps
CPU time 62.63 seconds
Started Aug 25 03:49:16 AM UTC 24
Finished Aug 25 03:50:20 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281923232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4281923232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_perf.1249508859
Short name T949
Test name
Test status
Simulation time 9321438267 ps
CPU time 719.24 seconds
Started Aug 25 03:49:22 AM UTC 24
Finished Aug 25 04:01:30 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249508859 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1249508859
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_rx_oversample.1725773708
Short name T630
Test name
Test status
Simulation time 6604787338 ps
CPU time 5.57 seconds
Started Aug 25 03:49:14 AM UTC 24
Finished Aug 25 03:49:21 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725773708 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1725773708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.3615021235
Short name T162
Test name
Test status
Simulation time 44636256213 ps
CPU time 39.95 seconds
Started Aug 25 03:49:18 AM UTC 24
Finished Aug 25 03:50:00 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615021235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3615021235
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.2469975999
Short name T631
Test name
Test status
Simulation time 4664439314 ps
CPU time 2.59 seconds
Started Aug 25 03:49:17 AM UTC 24
Finished Aug 25 03:49:21 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469975999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2469975999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_smoke.1268373938
Short name T627
Test name
Test status
Simulation time 492623890 ps
CPU time 3.2 seconds
Started Aug 25 03:49:11 AM UTC 24
Finished Aug 25 03:49:15 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268373938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1268373938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_stress_all.3292584968
Short name T668
Test name
Test status
Simulation time 49234738492 ps
CPU time 75.68 seconds
Started Aug 25 03:49:28 AM UTC 24
Finished Aug 25 03:50:45 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292584968 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3292584968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.3158918886
Short name T656
Test name
Test status
Simulation time 6461326707 ps
CPU time 53.83 seconds
Started Aug 25 03:49:28 AM UTC 24
Finished Aug 25 03:50:23 AM UTC 24
Peak memory 219784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3158918886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all
_with_rand_reset.3158918886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.1608503844
Short name T632
Test name
Test status
Simulation time 1173968424 ps
CPU time 6.78 seconds
Started Aug 25 03:49:18 AM UTC 24
Finished Aug 25 03:49:26 AM UTC 24
Peak memory 207572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608503844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1608503844
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/33.uart_tx_rx.1987210872
Short name T415
Test name
Test status
Simulation time 17936707373 ps
CPU time 59.43 seconds
Started Aug 25 03:49:11 AM UTC 24
Finished Aug 25 03:50:12 AM UTC 24
Peak memory 208600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987210872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1987210872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/33.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_alert_test.339910047
Short name T650
Test name
Test status
Simulation time 18043073 ps
CPU time 0.83 seconds
Started Aug 25 03:50:05 AM UTC 24
Finished Aug 25 03:50:07 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339910047 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.339910047
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_fifo_full.274813880
Short name T651
Test name
Test status
Simulation time 24141367460 ps
CPU time 32.44 seconds
Started Aug 25 03:49:35 AM UTC 24
Finished Aug 25 03:50:09 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274813880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.274813880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.907687466
Short name T1118
Test name
Test status
Simulation time 138170504068 ps
CPU time 1034.5 seconds
Started Aug 25 03:49:36 AM UTC 24
Finished Aug 25 04:07:04 AM UTC 24
Peak memory 212280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907687466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.907687466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_fifo_reset.3754559698
Short name T220
Test name
Test status
Simulation time 53013331105 ps
CPU time 192.55 seconds
Started Aug 25 03:49:36 AM UTC 24
Finished Aug 25 03:52:52 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754559698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3754559698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_intr.18033728
Short name T823
Test name
Test status
Simulation time 133059485525 ps
CPU time 444.42 seconds
Started Aug 25 03:49:43 AM UTC 24
Finished Aug 25 03:57:14 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18033728 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.18033728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.1869220559
Short name T939
Test name
Test status
Simulation time 95210404499 ps
CPU time 664.48 seconds
Started Aug 25 03:50:01 AM UTC 24
Finished Aug 25 04:01:14 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869220559 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1869220559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_loopback.729327025
Short name T652
Test name
Test status
Simulation time 4277735115 ps
CPU time 12.17 seconds
Started Aug 25 03:49:59 AM UTC 24
Finished Aug 25 03:50:12 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729327025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.uart_loopback.729327025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_noise_filter.10709782
Short name T664
Test name
Test status
Simulation time 13288647715 ps
CPU time 51.26 seconds
Started Aug 25 03:49:50 AM UTC 24
Finished Aug 25 03:50:43 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10709782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.10709782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_perf.1582067968
Short name T783
Test name
Test status
Simulation time 21037347720 ps
CPU time 313.06 seconds
Started Aug 25 03:50:00 AM UTC 24
Finished Aug 25 03:55:18 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582067968 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1582067968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_rx_oversample.4019556563
Short name T644
Test name
Test status
Simulation time 6457179317 ps
CPU time 16.06 seconds
Started Aug 25 03:49:39 AM UTC 24
Finished Aug 25 03:49:56 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019556563 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.4019556563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.3539539596
Short name T844
Test name
Test status
Simulation time 123200036612 ps
CPU time 470.45 seconds
Started Aug 25 03:49:56 AM UTC 24
Finished Aug 25 03:57:52 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539539596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3539539596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.950947215
Short name T646
Test name
Test status
Simulation time 1529591291 ps
CPU time 5.2 seconds
Started Aug 25 03:49:53 AM UTC 24
Finished Aug 25 03:49:59 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950947215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.950947215
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_smoke.1202456816
Short name T637
Test name
Test status
Simulation time 703278707 ps
CPU time 1.65 seconds
Started Aug 25 03:49:33 AM UTC 24
Finished Aug 25 03:49:36 AM UTC 24
Peak memory 208052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202456816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1202456816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_stress_all.2224115551
Short name T119
Test name
Test status
Simulation time 8165465140 ps
CPU time 10.76 seconds
Started Aug 25 03:50:03 AM UTC 24
Finished Aug 25 03:50:15 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224115551 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2224115551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.3413558666
Short name T684
Test name
Test status
Simulation time 10306064455 ps
CPU time 75.2 seconds
Started Aug 25 03:50:02 AM UTC 24
Finished Aug 25 03:51:20 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3413558666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all
_with_rand_reset.3413558666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.3234472822
Short name T649
Test name
Test status
Simulation time 852833921 ps
CPU time 4.97 seconds
Started Aug 25 03:49:58 AM UTC 24
Finished Aug 25 03:50:04 AM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234472822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3234472822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/34.uart_tx_rx.2731100425
Short name T726
Test name
Test status
Simulation time 68465011155 ps
CPU time 204.98 seconds
Started Aug 25 03:49:34 AM UTC 24
Finished Aug 25 03:53:02 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731100425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2731100425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/34.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_alert_test.562433819
Short name T663
Test name
Test status
Simulation time 15655345 ps
CPU time 0.85 seconds
Started Aug 25 03:50:38 AM UTC 24
Finished Aug 25 03:50:39 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562433819 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.562433819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_fifo_full.2649889854
Short name T888
Test name
Test status
Simulation time 194584762520 ps
CPU time 550.75 seconds
Started Aug 25 03:50:12 AM UTC 24
Finished Aug 25 03:59:31 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649889854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2649889854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.4283931147
Short name T705
Test name
Test status
Simulation time 83652808504 ps
CPU time 128.79 seconds
Started Aug 25 03:50:13 AM UTC 24
Finished Aug 25 03:52:24 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283931147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.4283931147
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_fifo_reset.2457692432
Short name T672
Test name
Test status
Simulation time 57525764691 ps
CPU time 39.56 seconds
Started Aug 25 03:50:15 AM UTC 24
Finished Aug 25 03:50:56 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457692432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2457692432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_intr.3132308873
Short name T743
Test name
Test status
Simulation time 116164720509 ps
CPU time 188.29 seconds
Started Aug 25 03:50:20 AM UTC 24
Finished Aug 25 03:53:31 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132308873 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3132308873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.217152213
Short name T722
Test name
Test status
Simulation time 84045262390 ps
CPU time 138.73 seconds
Started Aug 25 03:50:34 AM UTC 24
Finished Aug 25 03:52:55 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217152213 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.217152213
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_loopback.4165911867
Short name T662
Test name
Test status
Simulation time 4856296162 ps
CPU time 3.78 seconds
Started Aug 25 03:50:33 AM UTC 24
Finished Aug 25 03:50:38 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165911867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.uart_loopback.4165911867
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_noise_filter.1256960617
Short name T405
Test name
Test status
Simulation time 452662943564 ps
CPU time 136.88 seconds
Started Aug 25 03:50:21 AM UTC 24
Finished Aug 25 03:52:41 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256960617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1256960617
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_perf.641890153
Short name T832
Test name
Test status
Simulation time 10409735439 ps
CPU time 415.55 seconds
Started Aug 25 03:50:33 AM UTC 24
Finished Aug 25 03:57:35 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641890153 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.641890153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_rx_oversample.2090570304
Short name T689
Test name
Test status
Simulation time 7079844306 ps
CPU time 83.77 seconds
Started Aug 25 03:50:17 AM UTC 24
Finished Aug 25 03:51:43 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090570304 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2090570304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.3403757557
Short name T686
Test name
Test status
Simulation time 47666561542 ps
CPU time 66.92 seconds
Started Aug 25 03:50:24 AM UTC 24
Finished Aug 25 03:51:33 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403757557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3403757557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.2101179147
Short name T711
Test name
Test status
Simulation time 39934602845 ps
CPU time 127.96 seconds
Started Aug 25 03:50:22 AM UTC 24
Finished Aug 25 03:52:33 AM UTC 24
Peak memory 205160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101179147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2101179147
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_smoke.2362783270
Short name T653
Test name
Test status
Simulation time 742166574 ps
CPU time 3.04 seconds
Started Aug 25 03:50:08 AM UTC 24
Finished Aug 25 03:50:13 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362783270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2362783270
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_stress_all.1013623965
Short name T1180
Test name
Test status
Simulation time 280530055277 ps
CPU time 1450.55 seconds
Started Aug 25 03:50:36 AM UTC 24
Finished Aug 25 04:15:04 AM UTC 24
Peak memory 212336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013623965 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1013623965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.2626854355
Short name T679
Test name
Test status
Simulation time 17040265534 ps
CPU time 30.85 seconds
Started Aug 25 03:50:34 AM UTC 24
Finished Aug 25 03:51:07 AM UTC 24
Peak memory 219648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2626854355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all
_with_rand_reset.2626854355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.3287157021
Short name T657
Test name
Test status
Simulation time 799264479 ps
CPU time 5.08 seconds
Started Aug 25 03:50:26 AM UTC 24
Finished Aug 25 03:50:32 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287157021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3287157021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/35.uart_tx_rx.779854445
Short name T674
Test name
Test status
Simulation time 65011527040 ps
CPU time 49.9 seconds
Started Aug 25 03:50:09 AM UTC 24
Finished Aug 25 03:51:01 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779854445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.779854445
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/35.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_alert_test.1631106758
Short name T680
Test name
Test status
Simulation time 119492471 ps
CPU time 0.82 seconds
Started Aug 25 03:51:06 AM UTC 24
Finished Aug 25 03:51:08 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631106758 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1631106758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_fifo_full.2234556636
Short name T710
Test name
Test status
Simulation time 242425096877 ps
CPU time 106.63 seconds
Started Aug 25 03:50:44 AM UTC 24
Finished Aug 25 03:52:33 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234556636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2234556636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.37098321
Short name T411
Test name
Test status
Simulation time 150236285226 ps
CPU time 430.33 seconds
Started Aug 25 03:50:45 AM UTC 24
Finished Aug 25 03:58:00 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37098321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.37098321
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_fifo_reset.1181174935
Short name T784
Test name
Test status
Simulation time 89465568572 ps
CPU time 269.89 seconds
Started Aug 25 03:50:45 AM UTC 24
Finished Aug 25 03:55:19 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181174935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1181174935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_intr.405179368
Short name T678
Test name
Test status
Simulation time 18507425917 ps
CPU time 17.76 seconds
Started Aug 25 03:50:46 AM UTC 24
Finished Aug 25 03:51:05 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405179368 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.405179368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.3062054683
Short name T1182
Test name
Test status
Simulation time 139699275457 ps
CPU time 1870.72 seconds
Started Aug 25 03:51:03 AM UTC 24
Finished Aug 25 04:22:38 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062054683 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3062054683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_loopback.289464121
Short name T676
Test name
Test status
Simulation time 1962767408 ps
CPU time 3.94 seconds
Started Aug 25 03:50:58 AM UTC 24
Finished Aug 25 03:51:03 AM UTC 24
Peak memory 207084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289464121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.uart_loopback.289464121
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_noise_filter.2737922462
Short name T741
Test name
Test status
Simulation time 285862154108 ps
CPU time 151.69 seconds
Started Aug 25 03:50:53 AM UTC 24
Finished Aug 25 03:53:27 AM UTC 24
Peak memory 217796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737922462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2737922462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_perf.1760448247
Short name T1150
Test name
Test status
Simulation time 12165874106 ps
CPU time 1041.76 seconds
Started Aug 25 03:51:03 AM UTC 24
Finished Aug 25 04:08:37 AM UTC 24
Peak memory 212436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760448247 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1760448247
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_rx_oversample.2107941556
Short name T694
Test name
Test status
Simulation time 5677259197 ps
CPU time 61.91 seconds
Started Aug 25 03:50:46 AM UTC 24
Finished Aug 25 03:51:50 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107941556 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2107941556
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.1517285343
Short name T419
Test name
Test status
Simulation time 86197873348 ps
CPU time 17.83 seconds
Started Aug 25 03:50:56 AM UTC 24
Finished Aug 25 03:51:15 AM UTC 24
Peak memory 208492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517285343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1517285343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.2407901256
Short name T677
Test name
Test status
Simulation time 4431184737 ps
CPU time 9.7 seconds
Started Aug 25 03:50:54 AM UTC 24
Finished Aug 25 03:51:05 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407901256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2407901256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_smoke.4183029454
Short name T669
Test name
Test status
Simulation time 5759189236 ps
CPU time 12.3 seconds
Started Aug 25 03:50:39 AM UTC 24
Finished Aug 25 03:50:52 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183029454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_smoke.4183029454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_stress_all.2596376124
Short name T928
Test name
Test status
Simulation time 204262028039 ps
CPU time 581.71 seconds
Started Aug 25 03:51:05 AM UTC 24
Finished Aug 25 04:00:55 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596376124 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2596376124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.1729941334
Short name T692
Test name
Test status
Simulation time 2106362918 ps
CPU time 43.81 seconds
Started Aug 25 03:51:04 AM UTC 24
Finished Aug 25 03:51:49 AM UTC 24
Peak memory 217512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1729941334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all
_with_rand_reset.1729941334
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.3296878371
Short name T675
Test name
Test status
Simulation time 793414926 ps
CPU time 4.1 seconds
Started Aug 25 03:50:56 AM UTC 24
Finished Aug 25 03:51:02 AM UTC 24
Peak memory 208412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296878371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3296878371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/36.uart_tx_rx.4160342335
Short name T412
Test name
Test status
Simulation time 125547649334 ps
CPU time 132.66 seconds
Started Aug 25 03:50:41 AM UTC 24
Finished Aug 25 03:52:56 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160342335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.4160342335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/36.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_alert_test.4057548163
Short name T695
Test name
Test status
Simulation time 29522953 ps
CPU time 0.82 seconds
Started Aug 25 03:51:50 AM UTC 24
Finished Aug 25 03:51:52 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057548163 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.4057548163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_fifo_full.2726302039
Short name T1011
Test name
Test status
Simulation time 148629313778 ps
CPU time 716.34 seconds
Started Aug 25 03:51:08 AM UTC 24
Finished Aug 25 04:03:14 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726302039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2726302039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.1578350581
Short name T719
Test name
Test status
Simulation time 74549660924 ps
CPU time 100.4 seconds
Started Aug 25 03:51:10 AM UTC 24
Finished Aug 25 03:52:53 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578350581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1578350581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_fifo_reset.2496769830
Short name T697
Test name
Test status
Simulation time 64236159043 ps
CPU time 45.32 seconds
Started Aug 25 03:51:10 AM UTC 24
Finished Aug 25 03:51:57 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496769830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2496769830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_intr.257264786
Short name T738
Test name
Test status
Simulation time 95072451045 ps
CPU time 117.31 seconds
Started Aug 25 03:51:21 AM UTC 24
Finished Aug 25 03:53:20 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257264786 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.257264786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.562184385
Short name T793
Test name
Test status
Simulation time 81723087776 ps
CPU time 234.52 seconds
Started Aug 25 03:51:43 AM UTC 24
Finished Aug 25 03:55:42 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562184385 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.562184385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_loopback.2625418795
Short name T693
Test name
Test status
Simulation time 2986839869 ps
CPU time 9.13 seconds
Started Aug 25 03:51:39 AM UTC 24
Finished Aug 25 03:51:49 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625418795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2625418795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_noise_filter.18153574
Short name T789
Test name
Test status
Simulation time 67142030792 ps
CPU time 248.09 seconds
Started Aug 25 03:51:21 AM UTC 24
Finished Aug 25 03:55:32 AM UTC 24
Peak memory 209028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18153574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.18153574
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_perf.37510129
Short name T758
Test name
Test status
Simulation time 23228902343 ps
CPU time 142.31 seconds
Started Aug 25 03:51:40 AM UTC 24
Finished Aug 25 03:54:05 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37510129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.37510129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_rx_oversample.3268423805
Short name T683
Test name
Test status
Simulation time 1504789516 ps
CPU time 1.91 seconds
Started Aug 25 03:51:16 AM UTC 24
Finished Aug 25 03:51:19 AM UTC 24
Peak memory 204432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268423805 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3268423805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.84843670
Short name T700
Test name
Test status
Simulation time 44903810638 ps
CPU time 43.82 seconds
Started Aug 25 03:51:27 AM UTC 24
Finished Aug 25 03:52:12 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84843670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.84843670
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.2633360260
Short name T688
Test name
Test status
Simulation time 2923958165 ps
CPU time 12.19 seconds
Started Aug 25 03:51:26 AM UTC 24
Finished Aug 25 03:51:39 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633360260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2633360260
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_smoke.2965620195
Short name T681
Test name
Test status
Simulation time 290228128 ps
CPU time 2 seconds
Started Aug 25 03:51:06 AM UTC 24
Finished Aug 25 03:51:09 AM UTC 24
Peak memory 206380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965620195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2965620195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_stress_all.4075541309
Short name T891
Test name
Test status
Simulation time 473725028362 ps
CPU time 458.31 seconds
Started Aug 25 03:51:48 AM UTC 24
Finished Aug 25 03:59:33 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075541309 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4075541309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.3790481175
Short name T712
Test name
Test status
Simulation time 5472912227 ps
CPU time 47.9 seconds
Started Aug 25 03:51:47 AM UTC 24
Finished Aug 25 03:52:37 AM UTC 24
Peak memory 224132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3790481175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all
_with_rand_reset.3790481175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.2508019548
Short name T687
Test name
Test status
Simulation time 987629711 ps
CPU time 3.03 seconds
Started Aug 25 03:51:34 AM UTC 24
Finished Aug 25 03:51:38 AM UTC 24
Peak memory 207364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508019548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2508019548
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/37.uart_tx_rx.3795676855
Short name T716
Test name
Test status
Simulation time 50223618126 ps
CPU time 96.95 seconds
Started Aug 25 03:51:07 AM UTC 24
Finished Aug 25 03:52:46 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795676855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3795676855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/37.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_alert_test.2153167009
Short name T706
Test name
Test status
Simulation time 42057369 ps
CPU time 0.86 seconds
Started Aug 25 03:52:25 AM UTC 24
Finished Aug 25 03:52:27 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153167009 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2153167009
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_fifo_full.823072052
Short name T1013
Test name
Test status
Simulation time 219616914294 ps
CPU time 676.46 seconds
Started Aug 25 03:51:51 AM UTC 24
Finished Aug 25 04:03:17 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823072052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.823072052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.3769871788
Short name T702
Test name
Test status
Simulation time 9792390520 ps
CPU time 18.41 seconds
Started Aug 25 03:51:54 AM UTC 24
Finished Aug 25 03:52:13 AM UTC 24
Peak memory 208424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769871788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3769871788
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_fifo_reset.2694663683
Short name T182
Test name
Test status
Simulation time 18898960703 ps
CPU time 29.56 seconds
Started Aug 25 03:51:57 AM UTC 24
Finished Aug 25 03:52:28 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694663683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2694663683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_intr.4227414233
Short name T707
Test name
Test status
Simulation time 50712470142 ps
CPU time 29.29 seconds
Started Aug 25 03:51:58 AM UTC 24
Finished Aug 25 03:52:28 AM UTC 24
Peak memory 208736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227414233 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.4227414233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.1982492615
Short name T1181
Test name
Test status
Simulation time 135524274657 ps
CPU time 1349.7 seconds
Started Aug 25 03:52:22 AM UTC 24
Finished Aug 25 04:15:09 AM UTC 24
Peak memory 212208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982492615 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1982492615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_loopback.1585812996
Short name T703
Test name
Test status
Simulation time 2547768484 ps
CPU time 8.41 seconds
Started Aug 25 03:52:13 AM UTC 24
Finished Aug 25 03:52:23 AM UTC 24
Peak memory 205044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585812996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1585812996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_noise_filter.518141939
Short name T782
Test name
Test status
Simulation time 186121624969 ps
CPU time 193.86 seconds
Started Aug 25 03:51:59 AM UTC 24
Finished Aug 25 03:55:16 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518141939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.518141939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_perf.2571325124
Short name T997
Test name
Test status
Simulation time 6780536435 ps
CPU time 630.23 seconds
Started Aug 25 03:52:14 AM UTC 24
Finished Aug 25 04:02:54 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571325124 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2571325124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_rx_oversample.3701678328
Short name T715
Test name
Test status
Simulation time 7053426854 ps
CPU time 45.99 seconds
Started Aug 25 03:51:58 AM UTC 24
Finished Aug 25 03:52:45 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701678328 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3701678328
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.3477402597
Short name T181
Test name
Test status
Simulation time 111141688268 ps
CPU time 312.68 seconds
Started Aug 25 03:52:08 AM UTC 24
Finished Aug 25 03:57:25 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477402597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3477402597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.46381584
Short name T699
Test name
Test status
Simulation time 3527533990 ps
CPU time 3.91 seconds
Started Aug 25 03:52:02 AM UTC 24
Finished Aug 25 03:52:07 AM UTC 24
Peak memory 205236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46381584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.46381584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_smoke.3026133273
Short name T696
Test name
Test status
Simulation time 482404368 ps
CPU time 4.95 seconds
Started Aug 25 03:51:50 AM UTC 24
Finished Aug 25 03:51:57 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026133273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3026133273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_stress_all.2784040610
Short name T752
Test name
Test status
Simulation time 28196068223 ps
CPU time 82.44 seconds
Started Aug 25 03:52:23 AM UTC 24
Finished Aug 25 03:53:48 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784040610 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2784040610
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.460372054
Short name T736
Test name
Test status
Simulation time 4964283815 ps
CPU time 53.27 seconds
Started Aug 25 03:52:23 AM UTC 24
Finished Aug 25 03:53:19 AM UTC 24
Peak memory 217748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=460372054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all_
with_rand_reset.460372054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.719904892
Short name T732
Test name
Test status
Simulation time 6544437528 ps
CPU time 58.21 seconds
Started Aug 25 03:52:13 AM UTC 24
Finished Aug 25 03:53:13 AM UTC 24
Peak memory 208472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719904892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.719904892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/38.uart_tx_rx.1531077384
Short name T714
Test name
Test status
Simulation time 112418638209 ps
CPU time 51.61 seconds
Started Aug 25 03:51:50 AM UTC 24
Finished Aug 25 03:52:44 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531077384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1531077384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/38.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_alert_test.3445647239
Short name T720
Test name
Test status
Simulation time 15300123 ps
CPU time 0.84 seconds
Started Aug 25 03:52:53 AM UTC 24
Finished Aug 25 03:52:55 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445647239 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3445647239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_fifo_full.3545244109
Short name T757
Test name
Test status
Simulation time 30917373871 ps
CPU time 90.57 seconds
Started Aug 25 03:52:30 AM UTC 24
Finished Aug 25 03:54:02 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545244109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3545244109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.4243194760
Short name T178
Test name
Test status
Simulation time 18867868530 ps
CPU time 65.32 seconds
Started Aug 25 03:52:31 AM UTC 24
Finished Aug 25 03:53:38 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243194760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.4243194760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_fifo_reset.2131423301
Short name T778
Test name
Test status
Simulation time 180611846506 ps
CPU time 151.92 seconds
Started Aug 25 03:52:32 AM UTC 24
Finished Aug 25 03:55:07 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131423301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2131423301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_intr.4234865834
Short name T725
Test name
Test status
Simulation time 16955536369 ps
CPU time 26.02 seconds
Started Aug 25 03:52:34 AM UTC 24
Finished Aug 25 03:53:01 AM UTC 24
Peak memory 207640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234865834 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.4234865834
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.2520128609
Short name T906
Test name
Test status
Simulation time 95099390640 ps
CPU time 437.22 seconds
Started Aug 25 03:52:47 AM UTC 24
Finished Aug 25 04:00:10 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520128609 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2520128609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_loopback.2764218347
Short name T728
Test name
Test status
Simulation time 7613673593 ps
CPU time 19.37 seconds
Started Aug 25 03:52:44 AM UTC 24
Finished Aug 25 03:53:05 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764218347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2764218347
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_noise_filter.1660320383
Short name T729
Test name
Test status
Simulation time 9983454681 ps
CPU time 30.94 seconds
Started Aug 25 03:52:35 AM UTC 24
Finished Aug 25 03:53:07 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660320383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1660320383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_perf.1916321280
Short name T1093
Test name
Test status
Simulation time 11559883520 ps
CPU time 781.98 seconds
Started Aug 25 03:52:47 AM UTC 24
Finished Aug 25 04:05:59 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916321280 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1916321280
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_rx_oversample.2425208424
Short name T717
Test name
Test status
Simulation time 3466989766 ps
CPU time 10.86 seconds
Started Aug 25 03:52:34 AM UTC 24
Finished Aug 25 03:52:46 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425208424 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2425208424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.2796322310
Short name T721
Test name
Test status
Simulation time 17234746421 ps
CPU time 13.83 seconds
Started Aug 25 03:52:40 AM UTC 24
Finished Aug 25 03:52:55 AM UTC 24
Peak memory 208076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796322310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2796322310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.2440965123
Short name T713
Test name
Test status
Simulation time 3153590062 ps
CPU time 1.67 seconds
Started Aug 25 03:52:37 AM UTC 24
Finished Aug 25 03:52:40 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440965123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2440965123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_smoke.1546016218
Short name T708
Test name
Test status
Simulation time 91343953 ps
CPU time 1.13 seconds
Started Aug 25 03:52:28 AM UTC 24
Finished Aug 25 03:52:30 AM UTC 24
Peak memory 206428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546016218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1546016218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_stress_all.297120171
Short name T867
Test name
Test status
Simulation time 119397102050 ps
CPU time 345.41 seconds
Started Aug 25 03:52:48 AM UTC 24
Finished Aug 25 03:58:38 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297120171 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.297120171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.299019045
Short name T753
Test name
Test status
Simulation time 6897787131 ps
CPU time 60.37 seconds
Started Aug 25 03:52:47 AM UTC 24
Finished Aug 25 03:53:49 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=299019045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all_
with_rand_reset.299019045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1004184550
Short name T737
Test name
Test status
Simulation time 6444470815 ps
CPU time 35.78 seconds
Started Aug 25 03:52:41 AM UTC 24
Finished Aug 25 03:53:19 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004184550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1004184550
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/39.uart_tx_rx.1324333271
Short name T723
Test name
Test status
Simulation time 27699817367 ps
CPU time 26.07 seconds
Started Aug 25 03:52:29 AM UTC 24
Finished Aug 25 03:52:56 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324333271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1324333271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/39.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_alert_test.1939013477
Short name T45
Test name
Test status
Simulation time 13244889 ps
CPU time 0.81 seconds
Started Aug 25 03:34:52 AM UTC 24
Finished Aug 25 03:34:53 AM UTC 24
Peak memory 204504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939013477 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1939013477
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_fifo_full.1873098723
Short name T354
Test name
Test status
Simulation time 145936706591 ps
CPU time 555.47 seconds
Started Aug 25 03:34:32 AM UTC 24
Finished Aug 25 03:43:54 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873098723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1873098723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.1410632500
Short name T331
Test name
Test status
Simulation time 104823932464 ps
CPU time 99.86 seconds
Started Aug 25 03:34:33 AM UTC 24
Finished Aug 25 03:36:15 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410632500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1410632500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_fifo_reset.438669638
Short name T323
Test name
Test status
Simulation time 79652243448 ps
CPU time 55.59 seconds
Started Aug 25 03:34:33 AM UTC 24
Finished Aug 25 03:35:30 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438669638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.438669638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_intr.3702659662
Short name T109
Test name
Test status
Simulation time 21275713794 ps
CPU time 20.25 seconds
Started Aug 25 03:34:36 AM UTC 24
Finished Aug 25 03:34:57 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702659662 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3702659662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_loopback.3657772914
Short name T43
Test name
Test status
Simulation time 2711258991 ps
CPU time 5.6 seconds
Started Aug 25 03:34:44 AM UTC 24
Finished Aug 25 03:34:51 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657772914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3657772914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_noise_filter.880199476
Short name T288
Test name
Test status
Simulation time 23983794644 ps
CPU time 74.23 seconds
Started Aug 25 03:34:37 AM UTC 24
Finished Aug 25 03:35:53 AM UTC 24
Peak memory 207672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880199476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.880199476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_perf.851651197
Short name T308
Test name
Test status
Simulation time 18152279756 ps
CPU time 77.41 seconds
Started Aug 25 03:34:45 AM UTC 24
Finished Aug 25 03:36:05 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851651197 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.851651197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_rx_oversample.2724195678
Short name T430
Test name
Test status
Simulation time 5420709598 ps
CPU time 6.91 seconds
Started Aug 25 03:34:34 AM UTC 24
Finished Aug 25 03:34:42 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724195678 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2724195678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.3545689373
Short name T111
Test name
Test status
Simulation time 40774320427 ps
CPU time 43.91 seconds
Started Aug 25 03:34:41 AM UTC 24
Finished Aug 25 03:35:27 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545689373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3545689373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.1413984225
Short name T346
Test name
Test status
Simulation time 81109398990 ps
CPU time 219.16 seconds
Started Aug 25 03:34:37 AM UTC 24
Finished Aug 25 03:38:19 AM UTC 24
Peak memory 205232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413984225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1413984225
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_sec_cm.1808548647
Short name T44
Test name
Test status
Simulation time 65514474 ps
CPU time 1.33 seconds
Started Aug 25 03:34:51 AM UTC 24
Finished Aug 25 03:34:53 AM UTC 24
Peak memory 240196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808548647 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1808548647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_smoke.2925068525
Short name T318
Test name
Test status
Simulation time 722050762 ps
CPU time 3.58 seconds
Started Aug 25 03:34:31 AM UTC 24
Finished Aug 25 03:34:35 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925068525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2925068525
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.3410840677
Short name T35
Test name
Test status
Simulation time 2333146761 ps
CPU time 37.23 seconds
Started Aug 25 03:34:49 AM UTC 24
Finished Aug 25 03:35:28 AM UTC 24
Peak memory 217792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3410840677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_
with_rand_reset.3410840677
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.632024926
Short name T42
Test name
Test status
Simulation time 922358858 ps
CPU time 5.64 seconds
Started Aug 25 03:34:42 AM UTC 24
Finished Aug 25 03:34:49 AM UTC 24
Peak memory 208128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632024926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.632024926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/4.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_alert_test.2526269879
Short name T731
Test name
Test status
Simulation time 34378755 ps
CPU time 0.81 seconds
Started Aug 25 03:53:09 AM UTC 24
Finished Aug 25 03:53:12 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526269879 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2526269879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_fifo_full.2462960176
Short name T775
Test name
Test status
Simulation time 58929895429 ps
CPU time 117.77 seconds
Started Aug 25 03:52:56 AM UTC 24
Finished Aug 25 03:54:56 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462960176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2462960176
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.2523904292
Short name T833
Test name
Test status
Simulation time 157802981513 ps
CPU time 277.29 seconds
Started Aug 25 03:52:56 AM UTC 24
Finished Aug 25 03:57:38 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523904292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2523904292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_fifo_reset.2678900361
Short name T799
Test name
Test status
Simulation time 105344062000 ps
CPU time 177.07 seconds
Started Aug 25 03:52:56 AM UTC 24
Finished Aug 25 03:55:56 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678900361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2678900361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_intr.1401325912
Short name T770
Test name
Test status
Simulation time 39155508290 ps
CPU time 98.52 seconds
Started Aug 25 03:52:57 AM UTC 24
Finished Aug 25 03:54:38 AM UTC 24
Peak memory 208572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401325912 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1401325912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.950288849
Short name T994
Test name
Test status
Simulation time 86781246392 ps
CPU time 575.83 seconds
Started Aug 25 03:53:06 AM UTC 24
Finished Aug 25 04:02:50 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950288849 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.950288849
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_loopback.604169424
Short name T730
Test name
Test status
Simulation time 2654515221 ps
CPU time 4.47 seconds
Started Aug 25 03:53:03 AM UTC 24
Finished Aug 25 03:53:08 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604169424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.uart_loopback.604169424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_noise_filter.593784431
Short name T779
Test name
Test status
Simulation time 63850552267 ps
CPU time 128.76 seconds
Started Aug 25 03:52:57 AM UTC 24
Finished Aug 25 03:55:09 AM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593784431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.593784431
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_perf.492563982
Short name T916
Test name
Test status
Simulation time 24970637003 ps
CPU time 443.17 seconds
Started Aug 25 03:53:04 AM UTC 24
Finished Aug 25 04:00:33 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492563982 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.492563982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_rx_oversample.3937822323
Short name T727
Test name
Test status
Simulation time 2138468368 ps
CPU time 5.58 seconds
Started Aug 25 03:52:56 AM UTC 24
Finished Aug 25 03:53:03 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937822323 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3937822323
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.1736296101
Short name T755
Test name
Test status
Simulation time 132842505062 ps
CPU time 51.92 seconds
Started Aug 25 03:53:02 AM UTC 24
Finished Aug 25 03:53:55 AM UTC 24
Peak memory 208520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736296101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1736296101
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.1277362302
Short name T735
Test name
Test status
Simulation time 5834412245 ps
CPU time 16.78 seconds
Started Aug 25 03:52:59 AM UTC 24
Finished Aug 25 03:53:18 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277362302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1277362302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_smoke.380852916
Short name T724
Test name
Test status
Simulation time 884627292 ps
CPU time 5.81 seconds
Started Aug 25 03:52:54 AM UTC 24
Finished Aug 25 03:53:01 AM UTC 24
Peak memory 208080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380852916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 40.uart_smoke.380852916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_stress_all.3718997224
Short name T1126
Test name
Test status
Simulation time 280283130626 ps
CPU time 841.49 seconds
Started Aug 25 03:53:09 AM UTC 24
Finished Aug 25 04:07:21 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718997224 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3718997224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.16779132
Short name T754
Test name
Test status
Simulation time 3022671479 ps
CPU time 41.85 seconds
Started Aug 25 03:53:08 AM UTC 24
Finished Aug 25 03:53:51 AM UTC 24
Peak memory 217916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=16779132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all_w
ith_rand_reset.16779132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.3754626061
Short name T357
Test name
Test status
Simulation time 1035368729 ps
CPU time 5.16 seconds
Started Aug 25 03:53:03 AM UTC 24
Finished Aug 25 03:53:09 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754626061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3754626061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/40.uart_tx_rx.1801138239
Short name T403
Test name
Test status
Simulation time 29778730840 ps
CPU time 23.34 seconds
Started Aug 25 03:52:55 AM UTC 24
Finished Aug 25 03:53:20 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801138239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1801138239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/40.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_alert_test.2571344022
Short name T748
Test name
Test status
Simulation time 14620520 ps
CPU time 0.88 seconds
Started Aug 25 03:53:35 AM UTC 24
Finished Aug 25 03:53:37 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571344022 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2571344022
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_fifo_full.3026695956
Short name T815
Test name
Test status
Simulation time 346326337586 ps
CPU time 219.69 seconds
Started Aug 25 03:53:14 AM UTC 24
Finished Aug 25 03:56:58 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026695956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3026695956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.2415552504
Short name T759
Test name
Test status
Simulation time 39641194975 ps
CPU time 48.54 seconds
Started Aug 25 03:53:15 AM UTC 24
Finished Aug 25 03:54:06 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415552504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2415552504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_fifo_reset.3525346661
Short name T749
Test name
Test status
Simulation time 38207851596 ps
CPU time 25.07 seconds
Started Aug 25 03:53:15 AM UTC 24
Finished Aug 25 03:53:42 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525346661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3525346661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_intr.2029550248
Short name T761
Test name
Test status
Simulation time 68411855834 ps
CPU time 47.95 seconds
Started Aug 25 03:53:20 AM UTC 24
Finished Aug 25 03:54:09 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029550248 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2029550248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.1533537286
Short name T918
Test name
Test status
Simulation time 153312194061 ps
CPU time 418.19 seconds
Started Aug 25 03:53:30 AM UTC 24
Finished Aug 25 04:00:34 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533537286 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1533537286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_loopback.1549320474
Short name T746
Test name
Test status
Simulation time 2515889711 ps
CPU time 8.93 seconds
Started Aug 25 03:53:25 AM UTC 24
Finished Aug 25 03:53:35 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549320474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1549320474
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_noise_filter.91796023
Short name T798
Test name
Test status
Simulation time 108623235333 ps
CPU time 151.95 seconds
Started Aug 25 03:53:20 AM UTC 24
Finished Aug 25 03:55:54 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91796023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.91796023
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_perf.1096136417
Short name T982
Test name
Test status
Simulation time 15981851768 ps
CPU time 529.35 seconds
Started Aug 25 03:53:28 AM UTC 24
Finished Aug 25 04:02:25 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096136417 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1096136417
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_rx_oversample.671625747
Short name T747
Test name
Test status
Simulation time 5273065505 ps
CPU time 15.39 seconds
Started Aug 25 03:53:19 AM UTC 24
Finished Aug 25 03:53:35 AM UTC 24
Peak memory 208252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671625747 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.671625747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.2674568354
Short name T777
Test name
Test status
Simulation time 33030184573 ps
CPU time 97.55 seconds
Started Aug 25 03:53:21 AM UTC 24
Finished Aug 25 03:55:01 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674568354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2674568354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.1236706761
Short name T740
Test name
Test status
Simulation time 1898715532 ps
CPU time 2.23 seconds
Started Aug 25 03:53:21 AM UTC 24
Finished Aug 25 03:53:24 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236706761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1236706761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_smoke.4186374074
Short name T734
Test name
Test status
Simulation time 673594463 ps
CPU time 2.87 seconds
Started Aug 25 03:53:10 AM UTC 24
Finished Aug 25 03:53:14 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186374074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.4186374074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_stress_all.2869229819
Short name T1183
Test name
Test status
Simulation time 225296693803 ps
CPU time 2159.49 seconds
Started Aug 25 03:53:33 AM UTC 24
Finished Aug 25 04:30:00 AM UTC 24
Peak memory 212400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869229819 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2869229819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.2421791508
Short name T785
Test name
Test status
Simulation time 4076531022 ps
CPU time 107.84 seconds
Started Aug 25 03:53:32 AM UTC 24
Finished Aug 25 03:55:23 AM UTC 24
Peak memory 217868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2421791508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all
_with_rand_reset.2421791508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.3310877469
Short name T742
Test name
Test status
Simulation time 1008706639 ps
CPU time 5.91 seconds
Started Aug 25 03:53:22 AM UTC 24
Finished Aug 25 03:53:29 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310877469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3310877469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/41.uart_tx_rx.2249784485
Short name T811
Test name
Test status
Simulation time 62007842413 ps
CPU time 198.59 seconds
Started Aug 25 03:53:12 AM UTC 24
Finished Aug 25 03:56:34 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249784485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2249784485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/41.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_alert_test.1593990585
Short name T762
Test name
Test status
Simulation time 33845842 ps
CPU time 0.83 seconds
Started Aug 25 03:54:08 AM UTC 24
Finished Aug 25 03:54:10 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593990585 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1593990585
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_fifo_full.4127466425
Short name T804
Test name
Test status
Simulation time 95890219905 ps
CPU time 153.61 seconds
Started Aug 25 03:53:37 AM UTC 24
Finished Aug 25 03:56:13 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127466425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.4127466425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.2363754455
Short name T773
Test name
Test status
Simulation time 51669097796 ps
CPU time 70.15 seconds
Started Aug 25 03:53:38 AM UTC 24
Finished Aug 25 03:54:49 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363754455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2363754455
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_fifo_reset.3051893918
Short name T423
Test name
Test status
Simulation time 74495243811 ps
CPU time 279.27 seconds
Started Aug 25 03:53:39 AM UTC 24
Finished Aug 25 03:58:23 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051893918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3051893918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_intr.3619529543
Short name T1159
Test name
Test status
Simulation time 405226565518 ps
CPU time 917.84 seconds
Started Aug 25 03:53:44 AM UTC 24
Finished Aug 25 04:09:12 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619529543 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3619529543
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.203509310
Short name T862
Test name
Test status
Simulation time 237298578434 ps
CPU time 264.52 seconds
Started Aug 25 03:54:03 AM UTC 24
Finished Aug 25 03:58:32 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203509310 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.203509310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_loopback.2075643935
Short name T760
Test name
Test status
Simulation time 2120159484 ps
CPU time 9.07 seconds
Started Aug 25 03:53:56 AM UTC 24
Finished Aug 25 03:54:07 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075643935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2075643935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_noise_filter.1630162232
Short name T768
Test name
Test status
Simulation time 58710126244 ps
CPU time 44.68 seconds
Started Aug 25 03:53:48 AM UTC 24
Finished Aug 25 03:54:34 AM UTC 24
Peak memory 209036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630162232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1630162232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_perf.4091602034
Short name T913
Test name
Test status
Simulation time 16314882748 ps
CPU time 383.96 seconds
Started Aug 25 03:53:56 AM UTC 24
Finished Aug 25 04:00:26 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091602034 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.4091602034
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_rx_oversample.661239617
Short name T764
Test name
Test status
Simulation time 2955510602 ps
CPU time 29.49 seconds
Started Aug 25 03:53:43 AM UTC 24
Finished Aug 25 03:54:14 AM UTC 24
Peak memory 207936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661239617 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.661239617
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.2638180032
Short name T179
Test name
Test status
Simulation time 229939791552 ps
CPU time 268.57 seconds
Started Aug 25 03:53:50 AM UTC 24
Finished Aug 25 03:58:23 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638180032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2638180032
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.4058578272
Short name T767
Test name
Test status
Simulation time 46870133852 ps
CPU time 37.19 seconds
Started Aug 25 03:53:49 AM UTC 24
Finished Aug 25 03:54:28 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058578272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4058578272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_smoke.469128872
Short name T750
Test name
Test status
Simulation time 885557273 ps
CPU time 6.22 seconds
Started Aug 25 03:53:35 AM UTC 24
Finished Aug 25 03:53:43 AM UTC 24
Peak memory 207932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469128872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 42.uart_smoke.469128872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_stress_all.206045403
Short name T812
Test name
Test status
Simulation time 38685927617 ps
CPU time 156.14 seconds
Started Aug 25 03:54:07 AM UTC 24
Finished Aug 25 03:56:46 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206045403 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.206045403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.302436865
Short name T212
Test name
Test status
Simulation time 5857025837 ps
CPU time 24.74 seconds
Started Aug 25 03:54:07 AM UTC 24
Finished Aug 25 03:54:33 AM UTC 24
Peak memory 217592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=302436865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all_
with_rand_reset.302436865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.3851948707
Short name T756
Test name
Test status
Simulation time 719041411 ps
CPU time 2.67 seconds
Started Aug 25 03:53:52 AM UTC 24
Finished Aug 25 03:53:56 AM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851948707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3851948707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/42.uart_tx_rx.3257875842
Short name T766
Test name
Test status
Simulation time 59444248199 ps
CPU time 44.91 seconds
Started Aug 25 03:53:35 AM UTC 24
Finished Aug 25 03:54:22 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257875842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3257875842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/42.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_alert_test.1415756717
Short name T776
Test name
Test status
Simulation time 35271144 ps
CPU time 0.83 seconds
Started Aug 25 03:54:57 AM UTC 24
Finished Aug 25 03:54:59 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415756717 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1415756717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_fifo_full.1906580408
Short name T895
Test name
Test status
Simulation time 93411848507 ps
CPU time 319.82 seconds
Started Aug 25 03:54:14 AM UTC 24
Finished Aug 25 03:59:38 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906580408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1906580408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.3275661420
Short name T810
Test name
Test status
Simulation time 162274495343 ps
CPU time 136.71 seconds
Started Aug 25 03:54:15 AM UTC 24
Finished Aug 25 03:56:34 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275661420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3275661420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_fifo_reset.2102737221
Short name T409
Test name
Test status
Simulation time 47221904335 ps
CPU time 42.33 seconds
Started Aug 25 03:54:17 AM UTC 24
Finished Aug 25 03:55:01 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102737221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2102737221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_intr.823352850
Short name T821
Test name
Test status
Simulation time 225150370872 ps
CPU time 161.07 seconds
Started Aug 25 03:54:28 AM UTC 24
Finished Aug 25 03:57:12 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823352850 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.823352850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.1608579440
Short name T1023
Test name
Test status
Simulation time 98738485565 ps
CPU time 508.8 seconds
Started Aug 25 03:54:50 AM UTC 24
Finished Aug 25 04:03:26 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608579440 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1608579440
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_loopback.3377604532
Short name T774
Test name
Test status
Simulation time 3757033716 ps
CPU time 8.3 seconds
Started Aug 25 03:54:43 AM UTC 24
Finished Aug 25 03:54:52 AM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377604532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3377604532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_noise_filter.2703420316
Short name T865
Test name
Test status
Simulation time 64067325317 ps
CPU time 237.41 seconds
Started Aug 25 03:54:33 AM UTC 24
Finished Aug 25 03:58:35 AM UTC 24
Peak memory 208972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703420316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2703420316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_perf.243012890
Short name T1165
Test name
Test status
Simulation time 11032428207 ps
CPU time 884.36 seconds
Started Aug 25 03:54:45 AM UTC 24
Finished Aug 25 04:09:41 AM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243012890 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.243012890
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_rx_oversample.1026034299
Short name T769
Test name
Test status
Simulation time 3409582883 ps
CPU time 10.53 seconds
Started Aug 25 03:54:23 AM UTC 24
Finished Aug 25 03:54:35 AM UTC 24
Peak memory 207856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026034299 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1026034299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.1050310497
Short name T818
Test name
Test status
Simulation time 53052390899 ps
CPU time 146.25 seconds
Started Aug 25 03:54:35 AM UTC 24
Finished Aug 25 03:57:05 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050310497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1050310497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.2813462474
Short name T795
Test name
Test status
Simulation time 38298834201 ps
CPU time 72.64 seconds
Started Aug 25 03:54:35 AM UTC 24
Finished Aug 25 03:55:50 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813462474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2813462474
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_smoke.621129810
Short name T763
Test name
Test status
Simulation time 284912596 ps
CPU time 2.4 seconds
Started Aug 25 03:54:10 AM UTC 24
Finished Aug 25 03:54:13 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621129810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.uart_smoke.621129810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_stress_all.4092454388
Short name T1024
Test name
Test status
Simulation time 223005210474 ps
CPU time 515.09 seconds
Started Aug 25 03:54:53 AM UTC 24
Finished Aug 25 04:03:35 AM UTC 24
Peak memory 217804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092454388 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.4092454388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.3290450842
Short name T780
Test name
Test status
Simulation time 1310526394 ps
CPU time 21.54 seconds
Started Aug 25 03:54:50 AM UTC 24
Finished Aug 25 03:55:13 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3290450842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all
_with_rand_reset.3290450842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.2046010339
Short name T771
Test name
Test status
Simulation time 1192975626 ps
CPU time 2.53 seconds
Started Aug 25 03:54:39 AM UTC 24
Finished Aug 25 03:54:42 AM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046010339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2046010339
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/43.uart_tx_rx.1712072052
Short name T781
Test name
Test status
Simulation time 39028770733 ps
CPU time 62.43 seconds
Started Aug 25 03:54:11 AM UTC 24
Finished Aug 25 03:55:15 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712072052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1712072052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/43.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_alert_test.2757802544
Short name T791
Test name
Test status
Simulation time 40427253 ps
CPU time 0.82 seconds
Started Aug 25 03:55:34 AM UTC 24
Finished Aug 25 03:55:36 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757802544 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2757802544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_fifo_full.690758640
Short name T806
Test name
Test status
Simulation time 128073688952 ps
CPU time 81.97 seconds
Started Aug 25 03:55:01 AM UTC 24
Finished Aug 25 03:56:25 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690758640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.690758640
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.424488867
Short name T792
Test name
Test status
Simulation time 51676816041 ps
CPU time 30.17 seconds
Started Aug 25 03:55:07 AM UTC 24
Finished Aug 25 03:55:39 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424488867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.424488867
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_fifo_reset.710261216
Short name T813
Test name
Test status
Simulation time 32576524920 ps
CPU time 99.72 seconds
Started Aug 25 03:55:09 AM UTC 24
Finished Aug 25 03:56:51 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710261216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.710261216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_intr.3659655963
Short name T797
Test name
Test status
Simulation time 39759163111 ps
CPU time 35.49 seconds
Started Aug 25 03:55:16 AM UTC 24
Finished Aug 25 03:55:52 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659655963 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3659655963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.3147600376
Short name T1174
Test name
Test status
Simulation time 117030548692 ps
CPU time 895.95 seconds
Started Aug 25 03:55:28 AM UTC 24
Finished Aug 25 04:10:36 AM UTC 24
Peak memory 212144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147600376 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3147600376
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_loopback.561059057
Short name T787
Test name
Test status
Simulation time 65924914 ps
CPU time 1.07 seconds
Started Aug 25 03:55:25 AM UTC 24
Finished Aug 25 03:55:27 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561059057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.uart_loopback.561059057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_noise_filter.2728385364
Short name T957
Test name
Test status
Simulation time 194238366046 ps
CPU time 382.76 seconds
Started Aug 25 03:55:17 AM UTC 24
Finished Aug 25 04:01:45 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728385364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2728385364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_perf.1097548463
Short name T964
Test name
Test status
Simulation time 16713092002 ps
CPU time 384.07 seconds
Started Aug 25 03:55:28 AM UTC 24
Finished Aug 25 04:01:58 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097548463 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1097548463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_rx_oversample.4038767237
Short name T790
Test name
Test status
Simulation time 3223628221 ps
CPU time 18.51 seconds
Started Aug 25 03:55:14 AM UTC 24
Finished Aug 25 03:55:33 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038767237 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.4038767237
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.3089374997
Short name T180
Test name
Test status
Simulation time 31059512910 ps
CPU time 57.17 seconds
Started Aug 25 03:55:20 AM UTC 24
Finished Aug 25 03:56:19 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089374997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3089374997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.3937554091
Short name T826
Test name
Test status
Simulation time 47485644155 ps
CPU time 124.01 seconds
Started Aug 25 03:55:19 AM UTC 24
Finished Aug 25 03:57:25 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937554091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3937554091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_smoke.1079247600
Short name T788
Test name
Test status
Simulation time 6213273166 ps
CPU time 26.12 seconds
Started Aug 25 03:55:00 AM UTC 24
Finished Aug 25 03:55:28 AM UTC 24
Peak memory 208460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079247600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1079247600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_stress_all.794189308
Short name T1129
Test name
Test status
Simulation time 254567692758 ps
CPU time 706.57 seconds
Started Aug 25 03:55:33 AM UTC 24
Finished Aug 25 04:07:29 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794189308 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.794189308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.1411421618
Short name T796
Test name
Test status
Simulation time 1993919017 ps
CPU time 22.71 seconds
Started Aug 25 03:55:28 AM UTC 24
Finished Aug 25 03:55:52 AM UTC 24
Peak memory 217796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1411421618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all
_with_rand_reset.1411421618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.843709459
Short name T786
Test name
Test status
Simulation time 492051227 ps
CPU time 3.17 seconds
Started Aug 25 03:55:23 AM UTC 24
Finished Aug 25 03:55:27 AM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843709459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.843709459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/44.uart_tx_rx.973643911
Short name T802
Test name
Test status
Simulation time 32742192040 ps
CPU time 60.96 seconds
Started Aug 25 03:55:01 AM UTC 24
Finished Aug 25 03:56:04 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973643911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.973643911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/44.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_alert_test.3172810958
Short name T807
Test name
Test status
Simulation time 47174571 ps
CPU time 0.81 seconds
Started Aug 25 03:56:26 AM UTC 24
Finished Aug 25 03:56:28 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172810958 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3172810958
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_fifo_full.993512746
Short name T825
Test name
Test status
Simulation time 60647498086 ps
CPU time 97.54 seconds
Started Aug 25 03:55:43 AM UTC 24
Finished Aug 25 03:57:22 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993512746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.993512746
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.3280328404
Short name T1060
Test name
Test status
Simulation time 185103399974 ps
CPU time 532.52 seconds
Started Aug 25 03:55:46 AM UTC 24
Finished Aug 25 04:04:46 AM UTC 24
Peak memory 208580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280328404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3280328404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_fifo_reset.3669389759
Short name T809
Test name
Test status
Simulation time 13733321273 ps
CPU time 41.45 seconds
Started Aug 25 03:55:51 AM UTC 24
Finished Aug 25 03:56:34 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669389759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3669389759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_intr.3457446997
Short name T1124
Test name
Test status
Simulation time 216560445296 ps
CPU time 674.03 seconds
Started Aug 25 03:55:53 AM UTC 24
Finished Aug 25 04:07:15 AM UTC 24
Peak memory 208564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457446997 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3457446997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.246790131
Short name T1005
Test name
Test status
Simulation time 291099991916 ps
CPU time 403.7 seconds
Started Aug 25 03:56:14 AM UTC 24
Finished Aug 25 04:03:04 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246790131 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.246790131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_loopback.3103357280
Short name T805
Test name
Test status
Simulation time 4554824254 ps
CPU time 8.06 seconds
Started Aug 25 03:56:04 AM UTC 24
Finished Aug 25 03:56:14 AM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103357280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3103357280
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_noise_filter.472629690
Short name T901
Test name
Test status
Simulation time 225794057608 ps
CPU time 236.9 seconds
Started Aug 25 03:55:55 AM UTC 24
Finished Aug 25 03:59:56 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472629690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.472629690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_perf.1026024632
Short name T896
Test name
Test status
Simulation time 17792235594 ps
CPU time 202.4 seconds
Started Aug 25 03:56:13 AM UTC 24
Finished Aug 25 03:59:38 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026024632 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1026024632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_rx_oversample.2578432572
Short name T817
Test name
Test status
Simulation time 5240567272 ps
CPU time 67.57 seconds
Started Aug 25 03:55:53 AM UTC 24
Finished Aug 25 03:57:02 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578432572 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2578432572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.3820792642
Short name T1069
Test name
Test status
Simulation time 202755804803 ps
CPU time 540.1 seconds
Started Aug 25 03:56:01 AM UTC 24
Finished Aug 25 04:05:08 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820792642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3820792642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.4002947613
Short name T801
Test name
Test status
Simulation time 3712689033 ps
CPU time 5.49 seconds
Started Aug 25 03:55:57 AM UTC 24
Finished Aug 25 03:56:04 AM UTC 24
Peak memory 205028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002947613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4002947613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_smoke.3528305332
Short name T794
Test name
Test status
Simulation time 717208294 ps
CPU time 6.36 seconds
Started Aug 25 03:55:37 AM UTC 24
Finished Aug 25 03:55:45 AM UTC 24
Peak memory 208092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528305332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3528305332
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_stress_all.422280638
Short name T988
Test name
Test status
Simulation time 400616888545 ps
CPU time 373.94 seconds
Started Aug 25 03:56:20 AM UTC 24
Finished Aug 25 04:02:39 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422280638 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.422280638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.1108439630
Short name T816
Test name
Test status
Simulation time 9936679600 ps
CPU time 45.78 seconds
Started Aug 25 03:56:15 AM UTC 24
Finished Aug 25 03:57:02 AM UTC 24
Peak memory 225252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1108439630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all
_with_rand_reset.1108439630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.1560040344
Short name T803
Test name
Test status
Simulation time 756873888 ps
CPU time 5.66 seconds
Started Aug 25 03:56:04 AM UTC 24
Finished Aug 25 03:56:11 AM UTC 24
Peak memory 208016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560040344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1560040344
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/45.uart_tx_rx.2388533828
Short name T839
Test name
Test status
Simulation time 81269138505 ps
CPU time 119.48 seconds
Started Aug 25 03:55:40 AM UTC 24
Finished Aug 25 03:57:42 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388533828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2388533828
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/45.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_alert_test.2723094286
Short name T824
Test name
Test status
Simulation time 18012843 ps
CPU time 0.83 seconds
Started Aug 25 03:57:16 AM UTC 24
Finished Aug 25 03:57:18 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723094286 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2723094286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_fifo_full.2227847066
Short name T843
Test name
Test status
Simulation time 76385712583 ps
CPU time 76.07 seconds
Started Aug 25 03:56:34 AM UTC 24
Finished Aug 25 03:57:52 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227847066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2227847066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.1445043700
Short name T834
Test name
Test status
Simulation time 35187214755 ps
CPU time 60.55 seconds
Started Aug 25 03:56:35 AM UTC 24
Finished Aug 25 03:57:38 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445043700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1445043700
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_fifo_reset.2648354620
Short name T907
Test name
Test status
Simulation time 56933772516 ps
CPU time 211.45 seconds
Started Aug 25 03:56:35 AM UTC 24
Finished Aug 25 04:00:10 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648354620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2648354620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_intr.3975845491
Short name T1161
Test name
Test status
Simulation time 273686146575 ps
CPU time 738.28 seconds
Started Aug 25 03:56:52 AM UTC 24
Finished Aug 25 04:09:18 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975845491 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3975845491
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.3162946699
Short name T894
Test name
Test status
Simulation time 254563121801 ps
CPU time 144.6 seconds
Started Aug 25 03:57:10 AM UTC 24
Finished Aug 25 03:59:38 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162946699 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3162946699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_loopback.2551249510
Short name T820
Test name
Test status
Simulation time 585391289 ps
CPU time 2.72 seconds
Started Aug 25 03:57:06 AM UTC 24
Finished Aug 25 03:57:10 AM UTC 24
Peak memory 204972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551249510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2551249510
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_noise_filter.2553468651
Short name T837
Test name
Test status
Simulation time 24969907307 ps
CPU time 39.83 seconds
Started Aug 25 03:56:58 AM UTC 24
Finished Aug 25 03:57:39 AM UTC 24
Peak memory 207564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553468651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2553468651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_perf.3419825686
Short name T920
Test name
Test status
Simulation time 4179155646 ps
CPU time 204.88 seconds
Started Aug 25 03:57:08 AM UTC 24
Finished Aug 25 04:00:37 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419825686 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3419825686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_rx_oversample.2369429173
Short name T830
Test name
Test status
Simulation time 3826715156 ps
CPU time 42.77 seconds
Started Aug 25 03:56:46 AM UTC 24
Finished Aug 25 03:57:31 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369429173 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2369429173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.1582205505
Short name T173
Test name
Test status
Simulation time 37121041633 ps
CPU time 28.96 seconds
Started Aug 25 03:57:04 AM UTC 24
Finished Aug 25 03:57:34 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582205505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1582205505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.3034302326
Short name T819
Test name
Test status
Simulation time 1702626832 ps
CPU time 6.71 seconds
Started Aug 25 03:57:00 AM UTC 24
Finished Aug 25 03:57:08 AM UTC 24
Peak memory 205160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034302326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3034302326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_smoke.918946741
Short name T808
Test name
Test status
Simulation time 670124955 ps
CPU time 2.45 seconds
Started Aug 25 03:56:29 AM UTC 24
Finished Aug 25 03:56:32 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918946741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.uart_smoke.918946741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_stress_all.2190108376
Short name T909
Test name
Test status
Simulation time 169630378538 ps
CPU time 181.43 seconds
Started Aug 25 03:57:14 AM UTC 24
Finished Aug 25 04:00:19 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190108376 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2190108376
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.960529095
Short name T828
Test name
Test status
Simulation time 842026071 ps
CPU time 14.16 seconds
Started Aug 25 03:57:14 AM UTC 24
Finished Aug 25 03:57:30 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=960529095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all_
with_rand_reset.960529095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.2175798185
Short name T822
Test name
Test status
Simulation time 1228273290 ps
CPU time 8.03 seconds
Started Aug 25 03:57:04 AM UTC 24
Finished Aug 25 03:57:13 AM UTC 24
Peak memory 207688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175798185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2175798185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/46.uart_tx_rx.1010467057
Short name T866
Test name
Test status
Simulation time 50645248255 ps
CPU time 121.08 seconds
Started Aug 25 03:56:33 AM UTC 24
Finished Aug 25 03:58:37 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010467057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1010467057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/46.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_alert_test.2665338422
Short name T838
Test name
Test status
Simulation time 12008892 ps
CPU time 0.83 seconds
Started Aug 25 03:57:40 AM UTC 24
Finished Aug 25 03:57:42 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665338422 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2665338422
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_fifo_full.2253225002
Short name T1157
Test name
Test status
Simulation time 189028568094 ps
CPU time 692.1 seconds
Started Aug 25 03:57:26 AM UTC 24
Finished Aug 25 04:09:06 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253225002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2253225002
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.3583666160
Short name T872
Test name
Test status
Simulation time 189671939340 ps
CPU time 74.01 seconds
Started Aug 25 03:57:26 AM UTC 24
Finished Aug 25 03:58:42 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583666160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3583666160
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_fifo_reset.1897949437
Short name T853
Test name
Test status
Simulation time 26796147606 ps
CPU time 43.53 seconds
Started Aug 25 03:57:28 AM UTC 24
Finished Aug 25 03:58:13 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897949437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1897949437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_intr.2970432902
Short name T841
Test name
Test status
Simulation time 18196915098 ps
CPU time 16.82 seconds
Started Aug 25 03:57:30 AM UTC 24
Finished Aug 25 03:57:48 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970432902 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2970432902
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.121753278
Short name T960
Test name
Test status
Simulation time 151204985299 ps
CPU time 247.47 seconds
Started Aug 25 03:57:39 AM UTC 24
Finished Aug 25 04:01:50 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121753278 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.121753278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_loopback.446770072
Short name T846
Test name
Test status
Simulation time 7366439922 ps
CPU time 29.59 seconds
Started Aug 25 03:57:35 AM UTC 24
Finished Aug 25 03:58:07 AM UTC 24
Peak memory 208448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446770072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.uart_loopback.446770072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_noise_filter.4186809171
Short name T881
Test name
Test status
Simulation time 48384834975 ps
CPU time 96.2 seconds
Started Aug 25 03:57:31 AM UTC 24
Finished Aug 25 03:59:10 AM UTC 24
Peak memory 208972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186809171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.4186809171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_perf.3120035688
Short name T1033
Test name
Test status
Simulation time 6177904426 ps
CPU time 369.64 seconds
Started Aug 25 03:57:39 AM UTC 24
Finished Aug 25 04:03:54 AM UTC 24
Peak memory 208868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120035688 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3120035688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_rx_oversample.3850788994
Short name T863
Test name
Test status
Simulation time 5029034426 ps
CPU time 61.15 seconds
Started Aug 25 03:57:29 AM UTC 24
Finished Aug 25 03:58:32 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850788994 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3850788994
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.2366234474
Short name T989
Test name
Test status
Simulation time 118526364804 ps
CPU time 303.25 seconds
Started Aug 25 03:57:32 AM UTC 24
Finished Aug 25 04:02:40 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366234474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2366234474
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.587376169
Short name T835
Test name
Test status
Simulation time 6289779417 ps
CPU time 5.96 seconds
Started Aug 25 03:57:31 AM UTC 24
Finished Aug 25 03:57:38 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587376169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.587376169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_smoke.1776132611
Short name T842
Test name
Test status
Simulation time 5906874517 ps
CPU time 28.15 seconds
Started Aug 25 03:57:21 AM UTC 24
Finished Aug 25 03:57:50 AM UTC 24
Peak memory 207956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776132611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1776132611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_stress_all.2555207107
Short name T1100
Test name
Test status
Simulation time 163307865041 ps
CPU time 514.85 seconds
Started Aug 25 03:57:40 AM UTC 24
Finished Aug 25 04:06:22 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555207107 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2555207107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.4232373507
Short name T852
Test name
Test status
Simulation time 7623070323 ps
CPU time 32.07 seconds
Started Aug 25 03:57:40 AM UTC 24
Finished Aug 25 03:58:13 AM UTC 24
Peak memory 224004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4232373507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all
_with_rand_reset.4232373507
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.2821702117
Short name T836
Test name
Test status
Simulation time 363082807 ps
CPU time 2.2 seconds
Started Aug 25 03:57:35 AM UTC 24
Finished Aug 25 03:57:39 AM UTC 24
Peak memory 207104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821702117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2821702117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/47.uart_tx_rx.2177405301
Short name T426
Test name
Test status
Simulation time 61712159120 ps
CPU time 70.16 seconds
Started Aug 25 03:57:24 AM UTC 24
Finished Aug 25 03:58:36 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177405301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2177405301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/47.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_alert_test.3233551461
Short name T855
Test name
Test status
Simulation time 13074047 ps
CPU time 0.81 seconds
Started Aug 25 03:58:14 AM UTC 24
Finished Aug 25 03:58:16 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233551461 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3233551461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_fifo_full.3357664979
Short name T873
Test name
Test status
Simulation time 113958560004 ps
CPU time 53.83 seconds
Started Aug 25 03:57:47 AM UTC 24
Finished Aug 25 03:58:42 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357664979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3357664979
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.217524851
Short name T856
Test name
Test status
Simulation time 9122488580 ps
CPU time 26.08 seconds
Started Aug 25 03:57:49 AM UTC 24
Finished Aug 25 03:58:16 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217524851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.217524851
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_fifo_reset.1510785546
Short name T861
Test name
Test status
Simulation time 40957735066 ps
CPU time 34.52 seconds
Started Aug 25 03:57:51 AM UTC 24
Finished Aug 25 03:58:27 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510785546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1510785546
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_intr.2852288118
Short name T1048
Test name
Test status
Simulation time 308908032480 ps
CPU time 381.52 seconds
Started Aug 25 03:57:53 AM UTC 24
Finished Aug 25 04:04:20 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852288118 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2852288118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.2580430597
Short name T1095
Test name
Test status
Simulation time 42141541595 ps
CPU time 465.07 seconds
Started Aug 25 03:58:10 AM UTC 24
Finished Aug 25 04:06:02 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580430597 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2580430597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_loopback.1050053389
Short name T851
Test name
Test status
Simulation time 750527619 ps
CPU time 1.64 seconds
Started Aug 25 03:58:10 AM UTC 24
Finished Aug 25 03:58:13 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050053389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1050053389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_noise_filter.2682399099
Short name T857
Test name
Test status
Simulation time 12573800979 ps
CPU time 16.62 seconds
Started Aug 25 03:58:00 AM UTC 24
Finished Aug 25 03:58:18 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682399099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2682399099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_perf.2503103426
Short name T961
Test name
Test status
Simulation time 14389987276 ps
CPU time 219.34 seconds
Started Aug 25 03:58:10 AM UTC 24
Finished Aug 25 04:01:53 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503103426 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2503103426
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_rx_oversample.1112099484
Short name T871
Test name
Test status
Simulation time 6852499053 ps
CPU time 46.44 seconds
Started Aug 25 03:57:53 AM UTC 24
Finished Aug 25 03:58:42 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112099484 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1112099484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.184368368
Short name T879
Test name
Test status
Simulation time 18204801016 ps
CPU time 52.21 seconds
Started Aug 25 03:58:08 AM UTC 24
Finished Aug 25 03:59:01 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184368368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.184368368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.1945700877
Short name T849
Test name
Test status
Simulation time 1220278146 ps
CPU time 5.67 seconds
Started Aug 25 03:58:01 AM UTC 24
Finished Aug 25 03:58:08 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945700877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1945700877
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_smoke.1694791552
Short name T859
Test name
Test status
Simulation time 5320249385 ps
CPU time 38.58 seconds
Started Aug 25 03:57:42 AM UTC 24
Finished Aug 25 03:58:22 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694791552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1694791552
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_stress_all.1637840261
Short name T883
Test name
Test status
Simulation time 17185137834 ps
CPU time 55.71 seconds
Started Aug 25 03:58:14 AM UTC 24
Finished Aug 25 03:59:12 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637840261 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1637840261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.268962344
Short name T880
Test name
Test status
Simulation time 2689169969 ps
CPU time 49.92 seconds
Started Aug 25 03:58:14 AM UTC 24
Finished Aug 25 03:59:06 AM UTC 24
Peak memory 217804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=268962344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all_
with_rand_reset.268962344
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.4274249701
Short name T854
Test name
Test status
Simulation time 727861052 ps
CPU time 3.8 seconds
Started Aug 25 03:58:09 AM UTC 24
Finished Aug 25 03:58:14 AM UTC 24
Peak memory 207556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274249701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.4274249701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/48.uart_tx_rx.195983299
Short name T898
Test name
Test status
Simulation time 154422245724 ps
CPU time 120.17 seconds
Started Aug 25 03:57:43 AM UTC 24
Finished Aug 25 03:59:46 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195983299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.195983299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/48.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_alert_test.4052435031
Short name T869
Test name
Test status
Simulation time 26795467 ps
CPU time 0.85 seconds
Started Aug 25 03:58:39 AM UTC 24
Finished Aug 25 03:58:41 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052435031 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.4052435031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_fifo_full.2638363782
Short name T958
Test name
Test status
Simulation time 192633928118 ps
CPU time 206.29 seconds
Started Aug 25 03:58:17 AM UTC 24
Finished Aug 25 04:01:47 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638363782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2638363782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.2799561670
Short name T885
Test name
Test status
Simulation time 123796677873 ps
CPU time 63.17 seconds
Started Aug 25 03:58:19 AM UTC 24
Finished Aug 25 03:59:24 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799561670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2799561670
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_fifo_reset.1018775155
Short name T924
Test name
Test status
Simulation time 213931785869 ps
CPU time 137.82 seconds
Started Aug 25 03:58:21 AM UTC 24
Finished Aug 25 04:00:42 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018775155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1018775155
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_intr.4158429404
Short name T874
Test name
Test status
Simulation time 7191108808 ps
CPU time 19.67 seconds
Started Aug 25 03:58:24 AM UTC 24
Finished Aug 25 03:58:45 AM UTC 24
Peak memory 207076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158429404 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4158429404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.122958058
Short name T1175
Test name
Test status
Simulation time 162573935353 ps
CPU time 715.13 seconds
Started Aug 25 03:58:36 AM UTC 24
Finished Aug 25 04:10:41 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122958058 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.122958058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_loopback.49543251
Short name T876
Test name
Test status
Simulation time 4469608415 ps
CPU time 13.12 seconds
Started Aug 25 03:58:33 AM UTC 24
Finished Aug 25 03:58:47 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49543251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.uart_loopback.49543251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_noise_filter.1269239456
Short name T922
Test name
Test status
Simulation time 89589474334 ps
CPU time 134.9 seconds
Started Aug 25 03:58:24 AM UTC 24
Finished Aug 25 04:00:41 AM UTC 24
Peak memory 217800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269239456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1269239456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_perf.3877900571
Short name T945
Test name
Test status
Simulation time 7197962532 ps
CPU time 162.61 seconds
Started Aug 25 03:58:36 AM UTC 24
Finished Aug 25 04:01:22 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877900571 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3877900571
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_rx_oversample.147265465
Short name T864
Test name
Test status
Simulation time 4016649401 ps
CPU time 11.36 seconds
Started Aug 25 03:58:23 AM UTC 24
Finished Aug 25 03:58:35 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147265465 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.147265465
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.307292928
Short name T911
Test name
Test status
Simulation time 26655701792 ps
CPU time 115.18 seconds
Started Aug 25 03:58:28 AM UTC 24
Finished Aug 25 04:00:25 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307292928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.307292928
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.2898139846
Short name T875
Test name
Test status
Simulation time 36874898501 ps
CPU time 18.96 seconds
Started Aug 25 03:58:26 AM UTC 24
Finished Aug 25 03:58:46 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898139846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2898139846
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_smoke.1663094381
Short name T858
Test name
Test status
Simulation time 473530836 ps
CPU time 3.91 seconds
Started Aug 25 03:58:15 AM UTC 24
Finished Aug 25 03:58:20 AM UTC 24
Peak memory 207608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663094381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1663094381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_stress_all.4284575092
Short name T1177
Test name
Test status
Simulation time 125895880261 ps
CPU time 733.37 seconds
Started Aug 25 03:58:38 AM UTC 24
Finished Aug 25 04:11:01 AM UTC 24
Peak memory 210328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284575092 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.4284575092
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.1158973397
Short name T892
Test name
Test status
Simulation time 2259917063 ps
CPU time 56 seconds
Started Aug 25 03:58:36 AM UTC 24
Finished Aug 25 03:59:34 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1158973397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all
_with_rand_reset.1158973397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.1998893466
Short name T868
Test name
Test status
Simulation time 902940212 ps
CPU time 6.19 seconds
Started Aug 25 03:58:33 AM UTC 24
Finished Aug 25 03:58:40 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998893466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1998893466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/49.uart_tx_rx.3842586982
Short name T413
Test name
Test status
Simulation time 48952745497 ps
CPU time 155.87 seconds
Started Aug 25 03:58:17 AM UTC 24
Finished Aug 25 04:00:56 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842586982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3842586982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/49.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_alert_test.3027836414
Short name T100
Test name
Test status
Simulation time 12701638 ps
CPU time 0.82 seconds
Started Aug 25 03:35:11 AM UTC 24
Finished Aug 25 03:35:13 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027836414 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3027836414
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_loopback.608300965
Short name T99
Test name
Test status
Simulation time 5967609008 ps
CPU time 5.57 seconds
Started Aug 25 03:35:03 AM UTC 24
Finished Aug 25 03:35:10 AM UTC 24
Peak memory 207860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608300965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.uart_loopback.608300965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_noise_filter.1988727079
Short name T368
Test name
Test status
Simulation time 119077185200 ps
CPU time 563.17 seconds
Started Aug 25 03:34:58 AM UTC 24
Finished Aug 25 03:44:29 AM UTC 24
Peak memory 209024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988727079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1988727079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_perf.755025058
Short name T549
Test name
Test status
Simulation time 11396075521 ps
CPU time 683.39 seconds
Started Aug 25 03:35:03 AM UTC 24
Finished Aug 25 03:46:36 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755025058 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.755025058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_rx_oversample.4138669829
Short name T54
Test name
Test status
Simulation time 7564882135 ps
CPU time 77.25 seconds
Started Aug 25 03:34:56 AM UTC 24
Finished Aug 25 03:36:15 AM UTC 24
Peak memory 207880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138669829 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.4138669829
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.532675469
Short name T123
Test name
Test status
Simulation time 50863294349 ps
CPU time 38.54 seconds
Started Aug 25 03:34:59 AM UTC 24
Finished Aug 25 03:35:39 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532675469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.532675469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.1250860123
Short name T97
Test name
Test status
Simulation time 1671007381 ps
CPU time 3.4 seconds
Started Aug 25 03:34:58 AM UTC 24
Finished Aug 25 03:35:03 AM UTC 24
Peak memory 205040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250860123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1250860123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_smoke.4033576692
Short name T322
Test name
Test status
Simulation time 293458521 ps
CPU time 1.74 seconds
Started Aug 25 03:34:54 AM UTC 24
Finished Aug 25 03:34:57 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033576692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.uart_smoke.4033576692
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.3666949730
Short name T38
Test name
Test status
Simulation time 4675887060 ps
CPU time 114.19 seconds
Started Aug 25 03:35:07 AM UTC 24
Finished Aug 25 03:37:03 AM UTC 24
Peak memory 217604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3666949730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_
with_rand_reset.3666949730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.876301479
Short name T53
Test name
Test status
Simulation time 6438059614 ps
CPU time 38.27 seconds
Started Aug 25 03:35:00 AM UTC 24
Finished Aug 25 03:35:40 AM UTC 24
Peak memory 208068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876301479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.876301479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/5.uart_tx_rx.3802313758
Short name T395
Test name
Test status
Simulation time 339121295 ps
CPU time 2.05 seconds
Started Aug 25 03:34:54 AM UTC 24
Finished Aug 25 03:34:57 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802313758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3802313758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/5.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/50.uart_fifo_reset.965839399
Short name T213
Test name
Test status
Simulation time 63015961281 ps
CPU time 50.35 seconds
Started Aug 25 03:58:41 AM UTC 24
Finished Aug 25 03:59:33 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965839399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.965839399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/50.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.2979485694
Short name T884
Test name
Test status
Simulation time 3075235452 ps
CPU time 38.33 seconds
Started Aug 25 03:58:43 AM UTC 24
Finished Aug 25 03:59:22 AM UTC 24
Peak memory 217592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2979485694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all
_with_rand_reset.2979485694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/51.uart_fifo_reset.1817940047
Short name T915
Test name
Test status
Simulation time 30381528600 ps
CPU time 108.52 seconds
Started Aug 25 03:58:43 AM UTC 24
Finished Aug 25 04:00:33 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817940047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1817940047
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/51.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.1567553786
Short name T908
Test name
Test status
Simulation time 18017082527 ps
CPU time 92.96 seconds
Started Aug 25 03:58:43 AM UTC 24
Finished Aug 25 04:00:18 AM UTC 24
Peak memory 221884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1567553786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all
_with_rand_reset.1567553786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/52.uart_fifo_reset.514875911
Short name T878
Test name
Test status
Simulation time 18417948968 ps
CPU time 14.23 seconds
Started Aug 25 03:58:43 AM UTC 24
Finished Aug 25 03:58:58 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514875911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.514875911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/52.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.2673593771
Short name T893
Test name
Test status
Simulation time 2598288234 ps
CPU time 50.16 seconds
Started Aug 25 03:58:44 AM UTC 24
Finished Aug 25 03:59:36 AM UTC 24
Peak memory 219768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2673593771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all
_with_rand_reset.2673593771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/53.uart_fifo_reset.837263780
Short name T247
Test name
Test status
Simulation time 227037680062 ps
CPU time 93.02 seconds
Started Aug 25 03:58:46 AM UTC 24
Finished Aug 25 04:00:21 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837263780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.837263780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/53.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.767583090
Short name T196
Test name
Test status
Simulation time 20371040365 ps
CPU time 146.67 seconds
Started Aug 25 03:58:47 AM UTC 24
Finished Aug 25 04:01:17 AM UTC 24
Peak memory 219892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=767583090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all_
with_rand_reset.767583090
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/54.uart_fifo_reset.2080924674
Short name T261
Test name
Test status
Simulation time 113360559926 ps
CPU time 37.05 seconds
Started Aug 25 03:58:48 AM UTC 24
Finished Aug 25 03:59:26 AM UTC 24
Peak memory 208864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080924674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2080924674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/54.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.137186251
Short name T882
Test name
Test status
Simulation time 3713623156 ps
CPU time 11.78 seconds
Started Aug 25 03:58:58 AM UTC 24
Finished Aug 25 03:59:11 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=137186251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all_
with_rand_reset.137186251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/55.uart_fifo_reset.952520807
Short name T184
Test name
Test status
Simulation time 22385116722 ps
CPU time 68.5 seconds
Started Aug 25 03:58:59 AM UTC 24
Finished Aug 25 04:00:09 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952520807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.952520807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/55.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.873402419
Short name T890
Test name
Test status
Simulation time 1784342351 ps
CPU time 28.13 seconds
Started Aug 25 03:59:02 AM UTC 24
Finished Aug 25 03:59:32 AM UTC 24
Peak memory 223820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=873402419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all_
with_rand_reset.873402419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/56.uart_fifo_reset.612876632
Short name T887
Test name
Test status
Simulation time 11114914758 ps
CPU time 21.53 seconds
Started Aug 25 03:59:06 AM UTC 24
Finished Aug 25 03:59:29 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612876632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.612876632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/56.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.1625019534
Short name T902
Test name
Test status
Simulation time 11382109845 ps
CPU time 45.99 seconds
Started Aug 25 03:59:10 AM UTC 24
Finished Aug 25 03:59:58 AM UTC 24
Peak memory 224948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1625019534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all
_with_rand_reset.1625019534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/57.uart_fifo_reset.891832643
Short name T897
Test name
Test status
Simulation time 30703212575 ps
CPU time 28.51 seconds
Started Aug 25 03:59:12 AM UTC 24
Finished Aug 25 03:59:41 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891832643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.891832643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/57.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.3866322116
Short name T886
Test name
Test status
Simulation time 1667334072 ps
CPU time 13.38 seconds
Started Aug 25 03:59:13 AM UTC 24
Finished Aug 25 03:59:27 AM UTC 24
Peak memory 217868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3866322116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all
_with_rand_reset.3866322116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/58.uart_fifo_reset.4009494783
Short name T209
Test name
Test status
Simulation time 90317237439 ps
CPU time 74.06 seconds
Started Aug 25 03:59:24 AM UTC 24
Finished Aug 25 04:00:40 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009494783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.4009494783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/58.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.847258860
Short name T917
Test name
Test status
Simulation time 6320816428 ps
CPU time 66.79 seconds
Started Aug 25 03:59:25 AM UTC 24
Finished Aug 25 04:00:34 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=847258860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all_
with_rand_reset.847258860
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/59.uart_fifo_reset.1361296356
Short name T192
Test name
Test status
Simulation time 29478383507 ps
CPU time 67.63 seconds
Started Aug 25 03:59:27 AM UTC 24
Finished Aug 25 04:00:36 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361296356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1361296356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/59.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.771710326
Short name T910
Test name
Test status
Simulation time 12710579949 ps
CPU time 53.7 seconds
Started Aug 25 03:59:28 AM UTC 24
Finished Aug 25 04:00:24 AM UTC 24
Peak memory 219968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=771710326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all_
with_rand_reset.771710326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_alert_test.3025304275
Short name T431
Test name
Test status
Simulation time 17746540 ps
CPU time 0.77 seconds
Started Aug 25 03:35:31 AM UTC 24
Finished Aug 25 03:35:33 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025304275 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3025304275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_fifo_full.3597571336
Short name T125
Test name
Test status
Simulation time 24394767865 ps
CPU time 72.53 seconds
Started Aug 25 03:35:15 AM UTC 24
Finished Aug 25 03:36:29 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597571336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3597571336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.2094590591
Short name T132
Test name
Test status
Simulation time 39288214474 ps
CPU time 18.77 seconds
Started Aug 25 03:35:15 AM UTC 24
Finished Aug 25 03:35:35 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094590591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2094590591
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_fifo_reset.1978503673
Short name T136
Test name
Test status
Simulation time 61483699840 ps
CPU time 51.15 seconds
Started Aug 25 03:35:17 AM UTC 24
Finished Aug 25 03:36:10 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978503673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1978503673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_intr.3000000521
Short name T391
Test name
Test status
Simulation time 16272974949 ps
CPU time 15.23 seconds
Started Aug 25 03:35:19 AM UTC 24
Finished Aug 25 03:35:36 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000000521 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3000000521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.1944487548
Short name T351
Test name
Test status
Simulation time 99505103260 ps
CPU time 360.8 seconds
Started Aug 25 03:35:29 AM UTC 24
Finished Aug 25 03:41:35 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944487548 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1944487548
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_loopback.363731971
Short name T399
Test name
Test status
Simulation time 1050394141 ps
CPU time 1.76 seconds
Started Aug 25 03:35:28 AM UTC 24
Finished Aug 25 03:35:30 AM UTC 24
Peak memory 204444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363731971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.uart_loopback.363731971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_noise_filter.804879147
Short name T284
Test name
Test status
Simulation time 35227592032 ps
CPU time 36.81 seconds
Started Aug 25 03:35:21 AM UTC 24
Finished Aug 25 03:36:00 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804879147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.804879147
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_perf.4289008868
Short name T347
Test name
Test status
Simulation time 6253830454 ps
CPU time 212.64 seconds
Started Aug 25 03:35:29 AM UTC 24
Finished Aug 25 03:39:05 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289008868 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.4289008868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_rx_oversample.211570047
Short name T432
Test name
Test status
Simulation time 2647980318 ps
CPU time 23.84 seconds
Started Aug 25 03:35:18 AM UTC 24
Finished Aug 25 03:35:43 AM UTC 24
Peak memory 207680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211570047 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.211570047
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.1958588498
Short name T137
Test name
Test status
Simulation time 104074860795 ps
CPU time 94.09 seconds
Started Aug 25 03:35:22 AM UTC 24
Finished Aug 25 03:36:59 AM UTC 24
Peak memory 208548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958588498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1958588498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.929390784
Short name T287
Test name
Test status
Simulation time 4595815685 ps
CPU time 5.04 seconds
Started Aug 25 03:35:21 AM UTC 24
Finished Aug 25 03:35:28 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929390784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.929390784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_smoke.4254661016
Short name T336
Test name
Test status
Simulation time 697000945 ps
CPU time 3.78 seconds
Started Aug 25 03:35:14 AM UTC 24
Finished Aug 25 03:35:19 AM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254661016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.4254661016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_stress_all.3546987832
Short name T593
Test name
Test status
Simulation time 268062801242 ps
CPU time 743.01 seconds
Started Aug 25 03:35:31 AM UTC 24
Finished Aug 25 03:48:02 AM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546987832 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3546987832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.1618556938
Short name T36
Test name
Test status
Simulation time 4206396159 ps
CPU time 47.14 seconds
Started Aug 25 03:35:31 AM UTC 24
Finished Aug 25 03:36:19 AM UTC 24
Peak memory 217592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1618556938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_
with_rand_reset.1618556938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.1406181068
Short name T325
Test name
Test status
Simulation time 15611080095 ps
CPU time 10.15 seconds
Started Aug 25 03:35:23 AM UTC 24
Finished Aug 25 03:35:35 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406181068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1406181068
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/6.uart_tx_rx.4202965751
Short name T269
Test name
Test status
Simulation time 48268419486 ps
CPU time 44.67 seconds
Started Aug 25 03:35:15 AM UTC 24
Finished Aug 25 03:36:01 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202965751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4202965751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/6.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/60.uart_fifo_reset.4096901231
Short name T955
Test name
Test status
Simulation time 149950045018 ps
CPU time 130.71 seconds
Started Aug 25 03:59:30 AM UTC 24
Finished Aug 25 04:01:44 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096901231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4096901231
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/60.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.3189897721
Short name T927
Test name
Test status
Simulation time 3680234233 ps
CPU time 79.55 seconds
Started Aug 25 03:59:32 AM UTC 24
Finished Aug 25 04:00:54 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3189897721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all
_with_rand_reset.3189897721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.2138622178
Short name T903
Test name
Test status
Simulation time 19403311591 ps
CPU time 29.65 seconds
Started Aug 25 03:59:32 AM UTC 24
Finished Aug 25 04:00:03 AM UTC 24
Peak memory 225344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2138622178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all
_with_rand_reset.2138622178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/62.uart_fifo_reset.2262009369
Short name T203
Test name
Test status
Simulation time 42669314940 ps
CPU time 40.68 seconds
Started Aug 25 03:59:34 AM UTC 24
Finished Aug 25 04:00:17 AM UTC 24
Peak memory 208480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262009369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2262009369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/62.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.1889679142
Short name T932
Test name
Test status
Simulation time 3408479278 ps
CPU time 86.48 seconds
Started Aug 25 03:59:34 AM UTC 24
Finished Aug 25 04:01:03 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1889679142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all
_with_rand_reset.1889679142
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/63.uart_fifo_reset.587399769
Short name T985
Test name
Test status
Simulation time 128941489711 ps
CPU time 176.59 seconds
Started Aug 25 03:59:34 AM UTC 24
Finished Aug 25 04:02:34 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587399769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.587399769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/63.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.1482093600
Short name T926
Test name
Test status
Simulation time 14879326789 ps
CPU time 72.44 seconds
Started Aug 25 03:59:37 AM UTC 24
Finished Aug 25 04:00:51 AM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1482093600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all
_with_rand_reset.1482093600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/64.uart_fifo_reset.4291415275
Short name T923
Test name
Test status
Simulation time 90079709729 ps
CPU time 61.13 seconds
Started Aug 25 03:59:39 AM UTC 24
Finished Aug 25 04:00:42 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291415275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4291415275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/64.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.1253779534
Short name T905
Test name
Test status
Simulation time 2148059431 ps
CPU time 28.45 seconds
Started Aug 25 03:59:39 AM UTC 24
Finished Aug 25 04:00:08 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1253779534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all
_with_rand_reset.1253779534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/65.uart_fifo_reset.3512165742
Short name T974
Test name
Test status
Simulation time 109577093617 ps
CPU time 154.62 seconds
Started Aug 25 03:59:40 AM UTC 24
Finished Aug 25 04:02:17 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512165742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3512165742
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/65.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.2519758179
Short name T900
Test name
Test status
Simulation time 982652307 ps
CPU time 9.01 seconds
Started Aug 25 03:59:42 AM UTC 24
Finished Aug 25 03:59:52 AM UTC 24
Peak memory 217748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2519758179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all
_with_rand_reset.2519758179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.4127935901
Short name T904
Test name
Test status
Simulation time 3592841123 ps
CPU time 15.32 seconds
Started Aug 25 03:59:48 AM UTC 24
Finished Aug 25 04:00:05 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4127935901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all
_with_rand_reset.4127935901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/67.uart_fifo_reset.1955598525
Short name T969
Test name
Test status
Simulation time 66447919605 ps
CPU time 136.43 seconds
Started Aug 25 03:59:52 AM UTC 24
Finished Aug 25 04:02:11 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955598525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1955598525
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/67.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.241824857
Short name T912
Test name
Test status
Simulation time 2297659477 ps
CPU time 30.98 seconds
Started Aug 25 03:59:53 AM UTC 24
Finished Aug 25 04:00:26 AM UTC 24
Peak memory 222076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=241824857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all_
with_rand_reset.241824857
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/68.uart_fifo_reset.3125078912
Short name T983
Test name
Test status
Simulation time 56553493395 ps
CPU time 150.65 seconds
Started Aug 25 03:59:56 AM UTC 24
Finished Aug 25 04:02:29 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125078912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3125078912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/68.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.2020652547
Short name T919
Test name
Test status
Simulation time 2135692290 ps
CPU time 33.55 seconds
Started Aug 25 03:59:59 AM UTC 24
Finished Aug 25 04:00:34 AM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2020652547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all
_with_rand_reset.2020652547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/69.uart_fifo_reset.1743945395
Short name T193
Test name
Test status
Simulation time 107615738917 ps
CPU time 105.18 seconds
Started Aug 25 04:00:06 AM UTC 24
Finished Aug 25 04:01:54 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743945395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1743945395
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/69.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.3100895805
Short name T933
Test name
Test status
Simulation time 2954844321 ps
CPU time 54.9 seconds
Started Aug 25 04:00:07 AM UTC 24
Finished Aug 25 04:01:03 AM UTC 24
Peak memory 217732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3100895805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all
_with_rand_reset.3100895805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_alert_test.1929680622
Short name T433
Test name
Test status
Simulation time 41788315 ps
CPU time 0.79 seconds
Started Aug 25 03:35:51 AM UTC 24
Finished Aug 25 03:35:52 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929680622 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1929680622
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_fifo_full.1596645361
Short name T126
Test name
Test status
Simulation time 105567340508 ps
CPU time 218.09 seconds
Started Aug 25 03:35:36 AM UTC 24
Finished Aug 25 03:39:17 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596645361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1596645361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2353818863
Short name T296
Test name
Test status
Simulation time 46536727520 ps
CPU time 144.08 seconds
Started Aug 25 03:35:36 AM UTC 24
Finished Aug 25 03:38:03 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353818863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2353818863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_intr.913252783
Short name T112
Test name
Test status
Simulation time 55455927254 ps
CPU time 167.79 seconds
Started Aug 25 03:35:37 AM UTC 24
Finished Aug 25 03:38:28 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913252783 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.913252783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.529518876
Short name T889
Test name
Test status
Simulation time 99861729642 ps
CPU time 1403.19 seconds
Started Aug 25 03:35:50 AM UTC 24
Finished Aug 25 03:59:31 AM UTC 24
Peak memory 212212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529518876 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.529518876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_loopback.2935091946
Short name T436
Test name
Test status
Simulation time 11554191677 ps
CPU time 18.39 seconds
Started Aug 25 03:35:48 AM UTC 24
Finished Aug 25 03:36:08 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935091946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2935091946
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_noise_filter.3247856255
Short name T543
Test name
Test status
Simulation time 137150289656 ps
CPU time 635.27 seconds
Started Aug 25 03:35:40 AM UTC 24
Finished Aug 25 03:46:24 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247856255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3247856255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_rx_oversample.2862125089
Short name T434
Test name
Test status
Simulation time 3605851131 ps
CPU time 15.61 seconds
Started Aug 25 03:35:37 AM UTC 24
Finished Aug 25 03:35:54 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862125089 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2862125089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.3981353129
Short name T338
Test name
Test status
Simulation time 73487734088 ps
CPU time 203.92 seconds
Started Aug 25 03:35:43 AM UTC 24
Finished Aug 25 03:39:10 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981353129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3981353129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.3672825204
Short name T270
Test name
Test status
Simulation time 3519873866 ps
CPU time 11.65 seconds
Started Aug 25 03:35:41 AM UTC 24
Finished Aug 25 03:35:54 AM UTC 24
Peak memory 205040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672825204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3672825204
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_smoke.955196777
Short name T282
Test name
Test status
Simulation time 315694316 ps
CPU time 1.85 seconds
Started Aug 25 03:35:33 AM UTC 24
Finished Aug 25 03:35:36 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955196777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 7.uart_smoke.955196777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_stress_all.744547730
Short name T850
Test name
Test status
Simulation time 252741450204 ps
CPU time 1322.74 seconds
Started Aug 25 03:35:51 AM UTC 24
Finished Aug 25 03:58:09 AM UTC 24
Peak memory 221176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744547730 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.744547730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.3052370553
Short name T26
Test name
Test status
Simulation time 2998392275 ps
CPU time 33.32 seconds
Started Aug 25 03:35:50 AM UTC 24
Finished Aug 25 03:36:24 AM UTC 24
Peak memory 217644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3052370553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_
with_rand_reset.3052370553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.1970566572
Short name T339
Test name
Test status
Simulation time 1195041021 ps
CPU time 3.18 seconds
Started Aug 25 03:35:44 AM UTC 24
Finished Aug 25 03:35:49 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970566572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1970566572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/7.uart_tx_rx.290403838
Short name T299
Test name
Test status
Simulation time 23645053776 ps
CPU time 42.76 seconds
Started Aug 25 03:35:33 AM UTC 24
Finished Aug 25 03:36:17 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290403838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.290403838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/7.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/70.uart_fifo_reset.3038459078
Short name T199
Test name
Test status
Simulation time 104703141728 ps
CPU time 58.69 seconds
Started Aug 25 04:00:10 AM UTC 24
Finished Aug 25 04:01:10 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038459078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3038459078
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/70.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.4171668279
Short name T930
Test name
Test status
Simulation time 8774098091 ps
CPU time 43.52 seconds
Started Aug 25 04:00:11 AM UTC 24
Finished Aug 25 04:00:56 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4171668279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all
_with_rand_reset.4171668279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/71.uart_fifo_reset.2035560254
Short name T1018
Test name
Test status
Simulation time 209249214227 ps
CPU time 187.41 seconds
Started Aug 25 04:00:11 AM UTC 24
Finished Aug 25 04:03:21 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035560254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2035560254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/71.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.3921538558
Short name T942
Test name
Test status
Simulation time 4725615007 ps
CPU time 65.16 seconds
Started Aug 25 04:00:12 AM UTC 24
Finished Aug 25 04:01:19 AM UTC 24
Peak memory 217884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3921538558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all
_with_rand_reset.3921538558
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/72.uart_fifo_reset.2758506172
Short name T935
Test name
Test status
Simulation time 37740455712 ps
CPU time 49.66 seconds
Started Aug 25 04:00:15 AM UTC 24
Finished Aug 25 04:01:06 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758506172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2758506172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/72.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.1953365170
Short name T977
Test name
Test status
Simulation time 14143741059 ps
CPU time 120.1 seconds
Started Aug 25 04:00:18 AM UTC 24
Finished Aug 25 04:02:21 AM UTC 24
Peak memory 225496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1953365170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all
_with_rand_reset.1953365170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/73.uart_fifo_reset.4150687816
Short name T207
Test name
Test status
Simulation time 18483830346 ps
CPU time 61.76 seconds
Started Aug 25 04:00:19 AM UTC 24
Finished Aug 25 04:01:22 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150687816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.4150687816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/73.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.563222508
Short name T941
Test name
Test status
Simulation time 3075718237 ps
CPU time 55.9 seconds
Started Aug 25 04:00:20 AM UTC 24
Finished Aug 25 04:01:18 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=563222508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all_
with_rand_reset.563222508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/74.uart_fifo_reset.306528090
Short name T404
Test name
Test status
Simulation time 91521134475 ps
CPU time 24.64 seconds
Started Aug 25 04:00:21 AM UTC 24
Finished Aug 25 04:00:47 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306528090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.306528090
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/74.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.3412166084
Short name T914
Test name
Test status
Simulation time 170013580 ps
CPU time 3.66 seconds
Started Aug 25 04:00:24 AM UTC 24
Finished Aug 25 04:00:29 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3412166084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all
_with_rand_reset.3412166084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/75.uart_fifo_reset.927872043
Short name T931
Test name
Test status
Simulation time 31152104207 ps
CPU time 32.69 seconds
Started Aug 25 04:00:26 AM UTC 24
Finished Aug 25 04:01:01 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927872043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.927872043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/75.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.1255593860
Short name T950
Test name
Test status
Simulation time 13073637596 ps
CPU time 63.77 seconds
Started Aug 25 04:00:27 AM UTC 24
Finished Aug 25 04:01:32 AM UTC 24
Peak memory 217844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1255593860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all
_with_rand_reset.1255593860
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/76.uart_fifo_reset.1110133466
Short name T929
Test name
Test status
Simulation time 19438023171 ps
CPU time 27.98 seconds
Started Aug 25 04:00:27 AM UTC 24
Finished Aug 25 04:00:56 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110133466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1110133466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/76.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.3771093669
Short name T944
Test name
Test status
Simulation time 3569941310 ps
CPU time 49.4 seconds
Started Aug 25 04:00:30 AM UTC 24
Finished Aug 25 04:01:21 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3771093669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all
_with_rand_reset.3771093669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/77.uart_fifo_reset.22132102
Short name T197
Test name
Test status
Simulation time 136119011776 ps
CPU time 97.77 seconds
Started Aug 25 04:00:34 AM UTC 24
Finished Aug 25 04:02:13 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22132102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.22132102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/77.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.4246178980
Short name T934
Test name
Test status
Simulation time 6675810979 ps
CPU time 29.34 seconds
Started Aug 25 04:00:34 AM UTC 24
Finished Aug 25 04:01:05 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4246178980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all
_with_rand_reset.4246178980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/78.uart_fifo_reset.2812736231
Short name T953
Test name
Test status
Simulation time 227590127037 ps
CPU time 62.65 seconds
Started Aug 25 04:00:35 AM UTC 24
Finished Aug 25 04:01:39 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812736231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2812736231
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/78.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.4123178313
Short name T947
Test name
Test status
Simulation time 14384518543 ps
CPU time 50.55 seconds
Started Aug 25 04:00:35 AM UTC 24
Finished Aug 25 04:01:27 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4123178313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all
_with_rand_reset.4123178313
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/79.uart_fifo_reset.2137007912
Short name T1001
Test name
Test status
Simulation time 45785612229 ps
CPU time 140.98 seconds
Started Aug 25 04:00:35 AM UTC 24
Finished Aug 25 04:02:59 AM UTC 24
Peak memory 208948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137007912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2137007912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/79.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.3164354642
Short name T925
Test name
Test status
Simulation time 788790911 ps
CPU time 6.42 seconds
Started Aug 25 04:00:37 AM UTC 24
Finished Aug 25 04:00:45 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3164354642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all
_with_rand_reset.3164354642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_alert_test.3299468801
Short name T437
Test name
Test status
Simulation time 20084819 ps
CPU time 0.84 seconds
Started Aug 25 03:36:11 AM UTC 24
Finished Aug 25 03:36:13 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299468801 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3299468801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_fifo_full.3546145787
Short name T124
Test name
Test status
Simulation time 28934896548 ps
CPU time 26.32 seconds
Started Aug 25 03:35:55 AM UTC 24
Finished Aug 25 03:36:23 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546145787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3546145787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.2177853459
Short name T166
Test name
Test status
Simulation time 112079542708 ps
CPU time 403.47 seconds
Started Aug 25 03:35:55 AM UTC 24
Finished Aug 25 03:42:44 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177853459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2177853459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_intr.2347111425
Short name T396
Test name
Test status
Simulation time 30674253699 ps
CPU time 90.53 seconds
Started Aug 25 03:35:59 AM UTC 24
Finished Aug 25 03:37:32 AM UTC 24
Peak memory 208208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347111425 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2347111425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.2971788994
Short name T559
Test name
Test status
Simulation time 68818365287 ps
CPU time 639.74 seconds
Started Aug 25 03:36:06 AM UTC 24
Finished Aug 25 03:46:54 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971788994 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2971788994
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_loopback.3781390363
Short name T438
Test name
Test status
Simulation time 8057300735 ps
CPU time 9.21 seconds
Started Aug 25 03:36:03 AM UTC 24
Finished Aug 25 03:36:13 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781390363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3781390363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_noise_filter.3309997981
Short name T320
Test name
Test status
Simulation time 96107604925 ps
CPU time 159.55 seconds
Started Aug 25 03:35:59 AM UTC 24
Finished Aug 25 03:38:42 AM UTC 24
Peak memory 217460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309997981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3309997981
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_perf.2282728586
Short name T301
Test name
Test status
Simulation time 17104803392 ps
CPU time 371.18 seconds
Started Aug 25 03:36:05 AM UTC 24
Finished Aug 25 03:42:21 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282728586 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2282728586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_rx_oversample.918262272
Short name T435
Test name
Test status
Simulation time 2768078860 ps
CPU time 7.74 seconds
Started Aug 25 03:35:57 AM UTC 24
Finished Aug 25 03:36:06 AM UTC 24
Peak memory 207216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918262272 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.918262272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.3829004777
Short name T140
Test name
Test status
Simulation time 110320032575 ps
CPU time 36.31 seconds
Started Aug 25 03:36:01 AM UTC 24
Finished Aug 25 03:36:39 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829004777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3829004777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.1230665277
Short name T328
Test name
Test status
Simulation time 31116535822 ps
CPU time 17.17 seconds
Started Aug 25 03:36:00 AM UTC 24
Finished Aug 25 03:36:19 AM UTC 24
Peak memory 205104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230665277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1230665277
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_smoke.2147804221
Short name T334
Test name
Test status
Simulation time 627715025 ps
CPU time 4.5 seconds
Started Aug 25 03:35:53 AM UTC 24
Finished Aug 25 03:35:58 AM UTC 24
Peak memory 208212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147804221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2147804221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.2745212637
Short name T37
Test name
Test status
Simulation time 2105633758 ps
CPU time 35.4 seconds
Started Aug 25 03:36:07 AM UTC 24
Finished Aug 25 03:36:44 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2745212637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_
with_rand_reset.2745212637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.1863615449
Short name T340
Test name
Test status
Simulation time 6455024239 ps
CPU time 25.2 seconds
Started Aug 25 03:36:03 AM UTC 24
Finished Aug 25 03:36:29 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863615449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1863615449
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/8.uart_tx_rx.3955192907
Short name T281
Test name
Test status
Simulation time 107444045351 ps
CPU time 68.42 seconds
Started Aug 25 03:35:54 AM UTC 24
Finished Aug 25 03:37:04 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955192907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3955192907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/8.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/80.uart_fifo_reset.1721308615
Short name T952
Test name
Test status
Simulation time 18344466171 ps
CPU time 55.59 seconds
Started Aug 25 04:00:38 AM UTC 24
Finished Aug 25 04:01:35 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721308615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1721308615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/80.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.4015414941
Short name T948
Test name
Test status
Simulation time 12861837220 ps
CPU time 47.57 seconds
Started Aug 25 04:00:40 AM UTC 24
Finished Aug 25 04:01:29 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4015414941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all
_with_rand_reset.4015414941
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/81.uart_fifo_reset.2103301710
Short name T1169
Test name
Test status
Simulation time 245386338022 ps
CPU time 557.31 seconds
Started Aug 25 04:00:40 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103301710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2103301710
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/81.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.2755484412
Short name T943
Test name
Test status
Simulation time 24921854442 ps
CPU time 35.71 seconds
Started Aug 25 04:00:42 AM UTC 24
Finished Aug 25 04:01:20 AM UTC 24
Peak memory 219836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2755484412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all
_with_rand_reset.2755484412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/82.uart_fifo_reset.3300783632
Short name T971
Test name
Test status
Simulation time 143785527781 ps
CPU time 89.69 seconds
Started Aug 25 04:00:42 AM UTC 24
Finished Aug 25 04:02:15 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300783632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3300783632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/82.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.905689086
Short name T936
Test name
Test status
Simulation time 1423685387 ps
CPU time 22.33 seconds
Started Aug 25 04:00:43 AM UTC 24
Finished Aug 25 04:01:06 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=905689086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all_
with_rand_reset.905689086
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/83.uart_fifo_reset.1118976972
Short name T210
Test name
Test status
Simulation time 15735858084 ps
CPU time 48.2 seconds
Started Aug 25 04:00:46 AM UTC 24
Finished Aug 25 04:01:35 AM UTC 24
Peak memory 208356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118976972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1118976972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/83.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/84.uart_fifo_reset.947748020
Short name T1020
Test name
Test status
Simulation time 112843467431 ps
CPU time 147.93 seconds
Started Aug 25 04:00:52 AM UTC 24
Finished Aug 25 04:03:22 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947748020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.947748020
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/84.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.4180173380
Short name T959
Test name
Test status
Simulation time 4131970021 ps
CPU time 51.76 seconds
Started Aug 25 04:00:55 AM UTC 24
Finished Aug 25 04:01:48 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4180173380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all
_with_rand_reset.4180173380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/85.uart_fifo_reset.760895087
Short name T976
Test name
Test status
Simulation time 98846009407 ps
CPU time 81.23 seconds
Started Aug 25 04:00:56 AM UTC 24
Finished Aug 25 04:02:19 AM UTC 24
Peak memory 208548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760895087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.760895087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/85.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.2604948791
Short name T981
Test name
Test status
Simulation time 4736500101 ps
CPU time 86.55 seconds
Started Aug 25 04:00:56 AM UTC 24
Finished Aug 25 04:02:25 AM UTC 24
Peak memory 217848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2604948791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all
_with_rand_reset.2604948791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/86.uart_fifo_reset.4239325236
Short name T962
Test name
Test status
Simulation time 24342783335 ps
CPU time 56.34 seconds
Started Aug 25 04:00:57 AM UTC 24
Finished Aug 25 04:01:55 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239325236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.4239325236
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/86.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.1487108681
Short name T937
Test name
Test status
Simulation time 616927017 ps
CPU time 9.34 seconds
Started Aug 25 04:00:57 AM UTC 24
Finished Aug 25 04:01:08 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1487108681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all
_with_rand_reset.1487108681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/87.uart_fifo_reset.2191313367
Short name T218
Test name
Test status
Simulation time 12780000886 ps
CPU time 36.37 seconds
Started Aug 25 04:01:01 AM UTC 24
Finished Aug 25 04:01:39 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191313367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2191313367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/87.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.573999333
Short name T954
Test name
Test status
Simulation time 4713893358 ps
CPU time 33.83 seconds
Started Aug 25 04:01:04 AM UTC 24
Finished Aug 25 04:01:40 AM UTC 24
Peak memory 209160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=573999333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all_
with_rand_reset.573999333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/88.uart_fifo_reset.3363155273
Short name T979
Test name
Test status
Simulation time 96570357065 ps
CPU time 77.65 seconds
Started Aug 25 04:01:04 AM UTC 24
Finished Aug 25 04:02:24 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363155273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3363155273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/88.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.1320090586
Short name T965
Test name
Test status
Simulation time 5257680361 ps
CPU time 52.48 seconds
Started Aug 25 04:01:05 AM UTC 24
Finished Aug 25 04:02:00 AM UTC 24
Peak memory 225540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1320090586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all
_with_rand_reset.1320090586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/89.uart_fifo_reset.673705304
Short name T973
Test name
Test status
Simulation time 33678746995 ps
CPU time 67.18 seconds
Started Aug 25 04:01:07 AM UTC 24
Finished Aug 25 04:02:16 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673705304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.673705304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/89.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.3442965580
Short name T956
Test name
Test status
Simulation time 5784124348 ps
CPU time 35.73 seconds
Started Aug 25 04:01:07 AM UTC 24
Finished Aug 25 04:01:44 AM UTC 24
Peak memory 217484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3442965580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all
_with_rand_reset.3442965580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_alert_test.1314095111
Short name T441
Test name
Test status
Simulation time 14523590 ps
CPU time 0.85 seconds
Started Aug 25 03:36:30 AM UTC 24
Finished Aug 25 03:36:32 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314095111 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1314095111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.3778484605
Short name T141
Test name
Test status
Simulation time 101661933786 ps
CPU time 170.78 seconds
Started Aug 25 03:36:15 AM UTC 24
Finished Aug 25 03:39:09 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778484605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3778484605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_fifo_reset.819254980
Short name T329
Test name
Test status
Simulation time 133578770733 ps
CPU time 113.53 seconds
Started Aug 25 03:36:16 AM UTC 24
Finished Aug 25 03:38:12 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819254980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.819254980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_intr.4223820894
Short name T394
Test name
Test status
Simulation time 11518196947 ps
CPU time 39.26 seconds
Started Aug 25 03:36:18 AM UTC 24
Finished Aug 25 03:36:59 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223820894 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4223820894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.2090783651
Short name T576
Test name
Test status
Simulation time 109163406661 ps
CPU time 646.16 seconds
Started Aug 25 03:36:27 AM UTC 24
Finished Aug 25 03:47:22 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090783651 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2090783651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_loopback.3776188084
Short name T440
Test name
Test status
Simulation time 2436747586 ps
CPU time 4.88 seconds
Started Aug 25 03:36:26 AM UTC 24
Finished Aug 25 03:36:32 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776188084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3776188084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_noise_filter.1116933776
Short name T303
Test name
Test status
Simulation time 58916921268 ps
CPU time 190.75 seconds
Started Aug 25 03:36:19 AM UTC 24
Finished Aug 25 03:39:33 AM UTC 24
Peak memory 209024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116933776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1116933776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_perf.3220531733
Short name T665
Test name
Test status
Simulation time 27279183615 ps
CPU time 846.35 seconds
Started Aug 25 03:36:27 AM UTC 24
Finished Aug 25 03:50:44 AM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220531733 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3220531733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_rx_oversample.795440290
Short name T439
Test name
Test status
Simulation time 2746146439 ps
CPU time 6.34 seconds
Started Aug 25 03:36:18 AM UTC 24
Finished Aug 25 03:36:26 AM UTC 24
Peak memory 206968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795440290 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.795440290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.4039068910
Short name T175
Test name
Test status
Simulation time 17785014887 ps
CPU time 49.89 seconds
Started Aug 25 03:36:24 AM UTC 24
Finished Aug 25 03:37:15 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039068910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.4039068910
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.3364447104
Short name T361
Test name
Test status
Simulation time 39386727177 ps
CPU time 35.51 seconds
Started Aug 25 03:36:20 AM UTC 24
Finished Aug 25 03:36:57 AM UTC 24
Peak memory 207280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364447104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3364447104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_smoke.915197724
Short name T353
Test name
Test status
Simulation time 5865376564 ps
CPU time 12.23 seconds
Started Aug 25 03:36:12 AM UTC 24
Finished Aug 25 03:36:25 AM UTC 24
Peak memory 208072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915197724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.uart_smoke.915197724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_stress_all.1416295403
Short name T290
Test name
Test status
Simulation time 108611083774 ps
CPU time 83.21 seconds
Started Aug 25 03:36:30 AM UTC 24
Finished Aug 25 03:37:55 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416295403 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1416295403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.4168673091
Short name T39
Test name
Test status
Simulation time 2489985032 ps
CPU time 44.71 seconds
Started Aug 25 03:36:28 AM UTC 24
Finished Aug 25 03:37:14 AM UTC 24
Peak memory 218004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4168673091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_
with_rand_reset.4168673091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1145311708
Short name T341
Test name
Test status
Simulation time 6268127455 ps
CPU time 39.34 seconds
Started Aug 25 03:36:25 AM UTC 24
Finished Aug 25 03:37:05 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145311708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1145311708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/9.uart_tx_rx.181004800
Short name T277
Test name
Test status
Simulation time 28660227827 ps
CPU time 27.9 seconds
Started Aug 25 03:36:14 AM UTC 24
Finished Aug 25 03:36:43 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181004800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.181004800
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/9.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/90.uart_fifo_reset.3466510570
Short name T1000
Test name
Test status
Simulation time 87096907884 ps
CPU time 105.49 seconds
Started Aug 25 04:01:09 AM UTC 24
Finished Aug 25 04:02:57 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466510570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3466510570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/90.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.1969567226
Short name T946
Test name
Test status
Simulation time 9983207689 ps
CPU time 13.28 seconds
Started Aug 25 04:01:10 AM UTC 24
Finished Aug 25 04:01:24 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1969567226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all
_with_rand_reset.1969567226
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/91.uart_fifo_reset.1050442379
Short name T1061
Test name
Test status
Simulation time 54066562273 ps
CPU time 213.65 seconds
Started Aug 25 04:01:11 AM UTC 24
Finished Aug 25 04:04:48 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050442379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1050442379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/91.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.396986688
Short name T968
Test name
Test status
Simulation time 3226970344 ps
CPU time 53.13 seconds
Started Aug 25 04:01:15 AM UTC 24
Finished Aug 25 04:02:10 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=396986688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all_
with_rand_reset.396986688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/92.uart_fifo_reset.252522844
Short name T992
Test name
Test status
Simulation time 290481283954 ps
CPU time 84.36 seconds
Started Aug 25 04:01:17 AM UTC 24
Finished Aug 25 04:02:43 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252522844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.252522844
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/92.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.4139330512
Short name T951
Test name
Test status
Simulation time 724552522 ps
CPU time 13.47 seconds
Started Aug 25 04:01:18 AM UTC 24
Finished Aug 25 04:01:33 AM UTC 24
Peak memory 208468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4139330512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all
_with_rand_reset.4139330512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/93.uart_fifo_reset.942787986
Short name T219
Test name
Test status
Simulation time 51622805623 ps
CPU time 52.97 seconds
Started Aug 25 04:01:18 AM UTC 24
Finished Aug 25 04:02:13 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942787986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.942787986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/93.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.4254977124
Short name T990
Test name
Test status
Simulation time 3628717976 ps
CPU time 78.92 seconds
Started Aug 25 04:01:19 AM UTC 24
Finished Aug 25 04:02:40 AM UTC 24
Peak memory 217740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4254977124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all
_with_rand_reset.4254977124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/94.uart_fifo_reset.944463729
Short name T1080
Test name
Test status
Simulation time 109306209502 ps
CPU time 242.78 seconds
Started Aug 25 04:01:20 AM UTC 24
Finished Aug 25 04:05:27 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944463729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.944463729
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/94.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.1076613011
Short name T975
Test name
Test status
Simulation time 3082757629 ps
CPU time 54.53 seconds
Started Aug 25 04:01:21 AM UTC 24
Finished Aug 25 04:02:18 AM UTC 24
Peak memory 217736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1076613011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all
_with_rand_reset.1076613011
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/95.uart_fifo_reset.2275459061
Short name T1026
Test name
Test status
Simulation time 53060373525 ps
CPU time 137.23 seconds
Started Aug 25 04:01:23 AM UTC 24
Finished Aug 25 04:03:42 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275459061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2275459061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/95.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.3621353637
Short name T1027
Test name
Test status
Simulation time 6252546691 ps
CPU time 140.23 seconds
Started Aug 25 04:01:24 AM UTC 24
Finished Aug 25 04:03:47 AM UTC 24
Peak memory 220032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3621353637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all
_with_rand_reset.3621353637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/96.uart_fifo_reset.1802651999
Short name T978
Test name
Test status
Simulation time 26946942489 ps
CPU time 53.28 seconds
Started Aug 25 04:01:26 AM UTC 24
Finished Aug 25 04:02:21 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802651999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1802651999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/96.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.2044804858
Short name T980
Test name
Test status
Simulation time 3272186570 ps
CPU time 53.52 seconds
Started Aug 25 04:01:29 AM UTC 24
Finished Aug 25 04:02:24 AM UTC 24
Peak memory 217932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2044804858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all
_with_rand_reset.2044804858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/97.uart_fifo_reset.2575956675
Short name T200
Test name
Test status
Simulation time 78331054300 ps
CPU time 70 seconds
Started Aug 25 04:01:30 AM UTC 24
Finished Aug 25 04:02:42 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575956675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2575956675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/97.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.4051425556
Short name T972
Test name
Test status
Simulation time 5670613347 ps
CPU time 42.07 seconds
Started Aug 25 04:01:31 AM UTC 24
Finished Aug 25 04:02:15 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4051425556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all
_with_rand_reset.4051425556
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/98.uart_fifo_reset.251376410
Short name T993
Test name
Test status
Simulation time 81529712582 ps
CPU time 72.14 seconds
Started Aug 25 04:01:33 AM UTC 24
Finished Aug 25 04:02:47 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251376410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.251376410
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/98.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.4230580212
Short name T963
Test name
Test status
Simulation time 12102125276 ps
CPU time 19.83 seconds
Started Aug 25 04:01:34 AM UTC 24
Finished Aug 25 04:01:55 AM UTC 24
Peak memory 217592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4230580212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all
_with_rand_reset.4230580212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/99.uart_fifo_reset.4288251822
Short name T224
Test name
Test status
Simulation time 113173128918 ps
CPU time 62.05 seconds
Started Aug 25 04:01:36 AM UTC 24
Finished Aug 25 04:02:40 AM UTC 24
Peak memory 208476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288251822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4288251822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/99.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.758824339
Short name T1017
Test name
Test status
Simulation time 7424228621 ps
CPU time 101.71 seconds
Started Aug 25 04:01:36 AM UTC 24
Finished Aug 25 04:03:20 AM UTC 24
Peak memory 217544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=758824339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all_
with_rand_reset.758824339
Directory /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest
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