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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.50


Total test records in report: 1313
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T635 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_fifo_full.1118975080 Aug 27 04:53:19 AM UTC 24 Aug 27 04:55:55 AM UTC 24 85333303674 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.202605120 Aug 27 04:55:47 AM UTC 24 Aug 27 04:55:56 AM UTC 24 2479037524 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_noise_filter.296021693 Aug 27 04:55:10 AM UTC 24 Aug 27 04:56:04 AM UTC 24 79206164609 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.1560245770 Aug 27 04:54:38 AM UTC 24 Aug 27 04:56:07 AM UTC 24 69366611325 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_stress_all.771660555 Aug 27 04:39:28 AM UTC 24 Aug 27 04:56:08 AM UTC 24 429428572892 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_rx_oversample.2694888340 Aug 27 04:55:42 AM UTC 24 Aug 27 04:56:08 AM UTC 24 6645876955 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_alert_test.579097805 Aug 27 04:56:10 AM UTC 24 Aug 27 04:56:11 AM UTC 24 21108902 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.1251430755 Aug 27 04:46:26 AM UTC 24 Aug 27 04:56:14 AM UTC 24 66608440775 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_loopback.954263448 Aug 27 04:55:56 AM UTC 24 Aug 27 04:56:14 AM UTC 24 4212920890 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.1535830236 Aug 27 04:55:56 AM UTC 24 Aug 27 04:56:15 AM UTC 24 7689264930 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_tx_rx.3344152093 Aug 27 04:54:29 AM UTC 24 Aug 27 04:56:17 AM UTC 24 66857014557 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_intr.4119080842 Aug 27 04:55:45 AM UTC 24 Aug 27 04:56:17 AM UTC 24 42151445481 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_smoke.3428650463 Aug 27 04:56:13 AM UTC 24 Aug 27 04:56:18 AM UTC 24 646696571 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_rx_oversample.329368197 Aug 27 04:55:05 AM UTC 24 Aug 27 04:56:20 AM UTC 24 5716209559 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.257024681 Aug 27 04:52:25 AM UTC 24 Aug 27 04:56:22 AM UTC 24 56115155436 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.2136675233 Aug 27 04:56:09 AM UTC 24 Aug 27 04:56:26 AM UTC 24 1294057933 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.799143839 Aug 27 04:56:23 AM UTC 24 Aug 27 04:56:26 AM UTC 24 590957228 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_stress_all.682282462 Aug 27 04:49:43 AM UTC 24 Aug 27 04:56:28 AM UTC 24 73647552293 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_fifo_full.1206058795 Aug 27 04:52:39 AM UTC 24 Aug 27 04:56:28 AM UTC 24 239386634690 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.1823882325 Aug 27 04:55:23 AM UTC 24 Aug 27 04:56:30 AM UTC 24 284863577990 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.1991467296 Aug 27 04:56:28 AM UTC 24 Aug 27 04:56:31 AM UTC 24 971233482 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_loopback.1211349078 Aug 27 04:56:29 AM UTC 24 Aug 27 04:56:36 AM UTC 24 5710739391 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.1167065375 Aug 27 04:45:24 AM UTC 24 Aug 27 04:56:36 AM UTC 24 113606375020 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_fifo_full.583148428 Aug 27 04:56:15 AM UTC 24 Aug 27 04:56:36 AM UTC 24 50939328746 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_alert_test.2849605289 Aug 27 04:56:37 AM UTC 24 Aug 27 04:56:39 AM UTC 24 12566316 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_smoke.3080481238 Aug 27 04:56:37 AM UTC 24 Aug 27 04:56:39 AM UTC 24 87043494 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_intr.3668332007 Aug 27 04:56:19 AM UTC 24 Aug 27 04:56:41 AM UTC 24 36715892011 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_fifo_reset.3648912525 Aug 27 04:56:18 AM UTC 24 Aug 27 04:56:47 AM UTC 24 27403056284 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_stress_all.1474693549 Aug 27 04:55:36 AM UTC 24 Aug 27 04:56:49 AM UTC 24 169361136950 ps
T663 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.272625510 Aug 27 04:50:37 AM UTC 24 Aug 27 04:56:50 AM UTC 24 52283161107 ps
T664 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.621011233 Aug 27 04:50:08 AM UTC 24 Aug 27 04:56:58 AM UTC 24 100714342305 ps
T665 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_rx_oversample.3978665575 Aug 27 04:56:18 AM UTC 24 Aug 27 04:56:58 AM UTC 24 5020455637 ps
T666 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.2525629583 Aug 27 04:55:34 AM UTC 24 Aug 27 04:57:01 AM UTC 24 3176313197 ps
T667 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_noise_filter.2716289431 Aug 27 04:55:46 AM UTC 24 Aug 27 04:57:02 AM UTC 24 248411764769 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_stress_all.3473430077 Aug 27 04:54:23 AM UTC 24 Aug 27 04:57:07 AM UTC 24 323959868425 ps
T668 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.812627247 Aug 27 04:57:03 AM UTC 24 Aug 27 04:57:07 AM UTC 24 1142495819 ps
T669 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.334615527 Aug 27 04:56:27 AM UTC 24 Aug 27 04:57:08 AM UTC 24 71155716352 ps
T670 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_intr.3484341919 Aug 27 04:56:51 AM UTC 24 Aug 27 04:57:12 AM UTC 24 7412267834 ps
T671 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_rx_oversample.1568057903 Aug 27 04:56:50 AM UTC 24 Aug 27 04:57:14 AM UTC 24 7262170753 ps
T672 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.2602780839 Aug 27 04:51:59 AM UTC 24 Aug 27 04:57:14 AM UTC 24 112057770280 ps
T673 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_noise_filter.2613241867 Aug 27 04:52:48 AM UTC 24 Aug 27 04:57:15 AM UTC 24 84577314541 ps
T674 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_loopback.3275151895 Aug 27 04:57:07 AM UTC 24 Aug 27 04:57:15 AM UTC 24 2955776984 ps
T675 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_alert_test.416837069 Aug 27 04:57:15 AM UTC 24 Aug 27 04:57:16 AM UTC 24 12120827 ps
T676 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_fifo_full.1586255550 Aug 27 04:55:42 AM UTC 24 Aug 27 04:57:19 AM UTC 24 40331822632 ps
T677 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_perf.485614274 Aug 27 04:49:34 AM UTC 24 Aug 27 04:57:19 AM UTC 24 23879447035 ps
T678 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_smoke.3412445557 Aug 27 04:57:16 AM UTC 24 Aug 27 04:57:20 AM UTC 24 711376560 ps
T679 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_tx_rx.2919197528 Aug 27 04:56:15 AM UTC 24 Aug 27 04:57:20 AM UTC 24 27609665697 ps
T680 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_fifo_full.816192082 Aug 27 04:56:40 AM UTC 24 Aug 27 04:57:23 AM UTC 24 57473172289 ps
T681 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.1238484588 Aug 27 04:56:42 AM UTC 24 Aug 27 04:57:25 AM UTC 24 45253686212 ps
T682 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.4087172888 Aug 27 04:56:32 AM UTC 24 Aug 27 04:57:26 AM UTC 24 12619444239 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_fifo_reset.3622254778 Aug 27 04:52:42 AM UTC 24 Aug 27 04:57:26 AM UTC 24 100212368650 ps
T683 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_rx_oversample.3200208337 Aug 27 04:57:20 AM UTC 24 Aug 27 04:57:27 AM UTC 24 2453061947 ps
T684 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.3434831099 Aug 27 04:57:25 AM UTC 24 Aug 27 04:57:28 AM UTC 24 4606952414 ps
T685 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.1741005461 Aug 27 04:56:08 AM UTC 24 Aug 27 04:57:30 AM UTC 24 81452064450 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_fifo_full.574454862 Aug 27 04:54:58 AM UTC 24 Aug 27 04:57:32 AM UTC 24 180321276120 ps
T686 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.1199531913 Aug 27 04:56:59 AM UTC 24 Aug 27 04:57:38 AM UTC 24 28913973453 ps
T687 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_loopback.378499470 Aug 27 04:57:28 AM UTC 24 Aug 27 04:57:45 AM UTC 24 4300427212 ps
T688 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_alert_test.112209230 Aug 27 04:57:45 AM UTC 24 Aug 27 04:57:47 AM UTC 24 11791378 ps
T689 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.2378266428 Aug 27 04:57:28 AM UTC 24 Aug 27 04:57:49 AM UTC 24 7456401396 ps
T690 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_stress_all.3715124754 Aug 27 04:56:37 AM UTC 24 Aug 27 04:57:50 AM UTC 24 260952229584 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_fifo_reset.2679872052 Aug 27 04:56:47 AM UTC 24 Aug 27 04:57:51 AM UTC 24 40205090425 ps
T691 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.511629892 Aug 27 04:57:20 AM UTC 24 Aug 27 04:57:51 AM UTC 24 31613188900 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_noise_filter.2726421383 Aug 27 04:56:21 AM UTC 24 Aug 27 04:57:52 AM UTC 24 46667984973 ps
T692 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_smoke.1464486056 Aug 27 04:57:48 AM UTC 24 Aug 27 04:57:53 AM UTC 24 506613501 ps
T693 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_tx_rx.2544899475 Aug 27 04:56:39 AM UTC 24 Aug 27 04:57:54 AM UTC 24 41915296088 ps
T694 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_intr.3289430475 Aug 27 04:57:21 AM UTC 24 Aug 27 04:57:54 AM UTC 24 16089940888 ps
T695 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_stress_all.1744400920 Aug 27 04:49:01 AM UTC 24 Aug 27 04:57:56 AM UTC 24 203577679383 ps
T696 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.928199824 Aug 27 04:57:55 AM UTC 24 Aug 27 04:57:57 AM UTC 24 638718320 ps
T697 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_perf.1873791281 Aug 27 04:57:08 AM UTC 24 Aug 27 04:57:58 AM UTC 24 8299213031 ps
T698 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.1311315625 Aug 27 04:57:58 AM UTC 24 Aug 27 04:58:02 AM UTC 24 1650476549 ps
T699 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_loopback.3185801156 Aug 27 04:57:59 AM UTC 24 Aug 27 04:58:02 AM UTC 24 1423065644 ps
T700 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.2222064502 Aug 27 04:57:33 AM UTC 24 Aug 27 04:58:04 AM UTC 24 18379207420 ps
T701 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_rx_oversample.3717788207 Aug 27 04:57:54 AM UTC 24 Aug 27 04:58:05 AM UTC 24 2127148381 ps
T702 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.1986570935 Aug 27 04:57:02 AM UTC 24 Aug 27 04:58:07 AM UTC 24 21552241238 ps
T703 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_alert_test.1625798415 Aug 27 04:58:07 AM UTC 24 Aug 27 04:58:09 AM UTC 24 12535734 ps
T704 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.2062190904 Aug 27 04:52:56 AM UTC 24 Aug 27 04:58:10 AM UTC 24 250171877330 ps
T705 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_stress_all.179626714 Aug 27 04:53:10 AM UTC 24 Aug 27 04:58:11 AM UTC 24 385421509699 ps
T706 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_fifo_full.3232561697 Aug 27 04:57:17 AM UTC 24 Aug 27 04:58:17 AM UTC 24 75058669106 ps
T707 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_smoke.3770924745 Aug 27 04:58:11 AM UTC 24 Aug 27 04:58:18 AM UTC 24 5587983148 ps
T708 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.204428988 Aug 27 04:58:05 AM UTC 24 Aug 27 04:58:23 AM UTC 24 7487277709 ps
T709 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_noise_filter.3516925014 Aug 27 04:56:59 AM UTC 24 Aug 27 04:58:31 AM UTC 24 39232420937 ps
T710 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.4218995503 Aug 27 04:57:12 AM UTC 24 Aug 27 04:58:38 AM UTC 24 19216333559 ps
T711 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_intr.1751140744 Aug 27 04:54:35 AM UTC 24 Aug 27 04:58:38 AM UTC 24 107587747157 ps
T712 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_rx_oversample.3107355459 Aug 27 04:58:24 AM UTC 24 Aug 27 04:58:38 AM UTC 24 7825944707 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_stress_all.2737103187 Aug 27 04:57:38 AM UTC 24 Aug 27 04:58:41 AM UTC 24 57177719909 ps
T713 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.3609254520 Aug 27 04:58:38 AM UTC 24 Aug 27 04:58:42 AM UTC 24 713290112 ps
T714 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.1335861199 Aug 27 04:58:42 AM UTC 24 Aug 27 04:58:44 AM UTC 24 1042910715 ps
T715 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_stress_all.1984771909 Aug 27 04:52:31 AM UTC 24 Aug 27 04:58:46 AM UTC 24 149081960942 ps
T716 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.3683317944 Aug 27 04:42:56 AM UTC 24 Aug 27 04:58:48 AM UTC 24 174992174806 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_fifo_reset.2279251978 Aug 27 04:58:18 AM UTC 24 Aug 27 04:58:55 AM UTC 24 33240039245 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_stress_all.2706414217 Aug 27 04:56:10 AM UTC 24 Aug 27 04:58:57 AM UTC 24 376247501329 ps
T717 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_intr.3116725084 Aug 27 04:52:46 AM UTC 24 Aug 27 04:58:59 AM UTC 24 219219945948 ps
T718 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_alert_test.3843499461 Aug 27 04:58:58 AM UTC 24 Aug 27 04:59:00 AM UTC 24 11466518 ps
T719 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_fifo_reset.3622316121 Aug 27 04:54:30 AM UTC 24 Aug 27 04:59:05 AM UTC 24 130986575182 ps
T720 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_tx_rx.732574542 Aug 27 04:57:16 AM UTC 24 Aug 27 04:59:08 AM UTC 24 130398848297 ps
T721 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_loopback.4164790071 Aug 27 04:58:43 AM UTC 24 Aug 27 04:59:13 AM UTC 24 9593979406 ps
T722 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_smoke.1930766427 Aug 27 04:59:00 AM UTC 24 Aug 27 04:59:16 AM UTC 24 6288825427 ps
T723 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_noise_filter.3618931780 Aug 27 04:57:55 AM UTC 24 Aug 27 04:59:17 AM UTC 24 27763557841 ps
T724 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.4174099538 Aug 27 04:59:05 AM UTC 24 Aug 27 04:59:19 AM UTC 24 30889641087 ps
T725 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.2584146892 Aug 27 04:58:39 AM UTC 24 Aug 27 04:59:19 AM UTC 24 41154026133 ps
T726 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_perf.151748424 Aug 27 04:56:05 AM UTC 24 Aug 27 04:59:25 AM UTC 24 11738531672 ps
T727 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_noise_filter.3120593689 Aug 27 04:57:24 AM UTC 24 Aug 27 04:59:31 AM UTC 24 305712343450 ps
T728 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_perf.3604030354 Aug 27 04:56:29 AM UTC 24 Aug 27 04:59:32 AM UTC 24 10769888317 ps
T729 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_stress_all.2780772597 Aug 27 04:54:45 AM UTC 24 Aug 27 04:59:35 AM UTC 24 257157265900 ps
T730 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_rx_oversample.2010340538 Aug 27 04:59:14 AM UTC 24 Aug 27 04:59:37 AM UTC 24 5401172577 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_fifo_reset.1124321596 Aug 27 04:57:52 AM UTC 24 Aug 27 04:59:38 AM UTC 24 96870900942 ps
T731 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.680570207 Aug 27 04:59:26 AM UTC 24 Aug 27 04:59:42 AM UTC 24 5906948299 ps
T732 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_tx_rx.2744008147 Aug 27 04:59:01 AM UTC 24 Aug 27 04:59:42 AM UTC 24 41802053013 ps
T733 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_alert_test.2151249861 Aug 27 04:59:43 AM UTC 24 Aug 27 04:59:45 AM UTC 24 33509187 ps
T734 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.3869720258 Aug 27 04:58:49 AM UTC 24 Aug 27 04:59:45 AM UTC 24 11013417377 ps
T735 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.333089670 Aug 27 04:49:35 AM UTC 24 Aug 27 04:59:46 AM UTC 24 123375792418 ps
T736 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_intr.4201646656 Aug 27 04:58:31 AM UTC 24 Aug 27 04:59:49 AM UTC 24 41418726032 ps
T737 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.4030712383 Aug 27 04:57:26 AM UTC 24 Aug 27 04:59:52 AM UTC 24 63285980234 ps
T738 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.3949209562 Aug 27 04:59:20 AM UTC 24 Aug 27 04:59:54 AM UTC 24 32499168174 ps
T739 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_intr.1894471970 Aug 27 04:57:55 AM UTC 24 Aug 27 04:59:54 AM UTC 24 55530971249 ps
T740 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.1879411747 Aug 27 04:57:51 AM UTC 24 Aug 27 04:59:56 AM UTC 24 37108507907 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_fifo_reset.1433472207 Aug 27 04:55:42 AM UTC 24 Aug 27 05:00:05 AM UTC 24 95467526318 ps
T741 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_smoke.1666757614 Aug 27 04:59:43 AM UTC 24 Aug 27 05:00:07 AM UTC 24 5537643378 ps
T742 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_fifo_full.3417500346 Aug 27 04:58:12 AM UTC 24 Aug 27 05:00:09 AM UTC 24 143007122986 ps
T743 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_tx_rx.325837258 Aug 27 04:57:50 AM UTC 24 Aug 27 05:00:10 AM UTC 24 188854573034 ps
T744 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_loopback.1322266156 Aug 27 05:00:08 AM UTC 24 Aug 27 05:00:10 AM UTC 24 43970177 ps
T745 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_loopback.3221558299 Aug 27 04:59:32 AM UTC 24 Aug 27 05:00:10 AM UTC 24 7445615549 ps
T746 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1883648752 Aug 27 05:00:07 AM UTC 24 Aug 27 05:00:11 AM UTC 24 1201367002 ps
T747 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_alert_test.1171883722 Aug 27 05:00:11 AM UTC 24 Aug 27 05:00:13 AM UTC 24 35281647 ps
T748 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.1087242749 Aug 27 04:59:20 AM UTC 24 Aug 27 05:00:14 AM UTC 24 29155463825 ps
T749 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_smoke.3647469004 Aug 27 05:00:13 AM UTC 24 Aug 27 05:00:20 AM UTC 24 805082138 ps
T750 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_fifo_reset.2531178541 Aug 27 04:57:20 AM UTC 24 Aug 27 05:00:22 AM UTC 24 361471805278 ps
T751 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.3937592429 Aug 27 04:54:44 AM UTC 24 Aug 27 05:00:27 AM UTC 24 103669294368 ps
T752 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.431751260 Aug 27 04:44:53 AM UTC 24 Aug 27 05:00:28 AM UTC 24 87243488955 ps
T753 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.1523465446 Aug 27 04:59:56 AM UTC 24 Aug 27 05:00:28 AM UTC 24 37608256851 ps
T754 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_fifo_full.3736870113 Aug 27 04:59:46 AM UTC 24 Aug 27 05:00:28 AM UTC 24 103688018437 ps
T755 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_tx_rx.4247039897 Aug 27 05:00:15 AM UTC 24 Aug 27 05:00:32 AM UTC 24 37087882228 ps
T756 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_intr.4275779919 Aug 27 04:59:54 AM UTC 24 Aug 27 05:00:32 AM UTC 24 38967467409 ps
T757 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.635455295 Aug 27 05:00:11 AM UTC 24 Aug 27 05:00:37 AM UTC 24 5684439366 ps
T758 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.3326770948 Aug 27 04:59:38 AM UTC 24 Aug 27 05:00:39 AM UTC 24 9408715683 ps
T759 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_noise_filter.1712298959 Aug 27 04:59:18 AM UTC 24 Aug 27 05:00:43 AM UTC 24 152042153325 ps
T760 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.2828335679 Aug 27 05:00:37 AM UTC 24 Aug 27 05:00:44 AM UTC 24 1059412401 ps
T761 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_noise_filter.3038597476 Aug 27 04:58:38 AM UTC 24 Aug 27 05:00:45 AM UTC 24 60849919614 ps
T762 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_rx_oversample.112330033 Aug 27 05:00:29 AM UTC 24 Aug 27 05:00:46 AM UTC 24 5081719116 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_loopback.457021685 Aug 27 05:00:39 AM UTC 24 Aug 27 05:00:46 AM UTC 24 7611574730 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_alert_test.742498850 Aug 27 05:00:47 AM UTC 24 Aug 27 05:00:49 AM UTC 24 12910673 ps
T765 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.2949340809 Aug 27 05:00:23 AM UTC 24 Aug 27 05:00:50 AM UTC 24 14996373482 ps
T766 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_smoke.1587113722 Aug 27 05:00:50 AM UTC 24 Aug 27 05:00:53 AM UTC 24 486085672 ps
T767 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.760378683 Aug 27 04:57:08 AM UTC 24 Aug 27 05:00:58 AM UTC 24 45855823605 ps
T768 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_fifo_reset.641863576 Aug 27 05:00:28 AM UTC 24 Aug 27 05:01:04 AM UTC 24 32068008599 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_perf.2690593519 Aug 27 04:50:36 AM UTC 24 Aug 27 05:01:06 AM UTC 24 10149035680 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.1931678239 Aug 27 05:00:07 AM UTC 24 Aug 27 05:01:08 AM UTC 24 249359743857 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_rx_oversample.2037961146 Aug 27 04:59:52 AM UTC 24 Aug 27 05:01:11 AM UTC 24 7147943639 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_stress_all.2156467507 Aug 27 05:00:11 AM UTC 24 Aug 27 05:01:11 AM UTC 24 35859640209 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_rx_oversample.3896423561 Aug 27 05:01:06 AM UTC 24 Aug 27 05:01:14 AM UTC 24 1914609626 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.781143316 Aug 27 04:53:07 AM UTC 24 Aug 27 05:01:15 AM UTC 24 124342187763 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.2010374394 Aug 27 04:55:32 AM UTC 24 Aug 27 05:01:17 AM UTC 24 292766676860 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_fifo_reset.180741852 Aug 27 04:59:49 AM UTC 24 Aug 27 05:01:18 AM UTC 24 61886924357 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.1340639550 Aug 27 05:01:12 AM UTC 24 Aug 27 05:01:19 AM UTC 24 3029600795 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_stress_all.308389586 Aug 27 04:58:56 AM UTC 24 Aug 27 05:01:21 AM UTC 24 473038795510 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.728670125 Aug 27 05:01:16 AM UTC 24 Aug 27 05:01:22 AM UTC 24 856005878 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_loopback.3379537689 Aug 27 05:01:18 AM UTC 24 Aug 27 05:01:22 AM UTC 24 6613154477 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_alert_test.4221366994 Aug 27 05:01:23 AM UTC 24 Aug 27 05:01:25 AM UTC 24 13164373 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_noise_filter.2209970735 Aug 27 05:00:29 AM UTC 24 Aug 27 05:01:26 AM UTC 24 135441589963 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.1304766652 Aug 27 04:59:47 AM UTC 24 Aug 27 05:01:30 AM UTC 24 61396920936 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_fifo_reset.762552886 Aug 27 05:01:04 AM UTC 24 Aug 27 05:01:32 AM UTC 24 29117819302 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.966487722 Aug 27 04:55:42 AM UTC 24 Aug 27 05:01:33 AM UTC 24 123637844614 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_intr.3246159885 Aug 27 05:01:09 AM UTC 24 Aug 27 05:01:34 AM UTC 24 16401920347 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.3891291020 Aug 27 04:56:31 AM UTC 24 Aug 27 05:01:39 AM UTC 24 174142326433 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_stress_all.1607247190 Aug 27 04:48:22 AM UTC 24 Aug 27 05:01:40 AM UTC 24 648002678877 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.3544279516 Aug 27 04:48:57 AM UTC 24 Aug 27 05:01:42 AM UTC 24 117507162592 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_noise_filter.3592955255 Aug 27 05:01:12 AM UTC 24 Aug 27 05:01:42 AM UTC 24 58335329257 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_smoke.1684749750 Aug 27 05:01:25 AM UTC 24 Aug 27 05:01:44 AM UTC 24 6065765613 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.2732679808 Aug 27 05:00:33 AM UTC 24 Aug 27 05:01:46 AM UTC 24 128140245905 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.215874809 Aug 27 05:00:33 AM UTC 24 Aug 27 05:01:46 AM UTC 24 41491656628 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.1404747381 Aug 27 05:01:42 AM UTC 24 Aug 27 05:01:46 AM UTC 24 4402538111 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_noise_filter.684469311 Aug 27 04:59:55 AM UTC 24 Aug 27 05:01:49 AM UTC 24 123520938967 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_loopback.1234065201 Aug 27 05:01:47 AM UTC 24 Aug 27 05:01:50 AM UTC 24 2525169253 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.3375989838 Aug 27 05:01:45 AM UTC 24 Aug 27 05:01:51 AM UTC 24 5131384727 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_stress_all.204566739 Aug 27 04:57:15 AM UTC 24 Aug 27 05:01:51 AM UTC 24 288992466455 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_tx_rx.1846589270 Aug 27 05:01:27 AM UTC 24 Aug 27 05:01:52 AM UTC 24 11028978354 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_alert_test.557628873 Aug 27 05:01:52 AM UTC 24 Aug 27 05:01:54 AM UTC 24 12875170 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_smoke.2595113344 Aug 27 05:01:52 AM UTC 24 Aug 27 05:01:54 AM UTC 24 87055608 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_fifo_full.2141512283 Aug 27 05:01:31 AM UTC 24 Aug 27 05:01:54 AM UTC 24 128092816588 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_rx_oversample.2315023688 Aug 27 05:01:35 AM UTC 24 Aug 27 05:01:56 AM UTC 24 2943388193 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.1030843798 Aug 27 05:01:33 AM UTC 24 Aug 27 05:02:02 AM UTC 24 44174098669 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.1183818727 Aug 27 05:01:50 AM UTC 24 Aug 27 05:02:05 AM UTC 24 924648591 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_fifo_reset.995125004 Aug 27 05:01:34 AM UTC 24 Aug 27 05:02:05 AM UTC 24 170567925784 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1639816078 Aug 27 05:00:46 AM UTC 24 Aug 27 05:02:05 AM UTC 24 8683852043 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.2308018564 Aug 27 04:58:18 AM UTC 24 Aug 27 05:02:06 AM UTC 24 75214189892 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_noise_filter.3261067887 Aug 27 05:01:40 AM UTC 24 Aug 27 05:02:07 AM UTC 24 62909623003 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_rx_oversample.2455618431 Aug 27 05:01:57 AM UTC 24 Aug 27 05:02:08 AM UTC 24 1699877893 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_tx_rx.4223938407 Aug 27 04:59:46 AM UTC 24 Aug 27 05:02:08 AM UTC 24 65649133507 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_perf.4126347359 Aug 27 04:58:45 AM UTC 24 Aug 27 05:02:12 AM UTC 24 3701219309 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.842904955 Aug 27 05:02:07 AM UTC 24 Aug 27 05:02:12 AM UTC 24 1356757047 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_fifo_reset.983288164 Aug 27 04:59:09 AM UTC 24 Aug 27 05:02:14 AM UTC 24 71735411912 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.3250455697 Aug 27 05:01:22 AM UTC 24 Aug 27 05:02:16 AM UTC 24 9257492111 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_alert_test.2435108687 Aug 27 05:02:15 AM UTC 24 Aug 27 05:02:17 AM UTC 24 106675441 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_tx_rx.1861192296 Aug 27 05:01:53 AM UTC 24 Aug 27 05:02:18 AM UTC 24 30876386126 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_intr.383694024 Aug 27 05:00:29 AM UTC 24 Aug 27 05:02:22 AM UTC 24 203522699852 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.2609926889 Aug 27 05:02:06 AM UTC 24 Aug 27 05:02:23 AM UTC 24 6062374965 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.4150374596 Aug 27 05:01:55 AM UTC 24 Aug 27 05:02:27 AM UTC 24 17765006480 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_loopback.2188389294 Aug 27 05:02:08 AM UTC 24 Aug 27 05:02:31 AM UTC 24 5173348694 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_tx_rx.3582818297 Aug 27 05:02:18 AM UTC 24 Aug 27 05:02:32 AM UTC 24 9648439104 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.1489826306 Aug 27 05:02:12 AM UTC 24 Aug 27 05:02:32 AM UTC 24 6772571267 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_intr.2542794917 Aug 27 05:02:04 AM UTC 24 Aug 27 05:02:33 AM UTC 24 62122009411 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_fifo_reset.416629816 Aug 27 05:01:55 AM UTC 24 Aug 27 05:02:34 AM UTC 24 60911259698 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.2743506154 Aug 27 05:02:23 AM UTC 24 Aug 27 05:02:35 AM UTC 24 13155314812 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_fifo_full.686971901 Aug 27 05:00:22 AM UTC 24 Aug 27 05:02:38 AM UTC 24 137570207782 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.1562982050 Aug 27 05:02:33 AM UTC 24 Aug 27 05:02:38 AM UTC 24 2909372110 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.85443697 Aug 27 04:57:57 AM UTC 24 Aug 27 05:02:38 AM UTC 24 168128918009 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_noise_filter.898781057 Aug 27 05:02:06 AM UTC 24 Aug 27 05:02:41 AM UTC 24 19254391220 ps
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