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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.50


Total test records in report: 1313
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T1254 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1079465791 Aug 27 05:15:10 AM UTC 24 Aug 27 05:15:13 AM UTC 24 120655932 ps
T1255 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.198810964 Aug 27 05:15:10 AM UTC 24 Aug 27 05:15:13 AM UTC 24 71786372 ps
T1256 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3811529780 Aug 27 05:15:10 AM UTC 24 Aug 27 05:15:13 AM UTC 24 166488069 ps
T1257 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3639934938 Aug 27 05:15:10 AM UTC 24 Aug 27 05:15:13 AM UTC 24 163591611 ps
T1258 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.1772569859 Aug 27 05:15:10 AM UTC 24 Aug 27 05:15:13 AM UTC 24 77661769 ps
T1259 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.881258874 Aug 27 05:15:10 AM UTC 24 Aug 27 05:15:14 AM UTC 24 49643327 ps
T1260 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.4238116049 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:23 AM UTC 24 11056301 ps
T1261 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.714928239 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:23 AM UTC 24 18208355 ps
T1262 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.1598982605 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:23 AM UTC 24 47375568 ps
T1263 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.2733199896 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:23 AM UTC 24 14262899 ps
T1264 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.4247192827 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:23 AM UTC 24 12893354 ps
T1265 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.1445524926 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:23 AM UTC 24 20059603 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2498722341 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:23 AM UTC 24 58818043 ps
T1266 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1812434084 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:23 AM UTC 24 25968962 ps
T1267 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.950480386 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:23 AM UTC 24 30284524 ps
T1268 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.1957973836 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 15578211 ps
T1269 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2721952205 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:24 AM UTC 24 87133091 ps
T1270 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1078665150 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:24 AM UTC 24 21157593 ps
T1271 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3207769564 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:24 AM UTC 24 47074671 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.585084937 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 29963789 ps
T1272 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2199791563 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 23560979 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.3603459507 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 34130386 ps
T1273 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3578769217 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:24 AM UTC 24 25559742 ps
T1274 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.3650844181 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 11211102 ps
T1275 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.905731015 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 13862790 ps
T1276 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.4186053115 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 26151150 ps
T1277 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2355397482 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:24 AM UTC 24 33783912 ps
T1278 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.1200898869 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 19648883 ps
T1279 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3923070670 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 194828388 ps
T1280 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2730309777 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 31178099 ps
T1281 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.3052995242 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 974263325 ps
T1282 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.2543595417 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 378430714 ps
T1283 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.758709145 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 102758661 ps
T1284 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2368013864 Aug 27 05:15:22 AM UTC 24 Aug 27 05:15:24 AM UTC 24 30515467 ps
T1285 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.888338578 Aug 27 05:15:21 AM UTC 24 Aug 27 05:15:24 AM UTC 24 35155585 ps
T1286 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3961986953 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 37374213 ps
T1287 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.988495121 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 18362323 ps
T1288 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.2626263092 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 13143777 ps
T1289 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.3983462483 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 33385086 ps
T1290 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1090577453 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 14976682 ps
T1291 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.2411214067 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 29061631 ps
T1292 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.1418527693 Aug 27 05:15:35 AM UTC 24 Aug 27 05:15:36 AM UTC 24 13047265 ps
T1293 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.2478195374 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 27884234 ps
T1294 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.1931530045 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 103052767 ps
T1295 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.3652015566 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 134710847 ps
T1296 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.2019532298 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 57611931 ps
T1297 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.3769092383 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 34999689 ps
T1298 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.3923794929 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 15834298 ps
T1299 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2535323645 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 66746937 ps
T1300 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.590130588 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 12640730 ps
T1301 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.996808844 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 33279672 ps
T1302 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.174663477 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 36968846 ps
T1303 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.907907408 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 16463396 ps
T1304 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.267737708 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 17409197 ps
T1305 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2812935923 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 15090858 ps
T1306 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.2365958391 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 42824322 ps
T1307 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1806094143 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 11834277 ps
T1308 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3749403233 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 19604439 ps
T1309 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2312678988 Aug 27 05:15:35 AM UTC 24 Aug 27 05:15:36 AM UTC 24 13896662 ps
T1310 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1158030483 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 13691285 ps
T1311 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3331754363 Aug 27 05:15:35 AM UTC 24 Aug 27 05:15:36 AM UTC 24 15572330 ps
T1312 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.2090378304 Aug 27 05:15:34 AM UTC 24 Aug 27 05:15:36 AM UTC 24 15247946 ps
T1313 /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.77650949 Aug 27 05:15:35 AM UTC 24 Aug 27 05:15:36 AM UTC 24 13711945 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.849997556
Short name T9
Test name
Test status
Simulation time 6341986771 ps
CPU time 43.07 seconds
Started Aug 27 04:34:48 AM UTC 24
Finished Aug 27 04:35:33 AM UTC 24
Peak memory 217940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=849997556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_w
ith_rand_reset.849997556
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_fifo_reset.4235698529
Short name T12
Test name
Test status
Simulation time 29019426660 ps
CPU time 71.74 seconds
Started Aug 27 04:34:43 AM UTC 24
Finished Aug 27 04:35:56 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235698529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.4235698529
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_stress_all.2680015922
Short name T96
Test name
Test status
Simulation time 335029927438 ps
CPU time 242.98 seconds
Started Aug 27 04:38:53 AM UTC 24
Finished Aug 27 04:42:59 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680015922 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2680015922
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.1711352690
Short name T268
Test name
Test status
Simulation time 106035642965 ps
CPU time 254.68 seconds
Started Aug 27 04:37:00 AM UTC 24
Finished Aug 27 04:41:18 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711352690 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1711352690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_stress_all.3412482512
Short name T285
Test name
Test status
Simulation time 381133717188 ps
CPU time 563.54 seconds
Started Aug 27 04:34:49 AM UTC 24
Finished Aug 27 04:44:20 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412482512 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3412482512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.4008658435
Short name T11
Test name
Test status
Simulation time 33859762556 ps
CPU time 39.88 seconds
Started Aug 27 04:34:58 AM UTC 24
Finished Aug 27 04:35:39 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008658435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4008658435
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_perf.4244307782
Short name T280
Test name
Test status
Simulation time 26683136811 ps
CPU time 132.45 seconds
Started Aug 27 04:38:42 AM UTC 24
Finished Aug 27 04:40:57 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244307782 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.4244307782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_intr.592842568
Short name T93
Test name
Test status
Simulation time 87066793920 ps
CPU time 88.48 seconds
Started Aug 27 04:37:47 AM UTC 24
Finished Aug 27 04:39:18 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592842568 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.592842568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_fifo_full.63446717
Short name T108
Test name
Test status
Simulation time 118263676314 ps
CPU time 89.2 seconds
Started Aug 27 04:37:10 AM UTC 24
Finished Aug 27 04:38:42 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63446717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.63446717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.2167560959
Short name T295
Test name
Test status
Simulation time 128672399486 ps
CPU time 241.47 seconds
Started Aug 27 04:37:12 AM UTC 24
Finished Aug 27 04:41:16 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167560959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2167560959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_sec_cm.3381613213
Short name T4
Test name
Test status
Simulation time 781127869 ps
CPU time 1.74 seconds
Started Aug 27 04:34:50 AM UTC 24
Finished Aug 27 04:34:53 AM UTC 24
Peak memory 237796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381613213 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3381613213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_stress_all.439393513
Short name T91
Test name
Test status
Simulation time 141439041287 ps
CPU time 200.96 seconds
Started Aug 27 04:43:26 AM UTC 24
Finished Aug 27 04:46:50 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439393513 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.439393513
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_tx_rx.1874226423
Short name T254
Test name
Test status
Simulation time 193628191985 ps
CPU time 120.92 seconds
Started Aug 27 04:37:08 AM UTC 24
Finished Aug 27 04:39:12 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874226423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1874226423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_fifo_full.569351493
Short name T134
Test name
Test status
Simulation time 52527497633 ps
CPU time 99.96 seconds
Started Aug 27 04:41:21 AM UTC 24
Finished Aug 27 04:43:03 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569351493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.569351493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.767633346
Short name T34
Test name
Test status
Simulation time 4893802943 ps
CPU time 92.73 seconds
Started Aug 27 04:37:01 AM UTC 24
Finished Aug 27 04:38:36 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=767633346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_w
ith_rand_reset.767633346
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.137009825
Short name T53
Test name
Test status
Simulation time 14399192 ps
CPU time 0.87 seconds
Started Aug 27 05:14:54 AM UTC 24
Finished Aug 27 05:14:56 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137009825 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.137009825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.993738516
Short name T260
Test name
Test status
Simulation time 96548897679 ps
CPU time 199.7 seconds
Started Aug 27 04:37:25 AM UTC 24
Finished Aug 27 04:40:48 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993738516 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.993738516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.1535366520
Short name T306
Test name
Test status
Simulation time 111055699690 ps
CPU time 300.57 seconds
Started Aug 27 04:43:16 AM UTC 24
Finished Aug 27 04:48:20 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535366520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1535366520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_intr.899715288
Short name T87
Test name
Test status
Simulation time 62191829808 ps
CPU time 133.38 seconds
Started Aug 27 04:39:13 AM UTC 24
Finished Aug 27 04:41:29 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899715288 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.899715288
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_fifo_reset.1010028400
Short name T19
Test name
Test status
Simulation time 148096259308 ps
CPU time 151.25 seconds
Started Aug 27 04:35:57 AM UTC 24
Finished Aug 27 04:38:31 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010028400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1010028400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_perf.244583057
Short name T340
Test name
Test status
Simulation time 28013143554 ps
CPU time 673.47 seconds
Started Aug 27 04:35:40 AM UTC 24
Finished Aug 27 04:47:01 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244583057 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.244583057
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.4188696275
Short name T18
Test name
Test status
Simulation time 162013747430 ps
CPU time 148.06 seconds
Started Aug 27 04:34:43 AM UTC 24
Finished Aug 27 04:37:13 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188696275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.4188696275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.3169884792
Short name T119
Test name
Test status
Simulation time 134163961741 ps
CPU time 351.29 seconds
Started Aug 27 04:34:44 AM UTC 24
Finished Aug 27 04:40:40 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169884792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3169884792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_fifo_reset.1174999782
Short name T175
Test name
Test status
Simulation time 75138808791 ps
CPU time 86.87 seconds
Started Aug 27 04:40:30 AM UTC 24
Finished Aug 27 04:41:59 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174999782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1174999782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.757226410
Short name T376
Test name
Test status
Simulation time 108595215161 ps
CPU time 359.2 seconds
Started Aug 27 04:39:25 AM UTC 24
Finished Aug 27 04:45:29 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757226410 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.757226410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.384080776
Short name T77
Test name
Test status
Simulation time 177989449 ps
CPU time 1.51 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384080776 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.384080776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_fifo_full.3284779078
Short name T142
Test name
Test status
Simulation time 157163771068 ps
CPU time 311.22 seconds
Started Aug 27 04:46:37 AM UTC 24
Finished Aug 27 04:51:53 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284779078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3284779078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.3490404789
Short name T20
Test name
Test status
Simulation time 1485112378 ps
CPU time 17.28 seconds
Started Aug 27 04:36:26 AM UTC 24
Finished Aug 27 04:36:45 AM UTC 24
Peak memory 217864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3490404789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_
with_rand_reset.3490404789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_fifo_full.3581659639
Short name T28
Test name
Test status
Simulation time 134035585695 ps
CPU time 63.06 seconds
Started Aug 27 04:35:55 AM UTC 24
Finished Aug 27 04:37:00 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581659639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3581659639
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.2293663972
Short name T316
Test name
Test status
Simulation time 137694203218 ps
CPU time 813.6 seconds
Started Aug 27 04:37:17 AM UTC 24
Finished Aug 27 04:51:00 AM UTC 24
Peak memory 212156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293663972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2293663972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_alert_test.1795225272
Short name T6
Test name
Test status
Simulation time 12494071 ps
CPU time 0.85 seconds
Started Aug 27 04:34:54 AM UTC 24
Finished Aug 27 04:34:56 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795225272 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1795225272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_stress_all.813855813
Short name T125
Test name
Test status
Simulation time 83897076716 ps
CPU time 72.97 seconds
Started Aug 27 04:41:47 AM UTC 24
Finished Aug 27 04:43:02 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813855813 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.813855813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2039472765
Short name T109
Test name
Test status
Simulation time 37341637664 ps
CPU time 74.11 seconds
Started Aug 27 04:39:02 AM UTC 24
Finished Aug 27 04:40:18 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039472765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2039472765
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_fifo_reset.2989783867
Short name T176
Test name
Test status
Simulation time 119625603311 ps
CPU time 248.53 seconds
Started Aug 27 04:40:57 AM UTC 24
Finished Aug 27 04:45:09 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989783867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2989783867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.1066082230
Short name T146
Test name
Test status
Simulation time 39945428194 ps
CPU time 72.11 seconds
Started Aug 27 04:42:00 AM UTC 24
Finished Aug 27 04:43:14 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066082230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1066082230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_fifo_reset.2066295846
Short name T151
Test name
Test status
Simulation time 209364699985 ps
CPU time 78.17 seconds
Started Aug 27 04:48:38 AM UTC 24
Finished Aug 27 04:49:58 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066295846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2066295846
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.1869466946
Short name T360
Test name
Test status
Simulation time 19216451145 ps
CPU time 143.82 seconds
Started Aug 27 04:41:47 AM UTC 24
Finished Aug 27 04:44:14 AM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1869466946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all
_with_rand_reset.1869466946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.2929858984
Short name T74
Test name
Test status
Simulation time 304351965 ps
CPU time 1.36 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929858984 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2929858984
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_fifo_full.701309123
Short name T126
Test name
Test status
Simulation time 31074746681 ps
CPU time 63.58 seconds
Started Aug 27 04:39:01 AM UTC 24
Finished Aug 27 04:40:06 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701309123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.701309123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_intr.3425252608
Short name T92
Test name
Test status
Simulation time 52145417972 ps
CPU time 98.7 seconds
Started Aug 27 04:40:58 AM UTC 24
Finished Aug 27 04:42:39 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425252608 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3425252608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_fifo_full.245999825
Short name T105
Test name
Test status
Simulation time 44393311125 ps
CPU time 59.81 seconds
Started Aug 27 04:36:39 AM UTC 24
Finished Aug 27 04:37:40 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245999825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.245999825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.289169230
Short name T132
Test name
Test status
Simulation time 40352490415 ps
CPU time 69.37 seconds
Started Aug 27 04:45:22 AM UTC 24
Finished Aug 27 04:46:33 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289169230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.289169230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.2835976236
Short name T85
Test name
Test status
Simulation time 29802537239 ps
CPU time 50.68 seconds
Started Aug 27 04:46:28 AM UTC 24
Finished Aug 27 04:47:20 AM UTC 24
Peak memory 224132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2835976236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all
_with_rand_reset.2835976236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_fifo_reset.2324713760
Short name T104
Test name
Test status
Simulation time 20667335354 ps
CPU time 33.79 seconds
Started Aug 27 04:36:41 AM UTC 24
Finished Aug 27 04:37:16 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324713760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2324713760
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_stress_all.849114958
Short name T619
Test name
Test status
Simulation time 269310206104 ps
CPU time 521.26 seconds
Started Aug 27 04:46:34 AM UTC 24
Finished Aug 27 04:55:22 AM UTC 24
Peak memory 217812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849114958 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.849114958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_stress_all.2737103187
Short name T164
Test name
Test status
Simulation time 57177719909 ps
CPU time 61.44 seconds
Started Aug 27 04:57:38 AM UTC 24
Finished Aug 27 04:58:41 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737103187 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2737103187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_fifo_reset.158851921
Short name T305
Test name
Test status
Simulation time 185664662195 ps
CPU time 160.63 seconds
Started Aug 27 04:44:25 AM UTC 24
Finished Aug 27 04:47:09 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158851921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.158851921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/116.uart_fifo_reset.2609454056
Short name T215
Test name
Test status
Simulation time 57227227726 ps
CPU time 42.14 seconds
Started Aug 27 05:09:29 AM UTC 24
Finished Aug 27 05:10:13 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609454056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2609454056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/116.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.3585695470
Short name T386
Test name
Test status
Simulation time 8546071660 ps
CPU time 57.22 seconds
Started Aug 27 04:49:38 AM UTC 24
Finished Aug 27 04:50:37 AM UTC 24
Peak memory 217660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3585695470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all
_with_rand_reset.3585695470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_stress_all.3473430077
Short name T216
Test name
Test status
Simulation time 323959868425 ps
CPU time 161.45 seconds
Started Aug 27 04:54:23 AM UTC 24
Finished Aug 27 04:57:07 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473430077 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3473430077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.4134950608
Short name T145
Test name
Test status
Simulation time 21779928007 ps
CPU time 44.12 seconds
Started Aug 27 04:41:21 AM UTC 24
Finished Aug 27 04:42:07 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134950608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4134950608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/169.uart_fifo_reset.3105843889
Short name T240
Test name
Test status
Simulation time 77285565804 ps
CPU time 48.86 seconds
Started Aug 27 05:11:17 AM UTC 24
Finished Aug 27 05:12:07 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105843889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3105843889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/169.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_fifo_reset.3303268047
Short name T169
Test name
Test status
Simulation time 92213150884 ps
CPU time 174.64 seconds
Started Aug 27 04:47:20 AM UTC 24
Finished Aug 27 04:50:18 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303268047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3303268047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/58.uart_fifo_reset.16311874
Short name T160
Test name
Test status
Simulation time 89015715668 ps
CPU time 94.5 seconds
Started Aug 27 05:06:31 AM UTC 24
Finished Aug 27 05:08:08 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16311874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.16311874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/58.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_fifo_full.1904330754
Short name T127
Test name
Test status
Simulation time 156078375864 ps
CPU time 128.66 seconds
Started Aug 27 04:38:12 AM UTC 24
Finished Aug 27 04:40:23 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904330754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1904330754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/107.uart_fifo_reset.1867224387
Short name T1033
Test name
Test status
Simulation time 119265900021 ps
CPU time 112.68 seconds
Started Aug 27 05:09:21 AM UTC 24
Finished Aug 27 05:11:16 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867224387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1867224387
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/107.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/115.uart_fifo_reset.2869106788
Short name T1011
Test name
Test status
Simulation time 16903808428 ps
CPU time 37.48 seconds
Started Aug 27 05:09:29 AM UTC 24
Finished Aug 27 05:10:08 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869106788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2869106788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/115.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/124.uart_fifo_reset.702256252
Short name T194
Test name
Test status
Simulation time 112688061117 ps
CPU time 67.24 seconds
Started Aug 27 05:09:48 AM UTC 24
Finished Aug 27 05:10:57 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702256252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.702256252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/124.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_fifo_reset.3146705481
Short name T166
Test name
Test status
Simulation time 113502435808 ps
CPU time 79.21 seconds
Started Aug 27 04:49:14 AM UTC 24
Finished Aug 27 04:50:35 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146705481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3146705481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/73.uart_fifo_reset.3300504394
Short name T174
Test name
Test status
Simulation time 24341555765 ps
CPU time 34.73 seconds
Started Aug 27 05:07:42 AM UTC 24
Finished Aug 27 05:08:19 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300504394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3300504394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/73.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_perf.3651870843
Short name T331
Test name
Test status
Simulation time 18298377947 ps
CPU time 164.22 seconds
Started Aug 27 04:40:40 AM UTC 24
Finished Aug 27 04:43:27 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651870843 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3651870843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/105.uart_fifo_reset.1228267960
Short name T241
Test name
Test status
Simulation time 104045805137 ps
CPU time 178.82 seconds
Started Aug 27 05:09:20 AM UTC 24
Finished Aug 27 05:12:22 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228267960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1228267960
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/105.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_fifo_reset.2671856193
Short name T179
Test name
Test status
Simulation time 21755714558 ps
CPU time 43.32 seconds
Started Aug 27 04:42:02 AM UTC 24
Finished Aug 27 04:42:47 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671856193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2671856193
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/136.uart_fifo_reset.3948360726
Short name T192
Test name
Test status
Simulation time 272276023737 ps
CPU time 91.66 seconds
Started Aug 27 05:10:07 AM UTC 24
Finished Aug 27 05:11:40 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948360726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3948360726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/136.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.1836284458
Short name T314
Test name
Test status
Simulation time 128660483499 ps
CPU time 229.01 seconds
Started Aug 27 04:43:04 AM UTC 24
Finished Aug 27 04:46:56 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836284458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1836284458
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/205.uart_fifo_reset.2706408111
Short name T197
Test name
Test status
Simulation time 19142963374 ps
CPU time 35.43 seconds
Started Aug 27 05:12:17 AM UTC 24
Finished Aug 27 05:12:54 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706408111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2706408111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/205.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/212.uart_fifo_reset.3200043060
Short name T213
Test name
Test status
Simulation time 104564307427 ps
CPU time 52.48 seconds
Started Aug 27 05:12:23 AM UTC 24
Finished Aug 27 05:13:17 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200043060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3200043060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/212.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.129162502
Short name T530
Test name
Test status
Simulation time 30893274458 ps
CPU time 42.43 seconds
Started Aug 27 04:49:00 AM UTC 24
Finished Aug 27 04:49:44 AM UTC 24
Peak memory 217520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=129162502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all_
with_rand_reset.129162502
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/227.uart_fifo_reset.1185852357
Short name T239
Test name
Test status
Simulation time 60658118880 ps
CPU time 117.78 seconds
Started Aug 27 05:12:45 AM UTC 24
Finished Aug 27 05:14:45 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185852357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1185852357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/227.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/231.uart_fifo_reset.584308000
Short name T1175
Test name
Test status
Simulation time 123980316596 ps
CPU time 438.62 seconds
Started Aug 27 05:12:55 AM UTC 24
Finished Aug 27 05:20:19 AM UTC 24
Peak memory 212280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584308000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.584308000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/231.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_intr.228827927
Short name T631
Test name
Test status
Simulation time 70604497850 ps
CPU time 111.37 seconds
Started Aug 27 04:53:50 AM UTC 24
Finished Aug 27 04:55:43 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228827927 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.228827927
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_fifo_reset.1860899254
Short name T116
Test name
Test status
Simulation time 32258110540 ps
CPU time 82.28 seconds
Started Aug 27 04:38:13 AM UTC 24
Finished Aug 27 04:39:37 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860899254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1860899254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_fifo_reset.3837091444
Short name T45
Test name
Test status
Simulation time 268502185245 ps
CPU time 179.77 seconds
Started Aug 27 04:35:00 AM UTC 24
Finished Aug 27 04:38:02 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837091444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3837091444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2933812160
Short name T261
Test name
Test status
Simulation time 113973609150 ps
CPU time 256.69 seconds
Started Aug 27 04:35:34 AM UTC 24
Finished Aug 27 04:39:54 AM UTC 24
Peak memory 208648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933812160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2933812160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/100.uart_fifo_reset.561073289
Short name T161
Test name
Test status
Simulation time 15436660820 ps
CPU time 10.75 seconds
Started Aug 27 05:09:09 AM UTC 24
Finished Aug 27 05:09:21 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561073289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.561073289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/100.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/120.uart_fifo_reset.553734429
Short name T244
Test name
Test status
Simulation time 141842288380 ps
CPU time 161.05 seconds
Started Aug 27 05:09:31 AM UTC 24
Finished Aug 27 05:12:15 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553734429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.553734429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/120.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/141.uart_fifo_reset.2670201075
Short name T237
Test name
Test status
Simulation time 138246631353 ps
CPU time 119.79 seconds
Started Aug 27 05:10:13 AM UTC 24
Finished Aug 27 05:12:15 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670201075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2670201075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/141.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/148.uart_fifo_reset.2435229292
Short name T247
Test name
Test status
Simulation time 159691221841 ps
CPU time 95.73 seconds
Started Aug 27 05:10:36 AM UTC 24
Finished Aug 27 05:12:14 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435229292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2435229292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/148.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_fifo_reset.701224257
Short name T317
Test name
Test status
Simulation time 172399582113 ps
CPU time 249.93 seconds
Started Aug 27 04:43:41 AM UTC 24
Finished Aug 27 04:47:54 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701224257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.701224257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/159.uart_fifo_reset.3240954570
Short name T233
Test name
Test status
Simulation time 90655819571 ps
CPU time 93.38 seconds
Started Aug 27 05:10:53 AM UTC 24
Finished Aug 27 05:12:28 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240954570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3240954570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/159.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/160.uart_fifo_reset.1728142069
Short name T243
Test name
Test status
Simulation time 35574220222 ps
CPU time 39.71 seconds
Started Aug 27 05:10:58 AM UTC 24
Finished Aug 27 05:11:39 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728142069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1728142069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/160.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/163.uart_fifo_reset.3386000693
Short name T231
Test name
Test status
Simulation time 58568258590 ps
CPU time 27.37 seconds
Started Aug 27 05:11:09 AM UTC 24
Finished Aug 27 05:11:38 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386000693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3386000693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/163.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_stress_all.3668336259
Short name T199
Test name
Test status
Simulation time 331458238176 ps
CPU time 1182.72 seconds
Started Aug 27 04:47:09 AM UTC 24
Finished Aug 27 05:07:05 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668336259 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3668336259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/191.uart_fifo_reset.3464969388
Short name T251
Test name
Test status
Simulation time 76437906244 ps
CPU time 61.68 seconds
Started Aug 27 05:11:58 AM UTC 24
Finished Aug 27 05:13:01 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464969388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3464969388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/191.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2773933500
Short name T235
Test name
Test status
Simulation time 40218802382 ps
CPU time 22.64 seconds
Started Aug 27 05:12:17 AM UTC 24
Finished Aug 27 05:12:41 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773933500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2773933500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/206.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2526971218
Short name T228
Test name
Test status
Simulation time 27218892486 ps
CPU time 41.21 seconds
Started Aug 27 05:12:20 AM UTC 24
Finished Aug 27 05:13:03 AM UTC 24
Peak memory 208564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526971218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2526971218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/208.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3418237269
Short name T1080
Test name
Test status
Simulation time 29499583615 ps
CPU time 46.4 seconds
Started Aug 27 05:12:21 AM UTC 24
Finished Aug 27 05:13:09 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418237269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3418237269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/211.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1465897069
Short name T245
Test name
Test status
Simulation time 265191858687 ps
CPU time 165.73 seconds
Started Aug 27 05:12:31 AM UTC 24
Finished Aug 27 05:15:20 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465897069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1465897069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/218.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/240.uart_fifo_reset.262951386
Short name T248
Test name
Test status
Simulation time 42929053415 ps
CPU time 26.65 seconds
Started Aug 27 05:13:03 AM UTC 24
Finished Aug 27 05:13:31 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262951386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.262951386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/240.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/293.uart_fifo_reset.283147320
Short name T238
Test name
Test status
Simulation time 68803114391 ps
CPU time 37.94 seconds
Started Aug 27 05:14:23 AM UTC 24
Finished Aug 27 05:15:02 AM UTC 24
Peak memory 208500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283147320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.283147320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/293.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_fifo_reset.2279251978
Short name T226
Test name
Test status
Simulation time 33240039245 ps
CPU time 35.72 seconds
Started Aug 27 04:58:18 AM UTC 24
Finished Aug 27 04:58:55 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279251978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2279251978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/75.uart_fifo_reset.1671903073
Short name T250
Test name
Test status
Simulation time 50673504677 ps
CPU time 32.88 seconds
Started Aug 27 05:07:49 AM UTC 24
Finished Aug 27 05:08:24 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671903073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1671903073
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/75.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/93.uart_fifo_reset.2453494651
Short name T195
Test name
Test status
Simulation time 38297283386 ps
CPU time 45.05 seconds
Started Aug 27 05:08:43 AM UTC 24
Finished Aug 27 05:09:30 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453494651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2453494651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/93.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.4009040422
Short name T1184
Test name
Test status
Simulation time 72389566 ps
CPU time 0.89 seconds
Started Aug 27 05:14:36 AM UTC 24
Finished Aug 27 05:14:38 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009040422 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.4009040422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.2744512644
Short name T1186
Test name
Test status
Simulation time 129825858 ps
CPU time 2.21 seconds
Started Aug 27 05:14:36 AM UTC 24
Finished Aug 27 05:14:39 AM UTC 24
Peak memory 202572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744512644 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2744512644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.3850795167
Short name T48
Test name
Test status
Simulation time 25312090 ps
CPU time 0.85 seconds
Started Aug 27 05:14:34 AM UTC 24
Finished Aug 27 05:14:36 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850795167 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3850795167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1063909624
Short name T1185
Test name
Test status
Simulation time 35778379 ps
CPU time 0.89 seconds
Started Aug 27 05:14:37 AM UTC 24
Finished Aug 27 05:14:39 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1063909624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r
eset.1063909624
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.2861419092
Short name T49
Test name
Test status
Simulation time 18761667 ps
CPU time 0.94 seconds
Started Aug 27 05:14:36 AM UTC 24
Finished Aug 27 05:14:37 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861419092 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2861419092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.797764946
Short name T1182
Test name
Test status
Simulation time 51642159 ps
CPU time 0.85 seconds
Started Aug 27 05:14:33 AM UTC 24
Finished Aug 27 05:14:35 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797764946 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.797764946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.2623164637
Short name T61
Test name
Test status
Simulation time 74345550 ps
CPU time 1.04 seconds
Started Aug 27 05:14:37 AM UTC 24
Finished Aug 27 05:14:39 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623164637 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.2623164637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.419388899
Short name T1183
Test name
Test status
Simulation time 1113956356 ps
CPU time 2.55 seconds
Started Aug 27 05:14:32 AM UTC 24
Finished Aug 27 05:14:36 AM UTC 24
Peak memory 204712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419388899 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.419388899
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.2803790722
Short name T70
Test name
Test status
Simulation time 46557662 ps
CPU time 1.37 seconds
Started Aug 27 05:14:32 AM UTC 24
Finished Aug 27 05:14:35 AM UTC 24
Peak memory 201892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803790722 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2803790722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.3464311464
Short name T1190
Test name
Test status
Simulation time 128929717 ps
CPU time 1.16 seconds
Started Aug 27 05:14:39 AM UTC 24
Finished Aug 27 05:14:42 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464311464 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3464311464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3384030525
Short name T1191
Test name
Test status
Simulation time 938256213 ps
CPU time 2.13 seconds
Started Aug 27 05:14:39 AM UTC 24
Finished Aug 27 05:14:42 AM UTC 24
Peak memory 202756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384030525 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3384030525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.320654082
Short name T1189
Test name
Test status
Simulation time 28893703 ps
CPU time 0.9 seconds
Started Aug 27 05:14:39 AM UTC 24
Finished Aug 27 05:14:41 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320654082 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.320654082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2174291374
Short name T1194
Test name
Test status
Simulation time 33795421 ps
CPU time 1.28 seconds
Started Aug 27 05:14:42 AM UTC 24
Finished Aug 27 05:14:45 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2174291374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_r
eset.2174291374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.4067229770
Short name T58
Test name
Test status
Simulation time 17159158 ps
CPU time 0.9 seconds
Started Aug 27 05:14:39 AM UTC 24
Finished Aug 27 05:14:41 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067229770 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.4067229770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.2463460214
Short name T1188
Test name
Test status
Simulation time 23950911 ps
CPU time 0.84 seconds
Started Aug 27 05:14:39 AM UTC 24
Finished Aug 27 05:14:41 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463460214 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2463460214
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.2945299288
Short name T62
Test name
Test status
Simulation time 38117646 ps
CPU time 0.91 seconds
Started Aug 27 05:14:42 AM UTC 24
Finished Aug 27 05:14:44 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945299288 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.2945299288
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2055445519
Short name T1187
Test name
Test status
Simulation time 199377717 ps
CPU time 1.74 seconds
Started Aug 27 05:14:38 AM UTC 24
Finished Aug 27 05:14:41 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055445519 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2055445519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.1657825508
Short name T71
Test name
Test status
Simulation time 146752993 ps
CPU time 1.29 seconds
Started Aug 27 05:14:38 AM UTC 24
Finished Aug 27 05:14:40 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657825508 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1657825508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2799613504
Short name T1236
Test name
Test status
Simulation time 17836905 ps
CPU time 0.82 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:05 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2799613504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_
reset.2799613504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1744595872
Short name T1231
Test name
Test status
Simulation time 14453639 ps
CPU time 0.58 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:05 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744595872 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1744595872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2074919663
Short name T1215
Test name
Test status
Simulation time 21673802 ps
CPU time 0.62 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:05 AM UTC 24
Peak memory 201568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074919663 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2074919663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.3350359568
Short name T1234
Test name
Test status
Simulation time 75062537 ps
CPU time 0.84 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:05 AM UTC 24
Peak memory 203804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350359568 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.3350359568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1343884803
Short name T1238
Test name
Test status
Simulation time 293772155 ps
CPU time 1.88 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:06 AM UTC 24
Peak memory 203792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343884803 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1343884803
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.750355328
Short name T1237
Test name
Test status
Simulation time 338226481 ps
CPU time 1.5 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:06 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750355328 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.750355328
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3230064484
Short name T1242
Test name
Test status
Simulation time 24864107 ps
CPU time 0.8 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3230064484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_
reset.3230064484
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.2294127389
Short name T60
Test name
Test status
Simulation time 15941200 ps
CPU time 0.57 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294127389 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2294127389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.4256012225
Short name T1233
Test name
Test status
Simulation time 12403948 ps
CPU time 0.66 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:05 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256012225 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4256012225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1186795804
Short name T1241
Test name
Test status
Simulation time 15765527 ps
CPU time 0.81 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186795804 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.1186795804
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3365798815
Short name T1218
Test name
Test status
Simulation time 402704458 ps
CPU time 2.05 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:06 AM UTC 24
Peak memory 204860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365798815 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3365798815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.891453530
Short name T80
Test name
Test status
Simulation time 47098597 ps
CPU time 0.98 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:05 AM UTC 24
Peak memory 201612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891453530 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.891453530
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1863884703
Short name T1247
Test name
Test status
Simulation time 102560215 ps
CPU time 0.88 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1863884703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_
reset.1863884703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.3116990001
Short name T59
Test name
Test status
Simulation time 25815147 ps
CPU time 0.61 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116990001 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3116990001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.1264505868
Short name T1240
Test name
Test status
Simulation time 14348352 ps
CPU time 0.61 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264505868 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1264505868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.3428657368
Short name T1243
Test name
Test status
Simulation time 19492018 ps
CPU time 0.73 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428657368 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.3428657368
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3639934938
Short name T1257
Test name
Test status
Simulation time 163591611 ps
CPU time 1.83 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:13 AM UTC 24
Peak memory 203748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639934938 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3639934938
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2697579363
Short name T1253
Test name
Test status
Simulation time 54052603 ps
CPU time 1.06 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2697579363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_
reset.2697579363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.710111918
Short name T1248
Test name
Test status
Simulation time 65295755 ps
CPU time 0.68 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710111918 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.710111918
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.4264943296
Short name T1246
Test name
Test status
Simulation time 11440219 ps
CPU time 0.67 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264943296 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4264943296
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1751080276
Short name T1249
Test name
Test status
Simulation time 16358515 ps
CPU time 0.73 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751080276 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.1751080276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1079465791
Short name T1254
Test name
Test status
Simulation time 120655932 ps
CPU time 1.41 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:13 AM UTC 24
Peak memory 203792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079465791 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1079465791
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.3209871936
Short name T75
Test name
Test status
Simulation time 76306702 ps
CPU time 1.33 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:13 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209871936 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3209871936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2904463518
Short name T1250
Test name
Test status
Simulation time 72192291 ps
CPU time 0.73 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2904463518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_
reset.2904463518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3629772693
Short name T1245
Test name
Test status
Simulation time 42834706 ps
CPU time 0.57 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629772693 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3629772693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1019780039
Short name T1251
Test name
Test status
Simulation time 40786919 ps
CPU time 0.65 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019780039 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1019780039
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2139288356
Short name T1252
Test name
Test status
Simulation time 19304820 ps
CPU time 0.85 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139288356 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.2139288356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.881258874
Short name T1259
Test name
Test status
Simulation time 49643327 ps
CPU time 2.07 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:14 AM UTC 24
Peak memory 202692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881258874 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.881258874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3811529780
Short name T1256
Test name
Test status
Simulation time 166488069 ps
CPU time 1.22 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:13 AM UTC 24
Peak memory 200232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811529780 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3811529780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1078665150
Short name T1270
Test name
Test status
Simulation time 21157593 ps
CPU time 1.06 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1078665150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_
reset.1078665150
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.1598982605
Short name T1262
Test name
Test status
Simulation time 47375568 ps
CPU time 0.64 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:23 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598982605 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1598982605
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.4238116049
Short name T1260
Test name
Test status
Simulation time 11056301 ps
CPU time 0.52 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:23 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238116049 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.4238116049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.714928239
Short name T1261
Test name
Test status
Simulation time 18208355 ps
CPU time 0.6 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:23 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714928239 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.714928239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.1772569859
Short name T1258
Test name
Test status
Simulation time 77661769 ps
CPU time 1.5 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:13 AM UTC 24
Peak memory 200312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772569859 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1772569859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.198810964
Short name T1255
Test name
Test status
Simulation time 71786372 ps
CPU time 1.03 seconds
Started Aug 27 05:15:10 AM UTC 24
Finished Aug 27 05:15:13 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198810964 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.198810964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3578769217
Short name T1273
Test name
Test status
Simulation time 25559742 ps
CPU time 1.16 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3578769217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_
reset.3578769217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.1445524926
Short name T1265
Test name
Test status
Simulation time 20059603 ps
CPU time 0.75 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:23 AM UTC 24
Peak memory 201404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445524926 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1445524926
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.2733199896
Short name T1263
Test name
Test status
Simulation time 14262899 ps
CPU time 0.71 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:23 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733199896 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2733199896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1812434084
Short name T1266
Test name
Test status
Simulation time 25968962 ps
CPU time 0.75 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:23 AM UTC 24
Peak memory 201544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812434084 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.1812434084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2355397482
Short name T1277
Test name
Test status
Simulation time 33783912 ps
CPU time 1.51 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355397482 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2355397482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2721952205
Short name T1269
Test name
Test status
Simulation time 87133091 ps
CPU time 0.98 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721952205 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2721952205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2730309777
Short name T1280
Test name
Test status
Simulation time 31178099 ps
CPU time 1.29 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2730309777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_
reset.2730309777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2498722341
Short name T55
Test name
Test status
Simulation time 58818043 ps
CPU time 0.65 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:23 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498722341 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2498722341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.4247192827
Short name T1264
Test name
Test status
Simulation time 12893354 ps
CPU time 0.53 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:23 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247192827 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4247192827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.950480386
Short name T1267
Test name
Test status
Simulation time 30284524 ps
CPU time 0.64 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:23 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950480386 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.950480386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.888338578
Short name T1285
Test name
Test status
Simulation time 35155585 ps
CPU time 1.74 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888338578 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.888338578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3207769564
Short name T1271
Test name
Test status
Simulation time 47074671 ps
CPU time 0.94 seconds
Started Aug 27 05:15:21 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207769564 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3207769564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2199791563
Short name T1272
Test name
Test status
Simulation time 23560979 ps
CPU time 0.73 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2199791563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_
reset.2199791563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.585084937
Short name T56
Test name
Test status
Simulation time 29963789 ps
CPU time 0.73 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585084937 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.585084937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.1957973836
Short name T1268
Test name
Test status
Simulation time 15578211 ps
CPU time 0.63 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957973836 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1957973836
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.4186053115
Short name T1276
Test name
Test status
Simulation time 26151150 ps
CPU time 0.85 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186053115 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.4186053115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.3052995242
Short name T1281
Test name
Test status
Simulation time 974263325 ps
CPU time 1.38 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 203688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052995242 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3052995242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.3923070670
Short name T1279
Test name
Test status
Simulation time 194828388 ps
CPU time 1.17 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923070670 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3923070670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2368013864
Short name T1284
Test name
Test status
Simulation time 30515467 ps
CPU time 1.26 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 203736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2368013864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_
reset.2368013864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.3603459507
Short name T57
Test name
Test status
Simulation time 34130386 ps
CPU time 0.69 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603459507 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3603459507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.905731015
Short name T1275
Test name
Test status
Simulation time 13862790 ps
CPU time 0.72 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905731015 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.905731015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.1200898869
Short name T1278
Test name
Test status
Simulation time 19648883 ps
CPU time 0.77 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200898869 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.1200898869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.758709145
Short name T1283
Test name
Test status
Simulation time 102758661 ps
CPU time 1.35 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758709145 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.758709145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.2543595417
Short name T1282
Test name
Test status
Simulation time 378430714 ps
CPU time 1.29 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543595417 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2543595417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.2995474649
Short name T51
Test name
Test status
Simulation time 102267477 ps
CPU time 1.14 seconds
Started Aug 27 05:14:43 AM UTC 24
Finished Aug 27 05:14:46 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995474649 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2995474649
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.228096268
Short name T1196
Test name
Test status
Simulation time 398668542 ps
CPU time 2.1 seconds
Started Aug 27 05:14:43 AM UTC 24
Finished Aug 27 05:14:47 AM UTC 24
Peak memory 202828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228096268 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.228096268
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.1231125330
Short name T1193
Test name
Test status
Simulation time 46451800 ps
CPU time 0.86 seconds
Started Aug 27 05:14:42 AM UTC 24
Finished Aug 27 05:14:44 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231125330 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1231125330
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3731449180
Short name T1197
Test name
Test status
Simulation time 23140312 ps
CPU time 0.92 seconds
Started Aug 27 05:14:46 AM UTC 24
Finished Aug 27 05:14:49 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3731449180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_r
eset.3731449180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.1438726621
Short name T50
Test name
Test status
Simulation time 12959793 ps
CPU time 0.89 seconds
Started Aug 27 05:14:43 AM UTC 24
Finished Aug 27 05:14:45 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438726621 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1438726621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2658592379
Short name T1192
Test name
Test status
Simulation time 28712633 ps
CPU time 0.8 seconds
Started Aug 27 05:14:42 AM UTC 24
Finished Aug 27 05:14:44 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658592379 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2658592379
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.576347911
Short name T63
Test name
Test status
Simulation time 43331832 ps
CPU time 0.92 seconds
Started Aug 27 05:14:45 AM UTC 24
Finished Aug 27 05:14:47 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576347911 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.576347911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.3230701949
Short name T1195
Test name
Test status
Simulation time 26900960 ps
CPU time 1.7 seconds
Started Aug 27 05:14:42 AM UTC 24
Finished Aug 27 05:14:45 AM UTC 24
Peak memory 201644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230701949 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3230701949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.2295933864
Short name T72
Test name
Test status
Simulation time 276059302 ps
CPU time 1.9 seconds
Started Aug 27 05:14:42 AM UTC 24
Finished Aug 27 05:14:45 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295933864 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2295933864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.3650844181
Short name T1274
Test name
Test status
Simulation time 11211102 ps
CPU time 0.63 seconds
Started Aug 27 05:15:22 AM UTC 24
Finished Aug 27 05:15:24 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650844181 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3650844181
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.2626263092
Short name T1288
Test name
Test status
Simulation time 13143777 ps
CPU time 0.59 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626263092 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2626263092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1090577453
Short name T1290
Test name
Test status
Simulation time 14976682 ps
CPU time 0.52 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090577453 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1090577453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.2411214067
Short name T1291
Test name
Test status
Simulation time 29061631 ps
CPU time 0.53 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411214067 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2411214067
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3961986953
Short name T1286
Test name
Test status
Simulation time 37374213 ps
CPU time 0.48 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961986953 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3961986953
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.3983462483
Short name T1289
Test name
Test status
Simulation time 33385086 ps
CPU time 0.57 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983462483 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3983462483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.1931530045
Short name T1294
Test name
Test status
Simulation time 103052767 ps
CPU time 0.57 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931530045 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1931530045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.988495121
Short name T1287
Test name
Test status
Simulation time 18362323 ps
CPU time 0.51 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988495121 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.988495121
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.2478195374
Short name T1293
Test name
Test status
Simulation time 27884234 ps
CPU time 0.51 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478195374 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2478195374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.3769092383
Short name T1297
Test name
Test status
Simulation time 34999689 ps
CPU time 0.7 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769092383 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3769092383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2192494308
Short name T1200
Test name
Test status
Simulation time 15615760 ps
CPU time 0.94 seconds
Started Aug 27 05:14:47 AM UTC 24
Finished Aug 27 05:14:49 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192494308 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2192494308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.3977381321
Short name T1202
Test name
Test status
Simulation time 462129801 ps
CPU time 2.07 seconds
Started Aug 27 05:14:47 AM UTC 24
Finished Aug 27 05:14:50 AM UTC 24
Peak memory 202820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977381321 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3977381321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2526391716
Short name T1198
Test name
Test status
Simulation time 14521577 ps
CPU time 0.76 seconds
Started Aug 27 05:14:47 AM UTC 24
Finished Aug 27 05:14:49 AM UTC 24
Peak memory 201180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526391716 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2526391716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1343054170
Short name T1203
Test name
Test status
Simulation time 34541778 ps
CPU time 1.2 seconds
Started Aug 27 05:14:48 AM UTC 24
Finished Aug 27 05:14:51 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1343054170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r
eset.1343054170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2455270903
Short name T52
Test name
Test status
Simulation time 16014909 ps
CPU time 0.9 seconds
Started Aug 27 05:14:47 AM UTC 24
Finished Aug 27 05:14:49 AM UTC 24
Peak memory 201480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455270903 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2455270903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.1174938959
Short name T1199
Test name
Test status
Simulation time 13907257 ps
CPU time 0.86 seconds
Started Aug 27 05:14:47 AM UTC 24
Finished Aug 27 05:14:49 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174938959 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1174938959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.4263990523
Short name T64
Test name
Test status
Simulation time 18879316 ps
CPU time 0.97 seconds
Started Aug 27 05:14:48 AM UTC 24
Finished Aug 27 05:14:50 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263990523 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.4263990523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.1396177771
Short name T1201
Test name
Test status
Simulation time 174817675 ps
CPU time 2.11 seconds
Started Aug 27 05:14:46 AM UTC 24
Finished Aug 27 05:14:50 AM UTC 24
Peak memory 202672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396177771 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1396177771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.3775473076
Short name T79
Test name
Test status
Simulation time 96199917 ps
CPU time 1.67 seconds
Started Aug 27 05:14:46 AM UTC 24
Finished Aug 27 05:14:50 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775473076 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3775473076
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.590130588
Short name T1300
Test name
Test status
Simulation time 12640730 ps
CPU time 0.57 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590130588 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.590130588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.3652015566
Short name T1295
Test name
Test status
Simulation time 134710847 ps
CPU time 0.53 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652015566 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3652015566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2535323645
Short name T1299
Test name
Test status
Simulation time 66746937 ps
CPU time 0.57 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535323645 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2535323645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.907907408
Short name T1303
Test name
Test status
Simulation time 16463396 ps
CPU time 0.55 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907907408 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.907907408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.174663477
Short name T1302
Test name
Test status
Simulation time 36968846 ps
CPU time 0.53 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174663477 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.174663477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.3923794929
Short name T1298
Test name
Test status
Simulation time 15834298 ps
CPU time 0.55 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923794929 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3923794929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.2019532298
Short name T1296
Test name
Test status
Simulation time 57611931 ps
CPU time 0.55 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019532298 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2019532298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.996808844
Short name T1301
Test name
Test status
Simulation time 33279672 ps
CPU time 0.62 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996808844 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.996808844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2812935923
Short name T1305
Test name
Test status
Simulation time 15090858 ps
CPU time 0.64 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812935923 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2812935923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.267737708
Short name T1304
Test name
Test status
Simulation time 17409197 ps
CPU time 0.65 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267737708 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.267737708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.4248058603
Short name T1208
Test name
Test status
Simulation time 159500226 ps
CPU time 0.99 seconds
Started Aug 27 05:14:52 AM UTC 24
Finished Aug 27 05:14:54 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248058603 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.4248058603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3280120523
Short name T1211
Test name
Test status
Simulation time 123275867 ps
CPU time 1.77 seconds
Started Aug 27 05:14:52 AM UTC 24
Finished Aug 27 05:14:55 AM UTC 24
Peak memory 200804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280120523 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3280120523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.2540512322
Short name T1206
Test name
Test status
Simulation time 25872800 ps
CPU time 0.84 seconds
Started Aug 27 05:14:52 AM UTC 24
Finished Aug 27 05:14:54 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540512322 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2540512322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3187220387
Short name T1210
Test name
Test status
Simulation time 31291260 ps
CPU time 1.01 seconds
Started Aug 27 05:14:52 AM UTC 24
Finished Aug 27 05:14:54 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3187220387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_r
eset.3187220387
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.3501285297
Short name T1207
Test name
Test status
Simulation time 213780961 ps
CPU time 0.83 seconds
Started Aug 27 05:14:52 AM UTC 24
Finished Aug 27 05:14:54 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501285297 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3501285297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.4287686912
Short name T1205
Test name
Test status
Simulation time 12099306 ps
CPU time 0.83 seconds
Started Aug 27 05:14:52 AM UTC 24
Finished Aug 27 05:14:54 AM UTC 24
Peak memory 200820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287686912 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4287686912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2738972
Short name T65
Test name
Test status
Simulation time 18728584 ps
CPU time 1.01 seconds
Started Aug 27 05:14:52 AM UTC 24
Finished Aug 27 05:14:54 AM UTC 24
Peak memory 205532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738972 -assert nopostproc +UVM_T
ESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.2738972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.379356002
Short name T1204
Test name
Test status
Simulation time 45553147 ps
CPU time 1.82 seconds
Started Aug 27 05:14:49 AM UTC 24
Finished Aug 27 05:14:52 AM UTC 24
Peak memory 201640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379356002 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.379356002
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.4082901800
Short name T102
Test name
Test status
Simulation time 199385526 ps
CPU time 1.4 seconds
Started Aug 27 05:14:49 AM UTC 24
Finished Aug 27 05:14:52 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082901800 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.4082901800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.2365958391
Short name T1306
Test name
Test status
Simulation time 42824322 ps
CPU time 0.63 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365958391 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2365958391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3749403233
Short name T1308
Test name
Test status
Simulation time 19604439 ps
CPU time 0.62 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749403233 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3749403233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1158030483
Short name T1310
Test name
Test status
Simulation time 13691285 ps
CPU time 0.65 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158030483 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1158030483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1806094143
Short name T1307
Test name
Test status
Simulation time 11834277 ps
CPU time 0.6 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806094143 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1806094143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.2090378304
Short name T1312
Test name
Test status
Simulation time 15247946 ps
CPU time 0.6 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 200912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090378304 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2090378304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.13089200
Short name T1244
Test name
Test status
Simulation time 16186587 ps
CPU time 0.58 seconds
Started Aug 27 05:15:34 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13089200 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.13089200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.1418527693
Short name T1292
Test name
Test status
Simulation time 13047265 ps
CPU time 0.55 seconds
Started Aug 27 05:15:35 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418527693 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1418527693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2312678988
Short name T1309
Test name
Test status
Simulation time 13896662 ps
CPU time 0.49 seconds
Started Aug 27 05:15:35 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312678988 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2312678988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.77650949
Short name T1313
Test name
Test status
Simulation time 13711945 ps
CPU time 0.59 seconds
Started Aug 27 05:15:35 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77650949 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.77650949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3331754363
Short name T1311
Test name
Test status
Simulation time 15572330 ps
CPU time 0.49 seconds
Started Aug 27 05:15:35 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331754363 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3331754363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.581295732
Short name T1213
Test name
Test status
Simulation time 135363612 ps
CPU time 1.01 seconds
Started Aug 27 05:14:54 AM UTC 24
Finished Aug 27 05:14:56 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=581295732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_re
set.581295732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3924001733
Short name T1209
Test name
Test status
Simulation time 44838891 ps
CPU time 0.83 seconds
Started Aug 27 05:14:52 AM UTC 24
Finished Aug 27 05:14:54 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924001733 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3924001733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.2260054973
Short name T66
Test name
Test status
Simulation time 72966556 ps
CPU time 0.95 seconds
Started Aug 27 05:14:54 AM UTC 24
Finished Aug 27 05:14:56 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260054973 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.2260054973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.4038010187
Short name T1212
Test name
Test status
Simulation time 82638448 ps
CPU time 1.9 seconds
Started Aug 27 05:14:52 AM UTC 24
Finished Aug 27 05:14:55 AM UTC 24
Peak memory 201456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038010187 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4038010187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3423769514
Short name T76
Test name
Test status
Simulation time 332042203 ps
CPU time 1.89 seconds
Started Aug 27 05:14:52 AM UTC 24
Finished Aug 27 05:14:55 AM UTC 24
Peak memory 201576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423769514 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3423769514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1716003438
Short name T1224
Test name
Test status
Simulation time 52187162 ps
CPU time 1.27 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 203592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1716003438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_r
eset.1716003438
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.3827260944
Short name T67
Test name
Test status
Simulation time 16904218 ps
CPU time 0.71 seconds
Started Aug 27 05:14:57 AM UTC 24
Finished Aug 27 05:14:59 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827260944 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3827260944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.2807511595
Short name T1216
Test name
Test status
Simulation time 14814312 ps
CPU time 0.87 seconds
Started Aug 27 05:14:57 AM UTC 24
Finished Aug 27 05:14:59 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807511595 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2807511595
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.4074791570
Short name T1217
Test name
Test status
Simulation time 24253352 ps
CPU time 0.74 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:14:59 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074791570 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.4074791570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2202760815
Short name T1214
Test name
Test status
Simulation time 488191805 ps
CPU time 2.75 seconds
Started Aug 27 05:14:54 AM UTC 24
Finished Aug 27 05:14:58 AM UTC 24
Peak memory 202596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202760815 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2202760815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3637416478
Short name T101
Test name
Test status
Simulation time 57007762 ps
CPU time 1.38 seconds
Started Aug 27 05:14:57 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637416478 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3637416478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3360345570
Short name T1223
Test name
Test status
Simulation time 29331004 ps
CPU time 1.16 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3360345570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_r
eset.3360345570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.3105880469
Short name T54
Test name
Test status
Simulation time 34663659 ps
CPU time 0.83 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105880469 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3105880469
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.3734925167
Short name T1219
Test name
Test status
Simulation time 18801177 ps
CPU time 0.85 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:14:59 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734925167 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3734925167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.2608071609
Short name T1221
Test name
Test status
Simulation time 24455890 ps
CPU time 0.9 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608071609 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.2608071609
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.2307148940
Short name T1226
Test name
Test status
Simulation time 37458808 ps
CPU time 2.04 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:15:01 AM UTC 24
Peak memory 202692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307148940 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2307148940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2235438047
Short name T1235
Test name
Test status
Simulation time 116940357 ps
CPU time 1.45 seconds
Started Aug 27 05:15:02 AM UTC 24
Finished Aug 27 05:15:05 AM UTC 24
Peak memory 203620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2235438047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r
eset.2235438047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.3666388731
Short name T1222
Test name
Test status
Simulation time 48235464 ps
CPU time 0.75 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666388731 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3666388731
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.2005739935
Short name T1220
Test name
Test status
Simulation time 37081430 ps
CPU time 0.69 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005739935 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2005739935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.3402002498
Short name T1229
Test name
Test status
Simulation time 15215278 ps
CPU time 0.83 seconds
Started Aug 27 05:15:02 AM UTC 24
Finished Aug 27 05:15:04 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402002498 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.3402002498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1273979068
Short name T1225
Test name
Test status
Simulation time 303414780 ps
CPU time 1.47 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273979068 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1273979068
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3016065013
Short name T103
Test name
Test status
Simulation time 94241773 ps
CPU time 1.43 seconds
Started Aug 27 05:14:58 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016065013 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3016065013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2531958454
Short name T1230
Test name
Test status
Simulation time 43228899 ps
CPU time 0.8 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:05 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2531958454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r
eset.2531958454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.3471294043
Short name T1232
Test name
Test status
Simulation time 33687781 ps
CPU time 0.71 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:05 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471294043 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3471294043
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2401333321
Short name T1227
Test name
Test status
Simulation time 13662404 ps
CPU time 0.61 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:04 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401333321 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2401333321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.2880271963
Short name T1228
Test name
Test status
Simulation time 13986325 ps
CPU time 0.61 seconds
Started Aug 27 05:15:03 AM UTC 24
Finished Aug 27 05:15:04 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880271963 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.2880271963
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.137320012
Short name T1239
Test name
Test status
Simulation time 90282937 ps
CPU time 2.16 seconds
Started Aug 27 05:15:02 AM UTC 24
Finished Aug 27 05:15:06 AM UTC 24
Peak memory 204600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137320012 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.137320012
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.1671966928
Short name T78
Test name
Test status
Simulation time 89694451 ps
CPU time 1.34 seconds
Started Aug 27 05:15:02 AM UTC 24
Finished Aug 27 05:15:05 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671966928 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1671966928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_fifo_full.2717659532
Short name T282
Test name
Test status
Simulation time 102735068830 ps
CPU time 370.08 seconds
Started Aug 27 04:34:43 AM UTC 24
Finished Aug 27 04:40:58 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717659532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2717659532
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_intr.2651120908
Short name T5
Test name
Test status
Simulation time 14907916073 ps
CPU time 9.83 seconds
Started Aug 27 04:34:43 AM UTC 24
Finished Aug 27 04:34:54 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651120908 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2651120908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.1939555801
Short name T274
Test name
Test status
Simulation time 70163784835 ps
CPU time 272.06 seconds
Started Aug 27 04:34:46 AM UTC 24
Finished Aug 27 04:39:22 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939555801 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1939555801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_loopback.1206177409
Short name T3
Test name
Test status
Simulation time 1285743520 ps
CPU time 2.78 seconds
Started Aug 27 04:34:45 AM UTC 24
Finished Aug 27 04:34:49 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206177409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1206177409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_noise_filter.76201412
Short name T262
Test name
Test status
Simulation time 47436634444 ps
CPU time 150.94 seconds
Started Aug 27 04:34:44 AM UTC 24
Finished Aug 27 04:37:17 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76201412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.76201412
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_perf.1128004222
Short name T320
Test name
Test status
Simulation time 18373478095 ps
CPU time 307.01 seconds
Started Aug 27 04:34:45 AM UTC 24
Finished Aug 27 04:39:56 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128004222 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1128004222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_rx_oversample.1398743318
Short name T8
Test name
Test status
Simulation time 3275662992 ps
CPU time 16.98 seconds
Started Aug 27 04:34:43 AM UTC 24
Finished Aug 27 04:35:01 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398743318 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1398743318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.4022858408
Short name T7
Test name
Test status
Simulation time 5269796159 ps
CPU time 14.29 seconds
Started Aug 27 04:34:44 AM UTC 24
Finished Aug 27 04:34:59 AM UTC 24
Peak memory 205288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022858408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.4022858408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_smoke.755367857
Short name T1
Test name
Test status
Simulation time 249012827 ps
CPU time 3.11 seconds
Started Aug 27 04:34:42 AM UTC 24
Finished Aug 27 04:34:46 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755367857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.uart_smoke.755367857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.692908409
Short name T2
Test name
Test status
Simulation time 4802825321 ps
CPU time 3.09 seconds
Started Aug 27 04:34:44 AM UTC 24
Finished Aug 27 04:34:48 AM UTC 24
Peak memory 208192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692908409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.692908409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/0.uart_tx_rx.2227716902
Short name T26
Test name
Test status
Simulation time 142669991072 ps
CPU time 107.43 seconds
Started Aug 27 04:34:42 AM UTC 24
Finished Aug 27 04:36:31 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227716902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2227716902
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/0.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_alert_test.613353233
Short name T30
Test name
Test status
Simulation time 27120968 ps
CPU time 0.87 seconds
Started Aug 27 04:35:53 AM UTC 24
Finished Aug 27 04:35:55 AM UTC 24
Peak memory 204372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613353233 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.613353233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_fifo_full.933702741
Short name T107
Test name
Test status
Simulation time 74143022030 ps
CPU time 191.44 seconds
Started Aug 27 04:34:57 AM UTC 24
Finished Aug 27 04:38:11 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933702741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.933702741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_intr.3127125769
Short name T23
Test name
Test status
Simulation time 41753138166 ps
CPU time 74.84 seconds
Started Aug 27 04:35:05 AM UTC 24
Finished Aug 27 04:36:22 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127125769 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3127125769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.3365722149
Short name T259
Test name
Test status
Simulation time 105436482443 ps
CPU time 282.7 seconds
Started Aug 27 04:35:42 AM UTC 24
Finished Aug 27 04:40:29 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365722149 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3365722149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_loopback.563034279
Short name T15
Test name
Test status
Simulation time 2881825636 ps
CPU time 4.18 seconds
Started Aug 27 04:35:37 AM UTC 24
Finished Aug 27 04:35:42 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563034279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.uart_loopback.563034279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_noise_filter.680862710
Short name T27
Test name
Test status
Simulation time 171476784648 ps
CPU time 86.61 seconds
Started Aug 27 04:35:29 AM UTC 24
Finished Aug 27 04:36:58 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680862710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.680862710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_rx_oversample.1475175102
Short name T24
Test name
Test status
Simulation time 6106169903 ps
CPU time 67.59 seconds
Started Aug 27 04:35:02 AM UTC 24
Finished Aug 27 04:36:11 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475175102 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1475175102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.3889162265
Short name T16
Test name
Test status
Simulation time 38758138037 ps
CPU time 13.67 seconds
Started Aug 27 04:35:31 AM UTC 24
Finished Aug 27 04:35:45 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889162265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3889162265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_sec_cm.1550347152
Short name T29
Test name
Test status
Simulation time 65153097 ps
CPU time 1.04 seconds
Started Aug 27 04:35:51 AM UTC 24
Finished Aug 27 04:35:53 AM UTC 24
Peak memory 239516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550347152 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1550347152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_smoke.1336848893
Short name T10
Test name
Test status
Simulation time 11056444605 ps
CPU time 37.42 seconds
Started Aug 27 04:34:55 AM UTC 24
Finished Aug 27 04:35:34 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336848893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1336848893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_stress_all.2771403169
Short name T332
Test name
Test status
Simulation time 83006204965 ps
CPU time 589.22 seconds
Started Aug 27 04:35:46 AM UTC 24
Finished Aug 27 04:45:43 AM UTC 24
Peak memory 219576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771403169 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2771403169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.3676818748
Short name T21
Test name
Test status
Simulation time 691675450 ps
CPU time 11.81 seconds
Started Aug 27 04:35:43 AM UTC 24
Finished Aug 27 04:35:56 AM UTC 24
Peak memory 219716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3676818748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_
with_rand_reset.3676818748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.954377985
Short name T14
Test name
Test status
Simulation time 791718452 ps
CPU time 5.55 seconds
Started Aug 27 04:35:35 AM UTC 24
Finished Aug 27 04:35:41 AM UTC 24
Peak memory 207596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954377985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.954377985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/1.uart_tx_rx.1525046365
Short name T13
Test name
Test status
Simulation time 19051731944 ps
CPU time 71.7 seconds
Started Aug 27 04:34:57 AM UTC 24
Finished Aug 27 04:36:10 AM UTC 24
Peak memory 208584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525046365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1525046365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/1.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_alert_test.119236784
Short name T434
Test name
Test status
Simulation time 47036994 ps
CPU time 0.85 seconds
Started Aug 27 04:41:19 AM UTC 24
Finished Aug 27 04:41:21 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119236784 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.119236784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_fifo_full.2260082927
Short name T130
Test name
Test status
Simulation time 20475490327 ps
CPU time 28.13 seconds
Started Aug 27 04:40:57 AM UTC 24
Finished Aug 27 04:41:26 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260082927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2260082927
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.2191527716
Short name T359
Test name
Test status
Simulation time 33095284747 ps
CPU time 62.44 seconds
Started Aug 27 04:40:57 AM UTC 24
Finished Aug 27 04:42:01 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191527716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2191527716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.722325905
Short name T606
Test name
Test status
Simulation time 106877926363 ps
CPU time 789.23 seconds
Started Aug 27 04:41:17 AM UTC 24
Finished Aug 27 04:54:35 AM UTC 24
Peak memory 212212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722325905 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.722325905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_loopback.1914565129
Short name T436
Test name
Test status
Simulation time 8108571479 ps
CPU time 32.58 seconds
Started Aug 27 04:41:13 AM UTC 24
Finished Aug 27 04:41:47 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914565129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1914565129
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_noise_filter.1300425624
Short name T325
Test name
Test status
Simulation time 84887035573 ps
CPU time 252.99 seconds
Started Aug 27 04:40:59 AM UTC 24
Finished Aug 27 04:45:16 AM UTC 24
Peak memory 208924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300425624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1300425624
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_perf.1329247952
Short name T300
Test name
Test status
Simulation time 30572361493 ps
CPU time 840.22 seconds
Started Aug 27 04:41:15 AM UTC 24
Finished Aug 27 04:55:25 AM UTC 24
Peak memory 212348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329247952 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1329247952
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_rx_oversample.987301863
Short name T433
Test name
Test status
Simulation time 3037995685 ps
CPU time 19.67 seconds
Started Aug 27 04:40:58 AM UTC 24
Finished Aug 27 04:41:19 AM UTC 24
Peak memory 207216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987301863 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.987301863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.881417745
Short name T137
Test name
Test status
Simulation time 214372965842 ps
CPU time 212.94 seconds
Started Aug 27 04:41:06 AM UTC 24
Finished Aug 27 04:44:43 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881417745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.881417745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.4209049994
Short name T368
Test name
Test status
Simulation time 4448890495 ps
CPU time 10.23 seconds
Started Aug 27 04:41:02 AM UTC 24
Finished Aug 27 04:41:14 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209049994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.4209049994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_smoke.1514104074
Short name T310
Test name
Test status
Simulation time 449367418 ps
CPU time 3 seconds
Started Aug 27 04:40:52 AM UTC 24
Finished Aug 27 04:40:56 AM UTC 24
Peak memory 208348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514104074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1514104074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_stress_all.3075576135
Short name T279
Test name
Test status
Simulation time 225328896926 ps
CPU time 107.3 seconds
Started Aug 27 04:41:19 AM UTC 24
Finished Aug 27 04:43:08 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075576135 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3075576135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.1115329829
Short name T83
Test name
Test status
Simulation time 7990204656 ps
CPU time 27.32 seconds
Started Aug 27 04:41:18 AM UTC 24
Finished Aug 27 04:41:46 AM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1115329829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all
_with_rand_reset.1115329829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.3742402955
Short name T275
Test name
Test status
Simulation time 6721650671 ps
CPU time 21 seconds
Started Aug 27 04:41:10 AM UTC 24
Finished Aug 27 04:41:32 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742402955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3742402955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/10.uart_tx_rx.1694611584
Short name T289
Test name
Test status
Simulation time 38684801077 ps
CPU time 99.19 seconds
Started Aug 27 04:40:52 AM UTC 24
Finished Aug 27 04:42:33 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694611584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1694611584
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/10.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/101.uart_fifo_reset.3319640259
Short name T1023
Test name
Test status
Simulation time 103022518412 ps
CPU time 87.75 seconds
Started Aug 27 05:09:10 AM UTC 24
Finished Aug 27 05:10:40 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319640259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3319640259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/101.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/102.uart_fifo_reset.4267739829
Short name T1001
Test name
Test status
Simulation time 16685567314 ps
CPU time 29.21 seconds
Started Aug 27 05:09:16 AM UTC 24
Finished Aug 27 05:09:47 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267739829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4267739829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/102.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/103.uart_fifo_reset.255889937
Short name T408
Test name
Test status
Simulation time 53267729980 ps
CPU time 61.55 seconds
Started Aug 27 05:09:16 AM UTC 24
Finished Aug 27 05:10:19 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255889937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.255889937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/103.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/104.uart_fifo_reset.317943315
Short name T1012
Test name
Test status
Simulation time 61910352808 ps
CPU time 47.86 seconds
Started Aug 27 05:09:20 AM UTC 24
Finished Aug 27 05:10:10 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317943315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.317943315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/104.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/106.uart_fifo_reset.1944878005
Short name T1025
Test name
Test status
Simulation time 131379038485 ps
CPU time 81.21 seconds
Started Aug 27 05:09:21 AM UTC 24
Finished Aug 27 05:10:44 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944878005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1944878005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/106.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/108.uart_fifo_reset.1909766937
Short name T1054
Test name
Test status
Simulation time 136780653788 ps
CPU time 160.63 seconds
Started Aug 27 05:09:24 AM UTC 24
Finished Aug 27 05:12:08 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909766937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1909766937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/108.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/109.uart_fifo_reset.1919428993
Short name T196
Test name
Test status
Simulation time 108400628594 ps
CPU time 35.56 seconds
Started Aug 27 05:09:25 AM UTC 24
Finished Aug 27 05:10:01 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919428993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1919428993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/109.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_alert_test.1661036410
Short name T437
Test name
Test status
Simulation time 37960066 ps
CPU time 0.83 seconds
Started Aug 27 04:41:47 AM UTC 24
Finished Aug 27 04:41:49 AM UTC 24
Peak memory 204436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661036410 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1661036410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_fifo_reset.3187371633
Short name T385
Test name
Test status
Simulation time 122157422024 ps
CPU time 38.78 seconds
Started Aug 27 04:41:21 AM UTC 24
Finished Aug 27 04:42:02 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187371633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3187371633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_intr.2286385585
Short name T435
Test name
Test status
Simulation time 16276897487 ps
CPU time 11.57 seconds
Started Aug 27 04:41:27 AM UTC 24
Finished Aug 27 04:41:39 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286385585 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2286385585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.3118240435
Short name T512
Test name
Test status
Simulation time 78390324750 ps
CPU time 403.43 seconds
Started Aug 27 04:41:45 AM UTC 24
Finished Aug 27 04:48:34 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118240435 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3118240435
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_loopback.2156644343
Short name T438
Test name
Test status
Simulation time 3995433772 ps
CPU time 8.05 seconds
Started Aug 27 04:41:40 AM UTC 24
Finished Aug 27 04:41:49 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156644343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2156644343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_noise_filter.1551473425
Short name T287
Test name
Test status
Simulation time 49177833228 ps
CPU time 138.04 seconds
Started Aug 27 04:41:28 AM UTC 24
Finished Aug 27 04:43:48 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551473425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1551473425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_perf.3499932652
Short name T378
Test name
Test status
Simulation time 19661783536 ps
CPU time 212.14 seconds
Started Aug 27 04:41:40 AM UTC 24
Finished Aug 27 04:45:16 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499932652 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3499932652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_rx_oversample.2920655816
Short name T443
Test name
Test status
Simulation time 7148851412 ps
CPU time 80.48 seconds
Started Aug 27 04:41:27 AM UTC 24
Finished Aug 27 04:42:49 AM UTC 24
Peak memory 207912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920655816 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2920655816
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.3250605095
Short name T120
Test name
Test status
Simulation time 23748254077 ps
CPU time 59.44 seconds
Started Aug 27 04:41:33 AM UTC 24
Finished Aug 27 04:42:34 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250605095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3250605095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.3752447910
Short name T341
Test name
Test status
Simulation time 586477358 ps
CPU time 3.14 seconds
Started Aug 27 04:41:30 AM UTC 24
Finished Aug 27 04:41:34 AM UTC 24
Peak memory 205036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752447910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3752447910
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_smoke.1356123107
Short name T322
Test name
Test status
Simulation time 646463618 ps
CPU time 5.63 seconds
Started Aug 27 04:41:20 AM UTC 24
Finished Aug 27 04:41:27 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356123107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1356123107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.2210860458
Short name T356
Test name
Test status
Simulation time 472763230 ps
CPU time 3.01 seconds
Started Aug 27 04:41:35 AM UTC 24
Finished Aug 27 04:41:39 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210860458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2210860458
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/11.uart_tx_rx.854997512
Short name T273
Test name
Test status
Simulation time 32122442922 ps
CPU time 21.62 seconds
Started Aug 27 04:41:21 AM UTC 24
Finished Aug 27 04:41:44 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854997512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.854997512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/11.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/110.uart_fifo_reset.3871490719
Short name T1007
Test name
Test status
Simulation time 60694644888 ps
CPU time 31.95 seconds
Started Aug 27 05:09:26 AM UTC 24
Finished Aug 27 05:09:59 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871490719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3871490719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/110.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/111.uart_fifo_reset.531539634
Short name T1022
Test name
Test status
Simulation time 97578362848 ps
CPU time 72.14 seconds
Started Aug 27 05:09:26 AM UTC 24
Finished Aug 27 05:10:40 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531539634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.531539634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/111.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/112.uart_fifo_reset.1979781005
Short name T414
Test name
Test status
Simulation time 114568671453 ps
CPU time 105.58 seconds
Started Aug 27 05:09:27 AM UTC 24
Finished Aug 27 05:11:14 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979781005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1979781005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/112.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/113.uart_fifo_reset.3959698148
Short name T1017
Test name
Test status
Simulation time 35316151249 ps
CPU time 62.85 seconds
Started Aug 27 05:09:27 AM UTC 24
Finished Aug 27 05:10:31 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959698148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3959698148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/113.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/114.uart_fifo_reset.1228177128
Short name T1027
Test name
Test status
Simulation time 135310825305 ps
CPU time 88.71 seconds
Started Aug 27 05:09:29 AM UTC 24
Finished Aug 27 05:11:00 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228177128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1228177128
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/114.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/117.uart_fifo_reset.3316215561
Short name T1066
Test name
Test status
Simulation time 82478182311 ps
CPU time 184.43 seconds
Started Aug 27 05:09:29 AM UTC 24
Finished Aug 27 05:12:37 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316215561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3316215561
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/117.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/118.uart_fifo_reset.364248495
Short name T1002
Test name
Test status
Simulation time 19229821216 ps
CPU time 19.49 seconds
Started Aug 27 05:09:30 AM UTC 24
Finished Aug 27 05:09:51 AM UTC 24
Peak memory 208580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364248495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.364248495
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/118.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/119.uart_fifo_reset.2861625702
Short name T1005
Test name
Test status
Simulation time 27480659124 ps
CPU time 22.17 seconds
Started Aug 27 05:09:30 AM UTC 24
Finished Aug 27 05:09:54 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861625702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2861625702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/119.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_alert_test.100745345
Short name T442
Test name
Test status
Simulation time 81248929 ps
CPU time 0.85 seconds
Started Aug 27 04:42:34 AM UTC 24
Finished Aug 27 04:42:36 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100745345 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.100745345
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_fifo_full.2092073343
Short name T554
Test name
Test status
Simulation time 192309818572 ps
CPU time 542.36 seconds
Started Aug 27 04:41:55 AM UTC 24
Finished Aug 27 04:51:04 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092073343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2092073343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_intr.2356468972
Short name T382
Test name
Test status
Simulation time 68076123850 ps
CPU time 50.28 seconds
Started Aug 27 04:42:07 AM UTC 24
Finished Aug 27 04:42:59 AM UTC 24
Peak memory 208908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356468972 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2356468972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.3180387823
Short name T503
Test name
Test status
Simulation time 40554114867 ps
CPU time 334.65 seconds
Started Aug 27 04:42:28 AM UTC 24
Finished Aug 27 04:48:07 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180387823 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3180387823
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_loopback.508952772
Short name T441
Test name
Test status
Simulation time 2460956193 ps
CPU time 7.69 seconds
Started Aug 27 04:42:26 AM UTC 24
Finished Aug 27 04:42:34 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508952772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.uart_loopback.508952772
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_noise_filter.3507979452
Short name T278
Test name
Test status
Simulation time 338304648009 ps
CPU time 45.86 seconds
Started Aug 27 04:42:07 AM UTC 24
Finished Aug 27 04:42:55 AM UTC 24
Peak memory 217684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507979452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3507979452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_perf.2966139064
Short name T588
Test name
Test status
Simulation time 11230129679 ps
CPU time 638.7 seconds
Started Aug 27 04:42:27 AM UTC 24
Finished Aug 27 04:53:13 AM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966139064 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2966139064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_rx_oversample.2099236913
Short name T440
Test name
Test status
Simulation time 3479896736 ps
CPU time 14.41 seconds
Started Aug 27 04:42:03 AM UTC 24
Finished Aug 27 04:42:19 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099236913 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2099236913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.2857160482
Short name T323
Test name
Test status
Simulation time 36545961002 ps
CPU time 37.9 seconds
Started Aug 27 04:42:21 AM UTC 24
Finished Aug 27 04:43:01 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857160482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2857160482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.2690327049
Short name T343
Test name
Test status
Simulation time 1348553796 ps
CPU time 4.64 seconds
Started Aug 27 04:42:19 AM UTC 24
Finished Aug 27 04:42:25 AM UTC 24
Peak memory 205036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690327049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2690327049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_smoke.3179576859
Short name T439
Test name
Test status
Simulation time 633244885 ps
CPU time 3.19 seconds
Started Aug 27 04:41:50 AM UTC 24
Finished Aug 27 04:41:54 AM UTC 24
Peak memory 208384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179576859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3179576859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_stress_all.668160608
Short name T141
Test name
Test status
Simulation time 413380571788 ps
CPU time 440.81 seconds
Started Aug 27 04:42:33 AM UTC 24
Finished Aug 27 04:49:59 AM UTC 24
Peak memory 221752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668160608 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.668160608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.897550886
Short name T367
Test name
Test status
Simulation time 8230388792 ps
CPU time 64.52 seconds
Started Aug 27 04:42:30 AM UTC 24
Finished Aug 27 04:43:36 AM UTC 24
Peak memory 217580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=897550886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all_
with_rand_reset.897550886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.1613002712
Short name T366
Test name
Test status
Simulation time 1444205066 ps
CPU time 8.39 seconds
Started Aug 27 04:42:23 AM UTC 24
Finished Aug 27 04:42:32 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613002712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1613002712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/12.uart_tx_rx.1089150312
Short name T342
Test name
Test status
Simulation time 65839178931 ps
CPU time 29.96 seconds
Started Aug 27 04:41:51 AM UTC 24
Finished Aug 27 04:42:22 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089150312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1089150312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/12.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/121.uart_fifo_reset.3499441590
Short name T1013
Test name
Test status
Simulation time 133473964641 ps
CPU time 35.9 seconds
Started Aug 27 05:09:33 AM UTC 24
Finished Aug 27 05:10:11 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499441590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3499441590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/121.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/122.uart_fifo_reset.3373726853
Short name T1019
Test name
Test status
Simulation time 17140318237 ps
CPU time 54.52 seconds
Started Aug 27 05:09:41 AM UTC 24
Finished Aug 27 05:10:37 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373726853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3373726853
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/122.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/123.uart_fifo_reset.383799972
Short name T1008
Test name
Test status
Simulation time 12254365886 ps
CPU time 16.5 seconds
Started Aug 27 05:09:42 AM UTC 24
Finished Aug 27 05:09:59 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383799972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.383799972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/123.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/125.uart_fifo_reset.947407853
Short name T193
Test name
Test status
Simulation time 101608581475 ps
CPU time 56.51 seconds
Started Aug 27 05:09:48 AM UTC 24
Finished Aug 27 05:10:46 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947407853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.947407853
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/125.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/126.uart_fifo_reset.815628136
Short name T168
Test name
Test status
Simulation time 126398166036 ps
CPU time 176.17 seconds
Started Aug 27 05:09:52 AM UTC 24
Finished Aug 27 05:12:51 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815628136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.815628136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/126.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/127.uart_fifo_reset.1090064856
Short name T1060
Test name
Test status
Simulation time 89856295678 ps
CPU time 145.41 seconds
Started Aug 27 05:09:52 AM UTC 24
Finished Aug 27 05:12:20 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090064856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1090064856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/127.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/128.uart_fifo_reset.2512072941
Short name T1015
Test name
Test status
Simulation time 80489151767 ps
CPU time 27.15 seconds
Started Aug 27 05:09:53 AM UTC 24
Finished Aug 27 05:10:21 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512072941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2512072941
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/128.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/129.uart_fifo_reset.2422134213
Short name T1065
Test name
Test status
Simulation time 111769112690 ps
CPU time 157.52 seconds
Started Aug 27 05:09:55 AM UTC 24
Finished Aug 27 05:12:35 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422134213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2422134213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/129.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_alert_test.2318919766
Short name T446
Test name
Test status
Simulation time 12524171 ps
CPU time 0.85 seconds
Started Aug 27 04:43:00 AM UTC 24
Finished Aug 27 04:43:01 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318919766 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2318919766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_fifo_full.1543474711
Short name T345
Test name
Test status
Simulation time 113978022205 ps
CPU time 106.79 seconds
Started Aug 27 04:42:35 AM UTC 24
Finished Aug 27 04:44:24 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543474711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1543474711
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.2386096434
Short name T133
Test name
Test status
Simulation time 188796639992 ps
CPU time 83.75 seconds
Started Aug 27 04:42:36 AM UTC 24
Finished Aug 27 04:44:02 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386096434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2386096434
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_fifo_reset.2010325843
Short name T131
Test name
Test status
Simulation time 58809018080 ps
CPU time 44.79 seconds
Started Aug 27 04:42:39 AM UTC 24
Finished Aug 27 04:43:25 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010325843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2010325843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_intr.1856710171
Short name T284
Test name
Test status
Simulation time 39455273551 ps
CPU time 39.38 seconds
Started Aug 27 04:42:43 AM UTC 24
Finished Aug 27 04:43:23 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856710171 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1856710171
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.3683317944
Short name T716
Test name
Test status
Simulation time 174992174806 ps
CPU time 941.29 seconds
Started Aug 27 04:42:56 AM UTC 24
Finished Aug 27 04:58:48 AM UTC 24
Peak memory 212220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683317944 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3683317944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_loopback.359981592
Short name T445
Test name
Test status
Simulation time 882989294 ps
CPU time 1.13 seconds
Started Aug 27 04:42:55 AM UTC 24
Finished Aug 27 04:42:57 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359981592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.uart_loopback.359981592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_noise_filter.3291750900
Short name T266
Test name
Test status
Simulation time 34752986249 ps
CPU time 50.22 seconds
Started Aug 27 04:42:48 AM UTC 24
Finished Aug 27 04:43:40 AM UTC 24
Peak memory 208128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291750900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3291750900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_perf.2752347115
Short name T546
Test name
Test status
Simulation time 16982392865 ps
CPU time 452.41 seconds
Started Aug 27 04:42:56 AM UTC 24
Finished Aug 27 04:50:34 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752347115 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2752347115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_rx_oversample.2411479061
Short name T444
Test name
Test status
Simulation time 2326497360 ps
CPU time 14.56 seconds
Started Aug 27 04:42:40 AM UTC 24
Finished Aug 27 04:42:55 AM UTC 24
Peak memory 208040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411479061 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2411479061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.1180119542
Short name T156
Test name
Test status
Simulation time 96473745689 ps
CPU time 39.57 seconds
Started Aug 27 04:42:50 AM UTC 24
Finished Aug 27 04:43:31 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180119542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1180119542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.2320902215
Short name T357
Test name
Test status
Simulation time 1845247514 ps
CPU time 2.46 seconds
Started Aug 27 04:42:48 AM UTC 24
Finished Aug 27 04:42:51 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320902215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2320902215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_smoke.2472960212
Short name T355
Test name
Test status
Simulation time 933662155 ps
CPU time 6.65 seconds
Started Aug 27 04:42:34 AM UTC 24
Finished Aug 27 04:42:42 AM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472960212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2472960212
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_stress_all.3015734738
Short name T1165
Test name
Test status
Simulation time 205876169672 ps
CPU time 1971.75 seconds
Started Aug 27 04:43:00 AM UTC 24
Finished Aug 27 05:16:12 AM UTC 24
Peak memory 222652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015734738 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3015734738
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.100888795
Short name T98
Test name
Test status
Simulation time 16014289490 ps
CPU time 47.86 seconds
Started Aug 27 04:42:58 AM UTC 24
Finished Aug 27 04:43:48 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=100888795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all_
with_rand_reset.100888795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.1989787860
Short name T369
Test name
Test status
Simulation time 715215722 ps
CPU time 2.57 seconds
Started Aug 27 04:42:52 AM UTC 24
Finished Aug 27 04:42:56 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989787860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1989787860
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_tx_rx.3470314640
Short name T283
Test name
Test status
Simulation time 74671368702 ps
CPU time 39.24 seconds
Started Aug 27 04:42:34 AM UTC 24
Finished Aug 27 04:43:15 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470314640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3470314640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/13.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/130.uart_fifo_reset.2589421917
Short name T1046
Test name
Test status
Simulation time 99042777313 ps
CPU time 117.53 seconds
Started Aug 27 05:09:56 AM UTC 24
Finished Aug 27 05:11:56 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589421917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2589421917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/130.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/131.uart_fifo_reset.2298543837
Short name T1074
Test name
Test status
Simulation time 135319834698 ps
CPU time 176.69 seconds
Started Aug 27 05:09:58 AM UTC 24
Finished Aug 27 05:12:58 AM UTC 24
Peak memory 208512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298543837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2298543837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/131.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/132.uart_fifo_reset.2242710685
Short name T1097
Test name
Test status
Simulation time 92246033404 ps
CPU time 221.96 seconds
Started Aug 27 05:09:59 AM UTC 24
Finished Aug 27 05:13:45 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242710685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2242710685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/132.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/133.uart_fifo_reset.2460928152
Short name T1042
Test name
Test status
Simulation time 106472111488 ps
CPU time 105.4 seconds
Started Aug 27 05:10:01 AM UTC 24
Finished Aug 27 05:11:48 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460928152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2460928152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/133.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/134.uart_fifo_reset.1278688514
Short name T1028
Test name
Test status
Simulation time 45112890593 ps
CPU time 64.19 seconds
Started Aug 27 05:10:03 AM UTC 24
Finished Aug 27 05:11:08 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278688514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1278688514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/134.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/135.uart_fifo_reset.2787956464
Short name T167
Test name
Test status
Simulation time 78173909422 ps
CPU time 103.09 seconds
Started Aug 27 05:10:06 AM UTC 24
Finished Aug 27 05:11:51 AM UTC 24
Peak memory 208868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787956464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2787956464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/135.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/137.uart_fifo_reset.1492623037
Short name T204
Test name
Test status
Simulation time 75181629287 ps
CPU time 42.24 seconds
Started Aug 27 05:10:08 AM UTC 24
Finished Aug 27 05:10:52 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492623037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1492623037
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/137.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/138.uart_fifo_reset.1963003707
Short name T1021
Test name
Test status
Simulation time 66544570853 ps
CPU time 28.99 seconds
Started Aug 27 05:10:09 AM UTC 24
Finished Aug 27 05:10:39 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963003707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1963003707
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/138.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/139.uart_fifo_reset.536509910
Short name T1034
Test name
Test status
Simulation time 37294832479 ps
CPU time 64.83 seconds
Started Aug 27 05:10:10 AM UTC 24
Finished Aug 27 05:11:17 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536509910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.536509910
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/139.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_alert_test.2879926068
Short name T452
Test name
Test status
Simulation time 72996899 ps
CPU time 0.74 seconds
Started Aug 27 04:43:28 AM UTC 24
Finished Aug 27 04:43:30 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879926068 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2879926068
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_fifo_full.1633229001
Short name T135
Test name
Test status
Simulation time 41412905655 ps
CPU time 45.9 seconds
Started Aug 27 04:43:03 AM UTC 24
Finished Aug 27 04:43:50 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633229001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1633229001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_fifo_reset.3974005640
Short name T180
Test name
Test status
Simulation time 79468133949 ps
CPU time 77.56 seconds
Started Aug 27 04:43:05 AM UTC 24
Finished Aug 27 04:44:24 AM UTC 24
Peak memory 208324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974005640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3974005640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_intr.3560970195
Short name T449
Test name
Test status
Simulation time 4171098355 ps
CPU time 2.98 seconds
Started Aug 27 04:43:12 AM UTC 24
Finished Aug 27 04:43:17 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560970195 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3560970195
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.537009706
Short name T505
Test name
Test status
Simulation time 56157361159 ps
CPU time 282.56 seconds
Started Aug 27 04:43:25 AM UTC 24
Finished Aug 27 04:48:12 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537009706 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.537009706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_loopback.1390513678
Short name T451
Test name
Test status
Simulation time 563977090 ps
CPU time 2.67 seconds
Started Aug 27 04:43:20 AM UTC 24
Finished Aug 27 04:43:24 AM UTC 24
Peak memory 204972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390513678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1390513678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_noise_filter.2513340423
Short name T301
Test name
Test status
Simulation time 41512106445 ps
CPU time 39.91 seconds
Started Aug 27 04:43:14 AM UTC 24
Finished Aug 27 04:43:56 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513340423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2513340423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_perf.3058760025
Short name T481
Test name
Test status
Simulation time 36940545256 ps
CPU time 209.78 seconds
Started Aug 27 04:43:24 AM UTC 24
Finished Aug 27 04:46:57 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058760025 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3058760025
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_rx_oversample.795289328
Short name T448
Test name
Test status
Simulation time 1176115867 ps
CPU time 3 seconds
Started Aug 27 04:43:09 AM UTC 24
Finished Aug 27 04:43:13 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795289328 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.795289328
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.142858136
Short name T450
Test name
Test status
Simulation time 3594202614 ps
CPU time 3.57 seconds
Started Aug 27 04:43:15 AM UTC 24
Finished Aug 27 04:43:19 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142858136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.142858136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_smoke.423990122
Short name T447
Test name
Test status
Simulation time 493873881 ps
CPU time 1.92 seconds
Started Aug 27 04:43:02 AM UTC 24
Finished Aug 27 04:43:05 AM UTC 24
Peak memory 207044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423990122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.uart_smoke.423990122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.2049008259
Short name T84
Test name
Test status
Simulation time 9607176786 ps
CPU time 45.31 seconds
Started Aug 27 04:43:25 AM UTC 24
Finished Aug 27 04:44:12 AM UTC 24
Peak memory 217848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2049008259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all
_with_rand_reset.2049008259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.1714666464
Short name T377
Test name
Test status
Simulation time 944653496 ps
CPU time 5.55 seconds
Started Aug 27 04:43:18 AM UTC 24
Finished Aug 27 04:43:25 AM UTC 24
Peak memory 208528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714666464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1714666464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/14.uart_tx_rx.3998450321
Short name T348
Test name
Test status
Simulation time 45382258670 ps
CPU time 117.22 seconds
Started Aug 27 04:43:02 AM UTC 24
Finished Aug 27 04:45:01 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998450321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3998450321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/14.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/140.uart_fifo_reset.3824390095
Short name T220
Test name
Test status
Simulation time 44663978400 ps
CPU time 32.08 seconds
Started Aug 27 05:10:12 AM UTC 24
Finished Aug 27 05:10:46 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824390095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3824390095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/140.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/142.uart_fifo_reset.3923199793
Short name T1026
Test name
Test status
Simulation time 21671291527 ps
CPU time 37.6 seconds
Started Aug 27 05:10:13 AM UTC 24
Finished Aug 27 05:10:52 AM UTC 24
Peak memory 208984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923199793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3923199793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/142.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/143.uart_fifo_reset.1390834830
Short name T187
Test name
Test status
Simulation time 12967409097 ps
CPU time 39.26 seconds
Started Aug 27 05:10:16 AM UTC 24
Finished Aug 27 05:10:57 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390834830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1390834830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/143.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/144.uart_fifo_reset.3360024617
Short name T253
Test name
Test status
Simulation time 131581782236 ps
CPU time 71.08 seconds
Started Aug 27 05:10:21 AM UTC 24
Finished Aug 27 05:11:33 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360024617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3360024617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/144.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/145.uart_fifo_reset.3685336200
Short name T1041
Test name
Test status
Simulation time 38535699556 ps
CPU time 81.06 seconds
Started Aug 27 05:10:23 AM UTC 24
Finished Aug 27 05:11:46 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685336200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3685336200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/145.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/146.uart_fifo_reset.4269056197
Short name T1051
Test name
Test status
Simulation time 44676449375 ps
CPU time 95.36 seconds
Started Aug 27 05:10:26 AM UTC 24
Finished Aug 27 05:12:03 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269056197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.4269056197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/146.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/147.uart_fifo_reset.2601062069
Short name T416
Test name
Test status
Simulation time 35177355685 ps
CPU time 77.13 seconds
Started Aug 27 05:10:32 AM UTC 24
Finished Aug 27 05:11:51 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601062069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2601062069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/147.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/149.uart_fifo_reset.1102160365
Short name T1035
Test name
Test status
Simulation time 20551017493 ps
CPU time 40.16 seconds
Started Aug 27 05:10:37 AM UTC 24
Finished Aug 27 05:11:19 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102160365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1102160365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/149.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_alert_test.3735480516
Short name T458
Test name
Test status
Simulation time 14236181 ps
CPU time 0.83 seconds
Started Aug 27 04:44:13 AM UTC 24
Finished Aug 27 04:44:15 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735480516 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3735480516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_fifo_full.662006047
Short name T256
Test name
Test status
Simulation time 61560200492 ps
CPU time 414.7 seconds
Started Aug 27 04:43:36 AM UTC 24
Finished Aug 27 04:50:36 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662006047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.662006047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.3957997987
Short name T384
Test name
Test status
Simulation time 119523711617 ps
CPU time 255.89 seconds
Started Aug 27 04:43:38 AM UTC 24
Finished Aug 27 04:47:57 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957997987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3957997987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_intr.3499509592
Short name T361
Test name
Test status
Simulation time 36221829893 ps
CPU time 73.51 seconds
Started Aug 27 04:43:49 AM UTC 24
Finished Aug 27 04:45:04 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499509592 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3499509592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.3741355716
Short name T537
Test name
Test status
Simulation time 217670176202 ps
CPU time 369.57 seconds
Started Aug 27 04:43:59 AM UTC 24
Finished Aug 27 04:50:14 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741355716 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3741355716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_loopback.4005568654
Short name T457
Test name
Test status
Simulation time 4644963240 ps
CPU time 2.22 seconds
Started Aug 27 04:43:56 AM UTC 24
Finished Aug 27 04:44:00 AM UTC 24
Peak memory 207076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005568654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4005568654
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_noise_filter.2865192370
Short name T330
Test name
Test status
Simulation time 32736820241 ps
CPU time 22.55 seconds
Started Aug 27 04:43:51 AM UTC 24
Finished Aug 27 04:44:15 AM UTC 24
Peak memory 209028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865192370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2865192370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_perf.980225459
Short name T534
Test name
Test status
Simulation time 23255217147 ps
CPU time 359.45 seconds
Started Aug 27 04:43:59 AM UTC 24
Finished Aug 27 04:50:04 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980225459 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.980225459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_rx_oversample.2682830086
Short name T455
Test name
Test status
Simulation time 5281682153 ps
CPU time 3.43 seconds
Started Aug 27 04:43:49 AM UTC 24
Finished Aug 27 04:43:53 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682830086 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2682830086
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.4153881980
Short name T339
Test name
Test status
Simulation time 38428376753 ps
CPU time 43.19 seconds
Started Aug 27 04:43:54 AM UTC 24
Finished Aug 27 04:44:39 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153881980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4153881980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.3882550893
Short name T351
Test name
Test status
Simulation time 3461940393 ps
CPU time 4.7 seconds
Started Aug 27 04:43:53 AM UTC 24
Finished Aug 27 04:43:59 AM UTC 24
Peak memory 205028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882550893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3882550893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_smoke.2898732677
Short name T453
Test name
Test status
Simulation time 460369140 ps
CPU time 2.51 seconds
Started Aug 27 04:43:31 AM UTC 24
Finished Aug 27 04:43:35 AM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898732677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2898732677
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_stress_all.87959378
Short name T394
Test name
Test status
Simulation time 395032475545 ps
CPU time 470.39 seconds
Started Aug 27 04:44:03 AM UTC 24
Finished Aug 27 04:51:58 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87959378 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.87959378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.1450455539
Short name T324
Test name
Test status
Simulation time 10560110998 ps
CPU time 50.56 seconds
Started Aug 27 04:44:01 AM UTC 24
Finished Aug 27 04:44:53 AM UTC 24
Peak memory 217588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1450455539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all
_with_rand_reset.1450455539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.1826374795
Short name T456
Test name
Test status
Simulation time 868403249 ps
CPU time 3.25 seconds
Started Aug 27 04:43:54 AM UTC 24
Finished Aug 27 04:43:58 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826374795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1826374795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/15.uart_tx_rx.3158444189
Short name T299
Test name
Test status
Simulation time 86158702652 ps
CPU time 107.89 seconds
Started Aug 27 04:43:32 AM UTC 24
Finished Aug 27 04:45:23 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158444189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3158444189
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/15.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/150.uart_fifo_reset.1790929719
Short name T1053
Test name
Test status
Simulation time 38046848798 ps
CPU time 86.3 seconds
Started Aug 27 05:10:39 AM UTC 24
Finished Aug 27 05:12:07 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790929719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1790929719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/150.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/151.uart_fifo_reset.3605376151
Short name T1036
Test name
Test status
Simulation time 62810153643 ps
CPU time 42.31 seconds
Started Aug 27 05:10:40 AM UTC 24
Finished Aug 27 05:11:25 AM UTC 24
Peak memory 207900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605376151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3605376151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/151.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/152.uart_fifo_reset.1639137021
Short name T1031
Test name
Test status
Simulation time 77806518597 ps
CPU time 32.66 seconds
Started Aug 27 05:10:40 AM UTC 24
Finished Aug 27 05:11:15 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639137021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1639137021
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/152.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/153.uart_fifo_reset.3195493559
Short name T1030
Test name
Test status
Simulation time 25327017083 ps
CPU time 31.33 seconds
Started Aug 27 05:10:41 AM UTC 24
Finished Aug 27 05:11:14 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195493559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3195493559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/153.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/154.uart_fifo_reset.2336765888
Short name T184
Test name
Test status
Simulation time 165507094463 ps
CPU time 146.76 seconds
Started Aug 27 05:10:41 AM UTC 24
Finished Aug 27 05:13:11 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336765888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2336765888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/154.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/155.uart_fifo_reset.502437670
Short name T232
Test name
Test status
Simulation time 44988953532 ps
CPU time 112.55 seconds
Started Aug 27 05:10:46 AM UTC 24
Finished Aug 27 05:12:40 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502437670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.502437670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/155.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/156.uart_fifo_reset.1128736678
Short name T188
Test name
Test status
Simulation time 23287724295 ps
CPU time 37.37 seconds
Started Aug 27 05:10:47 AM UTC 24
Finished Aug 27 05:11:25 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128736678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1128736678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/156.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/157.uart_fifo_reset.336073369
Short name T1040
Test name
Test status
Simulation time 103102346907 ps
CPU time 52.83 seconds
Started Aug 27 05:10:47 AM UTC 24
Finished Aug 27 05:11:41 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336073369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.336073369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/157.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/158.uart_fifo_reset.1894159393
Short name T1029
Test name
Test status
Simulation time 11976044003 ps
CPU time 16.14 seconds
Started Aug 27 05:10:53 AM UTC 24
Finished Aug 27 05:11:10 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894159393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1894159393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/158.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_alert_test.2326389021
Short name T463
Test name
Test status
Simulation time 33363370 ps
CPU time 0.82 seconds
Started Aug 27 04:45:04 AM UTC 24
Finished Aug 27 04:45:06 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326389021 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2326389021
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_fifo_full.2019859557
Short name T344
Test name
Test status
Simulation time 148853299398 ps
CPU time 333.7 seconds
Started Aug 27 04:44:16 AM UTC 24
Finished Aug 27 04:49:54 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019859557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2019859557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.1001278077
Short name T121
Test name
Test status
Simulation time 14489591731 ps
CPU time 48.8 seconds
Started Aug 27 04:44:21 AM UTC 24
Finished Aug 27 04:45:11 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001278077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1001278077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_intr.2044947282
Short name T391
Test name
Test status
Simulation time 397415309164 ps
CPU time 169.38 seconds
Started Aug 27 04:44:27 AM UTC 24
Finished Aug 27 04:47:19 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044947282 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2044947282
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.431751260
Short name T752
Test name
Test status
Simulation time 87243488955 ps
CPU time 923.98 seconds
Started Aug 27 04:44:53 AM UTC 24
Finished Aug 27 05:00:28 AM UTC 24
Peak memory 212152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431751260 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.431751260
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_loopback.996422766
Short name T462
Test name
Test status
Simulation time 6938128749 ps
CPU time 13.61 seconds
Started Aug 27 04:44:48 AM UTC 24
Finished Aug 27 04:45:03 AM UTC 24
Peak memory 207868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996422766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.uart_loopback.996422766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_noise_filter.429092575
Short name T465
Test name
Test status
Simulation time 32259252144 ps
CPU time 34.38 seconds
Started Aug 27 04:44:35 AM UTC 24
Finished Aug 27 04:45:10 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429092575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.429092575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_perf.2485195681
Short name T577
Test name
Test status
Simulation time 30053777118 ps
CPU time 461.29 seconds
Started Aug 27 04:44:50 AM UTC 24
Finished Aug 27 04:52:37 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485195681 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2485195681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_rx_oversample.3427266310
Short name T460
Test name
Test status
Simulation time 3580518353 ps
CPU time 9.31 seconds
Started Aug 27 04:44:25 AM UTC 24
Finished Aug 27 04:44:36 AM UTC 24
Peak memory 207496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427266310 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3427266310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.1602071407
Short name T547
Test name
Test status
Simulation time 108208465225 ps
CPU time 350.87 seconds
Started Aug 27 04:44:40 AM UTC 24
Finished Aug 27 04:50:35 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602071407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1602071407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.3967389671
Short name T374
Test name
Test status
Simulation time 2857044890 ps
CPU time 11.74 seconds
Started Aug 27 04:44:37 AM UTC 24
Finished Aug 27 04:44:50 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967389671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3967389671
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_smoke.1799818357
Short name T459
Test name
Test status
Simulation time 5548104426 ps
CPU time 17.61 seconds
Started Aug 27 04:44:15 AM UTC 24
Finished Aug 27 04:44:34 AM UTC 24
Peak memory 208552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799818357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1799818357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_stress_all.1784469036
Short name T185
Test name
Test status
Simulation time 191426574011 ps
CPU time 116.34 seconds
Started Aug 27 04:45:03 AM UTC 24
Finished Aug 27 04:47:02 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784469036 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1784469036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.2073337210
Short name T379
Test name
Test status
Simulation time 2296134614 ps
CPU time 46.13 seconds
Started Aug 27 04:45:02 AM UTC 24
Finished Aug 27 04:45:50 AM UTC 24
Peak memory 217808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2073337210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all
_with_rand_reset.2073337210
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.1312593044
Short name T461
Test name
Test status
Simulation time 368624693 ps
CPU time 2.56 seconds
Started Aug 27 04:44:44 AM UTC 24
Finished Aug 27 04:44:47 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312593044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1312593044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/16.uart_tx_rx.1832343846
Short name T397
Test name
Test status
Simulation time 88996763763 ps
CPU time 47.11 seconds
Started Aug 27 04:44:16 AM UTC 24
Finished Aug 27 04:45:05 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832343846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1832343846
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/16.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/161.uart_fifo_reset.3801756928
Short name T1055
Test name
Test status
Simulation time 34461242614 ps
CPU time 72.97 seconds
Started Aug 27 05:10:58 AM UTC 24
Finished Aug 27 05:12:13 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801756928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3801756928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/161.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/162.uart_fifo_reset.2390259083
Short name T1131
Test name
Test status
Simulation time 53288296655 ps
CPU time 210.3 seconds
Started Aug 27 05:11:00 AM UTC 24
Finished Aug 27 05:14:34 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390259083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2390259083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/162.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/164.uart_fifo_reset.483392338
Short name T1052
Test name
Test status
Simulation time 115298876556 ps
CPU time 54.05 seconds
Started Aug 27 05:11:11 AM UTC 24
Finished Aug 27 05:12:07 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483392338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.483392338
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/164.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/165.uart_fifo_reset.1878257525
Short name T1038
Test name
Test status
Simulation time 12173831226 ps
CPU time 20.02 seconds
Started Aug 27 05:11:16 AM UTC 24
Finished Aug 27 05:11:37 AM UTC 24
Peak memory 208132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878257525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1878257525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/165.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/166.uart_fifo_reset.3716149076
Short name T1059
Test name
Test status
Simulation time 18512320385 ps
CPU time 61.89 seconds
Started Aug 27 05:11:16 AM UTC 24
Finished Aug 27 05:12:19 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716149076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3716149076
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/166.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/167.uart_fifo_reset.92625818
Short name T1112
Test name
Test status
Simulation time 56369025680 ps
CPU time 171.43 seconds
Started Aug 27 05:11:16 AM UTC 24
Finished Aug 27 05:14:10 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92625818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.92625818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/167.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/168.uart_fifo_reset.1130499940
Short name T1047
Test name
Test status
Simulation time 81832567284 ps
CPU time 39.3 seconds
Started Aug 27 05:11:17 AM UTC 24
Finished Aug 27 05:11:57 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130499940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1130499940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/168.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_alert_test.504800629
Short name T470
Test name
Test status
Simulation time 19351566 ps
CPU time 0.85 seconds
Started Aug 27 04:45:29 AM UTC 24
Finished Aug 27 04:45:31 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504800629 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.504800629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_fifo_full.1072835889
Short name T147
Test name
Test status
Simulation time 80421734055 ps
CPU time 39.66 seconds
Started Aug 27 04:45:10 AM UTC 24
Finished Aug 27 04:45:51 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072835889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1072835889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.542997198
Short name T277
Test name
Test status
Simulation time 236286413074 ps
CPU time 154.84 seconds
Started Aug 27 04:45:10 AM UTC 24
Finished Aug 27 04:47:48 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542997198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.542997198
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_fifo_reset.1543333974
Short name T399
Test name
Test status
Simulation time 9020721561 ps
CPU time 10.89 seconds
Started Aug 27 04:45:11 AM UTC 24
Finished Aug 27 04:45:23 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543333974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1543333974
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_intr.2991282302
Short name T467
Test name
Test status
Simulation time 9407164237 ps
CPU time 4.25 seconds
Started Aug 27 04:45:17 AM UTC 24
Finished Aug 27 04:45:22 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991282302 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2991282302
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.1167065375
Short name T656
Test name
Test status
Simulation time 113606375020 ps
CPU time 665.27 seconds
Started Aug 27 04:45:24 AM UTC 24
Finished Aug 27 04:56:36 AM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167065375 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1167065375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_loopback.1163248980
Short name T472
Test name
Test status
Simulation time 8029694964 ps
CPU time 26.28 seconds
Started Aug 27 04:45:24 AM UTC 24
Finished Aug 27 04:45:51 AM UTC 24
Peak memory 208736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163248980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1163248980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_noise_filter.2747587555
Short name T483
Test name
Test status
Simulation time 130399554544 ps
CPU time 101.05 seconds
Started Aug 27 04:45:17 AM UTC 24
Finished Aug 27 04:47:00 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747587555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2747587555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_perf.656665480
Short name T605
Test name
Test status
Simulation time 20217595933 ps
CPU time 538.62 seconds
Started Aug 27 04:45:24 AM UTC 24
Finished Aug 27 04:54:29 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656665480 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.656665480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_rx_oversample.3753499459
Short name T469
Test name
Test status
Simulation time 5394245183 ps
CPU time 14.13 seconds
Started Aug 27 04:45:12 AM UTC 24
Finished Aug 27 04:45:27 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753499459 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3753499459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.1816327806
Short name T468
Test name
Test status
Simulation time 4437885193 ps
CPU time 2.02 seconds
Started Aug 27 04:45:22 AM UTC 24
Finished Aug 27 04:45:25 AM UTC 24
Peak memory 207340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816327806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1816327806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_smoke.68446497
Short name T464
Test name
Test status
Simulation time 245718876 ps
CPU time 2.2 seconds
Started Aug 27 04:45:05 AM UTC 24
Finished Aug 27 04:45:09 AM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68446497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_smoke.68446497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_stress_all.2042133083
Short name T473
Test name
Test status
Simulation time 61115009980 ps
CPU time 50.92 seconds
Started Aug 27 04:45:28 AM UTC 24
Finished Aug 27 04:46:20 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042133083 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2042133083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.3925605244
Short name T97
Test name
Test status
Simulation time 8282222247 ps
CPU time 44.84 seconds
Started Aug 27 04:45:26 AM UTC 24
Finished Aug 27 04:46:12 AM UTC 24
Peak memory 219836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3925605244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all
_with_rand_reset.3925605244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.1592058644
Short name T471
Test name
Test status
Simulation time 1125418997 ps
CPU time 7.29 seconds
Started Aug 27 04:45:24 AM UTC 24
Finished Aug 27 04:45:32 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592058644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1592058644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/17.uart_tx_rx.1710295706
Short name T466
Test name
Test status
Simulation time 3782513292 ps
CPU time 13.18 seconds
Started Aug 27 04:45:07 AM UTC 24
Finished Aug 27 04:45:21 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710295706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1710295706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/17.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/170.uart_fifo_reset.4191644948
Short name T1163
Test name
Test status
Simulation time 95747158531 ps
CPU time 283.95 seconds
Started Aug 27 05:11:18 AM UTC 24
Finished Aug 27 05:16:06 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191644948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.4191644948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/170.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/171.uart_fifo_reset.3786647045
Short name T1061
Test name
Test status
Simulation time 24441699704 ps
CPU time 67.79 seconds
Started Aug 27 05:11:19 AM UTC 24
Finished Aug 27 05:12:28 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786647045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3786647045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/171.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/172.uart_fifo_reset.1265199116
Short name T1089
Test name
Test status
Simulation time 326008870634 ps
CPU time 119.16 seconds
Started Aug 27 05:11:25 AM UTC 24
Finished Aug 27 05:13:26 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265199116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1265199116
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/172.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/173.uart_fifo_reset.1408392185
Short name T1045
Test name
Test status
Simulation time 126524831531 ps
CPU time 23.45 seconds
Started Aug 27 05:11:26 AM UTC 24
Finished Aug 27 05:11:51 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408392185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1408392185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/173.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/174.uart_fifo_reset.3768889325
Short name T1124
Test name
Test status
Simulation time 102274613825 ps
CPU time 175.04 seconds
Started Aug 27 05:11:27 AM UTC 24
Finished Aug 27 05:14:25 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768889325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3768889325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/174.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/175.uart_fifo_reset.2642107378
Short name T1108
Test name
Test status
Simulation time 61636095328 ps
CPU time 146.37 seconds
Started Aug 27 05:11:34 AM UTC 24
Finished Aug 27 05:14:03 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642107378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2642107378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/175.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/176.uart_fifo_reset.1907452507
Short name T1048
Test name
Test status
Simulation time 38090359699 ps
CPU time 21.91 seconds
Started Aug 27 05:11:36 AM UTC 24
Finished Aug 27 05:11:59 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907452507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1907452507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/176.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/177.uart_fifo_reset.3138886730
Short name T1156
Test name
Test status
Simulation time 118831762270 ps
CPU time 231.81 seconds
Started Aug 27 05:11:38 AM UTC 24
Finished Aug 27 05:15:33 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138886730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3138886730
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/177.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/178.uart_fifo_reset.296894466
Short name T1056
Test name
Test status
Simulation time 43192073918 ps
CPU time 36.39 seconds
Started Aug 27 05:11:39 AM UTC 24
Finished Aug 27 05:12:16 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296894466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.296894466
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/178.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/179.uart_fifo_reset.482043253
Short name T1096
Test name
Test status
Simulation time 219109806865 ps
CPU time 122.39 seconds
Started Aug 27 05:11:40 AM UTC 24
Finished Aug 27 05:13:44 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482043253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.482043253
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/179.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_alert_test.660814047
Short name T480
Test name
Test status
Simulation time 36381283 ps
CPU time 0.81 seconds
Started Aug 27 04:46:35 AM UTC 24
Finished Aug 27 04:46:37 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660814047 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.660814047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_fifo_full.730102332
Short name T336
Test name
Test status
Simulation time 107827420188 ps
CPU time 208.67 seconds
Started Aug 27 04:45:43 AM UTC 24
Finished Aug 27 04:49:15 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730102332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.730102332
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.3844528250
Short name T479
Test name
Test status
Simulation time 62113874105 ps
CPU time 46.8 seconds
Started Aug 27 04:45:47 AM UTC 24
Finished Aug 27 04:46:36 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844528250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3844528250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_fifo_reset.3842460279
Short name T474
Test name
Test status
Simulation time 40291179512 ps
CPU time 31.75 seconds
Started Aug 27 04:45:50 AM UTC 24
Finished Aug 27 04:46:24 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842460279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3842460279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_intr.1184703220
Short name T476
Test name
Test status
Simulation time 52201656770 ps
CPU time 33.78 seconds
Started Aug 27 04:45:52 AM UTC 24
Finished Aug 27 04:46:27 AM UTC 24
Peak memory 208168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184703220 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1184703220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.1251430755
Short name T641
Test name
Test status
Simulation time 66608440775 ps
CPU time 581.58 seconds
Started Aug 27 04:46:26 AM UTC 24
Finished Aug 27 04:56:14 AM UTC 24
Peak memory 210476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251430755 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1251430755
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_loopback.3787792727
Short name T477
Test name
Test status
Simulation time 7950047119 ps
CPU time 11.32 seconds
Started Aug 27 04:46:21 AM UTC 24
Finished Aug 27 04:46:34 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787792727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3787792727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_noise_filter.1087800708
Short name T294
Test name
Test status
Simulation time 155110009796 ps
CPU time 84.81 seconds
Started Aug 27 04:46:02 AM UTC 24
Finished Aug 27 04:47:29 AM UTC 24
Peak memory 219632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087800708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1087800708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_perf.934251192
Short name T380
Test name
Test status
Simulation time 9885172930 ps
CPU time 120.01 seconds
Started Aug 27 04:46:24 AM UTC 24
Finished Aug 27 04:48:27 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934251192 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.934251192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1433058868
Short name T487
Test name
Test status
Simulation time 7632381362 ps
CPU time 78.15 seconds
Started Aug 27 04:45:52 AM UTC 24
Finished Aug 27 04:47:12 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433058868 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1433058868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.442533333
Short name T90
Test name
Test status
Simulation time 33650155279 ps
CPU time 24.58 seconds
Started Aug 27 04:46:13 AM UTC 24
Finished Aug 27 04:46:39 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442533333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.442533333
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.1861326413
Short name T475
Test name
Test status
Simulation time 5574001951 ps
CPU time 16.57 seconds
Started Aug 27 04:46:07 AM UTC 24
Finished Aug 27 04:46:25 AM UTC 24
Peak memory 205028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861326413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1861326413
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_smoke.2263213313
Short name T349
Test name
Test status
Simulation time 5903213706 ps
CPU time 27.24 seconds
Started Aug 27 04:45:32 AM UTC 24
Finished Aug 27 04:46:01 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263213313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2263213313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.847808389
Short name T478
Test name
Test status
Simulation time 7840673282 ps
CPU time 15.19 seconds
Started Aug 27 04:46:19 AM UTC 24
Finished Aug 27 04:46:36 AM UTC 24
Peak memory 208488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847808389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.847808389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/18.uart_tx_rx.716486165
Short name T335
Test name
Test status
Simulation time 140818220507 ps
CPU time 195.63 seconds
Started Aug 27 04:45:33 AM UTC 24
Finished Aug 27 04:48:52 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716486165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.716486165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/18.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/180.uart_fifo_reset.2811852395
Short name T1049
Test name
Test status
Simulation time 42901174543 ps
CPU time 17.98 seconds
Started Aug 27 05:11:40 AM UTC 24
Finished Aug 27 05:11:59 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811852395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2811852395
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/180.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/181.uart_fifo_reset.379719667
Short name T212
Test name
Test status
Simulation time 18969545643 ps
CPU time 36.77 seconds
Started Aug 27 05:11:41 AM UTC 24
Finished Aug 27 05:12:19 AM UTC 24
Peak memory 208496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379719667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.379719667
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/181.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/182.uart_fifo_reset.2232551029
Short name T1067
Test name
Test status
Simulation time 82164516245 ps
CPU time 54.46 seconds
Started Aug 27 05:11:42 AM UTC 24
Finished Aug 27 05:12:38 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232551029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2232551029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/182.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/183.uart_fifo_reset.2310573911
Short name T242
Test name
Test status
Simulation time 69422582177 ps
CPU time 63.82 seconds
Started Aug 27 05:11:46 AM UTC 24
Finished Aug 27 05:12:52 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310573911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2310573911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/183.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/184.uart_fifo_reset.90349311
Short name T1058
Test name
Test status
Simulation time 178763022376 ps
CPU time 27.63 seconds
Started Aug 27 05:11:49 AM UTC 24
Finished Aug 27 05:12:18 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90349311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.90349311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/184.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/185.uart_fifo_reset.3163363896
Short name T1076
Test name
Test status
Simulation time 20642001417 ps
CPU time 71.19 seconds
Started Aug 27 05:11:49 AM UTC 24
Finished Aug 27 05:13:02 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163363896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3163363896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/185.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/186.uart_fifo_reset.1273904399
Short name T205
Test name
Test status
Simulation time 7883511213 ps
CPU time 16.85 seconds
Started Aug 27 05:11:50 AM UTC 24
Finished Aug 27 05:12:08 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273904399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1273904399
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/186.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/187.uart_fifo_reset.3588301335
Short name T1064
Test name
Test status
Simulation time 52447916943 ps
CPU time 38.63 seconds
Started Aug 27 05:11:52 AM UTC 24
Finished Aug 27 05:12:32 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588301335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3588301335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/187.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/188.uart_fifo_reset.3173954934
Short name T1092
Test name
Test status
Simulation time 66730841652 ps
CPU time 100.14 seconds
Started Aug 27 05:11:52 AM UTC 24
Finished Aug 27 05:13:34 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173954934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3173954934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/188.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/189.uart_fifo_reset.3789688696
Short name T1160
Test name
Test status
Simulation time 108986283863 ps
CPU time 238.85 seconds
Started Aug 27 05:11:52 AM UTC 24
Finished Aug 27 05:15:54 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789688696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3789688696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/189.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_alert_test.1517450289
Short name T488
Test name
Test status
Simulation time 19002365 ps
CPU time 0.82 seconds
Started Aug 27 04:47:11 AM UTC 24
Finished Aug 27 04:47:13 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517450289 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1517450289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.4162422218
Short name T485
Test name
Test status
Simulation time 17338741139 ps
CPU time 24.78 seconds
Started Aug 27 04:46:40 AM UTC 24
Finished Aug 27 04:47:06 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162422218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.4162422218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_fifo_reset.829885310
Short name T352
Test name
Test status
Simulation time 51687955187 ps
CPU time 92.07 seconds
Started Aug 27 04:46:44 AM UTC 24
Finished Aug 27 04:48:18 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829885310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.829885310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_intr.727893692
Short name T486
Test name
Test status
Simulation time 25095252127 ps
CPU time 13.11 seconds
Started Aug 27 04:46:57 AM UTC 24
Finished Aug 27 04:47:11 AM UTC 24
Peak memory 207948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727893692 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.727893692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.3011792946
Short name T532
Test name
Test status
Simulation time 264851188444 ps
CPU time 161.52 seconds
Started Aug 27 04:47:07 AM UTC 24
Finished Aug 27 04:49:51 AM UTC 24
Peak memory 208380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011792946 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3011792946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_loopback.374544666
Short name T490
Test name
Test status
Simulation time 6199897553 ps
CPU time 17.77 seconds
Started Aug 27 04:47:03 AM UTC 24
Finished Aug 27 04:47:22 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374544666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.uart_loopback.374544666
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_noise_filter.2741400213
Short name T491
Test name
Test status
Simulation time 15710731341 ps
CPU time 30.46 seconds
Started Aug 27 04:46:58 AM UTC 24
Finished Aug 27 04:47:30 AM UTC 24
Peak memory 207480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741400213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2741400213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_perf.2533800501
Short name T1081
Test name
Test status
Simulation time 26780526122 ps
CPU time 1545.81 seconds
Started Aug 27 04:47:07 AM UTC 24
Finished Aug 27 05:13:09 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533800501 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2533800501
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_rx_oversample.3773739431
Short name T492
Test name
Test status
Simulation time 4550294322 ps
CPU time 36.84 seconds
Started Aug 27 04:46:51 AM UTC 24
Finished Aug 27 04:47:30 AM UTC 24
Peak memory 207476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773739431 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3773739431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.1053893864
Short name T138
Test name
Test status
Simulation time 34416569098 ps
CPU time 71.44 seconds
Started Aug 27 04:47:01 AM UTC 24
Finished Aug 27 04:48:14 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053893864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1053893864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.3342064884
Short name T489
Test name
Test status
Simulation time 3730952242 ps
CPU time 14.52 seconds
Started Aug 27 04:46:59 AM UTC 24
Finished Aug 27 04:47:14 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342064884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3342064884
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_smoke.2593345274
Short name T362
Test name
Test status
Simulation time 5584948394 ps
CPU time 4.56 seconds
Started Aug 27 04:46:37 AM UTC 24
Finished Aug 27 04:46:43 AM UTC 24
Peak memory 208440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593345274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2593345274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.1870906423
Short name T496
Test name
Test status
Simulation time 6488783396 ps
CPU time 38.49 seconds
Started Aug 27 04:47:08 AM UTC 24
Finished Aug 27 04:47:48 AM UTC 24
Peak memory 217748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1870906423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all
_with_rand_reset.1870906423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.2089334201
Short name T484
Test name
Test status
Simulation time 618438270 ps
CPU time 3.03 seconds
Started Aug 27 04:47:02 AM UTC 24
Finished Aug 27 04:47:06 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089334201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2089334201
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_tx_rx.1036394203
Short name T482
Test name
Test status
Simulation time 36578338351 ps
CPU time 19.1 seconds
Started Aug 27 04:46:37 AM UTC 24
Finished Aug 27 04:46:58 AM UTC 24
Peak memory 208592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036394203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1036394203
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/19.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/190.uart_fifo_reset.3818750080
Short name T1088
Test name
Test status
Simulation time 66015603949 ps
CPU time 84.34 seconds
Started Aug 27 05:11:57 AM UTC 24
Finished Aug 27 05:13:23 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818750080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3818750080
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/190.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/192.uart_fifo_reset.458842689
Short name T1072
Test name
Test status
Simulation time 44703827457 ps
CPU time 53.94 seconds
Started Aug 27 05:12:00 AM UTC 24
Finished Aug 27 05:12:56 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458842689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.458842689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/192.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3586686503
Short name T1095
Test name
Test status
Simulation time 105030851874 ps
CPU time 101.73 seconds
Started Aug 27 05:12:00 AM UTC 24
Finished Aug 27 05:13:44 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586686503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3586686503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/193.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/194.uart_fifo_reset.2150840197
Short name T1174
Test name
Test status
Simulation time 185470505052 ps
CPU time 449.3 seconds
Started Aug 27 05:12:00 AM UTC 24
Finished Aug 27 05:19:35 AM UTC 24
Peak memory 212352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150840197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2150840197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/194.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/195.uart_fifo_reset.93837351
Short name T1127
Test name
Test status
Simulation time 64242058423 ps
CPU time 142.16 seconds
Started Aug 27 05:12:04 AM UTC 24
Finished Aug 27 05:14:29 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93837351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.93837351
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/195.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/196.uart_fifo_reset.2365159470
Short name T1062
Test name
Test status
Simulation time 51905347009 ps
CPU time 21.81 seconds
Started Aug 27 05:12:07 AM UTC 24
Finished Aug 27 05:12:30 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365159470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2365159470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/196.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/197.uart_fifo_reset.2230367205
Short name T162
Test name
Test status
Simulation time 50155893580 ps
CPU time 20.2 seconds
Started Aug 27 05:12:08 AM UTC 24
Finished Aug 27 05:12:30 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230367205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2230367205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/197.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/198.uart_fifo_reset.2600476632
Short name T202
Test name
Test status
Simulation time 38360359288 ps
CPU time 17.79 seconds
Started Aug 27 05:12:08 AM UTC 24
Finished Aug 27 05:12:28 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600476632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2600476632
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/198.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/199.uart_fifo_reset.1116560257
Short name T1123
Test name
Test status
Simulation time 92056119421 ps
CPU time 131.93 seconds
Started Aug 27 05:12:09 AM UTC 24
Finished Aug 27 05:14:23 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116560257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1116560257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/199.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_alert_test.660204517
Short name T73
Test name
Test status
Simulation time 13140821 ps
CPU time 0.82 seconds
Started Aug 27 04:36:35 AM UTC 24
Finished Aug 27 04:36:38 AM UTC 24
Peak memory 204432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660204517 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.660204517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.197487051
Short name T46
Test name
Test status
Simulation time 141495114398 ps
CPU time 179.99 seconds
Started Aug 27 04:35:57 AM UTC 24
Finished Aug 27 04:39:00 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197487051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.197487051
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_intr.2472123434
Short name T22
Test name
Test status
Simulation time 8832791946 ps
CPU time 9.16 seconds
Started Aug 27 04:36:05 AM UTC 24
Finished Aug 27 04:36:16 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472123434 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2472123434
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.4188784482
Short name T311
Test name
Test status
Simulation time 117246604819 ps
CPU time 293.39 seconds
Started Aug 27 04:36:23 AM UTC 24
Finished Aug 27 04:41:21 AM UTC 24
Peak memory 207804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188784482 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4188784482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_loopback.1475507919
Short name T25
Test name
Test status
Simulation time 7404719803 ps
CPU time 18.14 seconds
Started Aug 27 04:36:22 AM UTC 24
Finished Aug 27 04:36:41 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475507919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1475507919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_noise_filter.3257009454
Short name T302
Test name
Test status
Simulation time 19826407166 ps
CPU time 42.74 seconds
Started Aug 27 04:36:11 AM UTC 24
Finished Aug 27 04:36:56 AM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257009454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3257009454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_perf.2460988028
Short name T290
Test name
Test status
Simulation time 10419614310 ps
CPU time 207.03 seconds
Started Aug 27 04:36:23 AM UTC 24
Finished Aug 27 04:39:53 AM UTC 24
Peak memory 207820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460988028 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2460988028
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_rx_oversample.931031640
Short name T68
Test name
Test status
Simulation time 2332171821 ps
CPU time 21.6 seconds
Started Aug 27 04:35:59 AM UTC 24
Finished Aug 27 04:36:22 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931031640 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.931031640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.1307552355
Short name T89
Test name
Test status
Simulation time 15380020469 ps
CPU time 30.19 seconds
Started Aug 27 04:36:17 AM UTC 24
Finished Aug 27 04:36:48 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307552355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1307552355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.1048482872
Short name T315
Test name
Test status
Simulation time 38931247980 ps
CPU time 58.05 seconds
Started Aug 27 04:36:12 AM UTC 24
Finished Aug 27 04:37:12 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048482872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1048482872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_sec_cm.2583528862
Short name T32
Test name
Test status
Simulation time 238101856 ps
CPU time 1.34 seconds
Started Aug 27 04:36:32 AM UTC 24
Finished Aug 27 04:36:35 AM UTC 24
Peak memory 240132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583528862 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2583528862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_smoke.676265038
Short name T40
Test name
Test status
Simulation time 688449054 ps
CPU time 4.25 seconds
Started Aug 27 04:35:53 AM UTC 24
Finished Aug 27 04:35:58 AM UTC 24
Peak memory 207096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676265038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.uart_smoke.676265038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_stress_all.3139235433
Short name T313
Test name
Test status
Simulation time 385550046118 ps
CPU time 552.41 seconds
Started Aug 27 04:36:27 AM UTC 24
Finished Aug 27 04:45:46 AM UTC 24
Peak memory 217756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139235433 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3139235433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.1082563276
Short name T41
Test name
Test status
Simulation time 2012445538 ps
CPU time 2.59 seconds
Started Aug 27 04:36:22 AM UTC 24
Finished Aug 27 04:36:26 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082563276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1082563276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/2.uart_tx_rx.3648062102
Short name T86
Test name
Test status
Simulation time 35748898737 ps
CPU time 31.16 seconds
Started Aug 27 04:35:54 AM UTC 24
Finished Aug 27 04:36:26 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648062102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3648062102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/2.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_alert_test.1242869620
Short name T499
Test name
Test status
Simulation time 12287113 ps
CPU time 0.82 seconds
Started Aug 27 04:47:51 AM UTC 24
Finished Aug 27 04:47:53 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242869620 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1242869620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_fifo_full.248201309
Short name T598
Test name
Test status
Simulation time 244280614079 ps
CPU time 417.02 seconds
Started Aug 27 04:47:16 AM UTC 24
Finished Aug 27 04:54:18 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248201309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.248201309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.679398204
Short name T143
Test name
Test status
Simulation time 91639572046 ps
CPU time 150.29 seconds
Started Aug 27 04:47:17 AM UTC 24
Finished Aug 27 04:49:50 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679398204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.679398204
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_intr.1702589560
Short name T363
Test name
Test status
Simulation time 49115684931 ps
CPU time 121.65 seconds
Started Aug 27 04:47:23 AM UTC 24
Finished Aug 27 04:49:27 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702589560 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1702589560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.1997146421
Short name T891
Test name
Test status
Simulation time 144258009940 ps
CPU time 1010.85 seconds
Started Aug 27 04:47:48 AM UTC 24
Finished Aug 27 05:04:50 AM UTC 24
Peak memory 212304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997146421 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1997146421
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_loopback.44390368
Short name T502
Test name
Test status
Simulation time 8740942383 ps
CPU time 25.13 seconds
Started Aug 27 04:47:40 AM UTC 24
Finished Aug 27 04:48:06 AM UTC 24
Peak memory 207356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44390368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.uart_loopback.44390368
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_noise_filter.1276365551
Short name T337
Test name
Test status
Simulation time 185667947175 ps
CPU time 146.59 seconds
Started Aug 27 04:47:29 AM UTC 24
Finished Aug 27 04:49:58 AM UTC 24
Peak memory 208948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276365551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1276365551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_perf.3205595793
Short name T587
Test name
Test status
Simulation time 10733158524 ps
CPU time 326.1 seconds
Started Aug 27 04:47:42 AM UTC 24
Finished Aug 27 04:53:12 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205595793 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3205595793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_rx_oversample.1848487036
Short name T493
Test name
Test status
Simulation time 5486177972 ps
CPU time 16.71 seconds
Started Aug 27 04:47:21 AM UTC 24
Finished Aug 27 04:47:39 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848487036 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1848487036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.566261208
Short name T150
Test name
Test status
Simulation time 48238819544 ps
CPU time 31.75 seconds
Started Aug 27 04:47:30 AM UTC 24
Finished Aug 27 04:48:03 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566261208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.566261208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.2668595007
Short name T494
Test name
Test status
Simulation time 27434076688 ps
CPU time 9.45 seconds
Started Aug 27 04:47:30 AM UTC 24
Finished Aug 27 04:47:41 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668595007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2668595007
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_smoke.2588195120
Short name T495
Test name
Test status
Simulation time 5913296663 ps
CPU time 33.91 seconds
Started Aug 27 04:47:13 AM UTC 24
Finished Aug 27 04:47:48 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588195120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2588195120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_stress_all.3686830905
Short name T182
Test name
Test status
Simulation time 223039468076 ps
CPU time 430.1 seconds
Started Aug 27 04:47:49 AM UTC 24
Finished Aug 27 04:55:04 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686830905 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3686830905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.861298307
Short name T387
Test name
Test status
Simulation time 10366423581 ps
CPU time 70.62 seconds
Started Aug 27 04:47:49 AM UTC 24
Finished Aug 27 04:49:01 AM UTC 24
Peak memory 217660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=861298307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all_
with_rand_reset.861298307
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.1142505441
Short name T498
Test name
Test status
Simulation time 8644235386 ps
CPU time 14.82 seconds
Started Aug 27 04:47:35 AM UTC 24
Finished Aug 27 04:47:51 AM UTC 24
Peak memory 208392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142505441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1142505441
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/20.uart_tx_rx.1429163898
Short name T504
Test name
Test status
Simulation time 89524372434 ps
CPU time 52.71 seconds
Started Aug 27 04:47:15 AM UTC 24
Finished Aug 27 04:48:09 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429163898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1429163898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/20.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/200.uart_fifo_reset.3857182172
Short name T1070
Test name
Test status
Simulation time 82163604637 ps
CPU time 33.32 seconds
Started Aug 27 05:12:10 AM UTC 24
Finished Aug 27 05:12:44 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857182172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3857182172
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/200.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/201.uart_fifo_reset.4104452119
Short name T1068
Test name
Test status
Simulation time 23031142146 ps
CPU time 28.41 seconds
Started Aug 27 05:12:14 AM UTC 24
Finished Aug 27 05:12:44 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104452119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.4104452119
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/201.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3564303658
Short name T203
Test name
Test status
Simulation time 25034490373 ps
CPU time 39.85 seconds
Started Aug 27 05:12:15 AM UTC 24
Finished Aug 27 05:12:56 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564303658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3564303658
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/202.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/203.uart_fifo_reset.3597607979
Short name T209
Test name
Test status
Simulation time 6485664123 ps
CPU time 8.17 seconds
Started Aug 27 05:12:16 AM UTC 24
Finished Aug 27 05:12:26 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597607979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3597607979
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/203.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/204.uart_fifo_reset.1293616958
Short name T1169
Test name
Test status
Simulation time 143111207884 ps
CPU time 268.42 seconds
Started Aug 27 05:12:16 AM UTC 24
Finished Aug 27 05:16:48 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293616958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1293616958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/204.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/209.uart_fifo_reset.2605121247
Short name T1073
Test name
Test status
Simulation time 52987472762 ps
CPU time 34.43 seconds
Started Aug 27 05:12:20 AM UTC 24
Finished Aug 27 05:12:56 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605121247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2605121247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/209.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_alert_test.1259125713
Short name T509
Test name
Test status
Simulation time 25980983 ps
CPU time 0.86 seconds
Started Aug 27 04:48:28 AM UTC 24
Finished Aug 27 04:48:30 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259125713 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1259125713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_fifo_full.3800122486
Short name T510
Test name
Test status
Simulation time 17812421605 ps
CPU time 35.39 seconds
Started Aug 27 04:47:54 AM UTC 24
Finished Aug 27 04:48:31 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800122486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3800122486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.1404675554
Short name T327
Test name
Test status
Simulation time 124480125329 ps
CPU time 65.92 seconds
Started Aug 27 04:47:57 AM UTC 24
Finished Aug 27 04:49:04 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404675554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1404675554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_fifo_reset.1436367386
Short name T411
Test name
Test status
Simulation time 46188565949 ps
CPU time 38.95 seconds
Started Aug 27 04:47:58 AM UTC 24
Finished Aug 27 04:48:38 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436367386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1436367386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_intr.4226180749
Short name T506
Test name
Test status
Simulation time 12890317197 ps
CPU time 6.57 seconds
Started Aug 27 04:48:05 AM UTC 24
Finished Aug 27 04:48:12 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226180749 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.4226180749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.343745882
Short name T536
Test name
Test status
Simulation time 51812691879 ps
CPU time 115.91 seconds
Started Aug 27 04:48:16 AM UTC 24
Finished Aug 27 04:50:14 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343745882 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.343745882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_loopback.3029532309
Short name T517
Test name
Test status
Simulation time 9019541576 ps
CPU time 33.18 seconds
Started Aug 27 04:48:13 AM UTC 24
Finished Aug 27 04:48:48 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029532309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3029532309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_noise_filter.2729388326
Short name T400
Test name
Test status
Simulation time 62107007882 ps
CPU time 61.15 seconds
Started Aug 27 04:48:07 AM UTC 24
Finished Aug 27 04:49:10 AM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729388326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2729388326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_perf.1258450045
Short name T375
Test name
Test status
Simulation time 16999408831 ps
CPU time 70.84 seconds
Started Aug 27 04:48:14 AM UTC 24
Finished Aug 27 04:49:27 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258450045 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1258450045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_rx_oversample.4280098231
Short name T514
Test name
Test status
Simulation time 3568800834 ps
CPU time 37.27 seconds
Started Aug 27 04:48:05 AM UTC 24
Finished Aug 27 04:48:43 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280098231 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.4280098231
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.2124748404
Short name T515
Test name
Test status
Simulation time 20695686506 ps
CPU time 34.51 seconds
Started Aug 27 04:48:10 AM UTC 24
Finished Aug 27 04:48:46 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124748404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2124748404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.2174795213
Short name T364
Test name
Test status
Simulation time 33428031300 ps
CPU time 28.69 seconds
Started Aug 27 04:48:08 AM UTC 24
Finished Aug 27 04:48:38 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174795213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2174795213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_smoke.4047144839
Short name T501
Test name
Test status
Simulation time 1004230061 ps
CPU time 1.72 seconds
Started Aug 27 04:47:53 AM UTC 24
Finished Aug 27 04:47:56 AM UTC 24
Peak memory 206320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047144839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.4047144839
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_stress_all.1607247190
Short name T157
Test name
Test status
Simulation time 648002678877 ps
CPU time 789.47 seconds
Started Aug 27 04:48:22 AM UTC 24
Finished Aug 27 05:01:40 AM UTC 24
Peak memory 212404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607247190 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1607247190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.2136730944
Short name T513
Test name
Test status
Simulation time 880417265 ps
CPU time 17.76 seconds
Started Aug 27 04:48:19 AM UTC 24
Finished Aug 27 04:48:38 AM UTC 24
Peak memory 217668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2136730944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all
_with_rand_reset.2136730944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.1166146612
Short name T508
Test name
Test status
Simulation time 785381616 ps
CPU time 1.54 seconds
Started Aug 27 04:48:12 AM UTC 24
Finished Aug 27 04:48:15 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166146612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1166146612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/21.uart_tx_rx.3251576599
Short name T401
Test name
Test status
Simulation time 5970737686 ps
CPU time 8.74 seconds
Started Aug 27 04:47:54 AM UTC 24
Finished Aug 27 04:48:04 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251576599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3251576599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/21.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3450677111
Short name T1071
Test name
Test status
Simulation time 35825365799 ps
CPU time 32.81 seconds
Started Aug 27 05:12:21 AM UTC 24
Finished Aug 27 05:12:55 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450677111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3450677111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/210.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/213.uart_fifo_reset.1616037274
Short name T225
Test name
Test status
Simulation time 102333097666 ps
CPU time 304.35 seconds
Started Aug 27 05:12:27 AM UTC 24
Finished Aug 27 05:17:35 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616037274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1616037274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/213.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/214.uart_fifo_reset.1790858698
Short name T1130
Test name
Test status
Simulation time 50617638550 ps
CPU time 122.81 seconds
Started Aug 27 05:12:28 AM UTC 24
Finished Aug 27 05:14:33 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790858698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1790858698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/214.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/215.uart_fifo_reset.542122453
Short name T1077
Test name
Test status
Simulation time 34108306125 ps
CPU time 32.42 seconds
Started Aug 27 05:12:29 AM UTC 24
Finished Aug 27 05:13:03 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542122453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.542122453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/215.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1219629423
Short name T1069
Test name
Test status
Simulation time 23795911775 ps
CPU time 14.01 seconds
Started Aug 27 05:12:29 AM UTC 24
Finished Aug 27 05:12:44 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219629423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1219629423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/216.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/217.uart_fifo_reset.429608131
Short name T1083
Test name
Test status
Simulation time 110354299284 ps
CPU time 40.15 seconds
Started Aug 27 05:12:31 AM UTC 24
Finished Aug 27 05:13:13 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429608131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.429608131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/217.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/219.uart_fifo_reset.145395753
Short name T1119
Test name
Test status
Simulation time 42671128847 ps
CPU time 103.24 seconds
Started Aug 27 05:12:32 AM UTC 24
Finished Aug 27 05:14:18 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145395753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.145395753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/219.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_alert_test.3430694923
Short name T522
Test name
Test status
Simulation time 26792296 ps
CPU time 0.83 seconds
Started Aug 27 04:49:02 AM UTC 24
Finished Aug 27 04:49:04 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430694923 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3430694923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_fifo_full.1233483500
Short name T519
Test name
Test status
Simulation time 21576581900 ps
CPU time 21.18 seconds
Started Aug 27 04:48:34 AM UTC 24
Finished Aug 27 04:48:56 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233483500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1233483500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.108806387
Short name T255
Test name
Test status
Simulation time 78593776565 ps
CPU time 66.64 seconds
Started Aug 27 04:48:34 AM UTC 24
Finished Aug 27 04:49:42 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108806387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.108806387
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_intr.2372897434
Short name T525
Test name
Test status
Simulation time 36275087550 ps
CPU time 43.43 seconds
Started Aug 27 04:48:38 AM UTC 24
Finished Aug 27 04:49:23 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372897434 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2372897434
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.3544279516
Short name T788
Test name
Test status
Simulation time 117507162592 ps
CPU time 756.52 seconds
Started Aug 27 04:48:57 AM UTC 24
Finished Aug 27 05:01:42 AM UTC 24
Peak memory 212208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544279516 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3544279516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_loopback.3523804587
Short name T521
Test name
Test status
Simulation time 1506415405 ps
CPU time 6.08 seconds
Started Aug 27 04:48:53 AM UTC 24
Finished Aug 27 04:49:00 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523804587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3523804587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_noise_filter.1686866973
Short name T572
Test name
Test status
Simulation time 149739469382 ps
CPU time 215.35 seconds
Started Aug 27 04:48:45 AM UTC 24
Finished Aug 27 04:52:23 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686866973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1686866973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_perf.4203538961
Short name T1043
Test name
Test status
Simulation time 22288013005 ps
CPU time 1357.52 seconds
Started Aug 27 04:48:56 AM UTC 24
Finished Aug 27 05:11:48 AM UTC 24
Peak memory 212224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203538961 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.4203538961
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_rx_oversample.1245184004
Short name T528
Test name
Test status
Simulation time 6126534165 ps
CPU time 53.97 seconds
Started Aug 27 04:48:38 AM UTC 24
Finished Aug 27 04:49:34 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245184004 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1245184004
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.1789555670
Short name T524
Test name
Test status
Simulation time 8837322389 ps
CPU time 24 seconds
Started Aug 27 04:48:48 AM UTC 24
Finished Aug 27 04:49:13 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789555670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1789555670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.1726896907
Short name T520
Test name
Test status
Simulation time 3169871035 ps
CPU time 11.26 seconds
Started Aug 27 04:48:47 AM UTC 24
Finished Aug 27 04:48:59 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726896907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1726896907
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_smoke.2748630752
Short name T321
Test name
Test status
Simulation time 10570025031 ps
CPU time 49.96 seconds
Started Aug 27 04:48:31 AM UTC 24
Finished Aug 27 04:49:23 AM UTC 24
Peak memory 208380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748630752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2748630752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_stress_all.1744400920
Short name T695
Test name
Test status
Simulation time 203577679383 ps
CPU time 527.96 seconds
Started Aug 27 04:49:01 AM UTC 24
Finished Aug 27 04:57:56 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744400920 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1744400920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.3509043038
Short name T518
Test name
Test status
Simulation time 992493276 ps
CPU time 5.17 seconds
Started Aug 27 04:48:49 AM UTC 24
Finished Aug 27 04:48:55 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509043038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3509043038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/22.uart_tx_rx.833077153
Short name T507
Test name
Test status
Simulation time 25565723335 ps
CPU time 79.4 seconds
Started Aug 27 04:48:32 AM UTC 24
Finished Aug 27 04:49:53 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833077153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.833077153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/22.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/220.uart_fifo_reset.2656497579
Short name T210
Test name
Test status
Simulation time 18913864032 ps
CPU time 28.38 seconds
Started Aug 27 05:12:32 AM UTC 24
Finished Aug 27 05:13:02 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656497579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2656497579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/220.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/221.uart_fifo_reset.377594911
Short name T1179
Test name
Test status
Simulation time 189054550040 ps
CPU time 704.3 seconds
Started Aug 27 05:12:35 AM UTC 24
Finished Aug 27 05:24:27 AM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377594911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.377594911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/221.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/222.uart_fifo_reset.31279449
Short name T1090
Test name
Test status
Simulation time 15225183131 ps
CPU time 47.79 seconds
Started Aug 27 05:12:38 AM UTC 24
Finished Aug 27 05:13:27 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31279449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.31279449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/222.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/223.uart_fifo_reset.1780903273
Short name T1091
Test name
Test status
Simulation time 242822001204 ps
CPU time 53.61 seconds
Started Aug 27 05:12:39 AM UTC 24
Finished Aug 27 05:13:34 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780903273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1780903273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/223.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/224.uart_fifo_reset.1436794377
Short name T1078
Test name
Test status
Simulation time 13416169710 ps
CPU time 20.04 seconds
Started Aug 27 05:12:42 AM UTC 24
Finished Aug 27 05:13:03 AM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436794377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1436794377
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/224.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/225.uart_fifo_reset.1379182972
Short name T1087
Test name
Test status
Simulation time 65202103776 ps
CPU time 38.41 seconds
Started Aug 27 05:12:42 AM UTC 24
Finished Aug 27 05:13:22 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379182972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1379182972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/225.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/226.uart_fifo_reset.3431732146
Short name T1102
Test name
Test status
Simulation time 32626894314 ps
CPU time 65.31 seconds
Started Aug 27 05:12:45 AM UTC 24
Finished Aug 27 05:13:52 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431732146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3431732146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/226.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/228.uart_fifo_reset.2599617973
Short name T1082
Test name
Test status
Simulation time 160153633828 ps
CPU time 24.5 seconds
Started Aug 27 05:12:45 AM UTC 24
Finished Aug 27 05:13:11 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599617973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2599617973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/228.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/229.uart_fifo_reset.2474217361
Short name T1079
Test name
Test status
Simulation time 51996942308 ps
CPU time 15.16 seconds
Started Aug 27 05:12:51 AM UTC 24
Finished Aug 27 05:13:07 AM UTC 24
Peak memory 208012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474217361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2474217361
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/229.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_alert_test.1720449925
Short name T531
Test name
Test status
Simulation time 12668705 ps
CPU time 0.84 seconds
Started Aug 27 04:49:44 AM UTC 24
Finished Aug 27 04:49:46 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720449925 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1720449925
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_fifo_full.2849757160
Short name T538
Test name
Test status
Simulation time 91797813906 ps
CPU time 65.69 seconds
Started Aug 27 04:49:08 AM UTC 24
Finished Aug 27 04:50:15 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849757160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2849757160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.3658024308
Short name T557
Test name
Test status
Simulation time 64339065467 ps
CPU time 113.58 seconds
Started Aug 27 04:49:11 AM UTC 24
Finished Aug 27 04:51:06 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658024308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3658024308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_intr.3007464974
Short name T392
Test name
Test status
Simulation time 42204116596 ps
CPU time 48.98 seconds
Started Aug 27 04:49:17 AM UTC 24
Finished Aug 27 04:50:08 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007464974 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3007464974
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.333089670
Short name T735
Test name
Test status
Simulation time 123375792418 ps
CPU time 604.32 seconds
Started Aug 27 04:49:35 AM UTC 24
Finished Aug 27 04:59:46 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333089670 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.333089670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_loopback.142611166
Short name T497
Test name
Test status
Simulation time 3305858618 ps
CPU time 4.16 seconds
Started Aug 27 04:49:32 AM UTC 24
Finished Aug 27 04:49:37 AM UTC 24
Peak memory 207076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142611166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.uart_loopback.142611166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_noise_filter.3972534981
Short name T592
Test name
Test status
Simulation time 70314191332 ps
CPU time 262.22 seconds
Started Aug 27 04:49:23 AM UTC 24
Finished Aug 27 04:53:49 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972534981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3972534981
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_perf.485614274
Short name T677
Test name
Test status
Simulation time 23879447035 ps
CPU time 459.44 seconds
Started Aug 27 04:49:34 AM UTC 24
Finished Aug 27 04:57:19 AM UTC 24
Peak memory 208604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485614274 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.485614274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_rx_oversample.576665312
Short name T529
Test name
Test status
Simulation time 2550688532 ps
CPU time 26.04 seconds
Started Aug 27 04:49:16 AM UTC 24
Finished Aug 27 04:49:43 AM UTC 24
Peak memory 207480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576665312 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.576665312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.1414293220
Short name T396
Test name
Test status
Simulation time 33827222755 ps
CPU time 35.16 seconds
Started Aug 27 04:49:27 AM UTC 24
Finished Aug 27 04:50:04 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414293220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1414293220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.85347204
Short name T526
Test name
Test status
Simulation time 4575780559 ps
CPU time 4.75 seconds
Started Aug 27 04:49:24 AM UTC 24
Finished Aug 27 04:49:30 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85347204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.85347204
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_smoke.1788817966
Short name T523
Test name
Test status
Simulation time 491505419 ps
CPU time 1.79 seconds
Started Aug 27 04:49:04 AM UTC 24
Finished Aug 27 04:49:07 AM UTC 24
Peak memory 207784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788817966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1788817966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_stress_all.682282462
Short name T651
Test name
Test status
Simulation time 73647552293 ps
CPU time 400.17 seconds
Started Aug 27 04:49:43 AM UTC 24
Finished Aug 27 04:56:28 AM UTC 24
Peak memory 217684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682282462 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.682282462
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.59020265
Short name T527
Test name
Test status
Simulation time 2670972802 ps
CPU time 3.41 seconds
Started Aug 27 04:49:28 AM UTC 24
Finished Aug 27 04:49:33 AM UTC 24
Peak memory 207552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59020265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.59020265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/23.uart_tx_rx.1731192502
Short name T539
Test name
Test status
Simulation time 31664847982 ps
CPU time 69.31 seconds
Started Aug 27 04:49:06 AM UTC 24
Finished Aug 27 04:50:17 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731192502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1731192502
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/23.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/230.uart_fifo_reset.2820913928
Short name T1143
Test name
Test status
Simulation time 84712442645 ps
CPU time 121.76 seconds
Started Aug 27 05:12:52 AM UTC 24
Finished Aug 27 05:14:56 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820913928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2820913928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/230.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/232.uart_fifo_reset.158953130
Short name T1106
Test name
Test status
Simulation time 17854952468 ps
CPU time 62.38 seconds
Started Aug 27 05:12:55 AM UTC 24
Finished Aug 27 05:13:59 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158953130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.158953130
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/232.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2050428262
Short name T1173
Test name
Test status
Simulation time 120363499565 ps
CPU time 246.26 seconds
Started Aug 27 05:12:56 AM UTC 24
Finished Aug 27 05:17:06 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050428262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2050428262
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/233.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/234.uart_fifo_reset.3165076652
Short name T1098
Test name
Test status
Simulation time 23133505531 ps
CPU time 45.69 seconds
Started Aug 27 05:12:58 AM UTC 24
Finished Aug 27 05:13:45 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165076652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3165076652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/234.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/235.uart_fifo_reset.955953166
Short name T1101
Test name
Test status
Simulation time 43808622718 ps
CPU time 51.75 seconds
Started Aug 27 05:12:58 AM UTC 24
Finished Aug 27 05:13:51 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955953166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.955953166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/235.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/236.uart_fifo_reset.4141679422
Short name T1105
Test name
Test status
Simulation time 216660380337 ps
CPU time 58.65 seconds
Started Aug 27 05:12:59 AM UTC 24
Finished Aug 27 05:13:59 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141679422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.4141679422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/236.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/237.uart_fifo_reset.4250371623
Short name T1086
Test name
Test status
Simulation time 23398942964 ps
CPU time 17.37 seconds
Started Aug 27 05:13:02 AM UTC 24
Finished Aug 27 05:13:20 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250371623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.4250371623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/237.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/238.uart_fifo_reset.2925309045
Short name T236
Test name
Test status
Simulation time 118884386700 ps
CPU time 174.87 seconds
Started Aug 27 05:13:03 AM UTC 24
Finished Aug 27 05:16:00 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925309045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2925309045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/238.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/239.uart_fifo_reset.2853218526
Short name T234
Test name
Test status
Simulation time 191424691704 ps
CPU time 55.01 seconds
Started Aug 27 05:13:03 AM UTC 24
Finished Aug 27 05:14:00 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853218526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2853218526
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/239.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_alert_test.2786244673
Short name T540
Test name
Test status
Simulation time 42164057 ps
CPU time 0.83 seconds
Started Aug 27 04:50:16 AM UTC 24
Finished Aug 27 04:50:17 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786244673 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2786244673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_fifo_full.976256801
Short name T371
Test name
Test status
Simulation time 151483645509 ps
CPU time 96.18 seconds
Started Aug 27 04:49:50 AM UTC 24
Finished Aug 27 04:51:29 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976256801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.976256801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.226769782
Short name T144
Test name
Test status
Simulation time 36509304112 ps
CPU time 28.59 seconds
Started Aug 27 04:49:52 AM UTC 24
Finished Aug 27 04:50:22 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226769782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.226769782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_fifo_reset.2753521619
Short name T567
Test name
Test status
Simulation time 73407447350 ps
CPU time 123.71 seconds
Started Aug 27 04:49:55 AM UTC 24
Finished Aug 27 04:52:00 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753521619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2753521619
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_intr.3311004571
Short name T544
Test name
Test status
Simulation time 25442307963 ps
CPU time 28.2 seconds
Started Aug 27 04:49:58 AM UTC 24
Finished Aug 27 04:50:27 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311004571 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3311004571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.621011233
Short name T664
Test name
Test status
Simulation time 100714342305 ps
CPU time 403.77 seconds
Started Aug 27 04:50:08 AM UTC 24
Finished Aug 27 04:56:58 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621011233 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.621011233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_loopback.2559244681
Short name T542
Test name
Test status
Simulation time 10082377738 ps
CPU time 12.35 seconds
Started Aug 27 04:50:05 AM UTC 24
Finished Aug 27 04:50:19 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559244681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2559244681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_noise_filter.2126453761
Short name T398
Test name
Test status
Simulation time 155758033610 ps
CPU time 74.78 seconds
Started Aug 27 04:49:59 AM UTC 24
Finished Aug 27 04:51:15 AM UTC 24
Peak memory 208924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126453761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2126453761
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_perf.80212421
Short name T405
Test name
Test status
Simulation time 24451535157 ps
CPU time 1183.85 seconds
Started Aug 27 04:50:07 AM UTC 24
Finished Aug 27 05:10:05 AM UTC 24
Peak memory 212204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80212421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.80212421
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_rx_oversample.2038423085
Short name T541
Test name
Test status
Simulation time 2620447348 ps
CPU time 22.3 seconds
Started Aug 27 04:49:55 AM UTC 24
Finished Aug 27 04:50:18 AM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038423085 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2038423085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.256263140
Short name T565
Test name
Test status
Simulation time 227065831909 ps
CPU time 113.06 seconds
Started Aug 27 04:50:00 AM UTC 24
Finished Aug 27 04:51:55 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256263140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.256263140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.1106361383
Short name T545
Test name
Test status
Simulation time 51759344542 ps
CPU time 29.54 seconds
Started Aug 27 04:49:59 AM UTC 24
Finished Aug 27 04:50:30 AM UTC 24
Peak memory 207340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106361383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1106361383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_smoke.3790632345
Short name T533
Test name
Test status
Simulation time 5556017230 ps
CPU time 10.51 seconds
Started Aug 27 04:49:45 AM UTC 24
Finished Aug 27 04:49:57 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790632345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3790632345
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_stress_all.3627817269
Short name T1115
Test name
Test status
Simulation time 168418443672 ps
CPU time 1421.64 seconds
Started Aug 27 04:50:15 AM UTC 24
Finished Aug 27 05:14:12 AM UTC 24
Peak memory 222568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627817269 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3627817269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.1397332234
Short name T551
Test name
Test status
Simulation time 9933916584 ps
CPU time 38.82 seconds
Started Aug 27 04:50:14 AM UTC 24
Finished Aug 27 04:50:55 AM UTC 24
Peak memory 217608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1397332234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all
_with_rand_reset.1397332234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.3053909241
Short name T535
Test name
Test status
Simulation time 3124905709 ps
CPU time 1.9 seconds
Started Aug 27 04:50:04 AM UTC 24
Finished Aug 27 04:50:07 AM UTC 24
Peak memory 206840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053909241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3053909241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_tx_rx.1402676598
Short name T549
Test name
Test status
Simulation time 19834238822 ps
CPU time 52.18 seconds
Started Aug 27 04:49:46 AM UTC 24
Finished Aug 27 04:50:40 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402676598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1402676598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/24.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/241.uart_fifo_reset.1471455648
Short name T170
Test name
Test status
Simulation time 24517368235 ps
CPU time 29.76 seconds
Started Aug 27 05:13:03 AM UTC 24
Finished Aug 27 05:13:34 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471455648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1471455648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/241.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/242.uart_fifo_reset.2459669826
Short name T1099
Test name
Test status
Simulation time 79735483039 ps
CPU time 42.21 seconds
Started Aug 27 05:13:04 AM UTC 24
Finished Aug 27 05:13:48 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459669826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2459669826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/242.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1730477240
Short name T201
Test name
Test status
Simulation time 124513599291 ps
CPU time 194.29 seconds
Started Aug 27 05:13:04 AM UTC 24
Finished Aug 27 05:16:21 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730477240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1730477240
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/243.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/244.uart_fifo_reset.3236528299
Short name T1118
Test name
Test status
Simulation time 97427847112 ps
CPU time 63.88 seconds
Started Aug 27 05:13:08 AM UTC 24
Finished Aug 27 05:14:14 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236528299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3236528299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/244.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3650589349
Short name T198
Test name
Test status
Simulation time 21090152672 ps
CPU time 11.9 seconds
Started Aug 27 05:13:09 AM UTC 24
Finished Aug 27 05:13:23 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650589349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3650589349
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/245.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/246.uart_fifo_reset.281274422
Short name T1100
Test name
Test status
Simulation time 78309130583 ps
CPU time 39.03 seconds
Started Aug 27 05:13:10 AM UTC 24
Finished Aug 27 05:13:50 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281274422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.281274422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/246.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3492697024
Short name T1116
Test name
Test status
Simulation time 125394760256 ps
CPU time 58.64 seconds
Started Aug 27 05:13:12 AM UTC 24
Finished Aug 27 05:14:12 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492697024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3492697024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/247.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/248.uart_fifo_reset.1119941178
Short name T1093
Test name
Test status
Simulation time 9030353961 ps
CPU time 22.39 seconds
Started Aug 27 05:13:12 AM UTC 24
Finished Aug 27 05:13:35 AM UTC 24
Peak memory 208804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119941178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1119941178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/248.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/249.uart_fifo_reset.3958817916
Short name T1161
Test name
Test status
Simulation time 98070587904 ps
CPU time 160.22 seconds
Started Aug 27 05:13:14 AM UTC 24
Finished Aug 27 05:15:56 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958817916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3958817916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/249.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_alert_test.2184765572
Short name T550
Test name
Test status
Simulation time 19524807 ps
CPU time 0.83 seconds
Started Aug 27 04:50:41 AM UTC 24
Finished Aug 27 04:50:43 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184765572 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2184765572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_fifo_full.280166614
Short name T595
Test name
Test status
Simulation time 307465354017 ps
CPU time 217.66 seconds
Started Aug 27 04:50:19 AM UTC 24
Finished Aug 27 04:54:00 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280166614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.280166614
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.1152504059
Short name T365
Test name
Test status
Simulation time 76154890210 ps
CPU time 144.23 seconds
Started Aug 27 04:50:19 AM UTC 24
Finished Aug 27 04:52:45 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152504059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1152504059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_fifo_reset.4141296147
Short name T178
Test name
Test status
Simulation time 197276487562 ps
CPU time 110.16 seconds
Started Aug 27 04:50:20 AM UTC 24
Finished Aug 27 04:52:12 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141296147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.4141296147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_intr.250799897
Short name T568
Test name
Test status
Simulation time 184617357919 ps
CPU time 109.14 seconds
Started Aug 27 04:50:23 AM UTC 24
Finished Aug 27 04:52:15 AM UTC 24
Peak memory 208556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250799897 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.250799897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.272625510
Short name T663
Test name
Test status
Simulation time 52283161107 ps
CPU time 368.4 seconds
Started Aug 27 04:50:37 AM UTC 24
Finished Aug 27 04:56:50 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272625510 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.272625510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_loopback.4133287372
Short name T553
Test name
Test status
Simulation time 7974128730 ps
CPU time 24.03 seconds
Started Aug 27 04:50:36 AM UTC 24
Finished Aug 27 04:51:01 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133287372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.uart_loopback.4133287372
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_noise_filter.417584102
Short name T395
Test name
Test status
Simulation time 149256860893 ps
CPU time 100.73 seconds
Started Aug 27 04:50:28 AM UTC 24
Finished Aug 27 04:52:11 AM UTC 24
Peak memory 217792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417584102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.417584102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_perf.2690593519
Short name T769
Test name
Test status
Simulation time 10149035680 ps
CPU time 622.69 seconds
Started Aug 27 04:50:36 AM UTC 24
Finished Aug 27 05:01:06 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690593519 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2690593519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_rx_oversample.3856649899
Short name T555
Test name
Test status
Simulation time 5833115368 ps
CPU time 39.36 seconds
Started Aug 27 04:50:23 AM UTC 24
Finished Aug 27 04:51:04 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856649899 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3856649899
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.2552865896
Short name T552
Test name
Test status
Simulation time 17823120234 ps
CPU time 27.98 seconds
Started Aug 27 04:50:31 AM UTC 24
Finished Aug 27 04:51:00 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552865896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2552865896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.2816716140
Short name T563
Test name
Test status
Simulation time 27735946871 ps
CPU time 80.49 seconds
Started Aug 27 04:50:28 AM UTC 24
Finished Aug 27 04:51:51 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816716140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2816716140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_smoke.3866767525
Short name T543
Test name
Test status
Simulation time 552845390 ps
CPU time 2.67 seconds
Started Aug 27 04:50:18 AM UTC 24
Finished Aug 27 04:50:22 AM UTC 24
Peak memory 207568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866767525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3866767525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_stress_all.3302269677
Short name T622
Test name
Test status
Simulation time 127392944402 ps
CPU time 286.28 seconds
Started Aug 27 04:50:40 AM UTC 24
Finished Aug 27 04:55:30 AM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302269677 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3302269677
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.3843237109
Short name T548
Test name
Test status
Simulation time 533677474 ps
CPU time 3.11 seconds
Started Aug 27 04:50:35 AM UTC 24
Finished Aug 27 04:50:39 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843237109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3843237109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/25.uart_tx_rx.1887810035
Short name T570
Test name
Test status
Simulation time 77989406307 ps
CPU time 116.55 seconds
Started Aug 27 04:50:19 AM UTC 24
Finished Aug 27 04:52:18 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887810035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1887810035
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1251378536
Short name T1147
Test name
Test status
Simulation time 51558630851 ps
CPU time 105.4 seconds
Started Aug 27 05:13:15 AM UTC 24
Finished Aug 27 05:15:02 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251378536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1251378536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/250.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/251.uart_fifo_reset.1578754484
Short name T1103
Test name
Test status
Simulation time 16977121883 ps
CPU time 34.58 seconds
Started Aug 27 05:13:17 AM UTC 24
Finished Aug 27 05:13:53 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578754484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1578754484
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/251.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/252.uart_fifo_reset.989582615
Short name T1094
Test name
Test status
Simulation time 56836365854 ps
CPU time 20.75 seconds
Started Aug 27 05:13:17 AM UTC 24
Finished Aug 27 05:13:39 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989582615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.989582615
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/252.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/253.uart_fifo_reset.889137521
Short name T1120
Test name
Test status
Simulation time 25821713741 ps
CPU time 54.92 seconds
Started Aug 27 05:13:21 AM UTC 24
Finished Aug 27 05:14:18 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889137521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.889137521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/253.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/254.uart_fifo_reset.2271077292
Short name T1145
Test name
Test status
Simulation time 187455080412 ps
CPU time 94.92 seconds
Started Aug 27 05:13:22 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271077292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2271077292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/254.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/255.uart_fifo_reset.565370399
Short name T1107
Test name
Test status
Simulation time 24673248852 ps
CPU time 37.37 seconds
Started Aug 27 05:13:23 AM UTC 24
Finished Aug 27 05:14:03 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565370399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.565370399
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/255.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/256.uart_fifo_reset.2563542678
Short name T1128
Test name
Test status
Simulation time 141162032215 ps
CPU time 65.49 seconds
Started Aug 27 05:13:24 AM UTC 24
Finished Aug 27 05:14:32 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563542678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2563542678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/256.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/257.uart_fifo_reset.3922657614
Short name T1121
Test name
Test status
Simulation time 60932133958 ps
CPU time 54.42 seconds
Started Aug 27 05:13:25 AM UTC 24
Finished Aug 27 05:14:22 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922657614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3922657614
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/257.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/258.uart_fifo_reset.3845904024
Short name T1109
Test name
Test status
Simulation time 52427859669 ps
CPU time 34.46 seconds
Started Aug 27 05:13:28 AM UTC 24
Finished Aug 27 05:14:04 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845904024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3845904024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/258.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/259.uart_fifo_reset.957093327
Short name T1138
Test name
Test status
Simulation time 36167148044 ps
CPU time 78.99 seconds
Started Aug 27 05:13:28 AM UTC 24
Finished Aug 27 05:14:49 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957093327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.957093327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/259.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_alert_test.2434403843
Short name T564
Test name
Test status
Simulation time 15535973 ps
CPU time 0.83 seconds
Started Aug 27 04:51:52 AM UTC 24
Finished Aug 27 04:51:54 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434403843 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2434403843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_fifo_full.122865705
Short name T558
Test name
Test status
Simulation time 71266600812 ps
CPU time 13.12 seconds
Started Aug 27 04:51:00 AM UTC 24
Finished Aug 27 04:51:15 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122865705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.122865705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.2660725088
Short name T140
Test name
Test status
Simulation time 125808391520 ps
CPU time 218.13 seconds
Started Aug 27 04:51:01 AM UTC 24
Finished Aug 27 04:54:42 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660725088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2660725088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_fifo_reset.189716557
Short name T177
Test name
Test status
Simulation time 94751551817 ps
CPU time 214.44 seconds
Started Aug 27 04:51:02 AM UTC 24
Finished Aug 27 04:54:39 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189716557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.189716557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_intr.1710303802
Short name T906
Test name
Test status
Simulation time 514572601120 ps
CPU time 854.57 seconds
Started Aug 27 04:51:05 AM UTC 24
Finished Aug 27 05:05:28 AM UTC 24
Peak memory 212320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710303802 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1710303802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.348662575
Short name T350
Test name
Test status
Simulation time 63559336981 ps
CPU time 178.09 seconds
Started Aug 27 04:51:31 AM UTC 24
Finished Aug 27 04:54:32 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348662575 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.348662575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_loopback.1584937066
Short name T562
Test name
Test status
Simulation time 7046718479 ps
CPU time 11.64 seconds
Started Aug 27 04:51:24 AM UTC 24
Finished Aug 27 04:51:37 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584937066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1584937066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_noise_filter.3561545047
Short name T402
Test name
Test status
Simulation time 186296629616 ps
CPU time 95.41 seconds
Started Aug 27 04:51:07 AM UTC 24
Finished Aug 27 04:52:44 AM UTC 24
Peak memory 217256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561545047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3561545047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_perf.3754568328
Short name T581
Test name
Test status
Simulation time 7173348320 ps
CPU time 81.31 seconds
Started Aug 27 04:51:29 AM UTC 24
Finished Aug 27 04:52:53 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754568328 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3754568328
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_rx_oversample.545224075
Short name T559
Test name
Test status
Simulation time 3243316714 ps
CPU time 16.47 seconds
Started Aug 27 04:51:05 AM UTC 24
Finished Aug 27 04:51:22 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545224075 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.545224075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.498771084
Short name T139
Test name
Test status
Simulation time 35783793201 ps
CPU time 107.97 seconds
Started Aug 27 04:51:16 AM UTC 24
Finished Aug 27 04:53:06 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498771084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.498771084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.1653461369
Short name T560
Test name
Test status
Simulation time 6287880006 ps
CPU time 6.25 seconds
Started Aug 27 04:51:16 AM UTC 24
Finished Aug 27 04:51:23 AM UTC 24
Peak memory 205164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653461369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1653461369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_smoke.1618705118
Short name T372
Test name
Test status
Simulation time 10594059025 ps
CPU time 61.28 seconds
Started Aug 27 04:50:44 AM UTC 24
Finished Aug 27 04:51:47 AM UTC 24
Peak memory 208496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618705118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1618705118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_stress_all.3136133326
Short name T99
Test name
Test status
Simulation time 212018375378 ps
CPU time 175.78 seconds
Started Aug 27 04:51:48 AM UTC 24
Finished Aug 27 04:54:46 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136133326 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3136133326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.2391392605
Short name T100
Test name
Test status
Simulation time 14217723167 ps
CPU time 77.09 seconds
Started Aug 27 04:51:38 AM UTC 24
Finished Aug 27 04:52:57 AM UTC 24
Peak memory 217760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2391392605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all
_with_rand_reset.2391392605
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.3466911156
Short name T561
Test name
Test status
Simulation time 1026165567 ps
CPU time 5.19 seconds
Started Aug 27 04:51:23 AM UTC 24
Finished Aug 27 04:51:29 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466911156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3466911156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/26.uart_tx_rx.897242394
Short name T575
Test name
Test status
Simulation time 110775896095 ps
CPU time 94.71 seconds
Started Aug 27 04:50:55 AM UTC 24
Finished Aug 27 04:52:32 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897242394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.897242394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/26.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/260.uart_fifo_reset.4292919895
Short name T1132
Test name
Test status
Simulation time 49463558918 ps
CPU time 60.89 seconds
Started Aug 27 05:13:32 AM UTC 24
Finished Aug 27 05:14:34 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292919895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.4292919895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/260.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/261.uart_fifo_reset.1297908442
Short name T1111
Test name
Test status
Simulation time 16263176281 ps
CPU time 31.3 seconds
Started Aug 27 05:13:35 AM UTC 24
Finished Aug 27 05:14:07 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297908442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1297908442
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/261.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2358220595
Short name T1136
Test name
Test status
Simulation time 105287278209 ps
CPU time 66.12 seconds
Started Aug 27 05:13:35 AM UTC 24
Finished Aug 27 05:14:43 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358220595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2358220595
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/262.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/263.uart_fifo_reset.1144034669
Short name T1134
Test name
Test status
Simulation time 140660929469 ps
CPU time 62.15 seconds
Started Aug 27 05:13:35 AM UTC 24
Finished Aug 27 05:14:39 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144034669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1144034669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/263.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/264.uart_fifo_reset.377392803
Short name T1104
Test name
Test status
Simulation time 21590726949 ps
CPU time 18.19 seconds
Started Aug 27 05:13:36 AM UTC 24
Finished Aug 27 05:13:56 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377392803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.377392803
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/264.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/265.uart_fifo_reset.3350829888
Short name T1110
Test name
Test status
Simulation time 29844439987 ps
CPU time 25.3 seconds
Started Aug 27 05:13:40 AM UTC 24
Finished Aug 27 05:14:07 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350829888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3350829888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/265.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/266.uart_fifo_reset.2006004298
Short name T1125
Test name
Test status
Simulation time 75326906722 ps
CPU time 40.11 seconds
Started Aug 27 05:13:45 AM UTC 24
Finished Aug 27 05:14:27 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006004298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2006004298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/266.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/267.uart_fifo_reset.706087699
Short name T1114
Test name
Test status
Simulation time 21956808779 ps
CPU time 24.16 seconds
Started Aug 27 05:13:45 AM UTC 24
Finished Aug 27 05:14:11 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706087699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.706087699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/267.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/268.uart_fifo_reset.251352727
Short name T1148
Test name
Test status
Simulation time 90447110910 ps
CPU time 77.69 seconds
Started Aug 27 05:13:46 AM UTC 24
Finished Aug 27 05:15:05 AM UTC 24
Peak memory 208572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251352727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.251352727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/268.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/269.uart_fifo_reset.959371637
Short name T1117
Test name
Test status
Simulation time 12620998724 ps
CPU time 25.6 seconds
Started Aug 27 05:13:46 AM UTC 24
Finished Aug 27 05:14:13 AM UTC 24
Peak memory 208800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959371637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.959371637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/269.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_alert_test.1947029638
Short name T576
Test name
Test status
Simulation time 61658935 ps
CPU time 0.82 seconds
Started Aug 27 04:52:32 AM UTC 24
Finished Aug 27 04:52:34 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947029638 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1947029638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_fifo_full.94261699
Short name T596
Test name
Test status
Simulation time 184949575041 ps
CPU time 127 seconds
Started Aug 27 04:51:56 AM UTC 24
Finished Aug 27 04:54:05 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94261699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.94261699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.2602780839
Short name T672
Test name
Test status
Simulation time 112057770280 ps
CPU time 310.73 seconds
Started Aug 27 04:51:59 AM UTC 24
Finished Aug 27 04:57:14 AM UTC 24
Peak memory 208964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602780839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2602780839
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_fifo_reset.2695776363
Short name T152
Test name
Test status
Simulation time 115666989455 ps
CPU time 26.36 seconds
Started Aug 27 04:52:00 AM UTC 24
Finished Aug 27 04:52:28 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695776363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2695776363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_intr.206832216
Short name T586
Test name
Test status
Simulation time 31237458511 ps
CPU time 54.52 seconds
Started Aug 27 04:52:12 AM UTC 24
Finished Aug 27 04:53:09 AM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206832216 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.206832216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.257024681
Short name T648
Test name
Test status
Simulation time 56115155436 ps
CPU time 233.32 seconds
Started Aug 27 04:52:25 AM UTC 24
Finished Aug 27 04:56:22 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257024681 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.257024681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_loopback.1630100627
Short name T574
Test name
Test status
Simulation time 1905475440 ps
CPU time 9.3 seconds
Started Aug 27 04:52:20 AM UTC 24
Finished Aug 27 04:52:31 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630100627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1630100627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_noise_filter.3085966234
Short name T579
Test name
Test status
Simulation time 9441032777 ps
CPU time 25.79 seconds
Started Aug 27 04:52:14 AM UTC 24
Finished Aug 27 04:52:41 AM UTC 24
Peak memory 207696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085966234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3085966234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_perf.2914155780
Short name T597
Test name
Test status
Simulation time 20078826563 ps
CPU time 106.73 seconds
Started Aug 27 04:52:24 AM UTC 24
Finished Aug 27 04:54:13 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914155780 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2914155780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_rx_oversample.1524449654
Short name T569
Test name
Test status
Simulation time 4304273200 ps
CPU time 13.03 seconds
Started Aug 27 04:52:01 AM UTC 24
Finished Aug 27 04:52:15 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524449654 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1524449654
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.1714040362
Short name T580
Test name
Test status
Simulation time 28853440189 ps
CPU time 29.1 seconds
Started Aug 27 04:52:17 AM UTC 24
Finished Aug 27 04:52:47 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714040362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1714040362
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.3896878303
Short name T571
Test name
Test status
Simulation time 4507332942 ps
CPU time 2.43 seconds
Started Aug 27 04:52:16 AM UTC 24
Finished Aug 27 04:52:19 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896878303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3896878303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_smoke.2021813901
Short name T566
Test name
Test status
Simulation time 649541896 ps
CPU time 4.69 seconds
Started Aug 27 04:51:54 AM UTC 24
Finished Aug 27 04:52:00 AM UTC 24
Peak memory 208396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021813901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2021813901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_stress_all.1984771909
Short name T715
Test name
Test status
Simulation time 149081960942 ps
CPU time 370.15 seconds
Started Aug 27 04:52:31 AM UTC 24
Finished Aug 27 04:58:46 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984771909 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1984771909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.3130880705
Short name T148
Test name
Test status
Simulation time 28636113949 ps
CPU time 48.58 seconds
Started Aug 27 04:52:28 AM UTC 24
Finished Aug 27 04:53:18 AM UTC 24
Peak memory 217688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3130880705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all
_with_rand_reset.3130880705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.2869669947
Short name T573
Test name
Test status
Simulation time 1051487099 ps
CPU time 4.87 seconds
Started Aug 27 04:52:18 AM UTC 24
Finished Aug 27 04:52:24 AM UTC 24
Peak memory 207476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869669947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2869669947
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/27.uart_tx_rx.1920129485
Short name T556
Test name
Test status
Simulation time 37238458548 ps
CPU time 97.27 seconds
Started Aug 27 04:51:55 AM UTC 24
Finished Aug 27 04:53:34 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920129485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1920129485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/27.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/270.uart_fifo_reset.3652421742
Short name T1158
Test name
Test status
Simulation time 135009548191 ps
CPU time 114.97 seconds
Started Aug 27 05:13:49 AM UTC 24
Finished Aug 27 05:15:46 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652421742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3652421742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/270.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/271.uart_fifo_reset.4243193202
Short name T1162
Test name
Test status
Simulation time 140859773384 ps
CPU time 129.49 seconds
Started Aug 27 05:13:51 AM UTC 24
Finished Aug 27 05:16:02 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243193202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.4243193202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/271.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/272.uart_fifo_reset.367091288
Short name T1135
Test name
Test status
Simulation time 167712486847 ps
CPU time 47.02 seconds
Started Aug 27 05:13:52 AM UTC 24
Finished Aug 27 05:14:40 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367091288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.367091288
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/272.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/273.uart_fifo_reset.1013794583
Short name T1170
Test name
Test status
Simulation time 77008857891 ps
CPU time 179.01 seconds
Started Aug 27 05:13:53 AM UTC 24
Finished Aug 27 05:16:55 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013794583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1013794583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/273.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/274.uart_fifo_reset.3438501517
Short name T1172
Test name
Test status
Simulation time 167147027387 ps
CPU time 184.84 seconds
Started Aug 27 05:13:54 AM UTC 24
Finished Aug 27 05:17:02 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438501517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3438501517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/274.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/275.uart_fifo_reset.4092018489
Short name T1154
Test name
Test status
Simulation time 38087044066 ps
CPU time 89.49 seconds
Started Aug 27 05:13:56 AM UTC 24
Finished Aug 27 05:15:27 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092018489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.4092018489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/275.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/276.uart_fifo_reset.3636860279
Short name T1113
Test name
Test status
Simulation time 11894124256 ps
CPU time 9.72 seconds
Started Aug 27 05:14:00 AM UTC 24
Finished Aug 27 05:14:11 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636860279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3636860279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/276.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/277.uart_fifo_reset.1871208373
Short name T1167
Test name
Test status
Simulation time 51506112865 ps
CPU time 141.38 seconds
Started Aug 27 05:14:00 AM UTC 24
Finished Aug 27 05:16:24 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871208373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1871208373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/277.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/278.uart_fifo_reset.2237372715
Short name T1155
Test name
Test status
Simulation time 135796075714 ps
CPU time 89.37 seconds
Started Aug 27 05:14:00 AM UTC 24
Finished Aug 27 05:15:32 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237372715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2237372715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/278.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2248447091
Short name T1126
Test name
Test status
Simulation time 14870598376 ps
CPU time 24.02 seconds
Started Aug 27 05:14:03 AM UTC 24
Finished Aug 27 05:14:29 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248447091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2248447091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/279.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_alert_test.2021913054
Short name T589
Test name
Test status
Simulation time 19163361 ps
CPU time 0.71 seconds
Started Aug 27 04:53:13 AM UTC 24
Finished Aug 27 04:53:15 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021913054 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2021913054
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_fifo_full.1206058795
Short name T652
Test name
Test status
Simulation time 239386634690 ps
CPU time 226.34 seconds
Started Aug 27 04:52:39 AM UTC 24
Finished Aug 27 04:56:28 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206058795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1206058795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.4185981715
Short name T582
Test name
Test status
Simulation time 25666207012 ps
CPU time 14.07 seconds
Started Aug 27 04:52:41 AM UTC 24
Finished Aug 27 04:52:56 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185981715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4185981715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_fifo_reset.3622254778
Short name T409
Test name
Test status
Simulation time 100212368650 ps
CPU time 280.4 seconds
Started Aug 27 04:52:42 AM UTC 24
Finished Aug 27 04:57:26 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622254778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3622254778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_intr.3116725084
Short name T717
Test name
Test status
Simulation time 219219945948 ps
CPU time 368.93 seconds
Started Aug 27 04:52:46 AM UTC 24
Finished Aug 27 04:58:59 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116725084 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3116725084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.781143316
Short name T774
Test name
Test status
Simulation time 124342187763 ps
CPU time 482.85 seconds
Started Aug 27 04:53:07 AM UTC 24
Finished Aug 27 05:01:15 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781143316 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.781143316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_loopback.3157389827
Short name T585
Test name
Test status
Simulation time 2547414989 ps
CPU time 8.5 seconds
Started Aug 27 04:52:58 AM UTC 24
Finished Aug 27 04:53:07 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157389827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3157389827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_noise_filter.2613241867
Short name T673
Test name
Test status
Simulation time 84577314541 ps
CPU time 262.78 seconds
Started Aug 27 04:52:48 AM UTC 24
Finished Aug 27 04:57:15 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613241867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2613241867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_perf.3710111944
Short name T1020
Test name
Test status
Simulation time 20449115614 ps
CPU time 1045.28 seconds
Started Aug 27 04:53:02 AM UTC 24
Finished Aug 27 05:10:38 AM UTC 24
Peak memory 212308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710111944 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3710111944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_rx_oversample.2590789880
Short name T584
Test name
Test status
Simulation time 5015825860 ps
CPU time 15.02 seconds
Started Aug 27 04:52:45 AM UTC 24
Finished Aug 27 04:53:01 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590789880 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2590789880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.2062190904
Short name T704
Test name
Test status
Simulation time 250171877330 ps
CPU time 309.8 seconds
Started Aug 27 04:52:56 AM UTC 24
Finished Aug 27 04:58:10 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062190904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2062190904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.1551117929
Short name T583
Test name
Test status
Simulation time 4372060498 ps
CPU time 2.49 seconds
Started Aug 27 04:52:53 AM UTC 24
Finished Aug 27 04:52:57 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551117929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1551117929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_smoke.3013773871
Short name T578
Test name
Test status
Simulation time 647999620 ps
CPU time 4.36 seconds
Started Aug 27 04:52:35 AM UTC 24
Finished Aug 27 04:52:40 AM UTC 24
Peak memory 207944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013773871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3013773871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_stress_all.179626714
Short name T705
Test name
Test status
Simulation time 385421509699 ps
CPU time 296.73 seconds
Started Aug 27 04:53:10 AM UTC 24
Finished Aug 27 04:58:11 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179626714 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.179626714
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.344514677
Short name T604
Test name
Test status
Simulation time 23053815202 ps
CPU time 78.08 seconds
Started Aug 27 04:53:08 AM UTC 24
Finished Aug 27 04:54:28 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=344514677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all_
with_rand_reset.344514677
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.3109671528
Short name T590
Test name
Test status
Simulation time 7492397576 ps
CPU time 20.52 seconds
Started Aug 27 04:52:58 AM UTC 24
Finished Aug 27 04:53:19 AM UTC 24
Peak memory 208508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109671528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3109671528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/28.uart_tx_rx.1910307338
Short name T601
Test name
Test status
Simulation time 71117642616 ps
CPU time 105.64 seconds
Started Aug 27 04:52:38 AM UTC 24
Finished Aug 27 04:54:25 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910307338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1910307338
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/28.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/280.uart_fifo_reset.1454458651
Short name T1133
Test name
Test status
Simulation time 17335604388 ps
CPU time 32.63 seconds
Started Aug 27 05:14:05 AM UTC 24
Finished Aug 27 05:14:38 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454458651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1454458651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/280.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/281.uart_fifo_reset.409318564
Short name T1129
Test name
Test status
Simulation time 33259643863 ps
CPU time 25.88 seconds
Started Aug 27 05:14:05 AM UTC 24
Finished Aug 27 05:14:32 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409318564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.409318564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/281.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2687918964
Short name T1137
Test name
Test status
Simulation time 17215817723 ps
CPU time 39.05 seconds
Started Aug 27 05:14:08 AM UTC 24
Finished Aug 27 05:14:48 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687918964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2687918964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/282.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/283.uart_fifo_reset.577107681
Short name T1150
Test name
Test status
Simulation time 118122918838 ps
CPU time 60.63 seconds
Started Aug 27 05:14:09 AM UTC 24
Finished Aug 27 05:15:11 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577107681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.577107681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/283.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/284.uart_fifo_reset.3144700323
Short name T1122
Test name
Test status
Simulation time 21407289940 ps
CPU time 10.07 seconds
Started Aug 27 05:14:11 AM UTC 24
Finished Aug 27 05:14:22 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144700323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3144700323
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/284.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/285.uart_fifo_reset.3601940920
Short name T1142
Test name
Test status
Simulation time 53594844078 ps
CPU time 42.7 seconds
Started Aug 27 05:14:12 AM UTC 24
Finished Aug 27 05:14:56 AM UTC 24
Peak memory 208528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601940920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3601940920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/285.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/286.uart_fifo_reset.2740739994
Short name T1157
Test name
Test status
Simulation time 106931784225 ps
CPU time 82.49 seconds
Started Aug 27 05:14:12 AM UTC 24
Finished Aug 27 05:15:36 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740739994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2740739994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/286.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3799052835
Short name T1139
Test name
Test status
Simulation time 15197918698 ps
CPU time 39.27 seconds
Started Aug 27 05:14:12 AM UTC 24
Finished Aug 27 05:14:53 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799052835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3799052835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/287.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/288.uart_fifo_reset.906796424
Short name T1152
Test name
Test status
Simulation time 122120596284 ps
CPU time 56.85 seconds
Started Aug 27 05:14:13 AM UTC 24
Finished Aug 27 05:15:12 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906796424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.906796424
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/288.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/289.uart_fifo_reset.1164625084
Short name T1140
Test name
Test status
Simulation time 231429439024 ps
CPU time 38.25 seconds
Started Aug 27 05:14:13 AM UTC 24
Finished Aug 27 05:14:53 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164625084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1164625084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/289.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_alert_test.2022045335
Short name T603
Test name
Test status
Simulation time 12860848 ps
CPU time 0.87 seconds
Started Aug 27 04:54:26 AM UTC 24
Finished Aug 27 04:54:28 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022045335 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2022045335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_fifo_full.1118975080
Short name T635
Test name
Test status
Simulation time 85333303674 ps
CPU time 153.33 seconds
Started Aug 27 04:53:19 AM UTC 24
Finished Aug 27 04:55:55 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118975080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1118975080
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.517116820
Short name T624
Test name
Test status
Simulation time 128668310342 ps
CPU time 130.19 seconds
Started Aug 27 04:53:20 AM UTC 24
Finished Aug 27 04:55:33 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517116820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.517116820
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_fifo_reset.1316201679
Short name T608
Test name
Test status
Simulation time 180154551032 ps
CPU time 61.16 seconds
Started Aug 27 04:53:35 AM UTC 24
Finished Aug 27 04:54:37 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316201679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1316201679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.120690753
Short name T634
Test name
Test status
Simulation time 36766703754 ps
CPU time 91.49 seconds
Started Aug 27 04:54:19 AM UTC 24
Finished Aug 27 04:55:52 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120690753 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.120690753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_loopback.2181591303
Short name T616
Test name
Test status
Simulation time 10347027804 ps
CPU time 47.01 seconds
Started Aug 27 04:54:14 AM UTC 24
Finished Aug 27 04:55:03 AM UTC 24
Peak memory 208648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181591303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2181591303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_noise_filter.3874273266
Short name T602
Test name
Test status
Simulation time 84925801219 ps
CPU time 30.17 seconds
Started Aug 27 04:53:54 AM UTC 24
Finished Aug 27 04:54:26 AM UTC 24
Peak memory 207768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874273266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3874273266
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_perf.1950714093
Short name T618
Test name
Test status
Simulation time 9453702841 ps
CPU time 51.78 seconds
Started Aug 27 04:54:15 AM UTC 24
Finished Aug 27 04:55:09 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950714093 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1950714093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_rx_oversample.401509540
Short name T593
Test name
Test status
Simulation time 3844412485 ps
CPU time 12.62 seconds
Started Aug 27 04:53:40 AM UTC 24
Finished Aug 27 04:53:53 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401509540 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.401509540
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.1524368534
Short name T163
Test name
Test status
Simulation time 67114278746 ps
CPU time 25.27 seconds
Started Aug 27 04:54:01 AM UTC 24
Finished Aug 27 04:54:28 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524368534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1524368534
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.249330183
Short name T599
Test name
Test status
Simulation time 37564448171 ps
CPU time 24.27 seconds
Started Aug 27 04:53:56 AM UTC 24
Finished Aug 27 04:54:22 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249330183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.249330183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_smoke.4049977723
Short name T594
Test name
Test status
Simulation time 5365423050 ps
CPU time 39.33 seconds
Started Aug 27 04:53:14 AM UTC 24
Finished Aug 27 04:53:55 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049977723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.4049977723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.468651531
Short name T614
Test name
Test status
Simulation time 9737589078 ps
CPU time 32.58 seconds
Started Aug 27 04:54:23 AM UTC 24
Finished Aug 27 04:54:57 AM UTC 24
Peak memory 217452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=468651531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all_
with_rand_reset.468651531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.355754051
Short name T600
Test name
Test status
Simulation time 6360613633 ps
CPU time 14.28 seconds
Started Aug 27 04:54:06 AM UTC 24
Finished Aug 27 04:54:22 AM UTC 24
Peak memory 208204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355754051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.355754051
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/29.uart_tx_rx.3618646565
Short name T413
Test name
Test status
Simulation time 67722643919 ps
CPU time 79.53 seconds
Started Aug 27 04:53:15 AM UTC 24
Finished Aug 27 04:54:36 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618646565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3618646565
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/29.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/290.uart_fifo_reset.326209294
Short name T1141
Test name
Test status
Simulation time 36842389468 ps
CPU time 38.75 seconds
Started Aug 27 05:14:14 AM UTC 24
Finished Aug 27 05:14:54 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326209294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.326209294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/290.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/291.uart_fifo_reset.57905360
Short name T1164
Test name
Test status
Simulation time 110301341652 ps
CPU time 106.67 seconds
Started Aug 27 05:14:18 AM UTC 24
Finished Aug 27 05:16:07 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57905360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.57905360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/291.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/292.uart_fifo_reset.3054702096
Short name T249
Test name
Test status
Simulation time 44372858472 ps
CPU time 34.44 seconds
Started Aug 27 05:14:19 AM UTC 24
Finished Aug 27 05:14:54 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054702096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3054702096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/292.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/294.uart_fifo_reset.1838921116
Short name T221
Test name
Test status
Simulation time 81939837727 ps
CPU time 37.96 seconds
Started Aug 27 05:14:23 AM UTC 24
Finished Aug 27 05:15:02 AM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838921116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1838921116
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/294.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/295.uart_fifo_reset.3239215287
Short name T1168
Test name
Test status
Simulation time 91254213403 ps
CPU time 122.44 seconds
Started Aug 27 05:14:24 AM UTC 24
Finished Aug 27 05:16:28 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239215287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3239215287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/295.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/296.uart_fifo_reset.3649631898
Short name T1149
Test name
Test status
Simulation time 92843954521 ps
CPU time 43.43 seconds
Started Aug 27 05:14:26 AM UTC 24
Finished Aug 27 05:15:11 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649631898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3649631898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/296.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/297.uart_fifo_reset.939902482
Short name T1146
Test name
Test status
Simulation time 122891965515 ps
CPU time 30.93 seconds
Started Aug 27 05:14:28 AM UTC 24
Finished Aug 27 05:15:00 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939902482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.939902482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/297.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/298.uart_fifo_reset.1929938998
Short name T1151
Test name
Test status
Simulation time 201311050225 ps
CPU time 40.64 seconds
Started Aug 27 05:14:29 AM UTC 24
Finished Aug 27 05:15:11 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929938998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1929938998
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/298.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/299.uart_fifo_reset.1162864665
Short name T1144
Test name
Test status
Simulation time 172363926088 ps
CPU time 27.82 seconds
Started Aug 27 05:14:30 AM UTC 24
Finished Aug 27 05:14:59 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162864665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1162864665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/299.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_alert_test.2348956241
Short name T31
Test name
Test status
Simulation time 11416135 ps
CPU time 0.83 seconds
Started Aug 27 04:37:06 AM UTC 24
Finished Aug 27 04:37:08 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348956241 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2348956241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.3510788050
Short name T136
Test name
Test status
Simulation time 45569540360 ps
CPU time 151.82 seconds
Started Aug 27 04:36:40 AM UTC 24
Finished Aug 27 04:39:14 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510788050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3510788050
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_intr.4014565945
Short name T17
Test name
Test status
Simulation time 24999002741 ps
CPU time 25.05 seconds
Started Aug 27 04:36:45 AM UTC 24
Finished Aug 27 04:37:11 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014565945 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4014565945
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_loopback.769438579
Short name T417
Test name
Test status
Simulation time 818138278 ps
CPU time 1.23 seconds
Started Aug 27 04:36:57 AM UTC 24
Finished Aug 27 04:36:59 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769438579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.uart_loopback.769438579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_noise_filter.263476679
Short name T370
Test name
Test status
Simulation time 7172158066 ps
CPU time 15.16 seconds
Started Aug 27 04:36:49 AM UTC 24
Finished Aug 27 04:37:06 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263476679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.263476679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_perf.528262151
Short name T358
Test name
Test status
Simulation time 25058899213 ps
CPU time 329.89 seconds
Started Aug 27 04:36:59 AM UTC 24
Finished Aug 27 04:42:33 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528262151 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.528262151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_rx_oversample.3094185688
Short name T69
Test name
Test status
Simulation time 6426624025 ps
CPU time 57.69 seconds
Started Aug 27 04:36:42 AM UTC 24
Finished Aug 27 04:37:41 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094185688 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3094185688
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.1002398036
Short name T269
Test name
Test status
Simulation time 97867169954 ps
CPU time 333.22 seconds
Started Aug 27 04:36:52 AM UTC 24
Finished Aug 27 04:42:29 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002398036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1002398036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.2503548712
Short name T318
Test name
Test status
Simulation time 28949138955 ps
CPU time 19.53 seconds
Started Aug 27 04:36:50 AM UTC 24
Finished Aug 27 04:37:11 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503548712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2503548712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_sec_cm.3021685735
Short name T81
Test name
Test status
Simulation time 82455571 ps
CPU time 1.33 seconds
Started Aug 27 04:37:04 AM UTC 24
Finished Aug 27 04:37:06 AM UTC 24
Peak memory 240196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021685735 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3021685735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_smoke.124779550
Short name T346
Test name
Test status
Simulation time 124069603 ps
CPU time 1.45 seconds
Started Aug 27 04:36:36 AM UTC 24
Finished Aug 27 04:36:39 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124779550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.uart_smoke.124779550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_stress_all.361152457
Short name T43
Test name
Test status
Simulation time 70743764046 ps
CPU time 41.09 seconds
Started Aug 27 04:37:01 AM UTC 24
Finished Aug 27 04:37:44 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361152457 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.361152457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.1636989744
Short name T326
Test name
Test status
Simulation time 525806721 ps
CPU time 2.81 seconds
Started Aug 27 04:36:57 AM UTC 24
Finished Aug 27 04:37:00 AM UTC 24
Peak memory 208228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636989744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1636989744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/3.uart_tx_rx.796006402
Short name T42
Test name
Test status
Simulation time 17500249454 ps
CPU time 16.29 seconds
Started Aug 27 04:36:38 AM UTC 24
Finished Aug 27 04:36:55 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796006402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.796006402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/3.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_alert_test.3360933294
Short name T612
Test name
Test status
Simulation time 11395107 ps
CPU time 0.8 seconds
Started Aug 27 04:54:47 AM UTC 24
Finished Aug 27 04:54:49 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360933294 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3360933294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_fifo_full.627814660
Short name T611
Test name
Test status
Simulation time 16897109455 ps
CPU time 13.72 seconds
Started Aug 27 04:54:29 AM UTC 24
Finished Aug 27 04:54:44 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627814660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.627814660
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.1243439770
Short name T153
Test name
Test status
Simulation time 6915994473 ps
CPU time 14.58 seconds
Started Aug 27 04:54:29 AM UTC 24
Finished Aug 27 04:54:45 AM UTC 24
Peak memory 208408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243439770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1243439770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_fifo_reset.3622316121
Short name T719
Test name
Test status
Simulation time 130986575182 ps
CPU time 271.08 seconds
Started Aug 27 04:54:30 AM UTC 24
Finished Aug 27 04:59:05 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622316121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3622316121
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_intr.1751140744
Short name T711
Test name
Test status
Simulation time 107587747157 ps
CPU time 238.84 seconds
Started Aug 27 04:54:35 AM UTC 24
Finished Aug 27 04:58:38 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751140744 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1751140744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.3937592429
Short name T751
Test name
Test status
Simulation time 103669294368 ps
CPU time 337.99 seconds
Started Aug 27 04:54:44 AM UTC 24
Finished Aug 27 05:00:27 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937592429 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3937592429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_loopback.438597370
Short name T613
Test name
Test status
Simulation time 1904005579 ps
CPU time 6.69 seconds
Started Aug 27 04:54:42 AM UTC 24
Finished Aug 27 04:54:50 AM UTC 24
Peak memory 205036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438597370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.uart_loopback.438597370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_noise_filter.2903583759
Short name T629
Test name
Test status
Simulation time 241584809076 ps
CPU time 63.17 seconds
Started Aug 27 04:54:37 AM UTC 24
Finished Aug 27 04:55:41 AM UTC 24
Peak memory 208928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903583759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2903583759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_perf.1622896416
Short name T955
Test name
Test status
Simulation time 15013756644 ps
CPU time 788.48 seconds
Started Aug 27 04:54:43 AM UTC 24
Finished Aug 27 05:08:00 AM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622896416 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1622896416
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_rx_oversample.543200303
Short name T615
Test name
Test status
Simulation time 3375556247 ps
CPU time 27.74 seconds
Started Aug 27 04:54:32 AM UTC 24
Finished Aug 27 04:55:01 AM UTC 24
Peak memory 207984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543200303 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.543200303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.1560245770
Short name T412
Test name
Test status
Simulation time 69366611325 ps
CPU time 87.94 seconds
Started Aug 27 04:54:38 AM UTC 24
Finished Aug 27 04:56:07 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560245770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1560245770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.4028503702
Short name T609
Test name
Test status
Simulation time 3330308660 ps
CPU time 3.41 seconds
Started Aug 27 04:54:38 AM UTC 24
Finished Aug 27 04:54:42 AM UTC 24
Peak memory 207076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028503702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4028503702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_smoke.4274354502
Short name T607
Test name
Test status
Simulation time 928044712 ps
CPU time 7.65 seconds
Started Aug 27 04:54:27 AM UTC 24
Finished Aug 27 04:54:36 AM UTC 24
Peak memory 208552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274354502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_smoke.4274354502
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_stress_all.2780772597
Short name T729
Test name
Test status
Simulation time 257157265900 ps
CPU time 285.83 seconds
Started Aug 27 04:54:45 AM UTC 24
Finished Aug 27 04:59:35 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780772597 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2780772597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.3584786509
Short name T625
Test name
Test status
Simulation time 9986488816 ps
CPU time 48.76 seconds
Started Aug 27 04:54:45 AM UTC 24
Finished Aug 27 04:55:35 AM UTC 24
Peak memory 221816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3584786509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all
_with_rand_reset.3584786509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.3566431165
Short name T610
Test name
Test status
Simulation time 848103022 ps
CPU time 2.4 seconds
Started Aug 27 04:54:40 AM UTC 24
Finished Aug 27 04:54:43 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566431165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3566431165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/30.uart_tx_rx.3344152093
Short name T644
Test name
Test status
Simulation time 66857014557 ps
CPU time 105.56 seconds
Started Aug 27 04:54:29 AM UTC 24
Finished Aug 27 04:56:17 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344152093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3344152093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/30.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_alert_test.2413955987
Short name T627
Test name
Test status
Simulation time 37361740 ps
CPU time 0.83 seconds
Started Aug 27 04:55:36 AM UTC 24
Finished Aug 27 04:55:38 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413955987 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2413955987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_fifo_full.574454862
Short name T149
Test name
Test status
Simulation time 180321276120 ps
CPU time 151.79 seconds
Started Aug 27 04:54:58 AM UTC 24
Finished Aug 27 04:57:32 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574454862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.574454862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.1529134863
Short name T626
Test name
Test status
Simulation time 39609029741 ps
CPU time 31.58 seconds
Started Aug 27 04:55:03 AM UTC 24
Finished Aug 27 04:55:36 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529134863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1529134863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_fifo_reset.698567809
Short name T211
Test name
Test status
Simulation time 33573684521 ps
CPU time 35.94 seconds
Started Aug 27 04:55:04 AM UTC 24
Finished Aug 27 04:55:41 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698567809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.698567809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_intr.540231528
Short name T620
Test name
Test status
Simulation time 27288925474 ps
CPU time 13.77 seconds
Started Aug 27 04:55:08 AM UTC 24
Finished Aug 27 04:55:23 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540231528 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.540231528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.2010374394
Short name T775
Test name
Test status
Simulation time 292766676860 ps
CPU time 341.33 seconds
Started Aug 27 04:55:32 AM UTC 24
Finished Aug 27 05:01:17 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010374394 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2010374394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_loopback.2430545593
Short name T630
Test name
Test status
Simulation time 4346913162 ps
CPU time 13.62 seconds
Started Aug 27 04:55:26 AM UTC 24
Finished Aug 27 04:55:41 AM UTC 24
Peak memory 207604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430545593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2430545593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_noise_filter.296021693
Short name T637
Test name
Test status
Simulation time 79206164609 ps
CPU time 52.26 seconds
Started Aug 27 04:55:10 AM UTC 24
Finished Aug 27 04:56:04 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296021693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.296021693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_perf.1597502526
Short name T1176
Test name
Test status
Simulation time 22970685386 ps
CPU time 1497.97 seconds
Started Aug 27 04:55:32 AM UTC 24
Finished Aug 27 05:20:46 AM UTC 24
Peak memory 212248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597502526 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1597502526
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_rx_oversample.329368197
Short name T647
Test name
Test status
Simulation time 5716209559 ps
CPU time 73.42 seconds
Started Aug 27 04:55:05 AM UTC 24
Finished Aug 27 04:56:20 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329368197 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.329368197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.1823882325
Short name T653
Test name
Test status
Simulation time 284863577990 ps
CPU time 65.1 seconds
Started Aug 27 04:55:23 AM UTC 24
Finished Aug 27 04:56:30 AM UTC 24
Peak memory 208496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823882325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1823882325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.957170775
Short name T621
Test name
Test status
Simulation time 2989598331 ps
CPU time 2.15 seconds
Started Aug 27 04:55:22 AM UTC 24
Finished Aug 27 04:55:25 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957170775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.957170775
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_smoke.4258425753
Short name T617
Test name
Test status
Simulation time 5446985235 ps
CPU time 15 seconds
Started Aug 27 04:54:50 AM UTC 24
Finished Aug 27 04:55:07 AM UTC 24
Peak memory 208216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258425753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4258425753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_stress_all.1474693549
Short name T662
Test name
Test status
Simulation time 169361136950 ps
CPU time 71.05 seconds
Started Aug 27 04:55:36 AM UTC 24
Finished Aug 27 04:56:49 AM UTC 24
Peak memory 209048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474693549 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1474693549
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.2525629583
Short name T666
Test name
Test status
Simulation time 3176313197 ps
CPU time 85.39 seconds
Started Aug 27 04:55:34 AM UTC 24
Finished Aug 27 04:57:01 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2525629583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all
_with_rand_reset.2525629583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.2629332722
Short name T623
Test name
Test status
Simulation time 686405862 ps
CPU time 3.93 seconds
Started Aug 27 04:55:25 AM UTC 24
Finished Aug 27 04:55:30 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629332722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2629332722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_tx_rx.342296498
Short name T632
Test name
Test status
Simulation time 164703830565 ps
CPU time 53.26 seconds
Started Aug 27 04:54:50 AM UTC 24
Finished Aug 27 04:55:45 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342296498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.342296498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/31.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_alert_test.579097805
Short name T640
Test name
Test status
Simulation time 21108902 ps
CPU time 0.83 seconds
Started Aug 27 04:56:10 AM UTC 24
Finished Aug 27 04:56:11 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579097805 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.579097805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_fifo_full.1586255550
Short name T676
Test name
Test status
Simulation time 40331822632 ps
CPU time 94.73 seconds
Started Aug 27 04:55:42 AM UTC 24
Finished Aug 27 04:57:19 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586255550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1586255550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.966487722
Short name T785
Test name
Test status
Simulation time 123637844614 ps
CPU time 346.27 seconds
Started Aug 27 04:55:42 AM UTC 24
Finished Aug 27 05:01:33 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966487722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.966487722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_fifo_reset.1433472207
Short name T229
Test name
Test status
Simulation time 95467526318 ps
CPU time 259.38 seconds
Started Aug 27 04:55:42 AM UTC 24
Finished Aug 27 05:00:05 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433472207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1433472207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_intr.4119080842
Short name T645
Test name
Test status
Simulation time 42151445481 ps
CPU time 31.17 seconds
Started Aug 27 04:55:45 AM UTC 24
Finished Aug 27 04:56:17 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119080842 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4119080842
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.1741005461
Short name T685
Test name
Test status
Simulation time 81452064450 ps
CPU time 79.59 seconds
Started Aug 27 04:56:08 AM UTC 24
Finished Aug 27 04:57:30 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741005461 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1741005461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_loopback.954263448
Short name T642
Test name
Test status
Simulation time 4212920890 ps
CPU time 16.49 seconds
Started Aug 27 04:55:56 AM UTC 24
Finished Aug 27 04:56:14 AM UTC 24
Peak memory 208172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954263448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.uart_loopback.954263448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_noise_filter.2716289431
Short name T667
Test name
Test status
Simulation time 248411764769 ps
CPU time 74.63 seconds
Started Aug 27 04:55:46 AM UTC 24
Finished Aug 27 04:57:02 AM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716289431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2716289431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_perf.151748424
Short name T726
Test name
Test status
Simulation time 11738531672 ps
CPU time 196.91 seconds
Started Aug 27 04:56:05 AM UTC 24
Finished Aug 27 04:59:25 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151748424 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.151748424
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_rx_oversample.2694888340
Short name T639
Test name
Test status
Simulation time 6645876955 ps
CPU time 24.41 seconds
Started Aug 27 04:55:42 AM UTC 24
Finished Aug 27 04:56:08 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694888340 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2694888340
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.86081106
Short name T853
Test name
Test status
Simulation time 285248912949 ps
CPU time 462.31 seconds
Started Aug 27 04:55:53 AM UTC 24
Finished Aug 27 05:03:41 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86081106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.86081106
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.202605120
Short name T636
Test name
Test status
Simulation time 2479037524 ps
CPU time 7.7 seconds
Started Aug 27 04:55:47 AM UTC 24
Finished Aug 27 04:55:56 AM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202605120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.202605120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_smoke.4236906038
Short name T633
Test name
Test status
Simulation time 6091789838 ps
CPU time 7.37 seconds
Started Aug 27 04:55:37 AM UTC 24
Finished Aug 27 04:55:46 AM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236906038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.4236906038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_stress_all.2706414217
Short name T155
Test name
Test status
Simulation time 376247501329 ps
CPU time 165.35 seconds
Started Aug 27 04:56:10 AM UTC 24
Finished Aug 27 04:58:57 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706414217 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2706414217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.2136675233
Short name T649
Test name
Test status
Simulation time 1294057933 ps
CPU time 15.55 seconds
Started Aug 27 04:56:09 AM UTC 24
Finished Aug 27 04:56:26 AM UTC 24
Peak memory 219776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2136675233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all
_with_rand_reset.2136675233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.1535830236
Short name T643
Test name
Test status
Simulation time 7689264930 ps
CPU time 17.44 seconds
Started Aug 27 04:55:56 AM UTC 24
Finished Aug 27 04:56:15 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535830236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1535830236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/32.uart_tx_rx.2826998331
Short name T628
Test name
Test status
Simulation time 998160142 ps
CPU time 1.78 seconds
Started Aug 27 04:55:38 AM UTC 24
Finished Aug 27 04:55:41 AM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826998331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2826998331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/32.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_alert_test.2849605289
Short name T658
Test name
Test status
Simulation time 12566316 ps
CPU time 0.82 seconds
Started Aug 27 04:56:37 AM UTC 24
Finished Aug 27 04:56:39 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849605289 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2849605289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_fifo_full.583148428
Short name T657
Test name
Test status
Simulation time 50939328746 ps
CPU time 20.36 seconds
Started Aug 27 04:56:15 AM UTC 24
Finished Aug 27 04:56:36 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583148428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.583148428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.3317399879
Short name T897
Test name
Test status
Simulation time 86462408470 ps
CPU time 520.36 seconds
Started Aug 27 04:56:16 AM UTC 24
Finished Aug 27 05:05:03 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317399879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3317399879
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_fifo_reset.3648912525
Short name T661
Test name
Test status
Simulation time 27403056284 ps
CPU time 27.51 seconds
Started Aug 27 04:56:18 AM UTC 24
Finished Aug 27 04:56:47 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648912525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3648912525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_intr.3668332007
Short name T660
Test name
Test status
Simulation time 36715892011 ps
CPU time 21.16 seconds
Started Aug 27 04:56:19 AM UTC 24
Finished Aug 27 04:56:41 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668332007 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3668332007
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.3891291020
Short name T787
Test name
Test status
Simulation time 174142326433 ps
CPU time 304.22 seconds
Started Aug 27 04:56:31 AM UTC 24
Finished Aug 27 05:01:39 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891291020 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3891291020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_loopback.1211349078
Short name T655
Test name
Test status
Simulation time 5710739391 ps
CPU time 6.56 seconds
Started Aug 27 04:56:29 AM UTC 24
Finished Aug 27 04:56:36 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211349078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1211349078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_noise_filter.2726421383
Short name T393
Test name
Test status
Simulation time 46667984973 ps
CPU time 89.11 seconds
Started Aug 27 04:56:21 AM UTC 24
Finished Aug 27 04:57:52 AM UTC 24
Peak memory 217604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726421383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2726421383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_perf.3604030354
Short name T728
Test name
Test status
Simulation time 10769888317 ps
CPU time 180.52 seconds
Started Aug 27 04:56:29 AM UTC 24
Finished Aug 27 04:59:32 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604030354 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3604030354
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_rx_oversample.3978665575
Short name T665
Test name
Test status
Simulation time 5020455637 ps
CPU time 38.87 seconds
Started Aug 27 04:56:18 AM UTC 24
Finished Aug 27 04:56:58 AM UTC 24
Peak memory 207868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978665575 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3978665575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.334615527
Short name T669
Test name
Test status
Simulation time 71155716352 ps
CPU time 39.03 seconds
Started Aug 27 04:56:27 AM UTC 24
Finished Aug 27 04:57:08 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334615527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.334615527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.799143839
Short name T650
Test name
Test status
Simulation time 590957228 ps
CPU time 2.07 seconds
Started Aug 27 04:56:23 AM UTC 24
Finished Aug 27 04:56:26 AM UTC 24
Peak memory 205160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799143839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.799143839
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_smoke.3428650463
Short name T646
Test name
Test status
Simulation time 646696571 ps
CPU time 4.32 seconds
Started Aug 27 04:56:13 AM UTC 24
Finished Aug 27 04:56:18 AM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428650463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3428650463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_stress_all.3715124754
Short name T690
Test name
Test status
Simulation time 260952229584 ps
CPU time 71.23 seconds
Started Aug 27 04:56:37 AM UTC 24
Finished Aug 27 04:57:50 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715124754 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3715124754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.4087172888
Short name T682
Test name
Test status
Simulation time 12619444239 ps
CPU time 52.25 seconds
Started Aug 27 04:56:32 AM UTC 24
Finished Aug 27 04:57:26 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4087172888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all
_with_rand_reset.4087172888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.1991467296
Short name T654
Test name
Test status
Simulation time 971233482 ps
CPU time 2.63 seconds
Started Aug 27 04:56:28 AM UTC 24
Finished Aug 27 04:56:31 AM UTC 24
Peak memory 207488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991467296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1991467296
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/33.uart_tx_rx.2919197528
Short name T679
Test name
Test status
Simulation time 27609665697 ps
CPU time 63.88 seconds
Started Aug 27 04:56:15 AM UTC 24
Finished Aug 27 04:57:20 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919197528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2919197528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/33.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_alert_test.416837069
Short name T675
Test name
Test status
Simulation time 12120827 ps
CPU time 0.8 seconds
Started Aug 27 04:57:15 AM UTC 24
Finished Aug 27 04:57:16 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416837069 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.416837069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_fifo_full.816192082
Short name T680
Test name
Test status
Simulation time 57473172289 ps
CPU time 41.58 seconds
Started Aug 27 04:56:40 AM UTC 24
Finished Aug 27 04:57:23 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816192082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.816192082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.1238484588
Short name T681
Test name
Test status
Simulation time 45253686212 ps
CPU time 41.08 seconds
Started Aug 27 04:56:42 AM UTC 24
Finished Aug 27 04:57:25 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238484588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1238484588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_fifo_reset.2679872052
Short name T154
Test name
Test status
Simulation time 40205090425 ps
CPU time 61.66 seconds
Started Aug 27 04:56:47 AM UTC 24
Finished Aug 27 04:57:51 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679872052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2679872052
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_intr.3484341919
Short name T670
Test name
Test status
Simulation time 7412267834 ps
CPU time 19.88 seconds
Started Aug 27 04:56:51 AM UTC 24
Finished Aug 27 04:57:12 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484341919 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3484341919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.760378683
Short name T767
Test name
Test status
Simulation time 45855823605 ps
CPU time 226.24 seconds
Started Aug 27 04:57:08 AM UTC 24
Finished Aug 27 05:00:58 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760378683 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.760378683
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_loopback.3275151895
Short name T674
Test name
Test status
Simulation time 2955776984 ps
CPU time 7.12 seconds
Started Aug 27 04:57:07 AM UTC 24
Finished Aug 27 04:57:15 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275151895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3275151895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_noise_filter.3516925014
Short name T709
Test name
Test status
Simulation time 39232420937 ps
CPU time 90.06 seconds
Started Aug 27 04:56:59 AM UTC 24
Finished Aug 27 04:58:31 AM UTC 24
Peak memory 217684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516925014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3516925014
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_perf.1873791281
Short name T697
Test name
Test status
Simulation time 8299213031 ps
CPU time 48 seconds
Started Aug 27 04:57:08 AM UTC 24
Finished Aug 27 04:57:58 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873791281 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1873791281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_rx_oversample.1568057903
Short name T671
Test name
Test status
Simulation time 7262170753 ps
CPU time 22.75 seconds
Started Aug 27 04:56:50 AM UTC 24
Finished Aug 27 04:57:14 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568057903 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1568057903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.1986570935
Short name T702
Test name
Test status
Simulation time 21552241238 ps
CPU time 63.16 seconds
Started Aug 27 04:57:02 AM UTC 24
Finished Aug 27 04:58:07 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986570935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1986570935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.1199531913
Short name T686
Test name
Test status
Simulation time 28913973453 ps
CPU time 37.45 seconds
Started Aug 27 04:56:59 AM UTC 24
Finished Aug 27 04:57:38 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199531913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1199531913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_smoke.3080481238
Short name T659
Test name
Test status
Simulation time 87043494 ps
CPU time 1.38 seconds
Started Aug 27 04:56:37 AM UTC 24
Finished Aug 27 04:56:39 AM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080481238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3080481238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_stress_all.204566739
Short name T796
Test name
Test status
Simulation time 288992466455 ps
CPU time 272.8 seconds
Started Aug 27 04:57:15 AM UTC 24
Finished Aug 27 05:01:51 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204566739 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.204566739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.4218995503
Short name T710
Test name
Test status
Simulation time 19216333559 ps
CPU time 83.47 seconds
Started Aug 27 04:57:12 AM UTC 24
Finished Aug 27 04:58:38 AM UTC 24
Peak memory 225408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4218995503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all
_with_rand_reset.4218995503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.812627247
Short name T668
Test name
Test status
Simulation time 1142495819 ps
CPU time 2.87 seconds
Started Aug 27 04:57:03 AM UTC 24
Finished Aug 27 04:57:07 AM UTC 24
Peak memory 207364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812627247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.812627247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/34.uart_tx_rx.2544899475
Short name T693
Test name
Test status
Simulation time 41915296088 ps
CPU time 72.81 seconds
Started Aug 27 04:56:39 AM UTC 24
Finished Aug 27 04:57:54 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544899475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2544899475
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/34.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_alert_test.112209230
Short name T688
Test name
Test status
Simulation time 11791378 ps
CPU time 0.82 seconds
Started Aug 27 04:57:45 AM UTC 24
Finished Aug 27 04:57:47 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112209230 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.112209230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_fifo_full.3232561697
Short name T706
Test name
Test status
Simulation time 75058669106 ps
CPU time 58.57 seconds
Started Aug 27 04:57:17 AM UTC 24
Finished Aug 27 04:58:17 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232561697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3232561697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.511629892
Short name T691
Test name
Test status
Simulation time 31613188900 ps
CPU time 29.45 seconds
Started Aug 27 04:57:20 AM UTC 24
Finished Aug 27 04:57:51 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511629892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.511629892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_fifo_reset.2531178541
Short name T750
Test name
Test status
Simulation time 361471805278 ps
CPU time 179.14 seconds
Started Aug 27 04:57:20 AM UTC 24
Finished Aug 27 05:00:22 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531178541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2531178541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_intr.3289430475
Short name T694
Test name
Test status
Simulation time 16089940888 ps
CPU time 30.74 seconds
Started Aug 27 04:57:21 AM UTC 24
Finished Aug 27 04:57:54 AM UTC 24
Peak memory 208540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289430475 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3289430475
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.38497678
Short name T856
Test name
Test status
Simulation time 200682614743 ps
CPU time 368.31 seconds
Started Aug 27 04:57:31 AM UTC 24
Finished Aug 27 05:03:45 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38497678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.38497678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_loopback.378499470
Short name T687
Test name
Test status
Simulation time 4300427212 ps
CPU time 15.87 seconds
Started Aug 27 04:57:28 AM UTC 24
Finished Aug 27 04:57:45 AM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378499470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_loopback.378499470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_noise_filter.3120593689
Short name T727
Test name
Test status
Simulation time 305712343450 ps
CPU time 124.85 seconds
Started Aug 27 04:57:24 AM UTC 24
Finished Aug 27 04:59:31 AM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120593689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3120593689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_perf.2529294900
Short name T834
Test name
Test status
Simulation time 28315814764 ps
CPU time 325.06 seconds
Started Aug 27 04:57:29 AM UTC 24
Finished Aug 27 05:02:58 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529294900 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2529294900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_rx_oversample.3200208337
Short name T683
Test name
Test status
Simulation time 2453061947 ps
CPU time 5.21 seconds
Started Aug 27 04:57:20 AM UTC 24
Finished Aug 27 04:57:27 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200208337 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3200208337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.4030712383
Short name T737
Test name
Test status
Simulation time 63285980234 ps
CPU time 142.84 seconds
Started Aug 27 04:57:26 AM UTC 24
Finished Aug 27 04:59:52 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030712383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.4030712383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.3434831099
Short name T684
Test name
Test status
Simulation time 4606952414 ps
CPU time 1.42 seconds
Started Aug 27 04:57:25 AM UTC 24
Finished Aug 27 04:57:28 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434831099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3434831099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_smoke.3412445557
Short name T678
Test name
Test status
Simulation time 711376560 ps
CPU time 2.84 seconds
Started Aug 27 04:57:16 AM UTC 24
Finished Aug 27 04:57:20 AM UTC 24
Peak memory 208356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412445557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3412445557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.2222064502
Short name T700
Test name
Test status
Simulation time 18379207420 ps
CPU time 29.69 seconds
Started Aug 27 04:57:33 AM UTC 24
Finished Aug 27 04:58:04 AM UTC 24
Peak memory 225568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2222064502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all
_with_rand_reset.2222064502
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.2378266428
Short name T689
Test name
Test status
Simulation time 7456401396 ps
CPU time 20.53 seconds
Started Aug 27 04:57:28 AM UTC 24
Finished Aug 27 04:57:49 AM UTC 24
Peak memory 208096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378266428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2378266428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/35.uart_tx_rx.732574542
Short name T720
Test name
Test status
Simulation time 130398848297 ps
CPU time 109.57 seconds
Started Aug 27 04:57:16 AM UTC 24
Finished Aug 27 04:59:08 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732574542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.732574542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/35.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_alert_test.1625798415
Short name T703
Test name
Test status
Simulation time 12535734 ps
CPU time 0.83 seconds
Started Aug 27 04:58:07 AM UTC 24
Finished Aug 27 04:58:09 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625798415 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1625798415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_fifo_full.3015445036
Short name T880
Test name
Test status
Simulation time 240461392909 ps
CPU time 395.49 seconds
Started Aug 27 04:57:50 AM UTC 24
Finished Aug 27 05:04:30 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015445036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3015445036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.1879411747
Short name T740
Test name
Test status
Simulation time 37108507907 ps
CPU time 122.19 seconds
Started Aug 27 04:57:51 AM UTC 24
Finished Aug 27 04:59:56 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879411747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1879411747
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_fifo_reset.1124321596
Short name T158
Test name
Test status
Simulation time 96870900942 ps
CPU time 103.15 seconds
Started Aug 27 04:57:52 AM UTC 24
Finished Aug 27 04:59:38 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124321596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1124321596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_intr.1894471970
Short name T739
Test name
Test status
Simulation time 55530971249 ps
CPU time 117.39 seconds
Started Aug 27 04:57:55 AM UTC 24
Finished Aug 27 04:59:54 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894471970 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1894471970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.2668972771
Short name T1050
Test name
Test status
Simulation time 76591317109 ps
CPU time 826.61 seconds
Started Aug 27 04:58:03 AM UTC 24
Finished Aug 27 05:11:59 AM UTC 24
Peak memory 212176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668972771 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2668972771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_loopback.3185801156
Short name T699
Test name
Test status
Simulation time 1423065644 ps
CPU time 2.18 seconds
Started Aug 27 04:57:59 AM UTC 24
Finished Aug 27 04:58:02 AM UTC 24
Peak memory 207100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185801156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3185801156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_noise_filter.3618931780
Short name T723
Test name
Test status
Simulation time 27763557841 ps
CPU time 80.82 seconds
Started Aug 27 04:57:55 AM UTC 24
Finished Aug 27 04:59:17 AM UTC 24
Peak memory 208084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618931780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3618931780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_perf.4205395693
Short name T836
Test name
Test status
Simulation time 17260953737 ps
CPU time 293.31 seconds
Started Aug 27 04:58:03 AM UTC 24
Finished Aug 27 05:03:01 AM UTC 24
Peak memory 208928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205395693 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4205395693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_rx_oversample.3717788207
Short name T701
Test name
Test status
Simulation time 2127148381 ps
CPU time 10.27 seconds
Started Aug 27 04:57:54 AM UTC 24
Finished Aug 27 04:58:05 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717788207 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3717788207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.85443697
Short name T824
Test name
Test status
Simulation time 168128918009 ps
CPU time 277.99 seconds
Started Aug 27 04:57:57 AM UTC 24
Finished Aug 27 05:02:38 AM UTC 24
Peak memory 208940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85443697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.85443697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.928199824
Short name T696
Test name
Test status
Simulation time 638718320 ps
CPU time 1.74 seconds
Started Aug 27 04:57:55 AM UTC 24
Finished Aug 27 04:57:57 AM UTC 24
Peak memory 204436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928199824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.928199824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_smoke.1464486056
Short name T692
Test name
Test status
Simulation time 506613501 ps
CPU time 4.2 seconds
Started Aug 27 04:57:48 AM UTC 24
Finished Aug 27 04:57:53 AM UTC 24
Peak memory 208076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464486056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1464486056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_stress_all.3222210153
Short name T173
Test name
Test status
Simulation time 310521655730 ps
CPU time 507.15 seconds
Started Aug 27 04:58:05 AM UTC 24
Finished Aug 27 05:06:38 AM UTC 24
Peak memory 220620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222210153 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3222210153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.204428988
Short name T708
Test name
Test status
Simulation time 7487277709 ps
CPU time 16.42 seconds
Started Aug 27 04:58:05 AM UTC 24
Finished Aug 27 04:58:23 AM UTC 24
Peak memory 223876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=204428988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all_
with_rand_reset.204428988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.1311315625
Short name T698
Test name
Test status
Simulation time 1650476549 ps
CPU time 2.93 seconds
Started Aug 27 04:57:58 AM UTC 24
Finished Aug 27 04:58:02 AM UTC 24
Peak memory 207632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311315625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1311315625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/36.uart_tx_rx.325837258
Short name T743
Test name
Test status
Simulation time 188854573034 ps
CPU time 136.91 seconds
Started Aug 27 04:57:50 AM UTC 24
Finished Aug 27 05:00:10 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325837258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.325837258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/36.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_alert_test.3843499461
Short name T718
Test name
Test status
Simulation time 11466518 ps
CPU time 0.8 seconds
Started Aug 27 04:58:58 AM UTC 24
Finished Aug 27 04:59:00 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843499461 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3843499461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_fifo_full.3417500346
Short name T742
Test name
Test status
Simulation time 143007122986 ps
CPU time 115.41 seconds
Started Aug 27 04:58:12 AM UTC 24
Finished Aug 27 05:00:09 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417500346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3417500346
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.2308018564
Short name T804
Test name
Test status
Simulation time 75214189892 ps
CPU time 224.83 seconds
Started Aug 27 04:58:18 AM UTC 24
Finished Aug 27 05:02:06 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308018564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2308018564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_intr.4201646656
Short name T736
Test name
Test status
Simulation time 41418726032 ps
CPU time 75.6 seconds
Started Aug 27 04:58:31 AM UTC 24
Finished Aug 27 04:59:49 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201646656 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.4201646656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.905970751
Short name T1010
Test name
Test status
Simulation time 111718882488 ps
CPU time 672.99 seconds
Started Aug 27 04:58:47 AM UTC 24
Finished Aug 27 05:10:07 AM UTC 24
Peak memory 212280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905970751 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.905970751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_loopback.4164790071
Short name T721
Test name
Test status
Simulation time 9593979406 ps
CPU time 28.82 seconds
Started Aug 27 04:58:43 AM UTC 24
Finished Aug 27 04:59:13 AM UTC 24
Peak memory 207948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164790071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4164790071
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_noise_filter.3038597476
Short name T761
Test name
Test status
Simulation time 60849919614 ps
CPU time 124.43 seconds
Started Aug 27 04:58:38 AM UTC 24
Finished Aug 27 05:00:45 AM UTC 24
Peak memory 208864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038597476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3038597476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_perf.4126347359
Short name T808
Test name
Test status
Simulation time 3701219309 ps
CPU time 204.11 seconds
Started Aug 27 04:58:45 AM UTC 24
Finished Aug 27 05:02:12 AM UTC 24
Peak memory 208984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126347359 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4126347359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_rx_oversample.3107355459
Short name T712
Test name
Test status
Simulation time 7825944707 ps
CPU time 12.8 seconds
Started Aug 27 04:58:24 AM UTC 24
Finished Aug 27 04:58:38 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107355459 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3107355459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.2584146892
Short name T725
Test name
Test status
Simulation time 41154026133 ps
CPU time 38.24 seconds
Started Aug 27 04:58:39 AM UTC 24
Finished Aug 27 04:59:19 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584146892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2584146892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.3609254520
Short name T713
Test name
Test status
Simulation time 713290112 ps
CPU time 2.29 seconds
Started Aug 27 04:58:38 AM UTC 24
Finished Aug 27 04:58:42 AM UTC 24
Peak memory 205036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609254520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3609254520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_smoke.3770924745
Short name T707
Test name
Test status
Simulation time 5587983148 ps
CPU time 5.79 seconds
Started Aug 27 04:58:11 AM UTC 24
Finished Aug 27 04:58:18 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770924745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3770924745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_stress_all.308389586
Short name T778
Test name
Test status
Simulation time 473038795510 ps
CPU time 143.16 seconds
Started Aug 27 04:58:56 AM UTC 24
Finished Aug 27 05:01:21 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308389586 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.308389586
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.3869720258
Short name T734
Test name
Test status
Simulation time 11013417377 ps
CPU time 54.37 seconds
Started Aug 27 04:58:49 AM UTC 24
Finished Aug 27 04:59:45 AM UTC 24
Peak memory 217792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3869720258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all
_with_rand_reset.3869720258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.1335861199
Short name T714
Test name
Test status
Simulation time 1042910715 ps
CPU time 1.89 seconds
Started Aug 27 04:58:42 AM UTC 24
Finished Aug 27 04:58:44 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335861199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1335861199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/37.uart_tx_rx.1556136239
Short name T900
Test name
Test status
Simulation time 131411653881 ps
CPU time 416.38 seconds
Started Aug 27 04:58:12 AM UTC 24
Finished Aug 27 05:05:13 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556136239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1556136239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/37.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_alert_test.2151249861
Short name T733
Test name
Test status
Simulation time 33509187 ps
CPU time 0.83 seconds
Started Aug 27 04:59:43 AM UTC 24
Finished Aug 27 04:59:45 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151249861 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2151249861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_fifo_full.1852217088
Short name T847
Test name
Test status
Simulation time 121727891844 ps
CPU time 257.4 seconds
Started Aug 27 04:59:01 AM UTC 24
Finished Aug 27 05:03:23 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852217088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1852217088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.4174099538
Short name T724
Test name
Test status
Simulation time 30889641087 ps
CPU time 12.01 seconds
Started Aug 27 04:59:05 AM UTC 24
Finished Aug 27 04:59:19 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174099538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.4174099538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_fifo_reset.983288164
Short name T227
Test name
Test status
Simulation time 71735411912 ps
CPU time 182.94 seconds
Started Aug 27 04:59:09 AM UTC 24
Finished Aug 27 05:02:14 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983288164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.983288164
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_intr.3905088239
Short name T872
Test name
Test status
Simulation time 141825979952 ps
CPU time 294.82 seconds
Started Aug 27 04:59:17 AM UTC 24
Finished Aug 27 05:04:16 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905088239 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3905088239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.571571102
Short name T1084
Test name
Test status
Simulation time 126233187161 ps
CPU time 808.48 seconds
Started Aug 27 04:59:35 AM UTC 24
Finished Aug 27 05:13:14 AM UTC 24
Peak memory 212404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571571102 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.571571102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_loopback.3221558299
Short name T745
Test name
Test status
Simulation time 7445615549 ps
CPU time 36.62 seconds
Started Aug 27 04:59:32 AM UTC 24
Finished Aug 27 05:00:10 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221558299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3221558299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_noise_filter.1712298959
Short name T759
Test name
Test status
Simulation time 152042153325 ps
CPU time 83.13 seconds
Started Aug 27 04:59:18 AM UTC 24
Finished Aug 27 05:00:43 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712298959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1712298959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_perf.1282265069
Short name T1009
Test name
Test status
Simulation time 10859229614 ps
CPU time 624.89 seconds
Started Aug 27 04:59:33 AM UTC 24
Finished Aug 27 05:10:06 AM UTC 24
Peak memory 212312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282265069 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1282265069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_rx_oversample.2010340538
Short name T730
Test name
Test status
Simulation time 5401172577 ps
CPU time 21.98 seconds
Started Aug 27 04:59:14 AM UTC 24
Finished Aug 27 04:59:37 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010340538 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2010340538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.3949209562
Short name T738
Test name
Test status
Simulation time 32499168174 ps
CPU time 32 seconds
Started Aug 27 04:59:20 AM UTC 24
Finished Aug 27 04:59:54 AM UTC 24
Peak memory 208736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949209562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3949209562
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.1087242749
Short name T748
Test name
Test status
Simulation time 29155463825 ps
CPU time 52.56 seconds
Started Aug 27 04:59:20 AM UTC 24
Finished Aug 27 05:00:14 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087242749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1087242749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_smoke.1930766427
Short name T722
Test name
Test status
Simulation time 6288825427 ps
CPU time 15.11 seconds
Started Aug 27 04:59:00 AM UTC 24
Finished Aug 27 04:59:16 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930766427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1930766427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_stress_all.3737252873
Short name T1180
Test name
Test status
Simulation time 266360444149 ps
CPU time 1710.27 seconds
Started Aug 27 04:59:39 AM UTC 24
Finished Aug 27 05:28:27 AM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737252873 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3737252873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.3326770948
Short name T758
Test name
Test status
Simulation time 9408715683 ps
CPU time 59.71 seconds
Started Aug 27 04:59:38 AM UTC 24
Finished Aug 27 05:00:39 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3326770948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all
_with_rand_reset.3326770948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.680570207
Short name T731
Test name
Test status
Simulation time 5906948299 ps
CPU time 14.24 seconds
Started Aug 27 04:59:26 AM UTC 24
Finished Aug 27 04:59:42 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680570207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.680570207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_tx_rx.2744008147
Short name T732
Test name
Test status
Simulation time 41802053013 ps
CPU time 38.65 seconds
Started Aug 27 04:59:01 AM UTC 24
Finished Aug 27 04:59:42 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744008147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2744008147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/38.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_alert_test.1171883722
Short name T747
Test name
Test status
Simulation time 35281647 ps
CPU time 0.77 seconds
Started Aug 27 05:00:11 AM UTC 24
Finished Aug 27 05:00:13 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171883722 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1171883722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_fifo_full.3736870113
Short name T754
Test name
Test status
Simulation time 103688018437 ps
CPU time 41.06 seconds
Started Aug 27 04:59:46 AM UTC 24
Finished Aug 27 05:00:28 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736870113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3736870113
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.1304766652
Short name T783
Test name
Test status
Simulation time 61396920936 ps
CPU time 101.15 seconds
Started Aug 27 04:59:47 AM UTC 24
Finished Aug 27 05:01:30 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304766652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1304766652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_fifo_reset.180741852
Short name T776
Test name
Test status
Simulation time 61886924357 ps
CPU time 87.36 seconds
Started Aug 27 04:59:49 AM UTC 24
Finished Aug 27 05:01:18 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180741852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.180741852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_intr.4275779919
Short name T756
Test name
Test status
Simulation time 38967467409 ps
CPU time 36.45 seconds
Started Aug 27 04:59:54 AM UTC 24
Finished Aug 27 05:00:32 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275779919 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.4275779919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.1846075487
Short name T860
Test name
Test status
Simulation time 81350960110 ps
CPU time 218.51 seconds
Started Aug 27 05:00:10 AM UTC 24
Finished Aug 27 05:03:52 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846075487 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1846075487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_loopback.1322266156
Short name T744
Test name
Test status
Simulation time 43970177 ps
CPU time 0.92 seconds
Started Aug 27 05:00:08 AM UTC 24
Finished Aug 27 05:00:10 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322266156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1322266156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_noise_filter.684469311
Short name T793
Test name
Test status
Simulation time 123520938967 ps
CPU time 111.92 seconds
Started Aug 27 04:59:55 AM UTC 24
Finished Aug 27 05:01:49 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684469311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.684469311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_perf.186525195
Short name T904
Test name
Test status
Simulation time 23643199158 ps
CPU time 308.22 seconds
Started Aug 27 05:00:10 AM UTC 24
Finished Aug 27 05:05:23 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186525195 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.186525195
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_rx_oversample.2037961146
Short name T771
Test name
Test status
Simulation time 7147943639 ps
CPU time 76.87 seconds
Started Aug 27 04:59:52 AM UTC 24
Finished Aug 27 05:01:11 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037961146 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2037961146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.1931678239
Short name T770
Test name
Test status
Simulation time 249359743857 ps
CPU time 59.96 seconds
Started Aug 27 05:00:07 AM UTC 24
Finished Aug 27 05:01:08 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931678239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1931678239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.1523465446
Short name T753
Test name
Test status
Simulation time 37608256851 ps
CPU time 30.51 seconds
Started Aug 27 04:59:56 AM UTC 24
Finished Aug 27 05:00:28 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523465446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1523465446
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_smoke.1666757614
Short name T741
Test name
Test status
Simulation time 5537643378 ps
CPU time 23.04 seconds
Started Aug 27 04:59:43 AM UTC 24
Finished Aug 27 05:00:07 AM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666757614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1666757614
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_stress_all.2156467507
Short name T772
Test name
Test status
Simulation time 35859640209 ps
CPU time 58.34 seconds
Started Aug 27 05:00:11 AM UTC 24
Finished Aug 27 05:01:11 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156467507 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2156467507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.635455295
Short name T757
Test name
Test status
Simulation time 5684439366 ps
CPU time 24.44 seconds
Started Aug 27 05:00:11 AM UTC 24
Finished Aug 27 05:00:37 AM UTC 24
Peak memory 217604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=635455295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all_
with_rand_reset.635455295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1883648752
Short name T746
Test name
Test status
Simulation time 1201367002 ps
CPU time 2.83 seconds
Started Aug 27 05:00:07 AM UTC 24
Finished Aug 27 05:00:11 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883648752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1883648752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/39.uart_tx_rx.4223938407
Short name T807
Test name
Test status
Simulation time 65649133507 ps
CPU time 139.44 seconds
Started Aug 27 04:59:46 AM UTC 24
Finished Aug 27 05:02:08 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223938407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.4223938407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/39.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_alert_test.4123191883
Short name T419
Test name
Test status
Simulation time 144572563 ps
CPU time 0.8 seconds
Started Aug 27 04:37:42 AM UTC 24
Finished Aug 27 04:37:44 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123191883 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4123191883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_fifo_reset.3684713300
Short name T122
Test name
Test status
Simulation time 58175980158 ps
CPU time 26.87 seconds
Started Aug 27 04:37:13 AM UTC 24
Finished Aug 27 04:37:41 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684713300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3684713300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_intr.2674194964
Short name T303
Test name
Test status
Simulation time 204976399858 ps
CPU time 105.01 seconds
Started Aug 27 04:37:14 AM UTC 24
Finished Aug 27 04:39:01 AM UTC 24
Peak memory 208928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674194964 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2674194964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_loopback.1778735573
Short name T418
Test name
Test status
Simulation time 9512422306 ps
CPU time 18.99 seconds
Started Aug 27 04:37:21 AM UTC 24
Finished Aug 27 04:37:41 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778735573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1778735573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_noise_filter.1413646511
Short name T257
Test name
Test status
Simulation time 79621922594 ps
CPU time 46.82 seconds
Started Aug 27 04:37:14 AM UTC 24
Finished Aug 27 04:38:02 AM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413646511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1413646511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_perf.2628668220
Short name T267
Test name
Test status
Simulation time 4618311861 ps
CPU time 223.63 seconds
Started Aug 27 04:37:25 AM UTC 24
Finished Aug 27 04:41:12 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628668220 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2628668220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_rx_oversample.1092936755
Short name T388
Test name
Test status
Simulation time 4286840867 ps
CPU time 42.14 seconds
Started Aug 27 04:37:14 AM UTC 24
Finished Aug 27 04:37:57 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092936755 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1092936755
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.869839312
Short name T271
Test name
Test status
Simulation time 5104330141 ps
CPU time 4.27 seconds
Started Aug 27 04:37:15 AM UTC 24
Finished Aug 27 04:37:20 AM UTC 24
Peak memory 205104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869839312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.869839312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_sec_cm.4009814916
Short name T82
Test name
Test status
Simulation time 296690297 ps
CPU time 1.37 seconds
Started Aug 27 04:37:41 AM UTC 24
Finished Aug 27 04:37:43 AM UTC 24
Peak memory 240132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009814916 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.4009814916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_smoke.2863704824
Short name T333
Test name
Test status
Simulation time 293988648 ps
CPU time 1.69 seconds
Started Aug 27 04:37:07 AM UTC 24
Finished Aug 27 04:37:10 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863704824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2863704824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_stress_all.3615265693
Short name T516
Test name
Test status
Simulation time 247214378757 ps
CPU time 657.99 seconds
Started Aug 27 04:37:41 AM UTC 24
Finished Aug 27 04:48:47 AM UTC 24
Peak memory 212436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615265693 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3615265693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.3874118462
Short name T33
Test name
Test status
Simulation time 3009229503 ps
CPU time 10.31 seconds
Started Aug 27 04:37:34 AM UTC 24
Finished Aug 27 04:37:45 AM UTC 24
Peak memory 219788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3874118462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_
with_rand_reset.3874118462
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.2479558402
Short name T307
Test name
Test status
Simulation time 970851032 ps
CPU time 5.28 seconds
Started Aug 27 04:37:18 AM UTC 24
Finished Aug 27 04:37:24 AM UTC 24
Peak memory 207692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479558402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2479558402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/4.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_alert_test.742498850
Short name T764
Test name
Test status
Simulation time 12910673 ps
CPU time 0.81 seconds
Started Aug 27 05:00:47 AM UTC 24
Finished Aug 27 05:00:49 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742498850 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.742498850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_fifo_full.686971901
Short name T822
Test name
Test status
Simulation time 137570207782 ps
CPU time 133.39 seconds
Started Aug 27 05:00:22 AM UTC 24
Finished Aug 27 05:02:38 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686971901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.686971901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.2949340809
Short name T765
Test name
Test status
Simulation time 14996373482 ps
CPU time 26.51 seconds
Started Aug 27 05:00:23 AM UTC 24
Finished Aug 27 05:00:50 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949340809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2949340809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_fifo_reset.641863576
Short name T768
Test name
Test status
Simulation time 32068008599 ps
CPU time 34.4 seconds
Started Aug 27 05:00:28 AM UTC 24
Finished Aug 27 05:01:04 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641863576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.641863576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_intr.383694024
Short name T813
Test name
Test status
Simulation time 203522699852 ps
CPU time 110.7 seconds
Started Aug 27 05:00:29 AM UTC 24
Finished Aug 27 05:02:22 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383694024 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.383694024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.46750574
Short name T831
Test name
Test status
Simulation time 74334382367 ps
CPU time 122.89 seconds
Started Aug 27 05:00:45 AM UTC 24
Finished Aug 27 05:02:50 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46750574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.46750574
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_loopback.457021685
Short name T763
Test name
Test status
Simulation time 7611574730 ps
CPU time 5.52 seconds
Started Aug 27 05:00:39 AM UTC 24
Finished Aug 27 05:00:46 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457021685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.uart_loopback.457021685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_noise_filter.2209970735
Short name T782
Test name
Test status
Simulation time 135441589963 ps
CPU time 55.07 seconds
Started Aug 27 05:00:29 AM UTC 24
Finished Aug 27 05:01:26 AM UTC 24
Peak memory 207628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209970735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2209970735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_perf.4231644187
Short name T850
Test name
Test status
Simulation time 20600332661 ps
CPU time 166.59 seconds
Started Aug 27 05:00:44 AM UTC 24
Finished Aug 27 05:03:33 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231644187 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.4231644187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_rx_oversample.112330033
Short name T762
Test name
Test status
Simulation time 5081719116 ps
CPU time 15.37 seconds
Started Aug 27 05:00:29 AM UTC 24
Finished Aug 27 05:00:46 AM UTC 24
Peak memory 208420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112330033 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.112330033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.2732679808
Short name T790
Test name
Test status
Simulation time 128140245905 ps
CPU time 70.78 seconds
Started Aug 27 05:00:33 AM UTC 24
Finished Aug 27 05:01:46 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732679808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2732679808
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.215874809
Short name T791
Test name
Test status
Simulation time 41491656628 ps
CPU time 70.76 seconds
Started Aug 27 05:00:33 AM UTC 24
Finished Aug 27 05:01:46 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215874809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.215874809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_smoke.3647469004
Short name T749
Test name
Test status
Simulation time 805082138 ps
CPU time 5.95 seconds
Started Aug 27 05:00:13 AM UTC 24
Finished Aug 27 05:00:20 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647469004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3647469004
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_stress_all.2224597808
Short name T887
Test name
Test status
Simulation time 132037377058 ps
CPU time 229.67 seconds
Started Aug 27 05:00:47 AM UTC 24
Finished Aug 27 05:04:40 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224597808 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2224597808
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1639816078
Short name T803
Test name
Test status
Simulation time 8683852043 ps
CPU time 77.8 seconds
Started Aug 27 05:00:46 AM UTC 24
Finished Aug 27 05:02:05 AM UTC 24
Peak memory 217748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1639816078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all
_with_rand_reset.1639816078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.2828335679
Short name T760
Test name
Test status
Simulation time 1059412401 ps
CPU time 5.31 seconds
Started Aug 27 05:00:37 AM UTC 24
Finished Aug 27 05:00:44 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828335679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2828335679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/40.uart_tx_rx.4247039897
Short name T755
Test name
Test status
Simulation time 37087882228 ps
CPU time 15.38 seconds
Started Aug 27 05:00:15 AM UTC 24
Finished Aug 27 05:00:32 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247039897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4247039897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/40.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_alert_test.4221366994
Short name T781
Test name
Test status
Simulation time 13164373 ps
CPU time 0.82 seconds
Started Aug 27 05:01:23 AM UTC 24
Finished Aug 27 05:01:25 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221366994 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4221366994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_fifo_full.502300440
Short name T936
Test name
Test status
Simulation time 143134847179 ps
CPU time 366.54 seconds
Started Aug 27 05:00:54 AM UTC 24
Finished Aug 27 05:07:06 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502300440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.502300440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.3430423801
Short name T172
Test name
Test status
Simulation time 178970553192 ps
CPU time 103.52 seconds
Started Aug 27 05:00:59 AM UTC 24
Finished Aug 27 05:02:45 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430423801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3430423801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_fifo_reset.762552886
Short name T784
Test name
Test status
Simulation time 29117819302 ps
CPU time 26.36 seconds
Started Aug 27 05:01:04 AM UTC 24
Finished Aug 27 05:01:32 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762552886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.762552886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_intr.3246159885
Short name T786
Test name
Test status
Simulation time 16401920347 ps
CPU time 23.13 seconds
Started Aug 27 05:01:09 AM UTC 24
Finished Aug 27 05:01:34 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246159885 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3246159885
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.4268073858
Short name T884
Test name
Test status
Simulation time 66228871049 ps
CPU time 191.47 seconds
Started Aug 27 05:01:20 AM UTC 24
Finished Aug 27 05:04:35 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268073858 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4268073858
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_loopback.3379537689
Short name T780
Test name
Test status
Simulation time 6613154477 ps
CPU time 3.43 seconds
Started Aug 27 05:01:18 AM UTC 24
Finished Aug 27 05:01:22 AM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379537689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3379537689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_noise_filter.3592955255
Short name T410
Test name
Test status
Simulation time 58335329257 ps
CPU time 28.98 seconds
Started Aug 27 05:01:12 AM UTC 24
Finished Aug 27 05:01:42 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592955255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3592955255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_perf.3256380680
Short name T966
Test name
Test status
Simulation time 16485461051 ps
CPU time 423.33 seconds
Started Aug 27 05:01:19 AM UTC 24
Finished Aug 27 05:08:28 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256380680 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3256380680
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_rx_oversample.3896423561
Short name T773
Test name
Test status
Simulation time 1914609626 ps
CPU time 6.41 seconds
Started Aug 27 05:01:06 AM UTC 24
Finished Aug 27 05:01:14 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896423561 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3896423561
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.1683765824
Short name T171
Test name
Test status
Simulation time 189672842772 ps
CPU time 84.86 seconds
Started Aug 27 05:01:15 AM UTC 24
Finished Aug 27 05:02:41 AM UTC 24
Peak memory 208600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683765824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1683765824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.1340639550
Short name T777
Test name
Test status
Simulation time 3029600795 ps
CPU time 6.33 seconds
Started Aug 27 05:01:12 AM UTC 24
Finished Aug 27 05:01:19 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340639550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1340639550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_smoke.1587113722
Short name T766
Test name
Test status
Simulation time 486085672 ps
CPU time 1.92 seconds
Started Aug 27 05:00:50 AM UTC 24
Finished Aug 27 05:00:53 AM UTC 24
Peak memory 206704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587113722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1587113722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_stress_all.676341424
Short name T871
Test name
Test status
Simulation time 64020863408 ps
CPU time 169.47 seconds
Started Aug 27 05:01:23 AM UTC 24
Finished Aug 27 05:04:15 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676341424 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.676341424
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.3250455697
Short name T810
Test name
Test status
Simulation time 9257492111 ps
CPU time 52.18 seconds
Started Aug 27 05:01:22 AM UTC 24
Finished Aug 27 05:02:16 AM UTC 24
Peak memory 217808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3250455697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all
_with_rand_reset.3250455697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.728670125
Short name T779
Test name
Test status
Simulation time 856005878 ps
CPU time 5.45 seconds
Started Aug 27 05:01:16 AM UTC 24
Finished Aug 27 05:01:22 AM UTC 24
Peak memory 207880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728670125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.728670125
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/41.uart_tx_rx.604941375
Short name T828
Test name
Test status
Simulation time 149669318415 ps
CPU time 111.63 seconds
Started Aug 27 05:00:51 AM UTC 24
Finished Aug 27 05:02:45 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604941375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.604941375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/41.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_alert_test.557628873
Short name T798
Test name
Test status
Simulation time 12875170 ps
CPU time 0.81 seconds
Started Aug 27 05:01:52 AM UTC 24
Finished Aug 27 05:01:54 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557628873 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.557628873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_fifo_full.2141512283
Short name T403
Test name
Test status
Simulation time 128092816588 ps
CPU time 22.41 seconds
Started Aug 27 05:01:31 AM UTC 24
Finished Aug 27 05:01:54 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141512283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2141512283
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.1030843798
Short name T801
Test name
Test status
Simulation time 44174098669 ps
CPU time 28.05 seconds
Started Aug 27 05:01:33 AM UTC 24
Finished Aug 27 05:02:02 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030843798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1030843798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_fifo_reset.995125004
Short name T159
Test name
Test status
Simulation time 170567925784 ps
CPU time 29.38 seconds
Started Aug 27 05:01:34 AM UTC 24
Finished Aug 27 05:02:05 AM UTC 24
Peak memory 208284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995125004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.995125004
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_intr.3595553553
Short name T954
Test name
Test status
Simulation time 236161881060 ps
CPU time 374.6 seconds
Started Aug 27 05:01:40 AM UTC 24
Finished Aug 27 05:07:59 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595553553 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3595553553
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.1004777917
Short name T944
Test name
Test status
Simulation time 131032275503 ps
CPU time 334.26 seconds
Started Aug 27 05:01:47 AM UTC 24
Finished Aug 27 05:07:25 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004777917 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1004777917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_loopback.1234065201
Short name T794
Test name
Test status
Simulation time 2525169253 ps
CPU time 1.96 seconds
Started Aug 27 05:01:47 AM UTC 24
Finished Aug 27 05:01:50 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234065201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1234065201
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_noise_filter.3261067887
Short name T805
Test name
Test status
Simulation time 62909623003 ps
CPU time 25.71 seconds
Started Aug 27 05:01:40 AM UTC 24
Finished Aug 27 05:02:07 AM UTC 24
Peak memory 207432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261067887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3261067887
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_perf.2788408253
Short name T849
Test name
Test status
Simulation time 19961917323 ps
CPU time 97.76 seconds
Started Aug 27 05:01:47 AM UTC 24
Finished Aug 27 05:03:26 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788408253 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2788408253
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_rx_oversample.2315023688
Short name T800
Test name
Test status
Simulation time 2943388193 ps
CPU time 20.13 seconds
Started Aug 27 05:01:35 AM UTC 24
Finished Aug 27 05:01:56 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315023688 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2315023688
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.1117255854
Short name T881
Test name
Test status
Simulation time 93276845723 ps
CPU time 165.1 seconds
Started Aug 27 05:01:43 AM UTC 24
Finished Aug 27 05:04:31 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117255854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1117255854
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.1404747381
Short name T792
Test name
Test status
Simulation time 4402538111 ps
CPU time 2.79 seconds
Started Aug 27 05:01:42 AM UTC 24
Finished Aug 27 05:01:46 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404747381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1404747381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_smoke.1684749750
Short name T789
Test name
Test status
Simulation time 6065765613 ps
CPU time 17.46 seconds
Started Aug 27 05:01:25 AM UTC 24
Finished Aug 27 05:01:44 AM UTC 24
Peak memory 208124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684749750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1684749750
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_stress_all.195753540
Short name T1018
Test name
Test status
Simulation time 13373676684 ps
CPU time 518 seconds
Started Aug 27 05:01:51 AM UTC 24
Finished Aug 27 05:10:36 AM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195753540 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.195753540
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.1183818727
Short name T802
Test name
Test status
Simulation time 924648591 ps
CPU time 13.7 seconds
Started Aug 27 05:01:50 AM UTC 24
Finished Aug 27 05:02:05 AM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1183818727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all
_with_rand_reset.1183818727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.3375989838
Short name T795
Test name
Test status
Simulation time 5131384727 ps
CPU time 4.07 seconds
Started Aug 27 05:01:45 AM UTC 24
Finished Aug 27 05:01:51 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375989838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3375989838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/42.uart_tx_rx.1846589270
Short name T797
Test name
Test status
Simulation time 11028978354 ps
CPU time 23.83 seconds
Started Aug 27 05:01:27 AM UTC 24
Finished Aug 27 05:01:52 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846589270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1846589270
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/42.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_alert_test.2435108687
Short name T811
Test name
Test status
Simulation time 106675441 ps
CPU time 0.82 seconds
Started Aug 27 05:02:15 AM UTC 24
Finished Aug 27 05:02:17 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435108687 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2435108687
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_fifo_full.194208156
Short name T833
Test name
Test status
Simulation time 44017545789 ps
CPU time 59.9 seconds
Started Aug 27 05:01:54 AM UTC 24
Finished Aug 27 05:02:56 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194208156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.194208156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.4150374596
Short name T815
Test name
Test status
Simulation time 17765006480 ps
CPU time 30.81 seconds
Started Aug 27 05:01:55 AM UTC 24
Finished Aug 27 05:02:27 AM UTC 24
Peak memory 208460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150374596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.4150374596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_fifo_reset.416629816
Short name T820
Test name
Test status
Simulation time 60911259698 ps
CPU time 37.82 seconds
Started Aug 27 05:01:55 AM UTC 24
Finished Aug 27 05:02:34 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416629816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.416629816
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_intr.2542794917
Short name T819
Test name
Test status
Simulation time 62122009411 ps
CPU time 28.46 seconds
Started Aug 27 05:02:04 AM UTC 24
Finished Aug 27 05:02:33 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542794917 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2542794917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.1900213962
Short name T1153
Test name
Test status
Simulation time 155018779557 ps
CPU time 788.54 seconds
Started Aug 27 05:02:09 AM UTC 24
Finished Aug 27 05:15:27 AM UTC 24
Peak memory 212280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900213962 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1900213962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_loopback.2188389294
Short name T816
Test name
Test status
Simulation time 5173348694 ps
CPU time 21.59 seconds
Started Aug 27 05:02:08 AM UTC 24
Finished Aug 27 05:02:31 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188389294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2188389294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_noise_filter.898781057
Short name T825
Test name
Test status
Simulation time 19254391220 ps
CPU time 34.16 seconds
Started Aug 27 05:02:06 AM UTC 24
Finished Aug 27 05:02:41 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898781057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.898781057
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_perf.4123540671
Short name T895
Test name
Test status
Simulation time 13068476998 ps
CPU time 168.52 seconds
Started Aug 27 05:02:08 AM UTC 24
Finished Aug 27 05:04:59 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123540671 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.4123540671
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_rx_oversample.2455618431
Short name T806
Test name
Test status
Simulation time 1699877893 ps
CPU time 9.15 seconds
Started Aug 27 05:01:57 AM UTC 24
Finished Aug 27 05:02:08 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455618431 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2455618431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.1845454021
Short name T830
Test name
Test status
Simulation time 48260501493 ps
CPU time 39.51 seconds
Started Aug 27 05:02:06 AM UTC 24
Finished Aug 27 05:02:47 AM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845454021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1845454021
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.2609926889
Short name T814
Test name
Test status
Simulation time 6062374965 ps
CPU time 16.46 seconds
Started Aug 27 05:02:06 AM UTC 24
Finished Aug 27 05:02:23 AM UTC 24
Peak memory 204920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609926889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2609926889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_smoke.2595113344
Short name T799
Test name
Test status
Simulation time 87055608 ps
CPU time 1.19 seconds
Started Aug 27 05:01:52 AM UTC 24
Finished Aug 27 05:01:54 AM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595113344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2595113344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_stress_all.419346978
Short name T991
Test name
Test status
Simulation time 80251875419 ps
CPU time 425.02 seconds
Started Aug 27 05:02:13 AM UTC 24
Finished Aug 27 05:09:24 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419346978 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.419346978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.1489826306
Short name T818
Test name
Test status
Simulation time 6772571267 ps
CPU time 18.39 seconds
Started Aug 27 05:02:12 AM UTC 24
Finished Aug 27 05:02:32 AM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1489826306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all
_with_rand_reset.1489826306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.842904955
Short name T809
Test name
Test status
Simulation time 1356757047 ps
CPU time 4.19 seconds
Started Aug 27 05:02:07 AM UTC 24
Finished Aug 27 05:02:12 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842904955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.842904955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_tx_rx.1861192296
Short name T812
Test name
Test status
Simulation time 30876386126 ps
CPU time 23.79 seconds
Started Aug 27 05:01:53 AM UTC 24
Finished Aug 27 05:02:18 AM UTC 24
Peak memory 208392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861192296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1861192296
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/43.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_alert_test.3494353050
Short name T827
Test name
Test status
Simulation time 11222537 ps
CPU time 0.83 seconds
Started Aug 27 05:02:42 AM UTC 24
Finished Aug 27 05:02:44 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494353050 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3494353050
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_fifo_full.1456921234
Short name T927
Test name
Test status
Simulation time 182422370573 ps
CPU time 253.43 seconds
Started Aug 27 05:02:19 AM UTC 24
Finished Aug 27 05:06:36 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456921234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1456921234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.2743506154
Short name T821
Test name
Test status
Simulation time 13155314812 ps
CPU time 11.11 seconds
Started Aug 27 05:02:23 AM UTC 24
Finished Aug 27 05:02:35 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743506154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2743506154
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_fifo_reset.3313163541
Short name T832
Test name
Test status
Simulation time 13470114044 ps
CPU time 26.76 seconds
Started Aug 27 05:02:24 AM UTC 24
Finished Aug 27 05:02:52 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313163541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3313163541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_intr.2804837236
Short name T841
Test name
Test status
Simulation time 39456259485 ps
CPU time 37.39 seconds
Started Aug 27 05:02:32 AM UTC 24
Finished Aug 27 05:03:11 AM UTC 24
Peak memory 208580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804837236 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2804837236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.1945784155
Short name T993
Test name
Test status
Simulation time 94070566382 ps
CPU time 401.67 seconds
Started Aug 27 05:02:39 AM UTC 24
Finished Aug 27 05:09:25 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945784155 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1945784155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_loopback.3376013775
Short name T826
Test name
Test status
Simulation time 13722068203 ps
CPU time 5.55 seconds
Started Aug 27 05:02:35 AM UTC 24
Finished Aug 27 05:02:42 AM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376013775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3376013775
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_noise_filter.1659362127
Short name T909
Test name
Test status
Simulation time 78606335457 ps
CPU time 180.91 seconds
Started Aug 27 05:02:32 AM UTC 24
Finished Aug 27 05:05:36 AM UTC 24
Peak memory 208948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659362127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1659362127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_perf.1372668861
Short name T852
Test name
Test status
Simulation time 9128147844 ps
CPU time 58.61 seconds
Started Aug 27 05:02:39 AM UTC 24
Finished Aug 27 05:03:39 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372668861 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1372668861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_rx_oversample.2775224533
Short name T829
Test name
Test status
Simulation time 5833399701 ps
CPU time 16.18 seconds
Started Aug 27 05:02:28 AM UTC 24
Finished Aug 27 05:02:45 AM UTC 24
Peak memory 207816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775224533 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2775224533
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.3144748822
Short name T886
Test name
Test status
Simulation time 67296864729 ps
CPU time 120.64 seconds
Started Aug 27 05:02:34 AM UTC 24
Finished Aug 27 05:04:37 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144748822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3144748822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.1562982050
Short name T823
Test name
Test status
Simulation time 2909372110 ps
CPU time 3.31 seconds
Started Aug 27 05:02:33 AM UTC 24
Finished Aug 27 05:02:38 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562982050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1562982050
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_smoke.3616730390
Short name T835
Test name
Test status
Simulation time 5522696898 ps
CPU time 40.47 seconds
Started Aug 27 05:02:17 AM UTC 24
Finished Aug 27 05:02:58 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616730390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3616730390
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_stress_all.1618035978
Short name T901
Test name
Test status
Simulation time 250541066473 ps
CPU time 153.84 seconds
Started Aug 27 05:02:42 AM UTC 24
Finished Aug 27 05:05:19 AM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618035978 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1618035978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.2195057893
Short name T867
Test name
Test status
Simulation time 4630524559 ps
CPU time 91.3 seconds
Started Aug 27 05:02:40 AM UTC 24
Finished Aug 27 05:04:13 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2195057893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all
_with_rand_reset.2195057893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.747966279
Short name T837
Test name
Test status
Simulation time 6632282886 ps
CPU time 26.05 seconds
Started Aug 27 05:02:35 AM UTC 24
Finished Aug 27 05:03:03 AM UTC 24
Peak memory 208516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747966279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.747966279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/44.uart_tx_rx.3582818297
Short name T817
Test name
Test status
Simulation time 9648439104 ps
CPU time 12.94 seconds
Started Aug 27 05:02:18 AM UTC 24
Finished Aug 27 05:02:32 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582818297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3582818297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/44.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_alert_test.1033606673
Short name T842
Test name
Test status
Simulation time 11680820 ps
CPU time 0.79 seconds
Started Aug 27 05:03:11 AM UTC 24
Finished Aug 27 05:03:13 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033606673 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1033606673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_fifo_full.9682084
Short name T840
Test name
Test status
Simulation time 14662938030 ps
CPU time 21.95 seconds
Started Aug 27 05:02:46 AM UTC 24
Finished Aug 27 05:03:09 AM UTC 24
Peak memory 208864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9682084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.9682084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.2614135914
Short name T846
Test name
Test status
Simulation time 78732068965 ps
CPU time 33.48 seconds
Started Aug 27 05:02:46 AM UTC 24
Finished Aug 27 05:03:21 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614135914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2614135914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_fifo_reset.2742317514
Short name T843
Test name
Test status
Simulation time 28079371852 ps
CPU time 30.76 seconds
Started Aug 27 05:02:46 AM UTC 24
Finished Aug 27 05:03:19 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742317514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2742317514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_intr.3270222608
Short name T956
Test name
Test status
Simulation time 86008559587 ps
CPU time 305.6 seconds
Started Aug 27 05:02:51 AM UTC 24
Finished Aug 27 05:08:00 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270222608 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3270222608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.290119590
Short name T925
Test name
Test status
Simulation time 61838242631 ps
CPU time 204.18 seconds
Started Aug 27 05:03:05 AM UTC 24
Finished Aug 27 05:06:32 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290119590 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.290119590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_loopback.504867528
Short name T844
Test name
Test status
Simulation time 6144215428 ps
CPU time 15.75 seconds
Started Aug 27 05:03:02 AM UTC 24
Finished Aug 27 05:03:19 AM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504867528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.uart_loopback.504867528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_noise_filter.3909425916
Short name T857
Test name
Test status
Simulation time 26869227141 ps
CPU time 52.04 seconds
Started Aug 27 05:02:53 AM UTC 24
Finished Aug 27 05:03:46 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909425916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3909425916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_perf.120667883
Short name T864
Test name
Test status
Simulation time 6395416719 ps
CPU time 56.46 seconds
Started Aug 27 05:03:04 AM UTC 24
Finished Aug 27 05:04:02 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120667883 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.120667883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_rx_oversample.3470669090
Short name T839
Test name
Test status
Simulation time 2545433383 ps
CPU time 20.28 seconds
Started Aug 27 05:02:47 AM UTC 24
Finished Aug 27 05:03:09 AM UTC 24
Peak memory 207624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470669090 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3470669090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.91162299
Short name T855
Test name
Test status
Simulation time 102085010371 ps
CPU time 44.28 seconds
Started Aug 27 05:02:59 AM UTC 24
Finished Aug 27 05:03:45 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91162299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.91162299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.114565318
Short name T851
Test name
Test status
Simulation time 40015441985 ps
CPU time 36.77 seconds
Started Aug 27 05:02:57 AM UTC 24
Finished Aug 27 05:03:35 AM UTC 24
Peak memory 205288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114565318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.114565318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_smoke.594795091
Short name T845
Test name
Test status
Simulation time 5864057128 ps
CPU time 34.39 seconds
Started Aug 27 05:02:43 AM UTC 24
Finished Aug 27 05:03:19 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594795091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 45.uart_smoke.594795091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_stress_all.2748393202
Short name T1181
Test name
Test status
Simulation time 248604681665 ps
CPU time 1640.11 seconds
Started Aug 27 05:03:10 AM UTC 24
Finished Aug 27 05:30:48 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748393202 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2748393202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.1321439850
Short name T877
Test name
Test status
Simulation time 2053638991 ps
CPU time 75.61 seconds
Started Aug 27 05:03:10 AM UTC 24
Finished Aug 27 05:04:28 AM UTC 24
Peak memory 208964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1321439850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all
_with_rand_reset.1321439850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.2735568096
Short name T838
Test name
Test status
Simulation time 834967417 ps
CPU time 4.61 seconds
Started Aug 27 05:02:59 AM UTC 24
Finished Aug 27 05:03:05 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735568096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2735568096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_tx_rx.2237413828
Short name T861
Test name
Test status
Simulation time 29409603024 ps
CPU time 65.68 seconds
Started Aug 27 05:02:45 AM UTC 24
Finished Aug 27 05:03:53 AM UTC 24
Peak memory 208868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237413828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2237413828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/45.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_alert_test.995004767
Short name T859
Test name
Test status
Simulation time 12452035 ps
CPU time 0.82 seconds
Started Aug 27 05:03:50 AM UTC 24
Finished Aug 27 05:03:52 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995004767 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.995004767
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_fifo_full.1238812621
Short name T926
Test name
Test status
Simulation time 164856736858 ps
CPU time 192.19 seconds
Started Aug 27 05:03:20 AM UTC 24
Finished Aug 27 05:06:35 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238812621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1238812621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.2471780119
Short name T870
Test name
Test status
Simulation time 84255904784 ps
CPU time 53.39 seconds
Started Aug 27 05:03:20 AM UTC 24
Finished Aug 27 05:04:15 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471780119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2471780119
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_fifo_reset.136030233
Short name T865
Test name
Test status
Simulation time 128721118877 ps
CPU time 45.51 seconds
Started Aug 27 05:03:22 AM UTC 24
Finished Aug 27 05:04:09 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136030233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.136030233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_intr.2671355779
Short name T896
Test name
Test status
Simulation time 305190684944 ps
CPU time 94.75 seconds
Started Aug 27 05:03:25 AM UTC 24
Finished Aug 27 05:05:02 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671355779 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2671355779
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.4080714252
Short name T1166
Test name
Test status
Simulation time 115446094376 ps
CPU time 739.54 seconds
Started Aug 27 05:03:46 AM UTC 24
Finished Aug 27 05:16:13 AM UTC 24
Peak memory 212220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080714252 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.4080714252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_loopback.3793464573
Short name T862
Test name
Test status
Simulation time 2798735600 ps
CPU time 9.68 seconds
Started Aug 27 05:03:42 AM UTC 24
Finished Aug 27 05:03:53 AM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793464573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3793464573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_noise_filter.2216155537
Short name T929
Test name
Test status
Simulation time 79514485075 ps
CPU time 196.3 seconds
Started Aug 27 05:03:27 AM UTC 24
Finished Aug 27 05:06:46 AM UTC 24
Peak memory 217472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216155537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2216155537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_perf.4281013707
Short name T952
Test name
Test status
Simulation time 14081086582 ps
CPU time 244.87 seconds
Started Aug 27 05:03:44 AM UTC 24
Finished Aug 27 05:07:52 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281013707 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.4281013707
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_rx_oversample.3472131118
Short name T858
Test name
Test status
Simulation time 3997981667 ps
CPU time 24.74 seconds
Started Aug 27 05:03:23 AM UTC 24
Finished Aug 27 05:03:49 AM UTC 24
Peak memory 207880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472131118 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3472131118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.1421142554
Short name T962
Test name
Test status
Simulation time 101238142793 ps
CPU time 275.7 seconds
Started Aug 27 05:03:36 AM UTC 24
Finished Aug 27 05:08:16 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421142554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1421142554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.3940438616
Short name T876
Test name
Test status
Simulation time 44633704966 ps
CPU time 52.08 seconds
Started Aug 27 05:03:33 AM UTC 24
Finished Aug 27 05:04:27 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940438616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3940438616
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_smoke.4276513845
Short name T848
Test name
Test status
Simulation time 884971429 ps
CPU time 8.39 seconds
Started Aug 27 05:03:14 AM UTC 24
Finished Aug 27 05:03:24 AM UTC 24
Peak memory 208736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276513845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4276513845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_stress_all.3180105307
Short name T973
Test name
Test status
Simulation time 543875434328 ps
CPU time 288.68 seconds
Started Aug 27 05:03:47 AM UTC 24
Finished Aug 27 05:08:40 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180105307 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3180105307
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.1698028637
Short name T902
Test name
Test status
Simulation time 9982134322 ps
CPU time 93.89 seconds
Started Aug 27 05:03:46 AM UTC 24
Finished Aug 27 05:05:22 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1698028637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all
_with_rand_reset.1698028637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.3352277695
Short name T854
Test name
Test status
Simulation time 2290710610 ps
CPU time 2.65 seconds
Started Aug 27 05:03:39 AM UTC 24
Finished Aug 27 05:03:43 AM UTC 24
Peak memory 207496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352277695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3352277695
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_tx_rx.357787530
Short name T869
Test name
Test status
Simulation time 66898953880 ps
CPU time 52.81 seconds
Started Aug 27 05:03:20 AM UTC 24
Finished Aug 27 05:04:14 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357787530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.357787530
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/46.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_alert_test.932511158
Short name T875
Test name
Test status
Simulation time 13169508 ps
CPU time 0.82 seconds
Started Aug 27 05:04:23 AM UTC 24
Finished Aug 27 05:04:26 AM UTC 24
Peak memory 204292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932511158 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.932511158
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_fifo_full.2414262497
Short name T893
Test name
Test status
Simulation time 77917787461 ps
CPU time 60.79 seconds
Started Aug 27 05:03:53 AM UTC 24
Finished Aug 27 05:04:56 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414262497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2414262497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.4268013572
Short name T931
Test name
Test status
Simulation time 99339993494 ps
CPU time 175.27 seconds
Started Aug 27 05:03:53 AM UTC 24
Finished Aug 27 05:06:51 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268013572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.4268013572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_fifo_reset.4212777090
Short name T415
Test name
Test status
Simulation time 161059416820 ps
CPU time 371.31 seconds
Started Aug 27 05:03:56 AM UTC 24
Finished Aug 27 05:10:12 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212777090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.4212777090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_intr.2386311502
Short name T868
Test name
Test status
Simulation time 27416930404 ps
CPU time 9.68 seconds
Started Aug 27 05:04:03 AM UTC 24
Finished Aug 27 05:04:13 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386311502 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2386311502
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.984606959
Short name T1075
Test name
Test status
Simulation time 62109802005 ps
CPU time 519.66 seconds
Started Aug 27 05:04:16 AM UTC 24
Finished Aug 27 05:13:02 AM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984606959 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.984606959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_loopback.2886008487
Short name T874
Test name
Test status
Simulation time 4175164237 ps
CPU time 6.52 seconds
Started Aug 27 05:04:15 AM UTC 24
Finished Aug 27 05:04:23 AM UTC 24
Peak memory 207688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886008487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2886008487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_noise_filter.1682385451
Short name T937
Test name
Test status
Simulation time 65823449172 ps
CPU time 179.52 seconds
Started Aug 27 05:04:10 AM UTC 24
Finished Aug 27 05:07:12 AM UTC 24
Peak memory 217528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682385451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1682385451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_perf.361095443
Short name T998
Test name
Test status
Simulation time 23036887740 ps
CPU time 313.55 seconds
Started Aug 27 05:04:15 AM UTC 24
Finished Aug 27 05:09:33 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361095443 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.361095443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_rx_oversample.2472078882
Short name T866
Test name
Test status
Simulation time 6885360475 ps
CPU time 12.7 seconds
Started Aug 27 05:03:59 AM UTC 24
Finished Aug 27 05:04:12 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472078882 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2472078882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.2031441707
Short name T915
Test name
Test status
Simulation time 117752433590 ps
CPU time 102.21 seconds
Started Aug 27 05:04:14 AM UTC 24
Finished Aug 27 05:05:58 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031441707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2031441707
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.3888137640
Short name T873
Test name
Test status
Simulation time 2447110077 ps
CPU time 8.58 seconds
Started Aug 27 05:04:13 AM UTC 24
Finished Aug 27 05:04:22 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888137640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3888137640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_smoke.2776085778
Short name T863
Test name
Test status
Simulation time 99522719 ps
CPU time 1.51 seconds
Started Aug 27 05:03:53 AM UTC 24
Finished Aug 27 05:03:56 AM UTC 24
Peak memory 205908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776085778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2776085778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_stress_all.3464256410
Short name T1003
Test name
Test status
Simulation time 277344827447 ps
CPU time 322.99 seconds
Started Aug 27 05:04:23 AM UTC 24
Finished Aug 27 05:09:51 AM UTC 24
Peak memory 208804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464256410 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3464256410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.271682163
Short name T883
Test name
Test status
Simulation time 1035119700 ps
CPU time 14.63 seconds
Started Aug 27 05:04:16 AM UTC 24
Finished Aug 27 05:04:32 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=271682163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all_
with_rand_reset.271682163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.507194174
Short name T878
Test name
Test status
Simulation time 6687310709 ps
CPU time 14.26 seconds
Started Aug 27 05:04:14 AM UTC 24
Finished Aug 27 05:04:29 AM UTC 24
Peak memory 208340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507194174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.507194174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_tx_rx.1455303320
Short name T958
Test name
Test status
Simulation time 95191016390 ps
CPU time 249.73 seconds
Started Aug 27 05:03:53 AM UTC 24
Finished Aug 27 05:08:06 AM UTC 24
Peak memory 208216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455303320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1455303320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/47.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_alert_test.3638410973
Short name T892
Test name
Test status
Simulation time 11618487 ps
CPU time 0.75 seconds
Started Aug 27 05:04:51 AM UTC 24
Finished Aug 27 05:04:53 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638410973 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3638410973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_fifo_full.3283067031
Short name T914
Test name
Test status
Simulation time 35205974416 ps
CPU time 83.08 seconds
Started Aug 27 05:04:29 AM UTC 24
Finished Aug 27 05:05:54 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283067031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3283067031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.1287449915
Short name T907
Test name
Test status
Simulation time 115327882786 ps
CPU time 60.15 seconds
Started Aug 27 05:04:30 AM UTC 24
Finished Aug 27 05:05:32 AM UTC 24
Peak memory 208432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287449915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1287449915
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_fifo_reset.4080874064
Short name T181
Test name
Test status
Simulation time 13303330538 ps
CPU time 41.1 seconds
Started Aug 27 05:04:31 AM UTC 24
Finished Aug 27 05:05:14 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080874064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.4080874064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_intr.141796938
Short name T1085
Test name
Test status
Simulation time 226677564095 ps
CPU time 517.99 seconds
Started Aug 27 05:04:32 AM UTC 24
Finished Aug 27 05:13:17 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141796938 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.141796938
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.500548256
Short name T1039
Test name
Test status
Simulation time 63222458300 ps
CPU time 412.28 seconds
Started Aug 27 05:04:42 AM UTC 24
Finished Aug 27 05:11:39 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500548256 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.500548256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_loopback.3045017136
Short name T890
Test name
Test status
Simulation time 5451807453 ps
CPU time 3.95 seconds
Started Aug 27 05:04:37 AM UTC 24
Finished Aug 27 05:04:43 AM UTC 24
Peak memory 208592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045017136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3045017136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_noise_filter.1125619318
Short name T898
Test name
Test status
Simulation time 41113515474 ps
CPU time 34.03 seconds
Started Aug 27 05:04:33 AM UTC 24
Finished Aug 27 05:05:09 AM UTC 24
Peak memory 207560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125619318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1125619318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_perf.3437562830
Short name T1159
Test name
Test status
Simulation time 31696527183 ps
CPU time 658.89 seconds
Started Aug 27 05:04:41 AM UTC 24
Finished Aug 27 05:15:47 AM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437562830 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3437562830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_rx_oversample.444174103
Short name T888
Test name
Test status
Simulation time 2128678423 ps
CPU time 8.61 seconds
Started Aug 27 05:04:31 AM UTC 24
Finished Aug 27 05:04:41 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444174103 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.444174103
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.2151547555
Short name T979
Test name
Test status
Simulation time 131446622052 ps
CPU time 246.02 seconds
Started Aug 27 05:04:35 AM UTC 24
Finished Aug 27 05:08:45 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151547555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2151547555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.876608840
Short name T885
Test name
Test status
Simulation time 1737705235 ps
CPU time 1.45 seconds
Started Aug 27 05:04:33 AM UTC 24
Finished Aug 27 05:04:36 AM UTC 24
Peak memory 204436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876608840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.876608840
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_smoke.3751433123
Short name T879
Test name
Test status
Simulation time 152914867 ps
CPU time 1.17 seconds
Started Aug 27 05:04:27 AM UTC 24
Finished Aug 27 05:04:30 AM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751433123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3751433123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_stress_all.3510783182
Short name T183
Test name
Test status
Simulation time 368233481195 ps
CPU time 161.13 seconds
Started Aug 27 05:04:44 AM UTC 24
Finished Aug 27 05:07:28 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510783182 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3510783182
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.3020461363
Short name T899
Test name
Test status
Simulation time 4757650304 ps
CPU time 28.78 seconds
Started Aug 27 05:04:43 AM UTC 24
Finished Aug 27 05:05:13 AM UTC 24
Peak memory 217616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3020461363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all
_with_rand_reset.3020461363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.2526221236
Short name T889
Test name
Test status
Simulation time 1321265167 ps
CPU time 4.85 seconds
Started Aug 27 05:04:36 AM UTC 24
Finished Aug 27 05:04:42 AM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526221236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2526221236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_tx_rx.3142590072
Short name T882
Test name
Test status
Simulation time 955891841 ps
CPU time 2.08 seconds
Started Aug 27 05:04:28 AM UTC 24
Finished Aug 27 05:04:32 AM UTC 24
Peak memory 207008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142590072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3142590072
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/48.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_alert_test.969961541
Short name T908
Test name
Test status
Simulation time 21723193 ps
CPU time 0.81 seconds
Started Aug 27 05:05:32 AM UTC 24
Finished Aug 27 05:05:34 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969961541 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.969961541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_fifo_full.510076717
Short name T948
Test name
Test status
Simulation time 101753661047 ps
CPU time 162.25 seconds
Started Aug 27 05:04:59 AM UTC 24
Finished Aug 27 05:07:44 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510076717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.510076717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.2942216939
Short name T913
Test name
Test status
Simulation time 30230513552 ps
CPU time 52.19 seconds
Started Aug 27 05:05:00 AM UTC 24
Finished Aug 27 05:05:54 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942216939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2942216939
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_fifo_reset.2992702778
Short name T942
Test name
Test status
Simulation time 169750797817 ps
CPU time 140.18 seconds
Started Aug 27 05:05:02 AM UTC 24
Finished Aug 27 05:07:25 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992702778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2992702778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_intr.347801790
Short name T928
Test name
Test status
Simulation time 135962848860 ps
CPU time 88.83 seconds
Started Aug 27 05:05:10 AM UTC 24
Finished Aug 27 05:06:40 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347801790 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.347801790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.2641552322
Short name T1178
Test name
Test status
Simulation time 121321921218 ps
CPU time 1017.98 seconds
Started Aug 27 05:05:23 AM UTC 24
Finished Aug 27 05:22:32 AM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641552322 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2641552322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_loopback.1991571870
Short name T912
Test name
Test status
Simulation time 6673434096 ps
CPU time 28.55 seconds
Started Aug 27 05:05:22 AM UTC 24
Finished Aug 27 05:05:52 AM UTC 24
Peak memory 207896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991571870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1991571870
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_noise_filter.3235266436
Short name T910
Test name
Test status
Simulation time 15122570908 ps
CPU time 25.32 seconds
Started Aug 27 05:05:14 AM UTC 24
Finished Aug 27 05:05:40 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235266436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3235266436
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_perf.3550341026
Short name T1063
Test name
Test status
Simulation time 14039184881 ps
CPU time 424.03 seconds
Started Aug 27 05:05:22 AM UTC 24
Finished Aug 27 05:12:31 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550341026 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3550341026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_rx_oversample.1637163729
Short name T903
Test name
Test status
Simulation time 2164350418 ps
CPU time 16.98 seconds
Started Aug 27 05:05:03 AM UTC 24
Finished Aug 27 05:05:22 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637163729 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1637163729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.1948905464
Short name T911
Test name
Test status
Simulation time 60811171326 ps
CPU time 34.54 seconds
Started Aug 27 05:05:15 AM UTC 24
Finished Aug 27 05:05:51 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948905464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1948905464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.998463549
Short name T918
Test name
Test status
Simulation time 40572507510 ps
CPU time 56.89 seconds
Started Aug 27 05:05:14 AM UTC 24
Finished Aug 27 05:06:12 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998463549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.998463549
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_smoke.3253797409
Short name T894
Test name
Test status
Simulation time 651937348 ps
CPU time 4.32 seconds
Started Aug 27 05:04:53 AM UTC 24
Finished Aug 27 05:04:58 AM UTC 24
Peak memory 208168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253797409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3253797409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_stress_all.2870715928
Short name T1177
Test name
Test status
Simulation time 35432609065 ps
CPU time 913.77 seconds
Started Aug 27 05:05:29 AM UTC 24
Finished Aug 27 05:20:53 AM UTC 24
Peak memory 212240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870715928 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2870715928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.3371236759
Short name T916
Test name
Test status
Simulation time 4944696582 ps
CPU time 37.45 seconds
Started Aug 27 05:05:24 AM UTC 24
Finished Aug 27 05:06:03 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3371236759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all
_with_rand_reset.3371236759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.2490008967
Short name T905
Test name
Test status
Simulation time 3041746625 ps
CPU time 3.43 seconds
Started Aug 27 05:05:19 AM UTC 24
Finished Aug 27 05:05:23 AM UTC 24
Peak memory 207828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490008967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2490008967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_tx_rx.630169708
Short name T935
Test name
Test status
Simulation time 66621374060 ps
CPU time 126.86 seconds
Started Aug 27 05:04:56 AM UTC 24
Finished Aug 27 05:07:05 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630169708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.630169708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/49.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_alert_test.3918653964
Short name T422
Test name
Test status
Simulation time 38354064 ps
CPU time 0.84 seconds
Started Aug 27 04:38:08 AM UTC 24
Finished Aug 27 04:38:10 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918653964 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3918653964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_fifo_full.1058789865
Short name T118
Test name
Test status
Simulation time 82051406336 ps
CPU time 26.74 seconds
Started Aug 27 04:37:44 AM UTC 24
Finished Aug 27 04:38:12 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058789865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1058789865
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.2420706499
Short name T111
Test name
Test status
Simulation time 16958858721 ps
CPU time 56.33 seconds
Started Aug 27 04:37:44 AM UTC 24
Finished Aug 27 04:38:42 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420706499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2420706499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_fifo_reset.2547969447
Short name T88
Test name
Test status
Simulation time 138666765962 ps
CPU time 278.27 seconds
Started Aug 27 04:37:44 AM UTC 24
Finished Aug 27 04:42:26 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547969447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2547969447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.863821033
Short name T286
Test name
Test status
Simulation time 44974446802 ps
CPU time 190.32 seconds
Started Aug 27 04:38:03 AM UTC 24
Finished Aug 27 04:41:17 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863821033 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.863821033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_loopback.405931757
Short name T420
Test name
Test status
Simulation time 234652961 ps
CPU time 1.04 seconds
Started Aug 27 04:38:02 AM UTC 24
Finished Aug 27 04:38:05 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405931757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.uart_loopback.405931757
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_noise_filter.2041260711
Short name T106
Test name
Test status
Simulation time 17145943298 ps
CPU time 13.31 seconds
Started Aug 27 04:37:53 AM UTC 24
Finished Aug 27 04:38:07 AM UTC 24
Peak memory 207964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041260711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2041260711
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_perf.559600249
Short name T264
Test name
Test status
Simulation time 9154051907 ps
CPU time 94.26 seconds
Started Aug 27 04:38:03 AM UTC 24
Finished Aug 27 04:39:40 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559600249 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.559600249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_rx_oversample.2097364488
Short name T421
Test name
Test status
Simulation time 4099653459 ps
CPU time 21.1 seconds
Started Aug 27 04:37:46 AM UTC 24
Finished Aug 27 04:38:09 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097364488 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2097364488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.2075681104
Short name T112
Test name
Test status
Simulation time 26600562584 ps
CPU time 33.29 seconds
Started Aug 27 04:37:57 AM UTC 24
Finished Aug 27 04:38:31 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075681104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2075681104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.18070042
Short name T288
Test name
Test status
Simulation time 4528812024 ps
CPU time 2.5 seconds
Started Aug 27 04:37:53 AM UTC 24
Finished Aug 27 04:37:56 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18070042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.18070042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_smoke.833023593
Short name T328
Test name
Test status
Simulation time 886390193 ps
CPU time 3.29 seconds
Started Aug 27 04:37:42 AM UTC 24
Finished Aug 27 04:37:46 AM UTC 24
Peak memory 207096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833023593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.uart_smoke.833023593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_stress_all.1353726428
Short name T113
Test name
Test status
Simulation time 491569114955 ps
CPU time 125.44 seconds
Started Aug 27 04:38:05 AM UTC 24
Finished Aug 27 04:40:13 AM UTC 24
Peak memory 217868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353726428 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1353726428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.85808312
Short name T35
Test name
Test status
Simulation time 7525051111 ps
CPU time 51.92 seconds
Started Aug 27 04:38:03 AM UTC 24
Finished Aug 27 04:38:58 AM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=85808312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_wi
th_rand_reset.85808312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.113418889
Short name T44
Test name
Test status
Simulation time 678109101 ps
CPU time 2.59 seconds
Started Aug 27 04:37:58 AM UTC 24
Finished Aug 27 04:38:02 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113418889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.113418889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/5.uart_tx_rx.831308699
Short name T381
Test name
Test status
Simulation time 17209759452 ps
CPU time 18.23 seconds
Started Aug 27 04:37:42 AM UTC 24
Finished Aug 27 04:38:01 AM UTC 24
Peak memory 208548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831308699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.831308699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/5.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/50.uart_fifo_reset.4270786325
Short name T920
Test name
Test status
Simulation time 50275738554 ps
CPU time 43.27 seconds
Started Aug 27 05:05:36 AM UTC 24
Finished Aug 27 05:06:20 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270786325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.4270786325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/50.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.500917550
Short name T917
Test name
Test status
Simulation time 3128683180 ps
CPU time 29.48 seconds
Started Aug 27 05:05:37 AM UTC 24
Finished Aug 27 05:06:07 AM UTC 24
Peak memory 217744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=500917550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all_
with_rand_reset.500917550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/51.uart_fifo_reset.3460039020
Short name T919
Test name
Test status
Simulation time 87246352435 ps
CPU time 33.7 seconds
Started Aug 27 05:05:41 AM UTC 24
Finished Aug 27 05:06:16 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460039020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3460039020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/51.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.3186893369
Short name T924
Test name
Test status
Simulation time 2208936924 ps
CPU time 38.45 seconds
Started Aug 27 05:05:52 AM UTC 24
Finished Aug 27 05:06:32 AM UTC 24
Peak memory 217736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3186893369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all
_with_rand_reset.3186893369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/52.uart_fifo_reset.1812121506
Short name T933
Test name
Test status
Simulation time 24768781885 ps
CPU time 63.38 seconds
Started Aug 27 05:05:53 AM UTC 24
Finished Aug 27 05:06:58 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812121506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1812121506
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/52.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.1037491009
Short name T206
Test name
Test status
Simulation time 3947896077 ps
CPU time 33.59 seconds
Started Aug 27 05:05:55 AM UTC 24
Finished Aug 27 05:06:30 AM UTC 24
Peak memory 209032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1037491009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all
_with_rand_reset.1037491009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/53.uart_fifo_reset.1398218132
Short name T923
Test name
Test status
Simulation time 36836669221 ps
CPU time 31.16 seconds
Started Aug 27 05:05:55 AM UTC 24
Finished Aug 27 05:06:28 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398218132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1398218132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/53.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.1819582159
Short name T922
Test name
Test status
Simulation time 8683221538 ps
CPU time 24.84 seconds
Started Aug 27 05:05:59 AM UTC 24
Finished Aug 27 05:06:25 AM UTC 24
Peak memory 217944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1819582159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all
_with_rand_reset.1819582159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/54.uart_fifo_reset.4102689541
Short name T940
Test name
Test status
Simulation time 18166702607 ps
CPU time 69.67 seconds
Started Aug 27 05:06:04 AM UTC 24
Finished Aug 27 05:07:16 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102689541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.4102689541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/54.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.302971838
Short name T921
Test name
Test status
Simulation time 1919948907 ps
CPU time 14.08 seconds
Started Aug 27 05:06:08 AM UTC 24
Finished Aug 27 05:06:24 AM UTC 24
Peak memory 217464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=302971838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all_
with_rand_reset.302971838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/55.uart_fifo_reset.2530301627
Short name T930
Test name
Test status
Simulation time 20135026150 ps
CPU time 34.46 seconds
Started Aug 27 05:06:13 AM UTC 24
Finished Aug 27 05:06:48 AM UTC 24
Peak memory 208508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530301627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2530301627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/55.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/56.uart_fifo_reset.2979166446
Short name T999
Test name
Test status
Simulation time 362289654906 ps
CPU time 196.29 seconds
Started Aug 27 05:06:21 AM UTC 24
Finished Aug 27 05:09:40 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979166446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2979166446
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/56.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/57.uart_fifo_reset.1430256170
Short name T974
Test name
Test status
Simulation time 81744331702 ps
CPU time 131.69 seconds
Started Aug 27 05:06:26 AM UTC 24
Finished Aug 27 05:08:40 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430256170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1430256170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/57.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.3679039070
Short name T932
Test name
Test status
Simulation time 15027647980 ps
CPU time 28.6 seconds
Started Aug 27 05:06:28 AM UTC 24
Finished Aug 27 05:06:58 AM UTC 24
Peak memory 223940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3679039070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all
_with_rand_reset.3679039070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.1739141862
Short name T938
Test name
Test status
Simulation time 4933994395 ps
CPU time 40.01 seconds
Started Aug 27 05:06:32 AM UTC 24
Finished Aug 27 05:07:14 AM UTC 24
Peak memory 223956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1739141862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all
_with_rand_reset.1739141862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/59.uart_fifo_reset.2716085481
Short name T252
Test name
Test status
Simulation time 86985993352 ps
CPU time 130.91 seconds
Started Aug 27 05:06:33 AM UTC 24
Finished Aug 27 05:08:46 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716085481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2716085481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/59.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.1712668807
Short name T934
Test name
Test status
Simulation time 1678144362 ps
CPU time 25.16 seconds
Started Aug 27 05:06:35 AM UTC 24
Finished Aug 27 05:07:02 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1712668807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all
_with_rand_reset.1712668807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_alert_test.3021292943
Short name T424
Test name
Test status
Simulation time 24598732 ps
CPU time 0.76 seconds
Started Aug 27 04:38:59 AM UTC 24
Finished Aug 27 04:39:00 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021292943 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3021292943
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.2376757132
Short name T115
Test name
Test status
Simulation time 19732448405 ps
CPU time 36.64 seconds
Started Aug 27 04:38:13 AM UTC 24
Finished Aug 27 04:38:51 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376757132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2376757132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_intr.3191692741
Short name T309
Test name
Test status
Simulation time 13751618129 ps
CPU time 50.94 seconds
Started Aug 27 04:38:32 AM UTC 24
Finished Aug 27 04:39:24 AM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191692741 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3191692741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.3763770849
Short name T334
Test name
Test status
Simulation time 52146110900 ps
CPU time 339.69 seconds
Started Aug 27 04:38:42 AM UTC 24
Finished Aug 27 04:44:26 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763770849 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3763770849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_loopback.1806368005
Short name T423
Test name
Test status
Simulation time 7128667884 ps
CPU time 16.59 seconds
Started Aug 27 04:38:40 AM UTC 24
Finished Aug 27 04:38:58 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806368005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1806368005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_noise_filter.3146438623
Short name T281
Test name
Test status
Simulation time 44114116301 ps
CPU time 116.23 seconds
Started Aug 27 04:38:32 AM UTC 24
Finished Aug 27 04:40:30 AM UTC 24
Peak memory 207624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146438623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3146438623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_rx_oversample.171039384
Short name T389
Test name
Test status
Simulation time 6440649514 ps
CPU time 71.09 seconds
Started Aug 27 04:38:27 AM UTC 24
Finished Aug 27 04:39:40 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171039384 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.171039384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.31239921
Short name T270
Test name
Test status
Simulation time 124274664804 ps
CPU time 53.19 seconds
Started Aug 27 04:38:36 AM UTC 24
Finished Aug 27 04:39:31 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31239921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.31239921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.1601328844
Short name T347
Test name
Test status
Simulation time 6016933009 ps
CPU time 4.49 seconds
Started Aug 27 04:38:34 AM UTC 24
Finished Aug 27 04:38:40 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601328844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1601328844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_smoke.2711608571
Short name T298
Test name
Test status
Simulation time 5634984904 ps
CPU time 15.33 seconds
Started Aug 27 04:38:09 AM UTC 24
Finished Aug 27 04:38:26 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711608571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2711608571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.238196193
Short name T36
Test name
Test status
Simulation time 7665000182 ps
CPU time 20.13 seconds
Started Aug 27 04:38:52 AM UTC 24
Finished Aug 27 04:39:13 AM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=238196193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_w
ith_rand_reset.238196193
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.2006115712
Short name T296
Test name
Test status
Simulation time 6711741199 ps
CPU time 12.71 seconds
Started Aug 27 04:38:38 AM UTC 24
Finished Aug 27 04:38:52 AM UTC 24
Peak memory 208516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006115712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2006115712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/6.uart_tx_rx.3234862632
Short name T263
Test name
Test status
Simulation time 13625595763 ps
CPU time 20.72 seconds
Started Aug 27 04:38:11 AM UTC 24
Finished Aug 27 04:38:33 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234862632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3234862632
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/6.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/60.uart_fifo_reset.972260182
Short name T222
Test name
Test status
Simulation time 8874590556 ps
CPU time 16.22 seconds
Started Aug 27 05:06:36 AM UTC 24
Finished Aug 27 05:06:54 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972260182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.972260182
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/60.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.582994615
Short name T945
Test name
Test status
Simulation time 12673961815 ps
CPU time 49.64 seconds
Started Aug 27 05:06:39 AM UTC 24
Finished Aug 27 05:07:30 AM UTC 24
Peak memory 219992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=582994615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all_
with_rand_reset.582994615
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/61.uart_fifo_reset.2363496493
Short name T1171
Test name
Test status
Simulation time 247507151765 ps
CPU time 610.59 seconds
Started Aug 27 05:06:41 AM UTC 24
Finished Aug 27 05:16:58 AM UTC 24
Peak memory 212352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363496493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2363496493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/61.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.3632551666
Short name T941
Test name
Test status
Simulation time 3274806773 ps
CPU time 39.75 seconds
Started Aug 27 05:06:41 AM UTC 24
Finished Aug 27 05:07:22 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3632551666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all
_with_rand_reset.3632551666
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/62.uart_fifo_reset.3939049987
Short name T947
Test name
Test status
Simulation time 260032982268 ps
CPU time 52.61 seconds
Started Aug 27 05:06:47 AM UTC 24
Finished Aug 27 05:07:41 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939049987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3939049987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/62.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.2484911053
Short name T214
Test name
Test status
Simulation time 3698378661 ps
CPU time 27.99 seconds
Started Aug 27 05:06:49 AM UTC 24
Finished Aug 27 05:07:18 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2484911053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all
_with_rand_reset.2484911053
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/63.uart_fifo_reset.679007299
Short name T200
Test name
Test status
Simulation time 18606108129 ps
CPU time 67.06 seconds
Started Aug 27 05:06:52 AM UTC 24
Finished Aug 27 05:08:01 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679007299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.679007299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/63.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.3894574503
Short name T953
Test name
Test status
Simulation time 4808932364 ps
CPU time 57.88 seconds
Started Aug 27 05:06:55 AM UTC 24
Finished Aug 27 05:07:55 AM UTC 24
Peak memory 223940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3894574503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all
_with_rand_reset.3894574503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/64.uart_fifo_reset.1523092408
Short name T223
Test name
Test status
Simulation time 67757106181 ps
CPU time 54.73 seconds
Started Aug 27 05:06:58 AM UTC 24
Finished Aug 27 05:07:55 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523092408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1523092408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/64.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.4253019411
Short name T943
Test name
Test status
Simulation time 8779373957 ps
CPU time 24.5 seconds
Started Aug 27 05:06:59 AM UTC 24
Finished Aug 27 05:07:25 AM UTC 24
Peak memory 224440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4253019411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all
_with_rand_reset.4253019411
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/65.uart_fifo_reset.2584743849
Short name T960
Test name
Test status
Simulation time 98133376705 ps
CPU time 69.5 seconds
Started Aug 27 05:07:02 AM UTC 24
Finished Aug 27 05:08:14 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584743849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2584743849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/65.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.2452211136
Short name T939
Test name
Test status
Simulation time 714282937 ps
CPU time 7.31 seconds
Started Aug 27 05:07:06 AM UTC 24
Finished Aug 27 05:07:14 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2452211136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all
_with_rand_reset.2452211136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/66.uart_fifo_reset.2059312762
Short name T976
Test name
Test status
Simulation time 246223164771 ps
CPU time 95.42 seconds
Started Aug 27 05:07:06 AM UTC 24
Finished Aug 27 05:08:43 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059312762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2059312762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/66.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.522565829
Short name T946
Test name
Test status
Simulation time 5343832618 ps
CPU time 22.31 seconds
Started Aug 27 05:07:07 AM UTC 24
Finished Aug 27 05:07:30 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=522565829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all_
with_rand_reset.522565829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/67.uart_fifo_reset.3043676105
Short name T988
Test name
Test status
Simulation time 113396533962 ps
CPU time 120.33 seconds
Started Aug 27 05:07:13 AM UTC 24
Finished Aug 27 05:09:15 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043676105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3043676105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/67.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.1517867011
Short name T949
Test name
Test status
Simulation time 2147637895 ps
CPU time 30.96 seconds
Started Aug 27 05:07:15 AM UTC 24
Finished Aug 27 05:07:47 AM UTC 24
Peak memory 217536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1517867011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all
_with_rand_reset.1517867011
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/68.uart_fifo_reset.3368081865
Short name T1044
Test name
Test status
Simulation time 119651383455 ps
CPU time 271.14 seconds
Started Aug 27 05:07:15 AM UTC 24
Finished Aug 27 05:11:50 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368081865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3368081865
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/68.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.3541549757
Short name T970
Test name
Test status
Simulation time 15525036727 ps
CPU time 72.7 seconds
Started Aug 27 05:07:17 AM UTC 24
Finished Aug 27 05:08:31 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3541549757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all
_with_rand_reset.3541549757
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/69.uart_fifo_reset.880656588
Short name T189
Test name
Test status
Simulation time 30857790550 ps
CPU time 39.94 seconds
Started Aug 27 05:07:19 AM UTC 24
Finished Aug 27 05:08:01 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880656588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.880656588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/69.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.3156432175
Short name T951
Test name
Test status
Simulation time 13831150782 ps
CPU time 27.1 seconds
Started Aug 27 05:07:22 AM UTC 24
Finished Aug 27 05:07:51 AM UTC 24
Peak memory 225632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3156432175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all
_with_rand_reset.3156432175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_alert_test.2514317829
Short name T426
Test name
Test status
Simulation time 34760204 ps
CPU time 0.82 seconds
Started Aug 27 04:39:30 AM UTC 24
Finished Aug 27 04:39:32 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514317829 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2514317829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.732105837
Short name T123
Test name
Test status
Simulation time 85025823449 ps
CPU time 136.2 seconds
Started Aug 27 04:39:02 AM UTC 24
Finished Aug 27 04:41:21 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732105837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.732105837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_loopback.1796744279
Short name T390
Test name
Test status
Simulation time 7676027171 ps
CPU time 5.54 seconds
Started Aug 27 04:39:23 AM UTC 24
Finished Aug 27 04:39:29 AM UTC 24
Peak memory 208552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796744279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1796744279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_noise_filter.1966181410
Short name T304
Test name
Test status
Simulation time 32894020591 ps
CPU time 72.81 seconds
Started Aug 27 04:39:15 AM UTC 24
Finished Aug 27 04:40:30 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966181410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1966181410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_perf.2526903011
Short name T591
Test name
Test status
Simulation time 14472663956 ps
CPU time 844.83 seconds
Started Aug 27 04:39:25 AM UTC 24
Finished Aug 27 04:53:39 AM UTC 24
Peak memory 212404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526903011 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2526903011
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_rx_oversample.668500961
Short name T425
Test name
Test status
Simulation time 7548687569 ps
CPU time 14.14 seconds
Started Aug 27 04:39:12 AM UTC 24
Finished Aug 27 04:39:27 AM UTC 24
Peak memory 207972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668500961 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.668500961
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.2511387299
Short name T117
Test name
Test status
Simulation time 59854311335 ps
CPU time 34.31 seconds
Started Aug 27 04:39:19 AM UTC 24
Finished Aug 27 04:39:54 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511387299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2511387299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.2664069913
Short name T297
Test name
Test status
Simulation time 622212771 ps
CPU time 1.29 seconds
Started Aug 27 04:39:17 AM UTC 24
Finished Aug 27 04:39:20 AM UTC 24
Peak memory 204432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664069913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2664069913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_smoke.1529052762
Short name T47
Test name
Test status
Simulation time 564006621 ps
CPU time 1.85 seconds
Started Aug 27 04:38:59 AM UTC 24
Finished Aug 27 04:39:02 AM UTC 24
Peak memory 207116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529052762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1529052762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_stress_all.771660555
Short name T638
Test name
Test status
Simulation time 429428572892 ps
CPU time 989.99 seconds
Started Aug 27 04:39:28 AM UTC 24
Finished Aug 27 04:56:08 AM UTC 24
Peak memory 212144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771660555 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.771660555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.1315529318
Short name T38
Test name
Test status
Simulation time 7735422784 ps
CPU time 89.51 seconds
Started Aug 27 04:39:27 AM UTC 24
Finished Aug 27 04:40:58 AM UTC 24
Peak memory 219840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1315529318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_
with_rand_reset.1315529318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.81828366
Short name T272
Test name
Test status
Simulation time 896922947 ps
CPU time 4.41 seconds
Started Aug 27 04:39:21 AM UTC 24
Finished Aug 27 04:39:26 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81828366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.81828366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/7.uart_tx_rx.2764382296
Short name T383
Test name
Test status
Simulation time 37012043137 ps
CPU time 22.38 seconds
Started Aug 27 04:39:01 AM UTC 24
Finished Aug 27 04:39:24 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764382296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2764382296
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/7.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/70.uart_fifo_reset.2354318286
Short name T219
Test name
Test status
Simulation time 41544030115 ps
CPU time 76.13 seconds
Started Aug 27 05:07:25 AM UTC 24
Finished Aug 27 05:08:43 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354318286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2354318286
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/70.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.2121129991
Short name T950
Test name
Test status
Simulation time 4487447683 ps
CPU time 20.24 seconds
Started Aug 27 05:07:25 AM UTC 24
Finished Aug 27 05:07:48 AM UTC 24
Peak memory 217664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2121129991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all
_with_rand_reset.2121129991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/71.uart_fifo_reset.2845228836
Short name T959
Test name
Test status
Simulation time 20582651908 ps
CPU time 38.99 seconds
Started Aug 27 05:07:27 AM UTC 24
Finished Aug 27 05:08:07 AM UTC 24
Peak memory 208192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845228836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2845228836
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/71.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.3011918552
Short name T957
Test name
Test status
Simulation time 11890841285 ps
CPU time 30.67 seconds
Started Aug 27 05:07:29 AM UTC 24
Finished Aug 27 05:08:01 AM UTC 24
Peak memory 224292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3011918552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all
_with_rand_reset.3011918552
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/72.uart_fifo_reset.3648215370
Short name T191
Test name
Test status
Simulation time 248995594802 ps
CPU time 57.87 seconds
Started Aug 27 05:07:31 AM UTC 24
Finished Aug 27 05:08:30 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648215370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3648215370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/72.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.3835417843
Short name T969
Test name
Test status
Simulation time 6088353149 ps
CPU time 43.25 seconds
Started Aug 27 05:07:45 AM UTC 24
Finished Aug 27 05:08:30 AM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3835417843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all
_with_rand_reset.3835417843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/74.uart_fifo_reset.2793679297
Short name T975
Test name
Test status
Simulation time 91896137051 ps
CPU time 52.55 seconds
Started Aug 27 05:07:47 AM UTC 24
Finished Aug 27 05:08:41 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793679297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2793679297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/74.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.4074048869
Short name T961
Test name
Test status
Simulation time 4937927192 ps
CPU time 24.25 seconds
Started Aug 27 05:07:48 AM UTC 24
Finished Aug 27 05:08:14 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4074048869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all
_with_rand_reset.4074048869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/76.uart_fifo_reset.935624419
Short name T963
Test name
Test status
Simulation time 15436287735 ps
CPU time 21.9 seconds
Started Aug 27 05:07:52 AM UTC 24
Finished Aug 27 05:08:16 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935624419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.935624419
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/76.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.2119649798
Short name T977
Test name
Test status
Simulation time 9777724333 ps
CPU time 45.91 seconds
Started Aug 27 05:07:56 AM UTC 24
Finished Aug 27 05:08:43 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2119649798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all
_with_rand_reset.2119649798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/77.uart_fifo_reset.734716144
Short name T186
Test name
Test status
Simulation time 18603420488 ps
CPU time 31.81 seconds
Started Aug 27 05:07:56 AM UTC 24
Finished Aug 27 05:08:29 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734716144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.734716144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/77.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.3502095683
Short name T980
Test name
Test status
Simulation time 27120072759 ps
CPU time 46.1 seconds
Started Aug 27 05:08:00 AM UTC 24
Finished Aug 27 05:08:48 AM UTC 24
Peak memory 225344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3502095683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all
_with_rand_reset.3502095683
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/78.uart_fifo_reset.2117360062
Short name T971
Test name
Test status
Simulation time 10597115020 ps
CPU time 33.01 seconds
Started Aug 27 05:08:01 AM UTC 24
Finished Aug 27 05:08:35 AM UTC 24
Peak memory 208380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117360062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2117360062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/78.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.4213417569
Short name T978
Test name
Test status
Simulation time 961904838 ps
CPU time 41.36 seconds
Started Aug 27 05:08:01 AM UTC 24
Finished Aug 27 05:08:44 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4213417569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all
_with_rand_reset.4213417569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/79.uart_fifo_reset.1982819506
Short name T989
Test name
Test status
Simulation time 148086935811 ps
CPU time 72.77 seconds
Started Aug 27 05:08:01 AM UTC 24
Finished Aug 27 05:09:15 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982819506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1982819506
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/79.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.1573145134
Short name T965
Test name
Test status
Simulation time 6159126866 ps
CPU time 20.86 seconds
Started Aug 27 05:08:02 AM UTC 24
Finished Aug 27 05:08:24 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1573145134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all
_with_rand_reset.1573145134
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_alert_test.2966284585
Short name T428
Test name
Test status
Simulation time 13658781 ps
CPU time 0.87 seconds
Started Aug 27 04:40:14 AM UTC 24
Finished Aug 27 04:40:16 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966284585 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2966284585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_fifo_full.3212483726
Short name T511
Test name
Test status
Simulation time 89131365810 ps
CPU time 533.35 seconds
Started Aug 27 04:39:33 AM UTC 24
Finished Aug 27 04:48:33 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212483726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3212483726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.3918930089
Short name T129
Test name
Test status
Simulation time 73028526338 ps
CPU time 31.21 seconds
Started Aug 27 04:39:34 AM UTC 24
Finished Aug 27 04:40:07 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918930089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3918930089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_fifo_reset.566115958
Short name T110
Test name
Test status
Simulation time 70455179285 ps
CPU time 56.45 seconds
Started Aug 27 04:39:38 AM UTC 24
Finished Aug 27 04:40:35 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566115958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.566115958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_intr.2518667939
Short name T94
Test name
Test status
Simulation time 143383928767 ps
CPU time 73.88 seconds
Started Aug 27 04:39:41 AM UTC 24
Finished Aug 27 04:40:57 AM UTC 24
Peak memory 207088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518667939 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2518667939
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.1473635001
Short name T265
Test name
Test status
Simulation time 246404195504 ps
CPU time 157.83 seconds
Started Aug 27 04:40:06 AM UTC 24
Finished Aug 27 04:42:47 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473635001 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1473635001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_loopback.2484793234
Short name T427
Test name
Test status
Simulation time 722043230 ps
CPU time 2.88 seconds
Started Aug 27 04:40:01 AM UTC 24
Finished Aug 27 04:40:05 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484793234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2484793234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_noise_filter.956387822
Short name T293
Test name
Test status
Simulation time 91885477389 ps
CPU time 144.7 seconds
Started Aug 27 04:39:54 AM UTC 24
Finished Aug 27 04:42:21 AM UTC 24
Peak memory 208588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956387822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.956387822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_perf.1351960343
Short name T454
Test name
Test status
Simulation time 16898080614 ps
CPU time 225.83 seconds
Started Aug 27 04:40:03 AM UTC 24
Finished Aug 27 04:43:52 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351960343 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1351960343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_rx_oversample.1404325818
Short name T429
Test name
Test status
Simulation time 4142973492 ps
CPU time 52.47 seconds
Started Aug 27 04:39:41 AM UTC 24
Finished Aug 27 04:40:35 AM UTC 24
Peak memory 208100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404325818 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1404325818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.1166996856
Short name T308
Test name
Test status
Simulation time 43022125395 ps
CPU time 36.92 seconds
Started Aug 27 04:39:55 AM UTC 24
Finished Aug 27 04:40:33 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166996856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1166996856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.1841952144
Short name T353
Test name
Test status
Simulation time 5111412185 ps
CPU time 4 seconds
Started Aug 27 04:39:55 AM UTC 24
Finished Aug 27 04:40:00 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841952144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1841952144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_smoke.1306436694
Short name T291
Test name
Test status
Simulation time 512752060 ps
CPU time 1.9 seconds
Started Aug 27 04:39:30 AM UTC 24
Finished Aug 27 04:39:33 AM UTC 24
Peak memory 207700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306436694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1306436694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_stress_all.1071213900
Short name T114
Test name
Test status
Simulation time 23515916799 ps
CPU time 46.66 seconds
Started Aug 27 04:40:07 AM UTC 24
Finished Aug 27 04:40:56 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071213900 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1071213900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.663985625
Short name T37
Test name
Test status
Simulation time 1394198997 ps
CPU time 25.87 seconds
Started Aug 27 04:40:07 AM UTC 24
Finished Aug 27 04:40:35 AM UTC 24
Peak memory 217792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=663985625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_w
ith_rand_reset.663985625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.2087105891
Short name T319
Test name
Test status
Simulation time 1581886945 ps
CPU time 4.56 seconds
Started Aug 27 04:39:57 AM UTC 24
Finished Aug 27 04:40:03 AM UTC 24
Peak memory 208580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087105891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2087105891
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/8.uart_tx_rx.4006992655
Short name T276
Test name
Test status
Simulation time 70835480399 ps
CPU time 183.69 seconds
Started Aug 27 04:39:31 AM UTC 24
Finished Aug 27 04:42:38 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006992655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.4006992655
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/8.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/80.uart_fifo_reset.707956045
Short name T967
Test name
Test status
Simulation time 33266011218 ps
CPU time 24.96 seconds
Started Aug 27 05:08:02 AM UTC 24
Finished Aug 27 05:08:28 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707956045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.707956045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/80.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2951080327
Short name T964
Test name
Test status
Simulation time 830117689 ps
CPU time 11.52 seconds
Started Aug 27 05:08:03 AM UTC 24
Finished Aug 27 05:08:16 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2951080327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all
_with_rand_reset.2951080327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.2505628823
Short name T972
Test name
Test status
Simulation time 12562380075 ps
CPU time 30.78 seconds
Started Aug 27 05:08:07 AM UTC 24
Finished Aug 27 05:08:39 AM UTC 24
Peak memory 219896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2505628823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all
_with_rand_reset.2505628823
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/82.uart_fifo_reset.3251699824
Short name T1057
Test name
Test status
Simulation time 117110545130 ps
CPU time 244.66 seconds
Started Aug 27 05:08:08 AM UTC 24
Finished Aug 27 05:12:16 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251699824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3251699824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/82.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.265286306
Short name T968
Test name
Test status
Simulation time 6858192379 ps
CPU time 12.65 seconds
Started Aug 27 05:08:15 AM UTC 24
Finished Aug 27 05:08:28 AM UTC 24
Peak memory 219756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=265286306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all_
with_rand_reset.265286306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/83.uart_fifo_reset.302391036
Short name T207
Test name
Test status
Simulation time 25493216060 ps
CPU time 26.59 seconds
Started Aug 27 05:08:15 AM UTC 24
Finished Aug 27 05:08:42 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302391036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.302391036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/83.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.751375563
Short name T987
Test name
Test status
Simulation time 13846777164 ps
CPU time 50.11 seconds
Started Aug 27 05:08:17 AM UTC 24
Finished Aug 27 05:09:08 AM UTC 24
Peak memory 219776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=751375563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all_
with_rand_reset.751375563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/84.uart_fifo_reset.1007341764
Short name T406
Test name
Test status
Simulation time 56403198975 ps
CPU time 60.68 seconds
Started Aug 27 05:08:17 AM UTC 24
Finished Aug 27 05:09:19 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007341764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1007341764
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/84.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.1083544618
Short name T224
Test name
Test status
Simulation time 6527301114 ps
CPU time 33.43 seconds
Started Aug 27 05:08:17 AM UTC 24
Finished Aug 27 05:08:52 AM UTC 24
Peak memory 217816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1083544618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all
_with_rand_reset.1083544618
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/85.uart_fifo_reset.3681265845
Short name T983
Test name
Test status
Simulation time 261871065374 ps
CPU time 36.25 seconds
Started Aug 27 05:08:19 AM UTC 24
Finished Aug 27 05:08:57 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681265845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3681265845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/85.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.4105118577
Short name T986
Test name
Test status
Simulation time 6159742426 ps
CPU time 42.71 seconds
Started Aug 27 05:08:24 AM UTC 24
Finished Aug 27 05:09:08 AM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4105118577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all
_with_rand_reset.4105118577
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3689579091
Short name T218
Test name
Test status
Simulation time 71937841084 ps
CPU time 178.59 seconds
Started Aug 27 05:08:25 AM UTC 24
Finished Aug 27 05:11:27 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689579091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3689579091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/86.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.3214472438
Short name T995
Test name
Test status
Simulation time 6270005401 ps
CPU time 57.76 seconds
Started Aug 27 05:08:28 AM UTC 24
Finished Aug 27 05:09:28 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3214472438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all
_with_rand_reset.3214472438
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/87.uart_fifo_reset.3145367546
Short name T1016
Test name
Test status
Simulation time 82677181615 ps
CPU time 113.35 seconds
Started Aug 27 05:08:29 AM UTC 24
Finished Aug 27 05:10:25 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145367546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3145367546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/87.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.1252130991
Short name T1004
Test name
Test status
Simulation time 15715264691 ps
CPU time 80.58 seconds
Started Aug 27 05:08:29 AM UTC 24
Finished Aug 27 05:09:52 AM UTC 24
Peak memory 217516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1252130991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all
_with_rand_reset.1252130991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/88.uart_fifo_reset.1332770145
Short name T981
Test name
Test status
Simulation time 17576908786 ps
CPU time 20.21 seconds
Started Aug 27 05:08:30 AM UTC 24
Finished Aug 27 05:08:51 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332770145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1332770145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/88.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.3768322617
Short name T992
Test name
Test status
Simulation time 1994870435 ps
CPU time 52.09 seconds
Started Aug 27 05:08:31 AM UTC 24
Finished Aug 27 05:09:24 AM UTC 24
Peak memory 219664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3768322617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all
_with_rand_reset.3768322617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/89.uart_fifo_reset.4272361752
Short name T208
Test name
Test status
Simulation time 36523536906 ps
CPU time 19.77 seconds
Started Aug 27 05:08:31 AM UTC 24
Finished Aug 27 05:08:52 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272361752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.4272361752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/89.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.3007018800
Short name T982
Test name
Test status
Simulation time 3524369966 ps
CPU time 19.34 seconds
Started Aug 27 05:08:33 AM UTC 24
Finished Aug 27 05:08:53 AM UTC 24
Peak memory 217592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3007018800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all
_with_rand_reset.3007018800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_alert_test.2015681600
Short name T432
Test name
Test status
Simulation time 49697678 ps
CPU time 0.81 seconds
Started Aug 27 04:40:50 AM UTC 24
Finished Aug 27 04:40:51 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015681600 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2015681600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_fifo_full.1790972715
Short name T312
Test name
Test status
Simulation time 173855748841 ps
CPU time 296.32 seconds
Started Aug 27 04:40:22 AM UTC 24
Finished Aug 27 04:45:21 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790972715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1790972715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.3535347256
Short name T338
Test name
Test status
Simulation time 112104077092 ps
CPU time 206.21 seconds
Started Aug 27 04:40:24 AM UTC 24
Finished Aug 27 04:43:53 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535347256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3535347256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_intr.3472956220
Short name T95
Test name
Test status
Simulation time 44267786518 ps
CPU time 46.33 seconds
Started Aug 27 04:40:31 AM UTC 24
Finished Aug 27 04:41:19 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472956220 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3472956220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.1691905047
Short name T500
Test name
Test status
Simulation time 165437450758 ps
CPU time 422.18 seconds
Started Aug 27 04:40:46 AM UTC 24
Finished Aug 27 04:47:54 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691905047 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1691905047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_loopback.2293577142
Short name T431
Test name
Test status
Simulation time 4527159287 ps
CPU time 7.6 seconds
Started Aug 27 04:40:40 AM UTC 24
Finished Aug 27 04:40:49 AM UTC 24
Peak memory 207632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293577142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2293577142
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_noise_filter.491012972
Short name T373
Test name
Test status
Simulation time 3995024262 ps
CPU time 15.86 seconds
Started Aug 27 04:40:34 AM UTC 24
Finished Aug 27 04:40:51 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491012972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.491012972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_rx_oversample.2515149143
Short name T430
Test name
Test status
Simulation time 7194298413 ps
CPU time 14.69 seconds
Started Aug 27 04:40:31 AM UTC 24
Finished Aug 27 04:40:47 AM UTC 24
Peak memory 207472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515149143 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2515149143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.1949350067
Short name T128
Test name
Test status
Simulation time 27370995257 ps
CPU time 47.99 seconds
Started Aug 27 04:40:36 AM UTC 24
Finished Aug 27 04:41:26 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949350067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1949350067
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.2076281220
Short name T354
Test name
Test status
Simulation time 1457185832 ps
CPU time 3.33 seconds
Started Aug 27 04:40:35 AM UTC 24
Finished Aug 27 04:40:39 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076281220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2076281220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_smoke.2968231318
Short name T258
Test name
Test status
Simulation time 244784894 ps
CPU time 1.97 seconds
Started Aug 27 04:40:17 AM UTC 24
Finished Aug 27 04:40:20 AM UTC 24
Peak memory 206248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968231318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2968231318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_stress_all.221647689
Short name T124
Test name
Test status
Simulation time 99775578198 ps
CPU time 55.82 seconds
Started Aug 27 04:40:50 AM UTC 24
Finished Aug 27 04:41:47 AM UTC 24
Peak memory 208748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221647689 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.221647689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.1934928199
Short name T39
Test name
Test status
Simulation time 8463674203 ps
CPU time 32.1 seconds
Started Aug 27 04:40:47 AM UTC 24
Finished Aug 27 04:41:21 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1934928199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_
with_rand_reset.1934928199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.2671897640
Short name T329
Test name
Test status
Simulation time 1406702967 ps
CPU time 8.96 seconds
Started Aug 27 04:40:36 AM UTC 24
Finished Aug 27 04:40:46 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671897640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2671897640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/9.uart_tx_rx.4057727476
Short name T292
Test name
Test status
Simulation time 79643541700 ps
CPU time 41.14 seconds
Started Aug 27 04:40:19 AM UTC 24
Finished Aug 27 04:41:01 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057727476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.4057727476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/9.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/90.uart_fifo_reset.2801301579
Short name T1037
Test name
Test status
Simulation time 112859555335 ps
CPU time 176.76 seconds
Started Aug 27 05:08:36 AM UTC 24
Finished Aug 27 05:11:35 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801301579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2801301579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/90.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.1418034240
Short name T984
Test name
Test status
Simulation time 2348409554 ps
CPU time 17.5 seconds
Started Aug 27 05:08:40 AM UTC 24
Finished Aug 27 05:08:59 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1418034240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all
_with_rand_reset.1418034240
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/91.uart_fifo_reset.3264248127
Short name T190
Test name
Test status
Simulation time 90960898231 ps
CPU time 41.89 seconds
Started Aug 27 05:08:40 AM UTC 24
Finished Aug 27 05:09:23 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264248127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3264248127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/91.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.4030018386
Short name T985
Test name
Test status
Simulation time 1603029453 ps
CPU time 17.03 seconds
Started Aug 27 05:08:41 AM UTC 24
Finished Aug 27 05:08:59 AM UTC 24
Peak memory 217816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4030018386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all
_with_rand_reset.4030018386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/92.uart_fifo_reset.4243321114
Short name T994
Test name
Test status
Simulation time 22713614199 ps
CPU time 41.77 seconds
Started Aug 27 05:08:42 AM UTC 24
Finished Aug 27 05:09:26 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243321114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4243321114
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/92.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.91675579
Short name T1014
Test name
Test status
Simulation time 2735558856 ps
CPU time 89.94 seconds
Started Aug 27 05:08:43 AM UTC 24
Finished Aug 27 05:10:15 AM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=91675579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all_w
ith_rand_reset.91675579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.4119223650
Short name T1024
Test name
Test status
Simulation time 17353171972 ps
CPU time 113.28 seconds
Started Aug 27 05:08:45 AM UTC 24
Finished Aug 27 05:10:40 AM UTC 24
Peak memory 217744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4119223650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all
_with_rand_reset.4119223650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/94.uart_fifo_reset.674774854
Short name T246
Test name
Test status
Simulation time 41919110067 ps
CPU time 41.82 seconds
Started Aug 27 05:08:45 AM UTC 24
Finished Aug 27 05:09:28 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674774854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.674774854
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/94.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.1479008228
Short name T990
Test name
Test status
Simulation time 3228812006 ps
CPU time 33.96 seconds
Started Aug 27 05:08:45 AM UTC 24
Finished Aug 27 05:09:20 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1479008228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all
_with_rand_reset.1479008228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/95.uart_fifo_reset.2367277521
Short name T217
Test name
Test status
Simulation time 33751895566 ps
CPU time 31.91 seconds
Started Aug 27 05:08:46 AM UTC 24
Finished Aug 27 05:09:19 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367277521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2367277521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/95.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.1921691028
Short name T1032
Test name
Test status
Simulation time 13697313828 ps
CPU time 146.02 seconds
Started Aug 27 05:08:47 AM UTC 24
Finished Aug 27 05:11:15 AM UTC 24
Peak memory 221912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1921691028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all
_with_rand_reset.1921691028
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/96.uart_fifo_reset.563741354
Short name T230
Test name
Test status
Simulation time 39116972951 ps
CPU time 38.5 seconds
Started Aug 27 05:08:48 AM UTC 24
Finished Aug 27 05:09:28 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563741354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.563741354
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/96.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.1032233313
Short name T996
Test name
Test status
Simulation time 4393403006 ps
CPU time 35.39 seconds
Started Aug 27 05:08:52 AM UTC 24
Finished Aug 27 05:09:29 AM UTC 24
Peak memory 219864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1032233313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all
_with_rand_reset.1032233313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/97.uart_fifo_reset.4103999734
Short name T407
Test name
Test status
Simulation time 19147370714 ps
CPU time 46.98 seconds
Started Aug 27 05:08:52 AM UTC 24
Finished Aug 27 05:09:41 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103999734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.4103999734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/97.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.228698706
Short name T1000
Test name
Test status
Simulation time 3866921406 ps
CPU time 52.77 seconds
Started Aug 27 05:08:52 AM UTC 24
Finished Aug 27 05:09:47 AM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=228698706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all_
with_rand_reset.228698706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2803253171
Short name T165
Test name
Test status
Simulation time 252267869752 ps
CPU time 201.77 seconds
Started Aug 27 05:08:54 AM UTC 24
Finished Aug 27 05:12:19 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803253171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2803253171
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/98.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.2631063114
Short name T1006
Test name
Test status
Simulation time 6552700288 ps
CPU time 58.32 seconds
Started Aug 27 05:08:57 AM UTC 24
Finished Aug 27 05:09:57 AM UTC 24
Peak memory 225360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2631063114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all
_with_rand_reset.2631063114
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/99.uart_fifo_reset.2531146324
Short name T404
Test name
Test status
Simulation time 8196122907 ps
CPU time 27.63 seconds
Started Aug 27 05:09:00 AM UTC 24
Finished Aug 27 05:09:28 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531146324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2531146324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/99.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.3336346424
Short name T997
Test name
Test status
Simulation time 2661409969 ps
CPU time 28.48 seconds
Started Aug 27 05:09:01 AM UTC 24
Finished Aug 27 05:09:30 AM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3336346424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all
_with_rand_reset.3336346424
Directory /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest
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