| T209 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/203.uart_fifo_reset.3597607979 |
|
|
Aug 27 05:12:16 AM UTC 24 |
Aug 27 05:12:26 AM UTC 24 |
6485664123 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/198.uart_fifo_reset.2600476632 |
|
|
Aug 27 05:12:08 AM UTC 24 |
Aug 27 05:12:28 AM UTC 24 |
38360359288 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/159.uart_fifo_reset.3240954570 |
|
|
Aug 27 05:10:53 AM UTC 24 |
Aug 27 05:12:28 AM UTC 24 |
90655819571 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/171.uart_fifo_reset.3786647045 |
|
|
Aug 27 05:11:19 AM UTC 24 |
Aug 27 05:12:28 AM UTC 24 |
24441699704 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/197.uart_fifo_reset.2230367205 |
|
|
Aug 27 05:12:08 AM UTC 24 |
Aug 27 05:12:30 AM UTC 24 |
50155893580 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/196.uart_fifo_reset.2365159470 |
|
|
Aug 27 05:12:07 AM UTC 24 |
Aug 27 05:12:30 AM UTC 24 |
51905347009 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_perf.3550341026 |
|
|
Aug 27 05:05:22 AM UTC 24 |
Aug 27 05:12:31 AM UTC 24 |
14039184881 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/187.uart_fifo_reset.3588301335 |
|
|
Aug 27 05:11:52 AM UTC 24 |
Aug 27 05:12:32 AM UTC 24 |
52447916943 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/129.uart_fifo_reset.2422134213 |
|
|
Aug 27 05:09:55 AM UTC 24 |
Aug 27 05:12:35 AM UTC 24 |
111769112690 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/117.uart_fifo_reset.3316215561 |
|
|
Aug 27 05:09:29 AM UTC 24 |
Aug 27 05:12:37 AM UTC 24 |
82478182311 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/182.uart_fifo_reset.2232551029 |
|
|
Aug 27 05:11:42 AM UTC 24 |
Aug 27 05:12:38 AM UTC 24 |
82164516245 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/155.uart_fifo_reset.502437670 |
|
|
Aug 27 05:10:46 AM UTC 24 |
Aug 27 05:12:40 AM UTC 24 |
44988953532 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2773933500 |
|
|
Aug 27 05:12:17 AM UTC 24 |
Aug 27 05:12:41 AM UTC 24 |
40218802382 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/201.uart_fifo_reset.4104452119 |
|
|
Aug 27 05:12:14 AM UTC 24 |
Aug 27 05:12:44 AM UTC 24 |
23031142146 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1219629423 |
|
|
Aug 27 05:12:29 AM UTC 24 |
Aug 27 05:12:44 AM UTC 24 |
23795911775 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/200.uart_fifo_reset.3857182172 |
|
|
Aug 27 05:12:10 AM UTC 24 |
Aug 27 05:12:44 AM UTC 24 |
82163604637 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/126.uart_fifo_reset.815628136 |
|
|
Aug 27 05:09:52 AM UTC 24 |
Aug 27 05:12:51 AM UTC 24 |
126398166036 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/183.uart_fifo_reset.2310573911 |
|
|
Aug 27 05:11:46 AM UTC 24 |
Aug 27 05:12:52 AM UTC 24 |
69422582177 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/205.uart_fifo_reset.2706408111 |
|
|
Aug 27 05:12:17 AM UTC 24 |
Aug 27 05:12:54 AM UTC 24 |
19142963374 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3450677111 |
|
|
Aug 27 05:12:21 AM UTC 24 |
Aug 27 05:12:55 AM UTC 24 |
35825365799 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/192.uart_fifo_reset.458842689 |
|
|
Aug 27 05:12:00 AM UTC 24 |
Aug 27 05:12:56 AM UTC 24 |
44703827457 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3564303658 |
|
|
Aug 27 05:12:15 AM UTC 24 |
Aug 27 05:12:56 AM UTC 24 |
25034490373 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/209.uart_fifo_reset.2605121247 |
|
|
Aug 27 05:12:20 AM UTC 24 |
Aug 27 05:12:56 AM UTC 24 |
52987472762 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/131.uart_fifo_reset.2298543837 |
|
|
Aug 27 05:09:58 AM UTC 24 |
Aug 27 05:12:58 AM UTC 24 |
135319834698 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/191.uart_fifo_reset.3464969388 |
|
|
Aug 27 05:11:58 AM UTC 24 |
Aug 27 05:13:01 AM UTC 24 |
76437906244 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/220.uart_fifo_reset.2656497579 |
|
|
Aug 27 05:12:32 AM UTC 24 |
Aug 27 05:13:02 AM UTC 24 |
18913864032 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.984606959 |
|
|
Aug 27 05:04:16 AM UTC 24 |
Aug 27 05:13:02 AM UTC 24 |
62109802005 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/185.uart_fifo_reset.3163363896 |
|
|
Aug 27 05:11:49 AM UTC 24 |
Aug 27 05:13:02 AM UTC 24 |
20642001417 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/215.uart_fifo_reset.542122453 |
|
|
Aug 27 05:12:29 AM UTC 24 |
Aug 27 05:13:03 AM UTC 24 |
34108306125 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/224.uart_fifo_reset.1436794377 |
|
|
Aug 27 05:12:42 AM UTC 24 |
Aug 27 05:13:03 AM UTC 24 |
13416169710 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2526971218 |
|
|
Aug 27 05:12:20 AM UTC 24 |
Aug 27 05:13:03 AM UTC 24 |
27218892486 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/229.uart_fifo_reset.2474217361 |
|
|
Aug 27 05:12:51 AM UTC 24 |
Aug 27 05:13:07 AM UTC 24 |
51996942308 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3418237269 |
|
|
Aug 27 05:12:21 AM UTC 24 |
Aug 27 05:13:09 AM UTC 24 |
29499583615 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/19.uart_perf.2533800501 |
|
|
Aug 27 04:47:07 AM UTC 24 |
Aug 27 05:13:09 AM UTC 24 |
26780526122 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/228.uart_fifo_reset.2599617973 |
|
|
Aug 27 05:12:45 AM UTC 24 |
Aug 27 05:13:11 AM UTC 24 |
160153633828 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/154.uart_fifo_reset.2336765888 |
|
|
Aug 27 05:10:41 AM UTC 24 |
Aug 27 05:13:11 AM UTC 24 |
165507094463 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/217.uart_fifo_reset.429608131 |
|
|
Aug 27 05:12:31 AM UTC 24 |
Aug 27 05:13:13 AM UTC 24 |
110354299284 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.571571102 |
|
|
Aug 27 04:59:35 AM UTC 24 |
Aug 27 05:13:14 AM UTC 24 |
126233187161 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_intr.141796938 |
|
|
Aug 27 05:04:32 AM UTC 24 |
Aug 27 05:13:17 AM UTC 24 |
226677564095 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/212.uart_fifo_reset.3200043060 |
|
|
Aug 27 05:12:23 AM UTC 24 |
Aug 27 05:13:17 AM UTC 24 |
104564307427 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/237.uart_fifo_reset.4250371623 |
|
|
Aug 27 05:13:02 AM UTC 24 |
Aug 27 05:13:20 AM UTC 24 |
23398942964 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/225.uart_fifo_reset.1379182972 |
|
|
Aug 27 05:12:42 AM UTC 24 |
Aug 27 05:13:22 AM UTC 24 |
65202103776 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3650589349 |
|
|
Aug 27 05:13:09 AM UTC 24 |
Aug 27 05:13:23 AM UTC 24 |
21090152672 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/190.uart_fifo_reset.3818750080 |
|
|
Aug 27 05:11:57 AM UTC 24 |
Aug 27 05:13:23 AM UTC 24 |
66015603949 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/172.uart_fifo_reset.1265199116 |
|
|
Aug 27 05:11:25 AM UTC 24 |
Aug 27 05:13:26 AM UTC 24 |
326008870634 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/222.uart_fifo_reset.31279449 |
|
|
Aug 27 05:12:38 AM UTC 24 |
Aug 27 05:13:27 AM UTC 24 |
15225183131 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/240.uart_fifo_reset.262951386 |
|
|
Aug 27 05:13:03 AM UTC 24 |
Aug 27 05:13:31 AM UTC 24 |
42929053415 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/223.uart_fifo_reset.1780903273 |
|
|
Aug 27 05:12:39 AM UTC 24 |
Aug 27 05:13:34 AM UTC 24 |
242822001204 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/188.uart_fifo_reset.3173954934 |
|
|
Aug 27 05:11:52 AM UTC 24 |
Aug 27 05:13:34 AM UTC 24 |
66730841652 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/241.uart_fifo_reset.1471455648 |
|
|
Aug 27 05:13:03 AM UTC 24 |
Aug 27 05:13:34 AM UTC 24 |
24517368235 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/248.uart_fifo_reset.1119941178 |
|
|
Aug 27 05:13:12 AM UTC 24 |
Aug 27 05:13:35 AM UTC 24 |
9030353961 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/252.uart_fifo_reset.989582615 |
|
|
Aug 27 05:13:17 AM UTC 24 |
Aug 27 05:13:39 AM UTC 24 |
56836365854 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3586686503 |
|
|
Aug 27 05:12:00 AM UTC 24 |
Aug 27 05:13:44 AM UTC 24 |
105030851874 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/179.uart_fifo_reset.482043253 |
|
|
Aug 27 05:11:40 AM UTC 24 |
Aug 27 05:13:44 AM UTC 24 |
219109806865 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/132.uart_fifo_reset.2242710685 |
|
|
Aug 27 05:09:59 AM UTC 24 |
Aug 27 05:13:45 AM UTC 24 |
92246033404 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/234.uart_fifo_reset.3165076652 |
|
|
Aug 27 05:12:58 AM UTC 24 |
Aug 27 05:13:45 AM UTC 24 |
23133505531 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/242.uart_fifo_reset.2459669826 |
|
|
Aug 27 05:13:04 AM UTC 24 |
Aug 27 05:13:48 AM UTC 24 |
79735483039 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/246.uart_fifo_reset.281274422 |
|
|
Aug 27 05:13:10 AM UTC 24 |
Aug 27 05:13:50 AM UTC 24 |
78309130583 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/235.uart_fifo_reset.955953166 |
|
|
Aug 27 05:12:58 AM UTC 24 |
Aug 27 05:13:51 AM UTC 24 |
43808622718 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/226.uart_fifo_reset.3431732146 |
|
|
Aug 27 05:12:45 AM UTC 24 |
Aug 27 05:13:52 AM UTC 24 |
32626894314 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/251.uart_fifo_reset.1578754484 |
|
|
Aug 27 05:13:17 AM UTC 24 |
Aug 27 05:13:53 AM UTC 24 |
16977121883 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/264.uart_fifo_reset.377392803 |
|
|
Aug 27 05:13:36 AM UTC 24 |
Aug 27 05:13:56 AM UTC 24 |
21590726949 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/236.uart_fifo_reset.4141679422 |
|
|
Aug 27 05:12:59 AM UTC 24 |
Aug 27 05:13:59 AM UTC 24 |
216660380337 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/232.uart_fifo_reset.158953130 |
|
|
Aug 27 05:12:55 AM UTC 24 |
Aug 27 05:13:59 AM UTC 24 |
17854952468 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/239.uart_fifo_reset.2853218526 |
|
|
Aug 27 05:13:03 AM UTC 24 |
Aug 27 05:14:00 AM UTC 24 |
191424691704 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/255.uart_fifo_reset.565370399 |
|
|
Aug 27 05:13:23 AM UTC 24 |
Aug 27 05:14:03 AM UTC 24 |
24673248852 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/175.uart_fifo_reset.2642107378 |
|
|
Aug 27 05:11:34 AM UTC 24 |
Aug 27 05:14:03 AM UTC 24 |
61636095328 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/258.uart_fifo_reset.3845904024 |
|
|
Aug 27 05:13:28 AM UTC 24 |
Aug 27 05:14:04 AM UTC 24 |
52427859669 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/265.uart_fifo_reset.3350829888 |
|
|
Aug 27 05:13:40 AM UTC 24 |
Aug 27 05:14:07 AM UTC 24 |
29844439987 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/261.uart_fifo_reset.1297908442 |
|
|
Aug 27 05:13:35 AM UTC 24 |
Aug 27 05:14:07 AM UTC 24 |
16263176281 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/167.uart_fifo_reset.92625818 |
|
|
Aug 27 05:11:16 AM UTC 24 |
Aug 27 05:14:10 AM UTC 24 |
56369025680 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/276.uart_fifo_reset.3636860279 |
|
|
Aug 27 05:14:00 AM UTC 24 |
Aug 27 05:14:11 AM UTC 24 |
11894124256 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/267.uart_fifo_reset.706087699 |
|
|
Aug 27 05:13:45 AM UTC 24 |
Aug 27 05:14:11 AM UTC 24 |
21956808779 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/24.uart_stress_all.3627817269 |
|
|
Aug 27 04:50:15 AM UTC 24 |
Aug 27 05:14:12 AM UTC 24 |
168418443672 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3492697024 |
|
|
Aug 27 05:13:12 AM UTC 24 |
Aug 27 05:14:12 AM UTC 24 |
125394760256 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/269.uart_fifo_reset.959371637 |
|
|
Aug 27 05:13:46 AM UTC 24 |
Aug 27 05:14:13 AM UTC 24 |
12620998724 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/244.uart_fifo_reset.3236528299 |
|
|
Aug 27 05:13:08 AM UTC 24 |
Aug 27 05:14:14 AM UTC 24 |
97427847112 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/219.uart_fifo_reset.145395753 |
|
|
Aug 27 05:12:32 AM UTC 24 |
Aug 27 05:14:18 AM UTC 24 |
42671128847 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/253.uart_fifo_reset.889137521 |
|
|
Aug 27 05:13:21 AM UTC 24 |
Aug 27 05:14:18 AM UTC 24 |
25821713741 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/257.uart_fifo_reset.3922657614 |
|
|
Aug 27 05:13:25 AM UTC 24 |
Aug 27 05:14:22 AM UTC 24 |
60932133958 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/284.uart_fifo_reset.3144700323 |
|
|
Aug 27 05:14:11 AM UTC 24 |
Aug 27 05:14:22 AM UTC 24 |
21407289940 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/199.uart_fifo_reset.1116560257 |
|
|
Aug 27 05:12:09 AM UTC 24 |
Aug 27 05:14:23 AM UTC 24 |
92056119421 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/174.uart_fifo_reset.3768889325 |
|
|
Aug 27 05:11:27 AM UTC 24 |
Aug 27 05:14:25 AM UTC 24 |
102274613825 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/266.uart_fifo_reset.2006004298 |
|
|
Aug 27 05:13:45 AM UTC 24 |
Aug 27 05:14:27 AM UTC 24 |
75326906722 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2248447091 |
|
|
Aug 27 05:14:03 AM UTC 24 |
Aug 27 05:14:29 AM UTC 24 |
14870598376 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/195.uart_fifo_reset.93837351 |
|
|
Aug 27 05:12:04 AM UTC 24 |
Aug 27 05:14:29 AM UTC 24 |
64242058423 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/256.uart_fifo_reset.2563542678 |
|
|
Aug 27 05:13:24 AM UTC 24 |
Aug 27 05:14:32 AM UTC 24 |
141162032215 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/281.uart_fifo_reset.409318564 |
|
|
Aug 27 05:14:05 AM UTC 24 |
Aug 27 05:14:32 AM UTC 24 |
33259643863 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/214.uart_fifo_reset.1790858698 |
|
|
Aug 27 05:12:28 AM UTC 24 |
Aug 27 05:14:33 AM UTC 24 |
50617638550 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/162.uart_fifo_reset.2390259083 |
|
|
Aug 27 05:11:00 AM UTC 24 |
Aug 27 05:14:34 AM UTC 24 |
53288296655 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/260.uart_fifo_reset.4292919895 |
|
|
Aug 27 05:13:32 AM UTC 24 |
Aug 27 05:14:34 AM UTC 24 |
49463558918 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/280.uart_fifo_reset.1454458651 |
|
|
Aug 27 05:14:05 AM UTC 24 |
Aug 27 05:14:38 AM UTC 24 |
17335604388 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/263.uart_fifo_reset.1144034669 |
|
|
Aug 27 05:13:35 AM UTC 24 |
Aug 27 05:14:39 AM UTC 24 |
140660929469 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/272.uart_fifo_reset.367091288 |
|
|
Aug 27 05:13:52 AM UTC 24 |
Aug 27 05:14:40 AM UTC 24 |
167712486847 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2358220595 |
|
|
Aug 27 05:13:35 AM UTC 24 |
Aug 27 05:14:43 AM UTC 24 |
105287278209 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/227.uart_fifo_reset.1185852357 |
|
|
Aug 27 05:12:45 AM UTC 24 |
Aug 27 05:14:45 AM UTC 24 |
60658118880 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2687918964 |
|
|
Aug 27 05:14:08 AM UTC 24 |
Aug 27 05:14:48 AM UTC 24 |
17215817723 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/259.uart_fifo_reset.957093327 |
|
|
Aug 27 05:13:28 AM UTC 24 |
Aug 27 05:14:49 AM UTC 24 |
36167148044 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3799052835 |
|
|
Aug 27 05:14:12 AM UTC 24 |
Aug 27 05:14:53 AM UTC 24 |
15197918698 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/289.uart_fifo_reset.1164625084 |
|
|
Aug 27 05:14:13 AM UTC 24 |
Aug 27 05:14:53 AM UTC 24 |
231429439024 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/292.uart_fifo_reset.3054702096 |
|
|
Aug 27 05:14:19 AM UTC 24 |
Aug 27 05:14:54 AM UTC 24 |
44372858472 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/290.uart_fifo_reset.326209294 |
|
|
Aug 27 05:14:14 AM UTC 24 |
Aug 27 05:14:54 AM UTC 24 |
36842389468 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/285.uart_fifo_reset.3601940920 |
|
|
Aug 27 05:14:12 AM UTC 24 |
Aug 27 05:14:56 AM UTC 24 |
53594844078 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/230.uart_fifo_reset.2820913928 |
|
|
Aug 27 05:12:52 AM UTC 24 |
Aug 27 05:14:56 AM UTC 24 |
84712442645 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/299.uart_fifo_reset.1162864665 |
|
|
Aug 27 05:14:30 AM UTC 24 |
Aug 27 05:14:59 AM UTC 24 |
172363926088 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/254.uart_fifo_reset.2271077292 |
|
|
Aug 27 05:13:22 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
187455080412 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/297.uart_fifo_reset.939902482 |
|
|
Aug 27 05:14:28 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
122891965515 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/293.uart_fifo_reset.283147320 |
|
|
Aug 27 05:14:23 AM UTC 24 |
Aug 27 05:15:02 AM UTC 24 |
68803114391 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/294.uart_fifo_reset.1838921116 |
|
|
Aug 27 05:14:23 AM UTC 24 |
Aug 27 05:15:02 AM UTC 24 |
81939837727 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1251378536 |
|
|
Aug 27 05:13:15 AM UTC 24 |
Aug 27 05:15:02 AM UTC 24 |
51558630851 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/268.uart_fifo_reset.251352727 |
|
|
Aug 27 05:13:46 AM UTC 24 |
Aug 27 05:15:05 AM UTC 24 |
90447110910 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/296.uart_fifo_reset.3649631898 |
|
|
Aug 27 05:14:26 AM UTC 24 |
Aug 27 05:15:11 AM UTC 24 |
92843954521 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/283.uart_fifo_reset.577107681 |
|
|
Aug 27 05:14:09 AM UTC 24 |
Aug 27 05:15:11 AM UTC 24 |
118122918838 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/298.uart_fifo_reset.1929938998 |
|
|
Aug 27 05:14:29 AM UTC 24 |
Aug 27 05:15:11 AM UTC 24 |
201311050225 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/288.uart_fifo_reset.906796424 |
|
|
Aug 27 05:14:13 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
122120596284 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1465897069 |
|
|
Aug 27 05:12:31 AM UTC 24 |
Aug 27 05:15:20 AM UTC 24 |
265191858687 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.1900213962 |
|
|
Aug 27 05:02:09 AM UTC 24 |
Aug 27 05:15:27 AM UTC 24 |
155018779557 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/275.uart_fifo_reset.4092018489 |
|
|
Aug 27 05:13:56 AM UTC 24 |
Aug 27 05:15:27 AM UTC 24 |
38087044066 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/278.uart_fifo_reset.2237372715 |
|
|
Aug 27 05:14:00 AM UTC 24 |
Aug 27 05:15:32 AM UTC 24 |
135796075714 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/177.uart_fifo_reset.3138886730 |
|
|
Aug 27 05:11:38 AM UTC 24 |
Aug 27 05:15:33 AM UTC 24 |
118831762270 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/286.uart_fifo_reset.2740739994 |
|
|
Aug 27 05:14:12 AM UTC 24 |
Aug 27 05:15:36 AM UTC 24 |
106931784225 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/270.uart_fifo_reset.3652421742 |
|
|
Aug 27 05:13:49 AM UTC 24 |
Aug 27 05:15:46 AM UTC 24 |
135009548191 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/48.uart_perf.3437562830 |
|
|
Aug 27 05:04:41 AM UTC 24 |
Aug 27 05:15:47 AM UTC 24 |
31696527183 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/189.uart_fifo_reset.3789688696 |
|
|
Aug 27 05:11:52 AM UTC 24 |
Aug 27 05:15:54 AM UTC 24 |
108986283863 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/249.uart_fifo_reset.3958817916 |
|
|
Aug 27 05:13:14 AM UTC 24 |
Aug 27 05:15:56 AM UTC 24 |
98070587904 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/238.uart_fifo_reset.2925309045 |
|
|
Aug 27 05:13:03 AM UTC 24 |
Aug 27 05:16:00 AM UTC 24 |
118884386700 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/271.uart_fifo_reset.4243193202 |
|
|
Aug 27 05:13:51 AM UTC 24 |
Aug 27 05:16:02 AM UTC 24 |
140859773384 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/170.uart_fifo_reset.4191644948 |
|
|
Aug 27 05:11:18 AM UTC 24 |
Aug 27 05:16:06 AM UTC 24 |
95747158531 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/291.uart_fifo_reset.57905360 |
|
|
Aug 27 05:14:18 AM UTC 24 |
Aug 27 05:16:07 AM UTC 24 |
110301341652 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/13.uart_stress_all.3015734738 |
|
|
Aug 27 04:43:00 AM UTC 24 |
Aug 27 05:16:12 AM UTC 24 |
205876169672 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.4080714252 |
|
|
Aug 27 05:03:46 AM UTC 24 |
Aug 27 05:16:13 AM UTC 24 |
115446094376 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1730477240 |
|
|
Aug 27 05:13:04 AM UTC 24 |
Aug 27 05:16:21 AM UTC 24 |
124513599291 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/277.uart_fifo_reset.1871208373 |
|
|
Aug 27 05:14:00 AM UTC 24 |
Aug 27 05:16:24 AM UTC 24 |
51506112865 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/295.uart_fifo_reset.3239215287 |
|
|
Aug 27 05:14:24 AM UTC 24 |
Aug 27 05:16:28 AM UTC 24 |
91254213403 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/204.uart_fifo_reset.1293616958 |
|
|
Aug 27 05:12:16 AM UTC 24 |
Aug 27 05:16:48 AM UTC 24 |
143111207884 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/273.uart_fifo_reset.1013794583 |
|
|
Aug 27 05:13:53 AM UTC 24 |
Aug 27 05:16:55 AM UTC 24 |
77008857891 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/61.uart_fifo_reset.2363496493 |
|
|
Aug 27 05:06:41 AM UTC 24 |
Aug 27 05:16:58 AM UTC 24 |
247507151765 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/274.uart_fifo_reset.3438501517 |
|
|
Aug 27 05:13:54 AM UTC 24 |
Aug 27 05:17:02 AM UTC 24 |
167147027387 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2050428262 |
|
|
Aug 27 05:12:56 AM UTC 24 |
Aug 27 05:17:06 AM UTC 24 |
120363499565 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/213.uart_fifo_reset.1616037274 |
|
|
Aug 27 05:12:27 AM UTC 24 |
Aug 27 05:17:35 AM UTC 24 |
102333097666 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/194.uart_fifo_reset.2150840197 |
|
|
Aug 27 05:12:00 AM UTC 24 |
Aug 27 05:19:35 AM UTC 24 |
185470505052 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/231.uart_fifo_reset.584308000 |
|
|
Aug 27 05:12:55 AM UTC 24 |
Aug 27 05:20:19 AM UTC 24 |
123980316596 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/31.uart_perf.1597502526 |
|
|
Aug 27 04:55:32 AM UTC 24 |
Aug 27 05:20:46 AM UTC 24 |
22970685386 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_stress_all.2870715928 |
|
|
Aug 27 05:05:29 AM UTC 24 |
Aug 27 05:20:53 AM UTC 24 |
35432609065 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.2641552322 |
|
|
Aug 27 05:05:23 AM UTC 24 |
Aug 27 05:22:32 AM UTC 24 |
121321921218 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/221.uart_fifo_reset.377594911 |
|
|
Aug 27 05:12:35 AM UTC 24 |
Aug 27 05:24:27 AM UTC 24 |
189054550040 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/38.uart_stress_all.3737252873 |
|
|
Aug 27 04:59:39 AM UTC 24 |
Aug 27 05:28:27 AM UTC 24 |
266360444149 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/default/45.uart_stress_all.2748393202 |
|
|
Aug 27 05:03:10 AM UTC 24 |
Aug 27 05:30:48 AM UTC 24 |
248604681665 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.2803790722 |
|
|
Aug 27 05:14:32 AM UTC 24 |
Aug 27 05:14:35 AM UTC 24 |
46557662 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.797764946 |
|
|
Aug 27 05:14:33 AM UTC 24 |
Aug 27 05:14:35 AM UTC 24 |
51642159 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.419388899 |
|
|
Aug 27 05:14:32 AM UTC 24 |
Aug 27 05:14:36 AM UTC 24 |
1113956356 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.3850795167 |
|
|
Aug 27 05:14:34 AM UTC 24 |
Aug 27 05:14:36 AM UTC 24 |
25312090 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.2861419092 |
|
|
Aug 27 05:14:36 AM UTC 24 |
Aug 27 05:14:37 AM UTC 24 |
18761667 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.4009040422 |
|
|
Aug 27 05:14:36 AM UTC 24 |
Aug 27 05:14:38 AM UTC 24 |
72389566 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1063909624 |
|
|
Aug 27 05:14:37 AM UTC 24 |
Aug 27 05:14:39 AM UTC 24 |
35778379 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.2623164637 |
|
|
Aug 27 05:14:37 AM UTC 24 |
Aug 27 05:14:39 AM UTC 24 |
74345550 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.2744512644 |
|
|
Aug 27 05:14:36 AM UTC 24 |
Aug 27 05:14:39 AM UTC 24 |
129825858 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.1657825508 |
|
|
Aug 27 05:14:38 AM UTC 24 |
Aug 27 05:14:40 AM UTC 24 |
146752993 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2055445519 |
|
|
Aug 27 05:14:38 AM UTC 24 |
Aug 27 05:14:41 AM UTC 24 |
199377717 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.2463460214 |
|
|
Aug 27 05:14:39 AM UTC 24 |
Aug 27 05:14:41 AM UTC 24 |
23950911 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.320654082 |
|
|
Aug 27 05:14:39 AM UTC 24 |
Aug 27 05:14:41 AM UTC 24 |
28893703 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.4067229770 |
|
|
Aug 27 05:14:39 AM UTC 24 |
Aug 27 05:14:41 AM UTC 24 |
17159158 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.3464311464 |
|
|
Aug 27 05:14:39 AM UTC 24 |
Aug 27 05:14:42 AM UTC 24 |
128929717 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3384030525 |
|
|
Aug 27 05:14:39 AM UTC 24 |
Aug 27 05:14:42 AM UTC 24 |
938256213 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.2945299288 |
|
|
Aug 27 05:14:42 AM UTC 24 |
Aug 27 05:14:44 AM UTC 24 |
38117646 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2658592379 |
|
|
Aug 27 05:14:42 AM UTC 24 |
Aug 27 05:14:44 AM UTC 24 |
28712633 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.1231125330 |
|
|
Aug 27 05:14:42 AM UTC 24 |
Aug 27 05:14:44 AM UTC 24 |
46451800 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2174291374 |
|
|
Aug 27 05:14:42 AM UTC 24 |
Aug 27 05:14:45 AM UTC 24 |
33795421 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.3230701949 |
|
|
Aug 27 05:14:42 AM UTC 24 |
Aug 27 05:14:45 AM UTC 24 |
26900960 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.2295933864 |
|
|
Aug 27 05:14:42 AM UTC 24 |
Aug 27 05:14:45 AM UTC 24 |
276059302 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.1438726621 |
|
|
Aug 27 05:14:43 AM UTC 24 |
Aug 27 05:14:45 AM UTC 24 |
12959793 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.2995474649 |
|
|
Aug 27 05:14:43 AM UTC 24 |
Aug 27 05:14:46 AM UTC 24 |
102267477 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.228096268 |
|
|
Aug 27 05:14:43 AM UTC 24 |
Aug 27 05:14:47 AM UTC 24 |
398668542 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.576347911 |
|
|
Aug 27 05:14:45 AM UTC 24 |
Aug 27 05:14:47 AM UTC 24 |
43331832 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3731449180 |
|
|
Aug 27 05:14:46 AM UTC 24 |
Aug 27 05:14:49 AM UTC 24 |
23140312 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2526391716 |
|
|
Aug 27 05:14:47 AM UTC 24 |
Aug 27 05:14:49 AM UTC 24 |
14521577 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.1174938959 |
|
|
Aug 27 05:14:47 AM UTC 24 |
Aug 27 05:14:49 AM UTC 24 |
13907257 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2455270903 |
|
|
Aug 27 05:14:47 AM UTC 24 |
Aug 27 05:14:49 AM UTC 24 |
16014909 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2192494308 |
|
|
Aug 27 05:14:47 AM UTC 24 |
Aug 27 05:14:49 AM UTC 24 |
15615760 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.3775473076 |
|
|
Aug 27 05:14:46 AM UTC 24 |
Aug 27 05:14:50 AM UTC 24 |
96199917 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.1396177771 |
|
|
Aug 27 05:14:46 AM UTC 24 |
Aug 27 05:14:50 AM UTC 24 |
174817675 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.3977381321 |
|
|
Aug 27 05:14:47 AM UTC 24 |
Aug 27 05:14:50 AM UTC 24 |
462129801 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.4263990523 |
|
|
Aug 27 05:14:48 AM UTC 24 |
Aug 27 05:14:50 AM UTC 24 |
18879316 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1343054170 |
|
|
Aug 27 05:14:48 AM UTC 24 |
Aug 27 05:14:51 AM UTC 24 |
34541778 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.4082901800 |
|
|
Aug 27 05:14:49 AM UTC 24 |
Aug 27 05:14:52 AM UTC 24 |
199385526 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.379356002 |
|
|
Aug 27 05:14:49 AM UTC 24 |
Aug 27 05:14:52 AM UTC 24 |
45553147 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.4287686912 |
|
|
Aug 27 05:14:52 AM UTC 24 |
Aug 27 05:14:54 AM UTC 24 |
12099306 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.2540512322 |
|
|
Aug 27 05:14:52 AM UTC 24 |
Aug 27 05:14:54 AM UTC 24 |
25872800 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.3501285297 |
|
|
Aug 27 05:14:52 AM UTC 24 |
Aug 27 05:14:54 AM UTC 24 |
213780961 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.4248058603 |
|
|
Aug 27 05:14:52 AM UTC 24 |
Aug 27 05:14:54 AM UTC 24 |
159500226 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2738972 |
|
|
Aug 27 05:14:52 AM UTC 24 |
Aug 27 05:14:54 AM UTC 24 |
18728584 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3924001733 |
|
|
Aug 27 05:14:52 AM UTC 24 |
Aug 27 05:14:54 AM UTC 24 |
44838891 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3187220387 |
|
|
Aug 27 05:14:52 AM UTC 24 |
Aug 27 05:14:54 AM UTC 24 |
31291260 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3280120523 |
|
|
Aug 27 05:14:52 AM UTC 24 |
Aug 27 05:14:55 AM UTC 24 |
123275867 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.4038010187 |
|
|
Aug 27 05:14:52 AM UTC 24 |
Aug 27 05:14:55 AM UTC 24 |
82638448 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3423769514 |
|
|
Aug 27 05:14:52 AM UTC 24 |
Aug 27 05:14:55 AM UTC 24 |
332042203 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.137009825 |
|
|
Aug 27 05:14:54 AM UTC 24 |
Aug 27 05:14:56 AM UTC 24 |
14399192 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.2260054973 |
|
|
Aug 27 05:14:54 AM UTC 24 |
Aug 27 05:14:56 AM UTC 24 |
72966556 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.581295732 |
|
|
Aug 27 05:14:54 AM UTC 24 |
Aug 27 05:14:56 AM UTC 24 |
135363612 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.2202760815 |
|
|
Aug 27 05:14:54 AM UTC 24 |
Aug 27 05:14:58 AM UTC 24 |
488191805 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2074919663 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:05 AM UTC 24 |
21673802 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.3827260944 |
|
|
Aug 27 05:14:57 AM UTC 24 |
Aug 27 05:14:59 AM UTC 24 |
16904218 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.2807511595 |
|
|
Aug 27 05:14:57 AM UTC 24 |
Aug 27 05:14:59 AM UTC 24 |
14814312 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.4074791570 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:14:59 AM UTC 24 |
24253352 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3365798815 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:06 AM UTC 24 |
402704458 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.3734925167 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:14:59 AM UTC 24 |
18801177 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.3105880469 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
34663659 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.2005739935 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
37081430 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.2608071609 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
24455890 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.3666388731 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
48235464 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3637416478 |
|
|
Aug 27 05:14:57 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
57007762 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3360345570 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
29331004 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1716003438 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
52187162 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.384080776 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
177989449 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3016065013 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
94241773 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1273979068 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:15:00 AM UTC 24 |
303414780 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.2307148940 |
|
|
Aug 27 05:14:58 AM UTC 24 |
Aug 27 05:15:01 AM UTC 24 |
37458808 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2401333321 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:04 AM UTC 24 |
13662404 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.2880271963 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:04 AM UTC 24 |
13986325 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.3402002498 |
|
|
Aug 27 05:15:02 AM UTC 24 |
Aug 27 05:15:04 AM UTC 24 |
15215278 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2531958454 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:05 AM UTC 24 |
43228899 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1744595872 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:05 AM UTC 24 |
14453639 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.3116990001 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
25815147 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.3471294043 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:05 AM UTC 24 |
33687781 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.1671966928 |
|
|
Aug 27 05:15:02 AM UTC 24 |
Aug 27 05:15:05 AM UTC 24 |
89694451 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.4256012225 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:05 AM UTC 24 |
12403948 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.3350359568 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:05 AM UTC 24 |
75062537 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2235438047 |
|
|
Aug 27 05:15:02 AM UTC 24 |
Aug 27 05:15:05 AM UTC 24 |
116940357 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2799613504 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:05 AM UTC 24 |
17836905 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.891453530 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:05 AM UTC 24 |
47098597 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.750355328 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:06 AM UTC 24 |
338226481 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1343884803 |
|
|
Aug 27 05:15:03 AM UTC 24 |
Aug 27 05:15:06 AM UTC 24 |
293772155 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.137320012 |
|
|
Aug 27 05:15:02 AM UTC 24 |
Aug 27 05:15:06 AM UTC 24 |
90282937 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.2294127389 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
15941200 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.1264505868 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
14348352 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1186795804 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
15765527 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3230064484 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
24864107 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.3428657368 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
19492018 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.13089200 |
|
|
Aug 27 05:15:34 AM UTC 24 |
Aug 27 05:15:36 AM UTC 24 |
16186587 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3629772693 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
42834706 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.4264943296 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
11440219 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1863884703 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
102560215 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.710111918 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
65295755 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1751080276 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
16358515 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2904463518 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
72192291 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1019780039 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
40786919 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2139288356 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
19304820 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.2929858984 |
|
|
Aug 27 05:15:10 AM UTC 24 |
Aug 27 05:15:12 AM UTC 24 |
304351965 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2697579363 |
|
|
Aug 27 05:15:10 AM UTC 24 |
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