T637 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_intr.599781739 |
|
|
Aug 29 11:21:23 AM UTC 24 |
Aug 29 11:22:21 AM UTC 24 |
17519413117 ps |
T638 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_alert_test.369051550 |
|
|
Aug 29 11:22:21 AM UTC 24 |
Aug 29 11:22:23 AM UTC 24 |
28072141 ps |
T639 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_tx_rx.4118344628 |
|
|
Aug 29 11:20:30 AM UTC 24 |
Aug 29 11:22:25 AM UTC 24 |
73672853081 ps |
T640 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_rx_oversample.4164092994 |
|
|
Aug 29 11:21:20 AM UTC 24 |
Aug 29 11:22:26 AM UTC 24 |
5511765196 ps |
T641 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_fifo_full.2884108554 |
|
|
Aug 29 11:21:54 AM UTC 24 |
Aug 29 11:22:29 AM UTC 24 |
107798160735 ps |
T642 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.1507381738 |
|
|
Aug 29 11:06:28 AM UTC 24 |
Aug 29 11:22:40 AM UTC 24 |
131045679857 ps |
T643 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_intr.481535487 |
|
|
Aug 29 11:19:02 AM UTC 24 |
Aug 29 11:22:42 AM UTC 24 |
73219578081 ps |
T644 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_smoke.2252230253 |
|
|
Aug 29 11:22:23 AM UTC 24 |
Aug 29 11:22:44 AM UTC 24 |
6008319755 ps |
T645 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_perf.1652781958 |
|
|
Aug 29 11:06:54 AM UTC 24 |
Aug 29 11:22:45 AM UTC 24 |
16574397732 ps |
T646 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_intr.1125066242 |
|
|
Aug 29 11:18:32 AM UTC 24 |
Aug 29 11:22:47 AM UTC 24 |
150276459444 ps |
T647 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.1830021767 |
|
|
Aug 29 11:19:08 AM UTC 24 |
Aug 29 11:22:49 AM UTC 24 |
89995358278 ps |
T648 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_fifo_full.61714481 |
|
|
Aug 29 11:22:28 AM UTC 24 |
Aug 29 11:22:51 AM UTC 24 |
38260902715 ps |
T649 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_smoke.1728403305 |
|
|
Aug 29 11:21:49 AM UTC 24 |
Aug 29 11:22:51 AM UTC 24 |
11618503227 ps |
T650 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.1026267900 |
|
|
Aug 29 11:22:46 AM UTC 24 |
Aug 29 11:22:51 AM UTC 24 |
3992019668 ps |
T651 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.2790961279 |
|
|
Aug 29 11:22:49 AM UTC 24 |
Aug 29 11:22:54 AM UTC 24 |
560822456 ps |
T652 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_intr.3506451119 |
|
|
Aug 29 11:22:07 AM UTC 24 |
Aug 29 11:22:54 AM UTC 24 |
45076591616 ps |
T653 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.4033059179 |
|
|
Aug 29 11:22:09 AM UTC 24 |
Aug 29 11:22:56 AM UTC 24 |
24131198152 ps |
T654 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.1312854502 |
|
|
Aug 29 11:22:11 AM UTC 24 |
Aug 29 11:22:57 AM UTC 24 |
11950643278 ps |
T655 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_fifo_reset.158621119 |
|
|
Aug 29 11:22:30 AM UTC 24 |
Aug 29 11:22:58 AM UTC 24 |
8126111848 ps |
T656 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_alert_test.1317764841 |
|
|
Aug 29 11:22:57 AM UTC 24 |
Aug 29 11:22:59 AM UTC 24 |
34274132 ps |
T657 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_perf.706139635 |
|
|
Aug 29 11:19:16 AM UTC 24 |
Aug 29 11:23:01 AM UTC 24 |
7335726939 ps |
T658 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_perf.2871832082 |
|
|
Aug 29 11:21:09 AM UTC 24 |
Aug 29 11:23:03 AM UTC 24 |
6690105592 ps |
T659 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.3342494530 |
|
|
Aug 29 11:20:20 AM UTC 24 |
Aug 29 11:23:03 AM UTC 24 |
182732868693 ps |
T660 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.138008226 |
|
|
Aug 29 11:21:18 AM UTC 24 |
Aug 29 11:23:05 AM UTC 24 |
63577762658 ps |
T661 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_rx_oversample.1091473048 |
|
|
Aug 29 11:22:41 AM UTC 24 |
Aug 29 11:23:06 AM UTC 24 |
6533611344 ps |
T407 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.42382494 |
|
|
Aug 29 11:22:48 AM UTC 24 |
Aug 29 11:23:11 AM UTC 24 |
12295496887 ps |
T662 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_stress_all.1837134331 |
|
|
Aug 29 11:11:17 AM UTC 24 |
Aug 29 11:23:11 AM UTC 24 |
108282032891 ps |
T663 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_loopback.1568114292 |
|
|
Aug 29 11:22:51 AM UTC 24 |
Aug 29 11:23:14 AM UTC 24 |
9127705132 ps |
T197 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_fifo_reset.2755085372 |
|
|
Aug 29 11:21:19 AM UTC 24 |
Aug 29 11:23:14 AM UTC 24 |
25771176492 ps |
T664 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.2408054187 |
|
|
Aug 29 11:12:32 AM UTC 24 |
Aug 29 11:23:17 AM UTC 24 |
121972283715 ps |
T665 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.2582925020 |
|
|
Aug 29 11:23:12 AM UTC 24 |
Aug 29 11:23:18 AM UTC 24 |
4230167803 ps |
T409 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_fifo_reset.736098531 |
|
|
Aug 29 11:18:26 AM UTC 24 |
Aug 29 11:23:21 AM UTC 24 |
114341548031 ps |
T666 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_smoke.855495027 |
|
|
Aug 29 11:22:58 AM UTC 24 |
Aug 29 11:23:25 AM UTC 24 |
11064023820 ps |
T667 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_intr.3344272202 |
|
|
Aug 29 11:22:43 AM UTC 24 |
Aug 29 11:23:25 AM UTC 24 |
59464418680 ps |
T668 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_tx_rx.1850149286 |
|
|
Aug 29 11:21:14 AM UTC 24 |
Aug 29 11:23:28 AM UTC 24 |
40941220851 ps |
T669 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_alert_test.1729781779 |
|
|
Aug 29 11:23:26 AM UTC 24 |
Aug 29 11:23:28 AM UTC 24 |
33586002 ps |
T670 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_fifo_full.1522430809 |
|
|
Aug 29 11:19:30 AM UTC 24 |
Aug 29 11:23:28 AM UTC 24 |
125222057768 ps |
T671 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.3570185452 |
|
|
Aug 29 11:23:15 AM UTC 24 |
Aug 29 11:23:29 AM UTC 24 |
6914196304 ps |
T672 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_fifo_reset.539229623 |
|
|
Aug 29 11:23:03 AM UTC 24 |
Aug 29 11:23:30 AM UTC 24 |
63034101316 ps |
T673 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_perf.2310163376 |
|
|
Aug 29 11:09:09 AM UTC 24 |
Aug 29 11:23:32 AM UTC 24 |
20552017759 ps |
T674 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_noise_filter.3783173575 |
|
|
Aug 29 11:22:45 AM UTC 24 |
Aug 29 11:23:37 AM UTC 24 |
34587751289 ps |
T398 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.4072280856 |
|
|
Aug 29 11:22:19 AM UTC 24 |
Aug 29 11:23:39 AM UTC 24 |
3162404525 ps |
T675 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_loopback.1701837269 |
|
|
Aug 29 11:23:15 AM UTC 24 |
Aug 29 11:23:41 AM UTC 24 |
4960110285 ps |
T417 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_noise_filter.1455481693 |
|
|
Aug 29 11:22:09 AM UTC 24 |
Aug 29 11:23:41 AM UTC 24 |
42751032601 ps |
T676 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.4238590019 |
|
|
Aug 29 11:23:21 AM UTC 24 |
Aug 29 11:23:41 AM UTC 24 |
1316798869 ps |
T677 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_smoke.722899777 |
|
|
Aug 29 11:23:28 AM UTC 24 |
Aug 29 11:23:41 AM UTC 24 |
6075711842 ps |
T678 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.3777427173 |
|
|
Aug 29 11:21:42 AM UTC 24 |
Aug 29 11:23:43 AM UTC 24 |
4305290293 ps |
T679 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_perf.2283723292 |
|
|
Aug 29 11:15:05 AM UTC 24 |
Aug 29 11:23:45 AM UTC 24 |
12145040857 ps |
T680 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.1385637251 |
|
|
Aug 29 11:21:54 AM UTC 24 |
Aug 29 11:23:45 AM UTC 24 |
112832008418 ps |
T681 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_rx_oversample.1260234861 |
|
|
Aug 29 11:23:04 AM UTC 24 |
Aug 29 11:23:46 AM UTC 24 |
4075330352 ps |
T682 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_tx_rx.2188946083 |
|
|
Aug 29 11:22:25 AM UTC 24 |
Aug 29 11:23:46 AM UTC 24 |
30505411601 ps |
T683 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_intr.3385920638 |
|
|
Aug 29 11:23:05 AM UTC 24 |
Aug 29 11:23:47 AM UTC 24 |
53542253524 ps |
T684 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.1100250013 |
|
|
Aug 29 11:23:42 AM UTC 24 |
Aug 29 11:23:48 AM UTC 24 |
804998303 ps |
T685 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_alert_test.547545821 |
|
|
Aug 29 11:23:47 AM UTC 24 |
Aug 29 11:23:48 AM UTC 24 |
38769875 ps |
T686 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_tx_rx.229446068 |
|
|
Aug 29 11:23:30 AM UTC 24 |
Aug 29 11:23:50 AM UTC 24 |
14750573275 ps |
T687 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_smoke.3653732304 |
|
|
Aug 29 11:23:48 AM UTC 24 |
Aug 29 11:23:53 AM UTC 24 |
605545532 ps |
T688 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_stress_all.4083217214 |
|
|
Aug 29 11:18:47 AM UTC 24 |
Aug 29 11:23:54 AM UTC 24 |
103828349896 ps |
T689 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.292128574 |
|
|
Aug 29 11:23:02 AM UTC 24 |
Aug 29 11:23:54 AM UTC 24 |
68148214448 ps |
T94 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.18314074 |
|
|
Aug 29 11:22:55 AM UTC 24 |
Aug 29 11:23:56 AM UTC 24 |
10256372227 ps |
T690 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_tx_rx.1909890564 |
|
|
Aug 29 11:22:59 AM UTC 24 |
Aug 29 11:23:57 AM UTC 24 |
75793009526 ps |
T691 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_smoke.741603631 |
|
|
Aug 29 11:26:37 AM UTC 24 |
Aug 29 11:26:52 AM UTC 24 |
6332666126 ps |
T692 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_loopback.3313602553 |
|
|
Aug 29 11:23:42 AM UTC 24 |
Aug 29 11:23:59 AM UTC 24 |
8159575267 ps |
T693 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.1552145197 |
|
|
Aug 29 11:23:57 AM UTC 24 |
Aug 29 11:24:03 AM UTC 24 |
2887087632 ps |
T694 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_intr.2700337465 |
|
|
Aug 29 11:23:38 AM UTC 24 |
Aug 29 11:24:10 AM UTC 24 |
19018677498 ps |
T695 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_perf.1352413130 |
|
|
Aug 29 11:21:40 AM UTC 24 |
Aug 29 11:24:18 AM UTC 24 |
28489174955 ps |
T696 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_noise_filter.848381315 |
|
|
Aug 29 11:23:07 AM UTC 24 |
Aug 29 11:24:18 AM UTC 24 |
28174194033 ps |
T697 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.638432403 |
|
|
Aug 29 11:24:04 AM UTC 24 |
Aug 29 11:24:20 AM UTC 24 |
8116655984 ps |
T698 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_tx_rx.2089716497 |
|
|
Aug 29 11:23:49 AM UTC 24 |
Aug 29 11:24:24 AM UTC 24 |
24713588953 ps |
T699 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.3445137758 |
|
|
Aug 29 11:23:12 AM UTC 24 |
Aug 29 11:24:26 AM UTC 24 |
85491589537 ps |
T700 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_alert_test.3805375874 |
|
|
Aug 29 11:24:26 AM UTC 24 |
Aug 29 11:24:28 AM UTC 24 |
42112788 ps |
T212 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_fifo_reset.4287871386 |
|
|
Aug 29 11:18:59 AM UTC 24 |
Aug 29 11:24:40 AM UTC 24 |
124492980075 ps |
T701 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.3600022382 |
|
|
Aug 29 11:23:45 AM UTC 24 |
Aug 29 11:24:43 AM UTC 24 |
11150697362 ps |
T702 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_rx_oversample.1052146064 |
|
|
Aug 29 11:23:54 AM UTC 24 |
Aug 29 11:24:43 AM UTC 24 |
4091933914 ps |
T703 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_smoke.2544587206 |
|
|
Aug 29 11:24:29 AM UTC 24 |
Aug 29 11:24:43 AM UTC 24 |
5490194570 ps |
T704 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.1003639579 |
|
|
Aug 29 11:22:29 AM UTC 24 |
Aug 29 11:24:45 AM UTC 24 |
156175284482 ps |
T201 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_fifo_reset.2182748359 |
|
|
Aug 29 11:22:01 AM UTC 24 |
Aug 29 11:24:49 AM UTC 24 |
106752726585 ps |
T705 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_rx_oversample.2550569381 |
|
|
Aug 29 11:24:46 AM UTC 24 |
Aug 29 11:24:49 AM UTC 24 |
1420179849 ps |
T706 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_rx_oversample.2422610329 |
|
|
Aug 29 11:23:33 AM UTC 24 |
Aug 29 11:24:49 AM UTC 24 |
6726179382 ps |
T707 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.1454951290 |
|
|
Aug 29 11:10:02 AM UTC 24 |
Aug 29 11:24:56 AM UTC 24 |
117592427961 ps |
T708 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_loopback.3419375737 |
|
|
Aug 29 11:24:11 AM UTC 24 |
Aug 29 11:25:04 AM UTC 24 |
7908694191 ps |
T413 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_perf.1116549055 |
|
|
Aug 29 11:22:53 AM UTC 24 |
Aug 29 11:25:07 AM UTC 24 |
24031569298 ps |
T709 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_perf.3326656267 |
|
|
Aug 29 11:12:11 AM UTC 24 |
Aug 29 11:25:08 AM UTC 24 |
11836333050 ps |
T710 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.1816528539 |
|
|
Aug 29 11:25:04 AM UTC 24 |
Aug 29 11:25:08 AM UTC 24 |
1840363451 ps |
T176 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.2821595549 |
|
|
Aug 29 11:23:42 AM UTC 24 |
Aug 29 11:25:09 AM UTC 24 |
120144324184 ps |
T711 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_fifo_reset.3826979387 |
|
|
Aug 29 11:24:44 AM UTC 24 |
Aug 29 11:25:12 AM UTC 24 |
17369009227 ps |
T712 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.803740009 |
|
|
Aug 29 11:24:57 AM UTC 24 |
Aug 29 11:25:19 AM UTC 24 |
11363801512 ps |
T713 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.497025889 |
|
|
Aug 29 11:23:51 AM UTC 24 |
Aug 29 11:25:21 AM UTC 24 |
52700305212 ps |
T714 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_alert_test.3945688597 |
|
|
Aug 29 11:25:20 AM UTC 24 |
Aug 29 11:25:22 AM UTC 24 |
20181197 ps |
T162 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_stress_all.3374057696 |
|
|
Aug 29 11:24:25 AM UTC 24 |
Aug 29 11:25:26 AM UTC 24 |
174064386109 ps |
T715 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.4202712664 |
|
|
Aug 29 11:08:40 AM UTC 24 |
Aug 29 11:25:28 AM UTC 24 |
129432042107 ps |
T716 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_loopback.4240148596 |
|
|
Aug 29 11:25:07 AM UTC 24 |
Aug 29 11:25:28 AM UTC 24 |
5207546375 ps |
T717 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.1078248094 |
|
|
Aug 29 11:24:50 AM UTC 24 |
Aug 29 11:25:29 AM UTC 24 |
45068236817 ps |
T718 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_smoke.4024187044 |
|
|
Aug 29 11:25:22 AM UTC 24 |
Aug 29 11:25:30 AM UTC 24 |
6409851779 ps |
T719 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_fifo_full.52643650 |
|
|
Aug 29 11:23:30 AM UTC 24 |
Aug 29 11:25:31 AM UTC 24 |
45534754044 ps |
T720 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.1719084829 |
|
|
Aug 29 11:24:20 AM UTC 24 |
Aug 29 11:25:31 AM UTC 24 |
14896003760 ps |
T721 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.3842831154 |
|
|
Aug 29 11:25:33 AM UTC 24 |
Aug 29 11:25:36 AM UTC 24 |
2797530423 ps |
T196 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_fifo_reset.851168255 |
|
|
Aug 29 11:17:04 AM UTC 24 |
Aug 29 11:25:37 AM UTC 24 |
172145877490 ps |
T722 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.1922668577 |
|
|
Aug 29 11:25:35 AM UTC 24 |
Aug 29 11:25:38 AM UTC 24 |
318190261 ps |
T723 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_fifo_reset.873693627 |
|
|
Aug 29 11:23:54 AM UTC 24 |
Aug 29 11:25:40 AM UTC 24 |
85687294387 ps |
T724 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_rx_oversample.1848464054 |
|
|
Aug 29 11:25:30 AM UTC 24 |
Aug 29 11:25:42 AM UTC 24 |
4157865407 ps |
T725 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_intr.2509748330 |
|
|
Aug 29 11:24:50 AM UTC 24 |
Aug 29 11:25:45 AM UTC 24 |
31704297136 ps |
T726 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_noise_filter.2362051649 |
|
|
Aug 29 11:23:57 AM UTC 24 |
Aug 29 11:25:47 AM UTC 24 |
33656338346 ps |
T727 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_loopback.3268067511 |
|
|
Aug 29 11:25:37 AM UTC 24 |
Aug 29 11:25:47 AM UTC 24 |
2408508479 ps |
T728 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_intr.764865302 |
|
|
Aug 29 11:25:30 AM UTC 24 |
Aug 29 11:25:48 AM UTC 24 |
9095792085 ps |
T729 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_alert_test.1613816313 |
|
|
Aug 29 11:25:46 AM UTC 24 |
Aug 29 11:25:48 AM UTC 24 |
158767488 ps |
T730 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_perf.2367722966 |
|
|
Aug 29 11:16:49 AM UTC 24 |
Aug 29 11:25:50 AM UTC 24 |
7932485011 ps |
T731 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.3643316396 |
|
|
Aug 29 11:24:00 AM UTC 24 |
Aug 29 11:25:51 AM UTC 24 |
32242166090 ps |
T732 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.3272165978 |
|
|
Aug 29 11:25:10 AM UTC 24 |
Aug 29 11:26:01 AM UTC 24 |
6800519723 ps |
T733 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.2276766752 |
|
|
Aug 29 11:23:42 AM UTC 24 |
Aug 29 11:26:06 AM UTC 24 |
35530969797 ps |
T734 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.915674541 |
|
|
Aug 29 11:25:28 AM UTC 24 |
Aug 29 11:26:08 AM UTC 24 |
187243188055 ps |
T735 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.2067299829 |
|
|
Aug 29 11:26:09 AM UTC 24 |
Aug 29 11:26:14 AM UTC 24 |
729602020 ps |
T736 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_rx_oversample.2312289005 |
|
|
Aug 29 11:25:52 AM UTC 24 |
Aug 29 11:26:16 AM UTC 24 |
6981845531 ps |
T737 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_stress_all.4208132463 |
|
|
Aug 29 11:19:24 AM UTC 24 |
Aug 29 11:26:19 AM UTC 24 |
596603979422 ps |
T418 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_noise_filter.2408333988 |
|
|
Aug 29 11:25:31 AM UTC 24 |
Aug 29 11:26:22 AM UTC 24 |
56851008617 ps |
T738 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_smoke.1803528462 |
|
|
Aug 29 11:25:48 AM UTC 24 |
Aug 29 11:26:24 AM UTC 24 |
5489012344 ps |
T163 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.3402524601 |
|
|
Aug 29 11:25:33 AM UTC 24 |
Aug 29 11:26:29 AM UTC 24 |
99727272657 ps |
T739 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_loopback.1483539857 |
|
|
Aug 29 11:26:20 AM UTC 24 |
Aug 29 11:26:29 AM UTC 24 |
12161953106 ps |
T740 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_stress_all.480429973 |
|
|
Aug 29 11:06:30 AM UTC 24 |
Aug 29 11:26:33 AM UTC 24 |
270746779359 ps |
T741 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_alert_test.2318372222 |
|
|
Aug 29 11:26:34 AM UTC 24 |
Aug 29 11:26:36 AM UTC 24 |
24693459 ps |
T742 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_noise_filter.411287642 |
|
|
Aug 29 11:24:50 AM UTC 24 |
Aug 29 11:26:50 AM UTC 24 |
304651533852 ps |
T743 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.1250562195 |
|
|
Aug 29 11:24:44 AM UTC 24 |
Aug 29 11:26:52 AM UTC 24 |
131271073448 ps |
T744 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_fifo_full.3436556277 |
|
|
Aug 29 11:23:00 AM UTC 24 |
Aug 29 11:27:00 AM UTC 24 |
98801279182 ps |
T745 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.2805696944 |
|
|
Aug 29 11:19:17 AM UTC 24 |
Aug 29 11:27:01 AM UTC 24 |
75493522109 ps |
T746 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.3162548671 |
|
|
Aug 29 11:25:50 AM UTC 24 |
Aug 29 11:27:16 AM UTC 24 |
110355200244 ps |
T747 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_fifo_full.2235762348 |
|
|
Aug 29 11:24:44 AM UTC 24 |
Aug 29 11:27:17 AM UTC 24 |
88483659644 ps |
T748 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_tx_rx.2724724885 |
|
|
Aug 29 11:25:22 AM UTC 24 |
Aug 29 11:27:18 AM UTC 24 |
55658169283 ps |
T749 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.1994246556 |
|
|
Aug 29 11:27:19 AM UTC 24 |
Aug 29 11:27:21 AM UTC 24 |
700593342 ps |
T750 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_noise_filter.2535228768 |
|
|
Aug 29 11:23:40 AM UTC 24 |
Aug 29 11:27:21 AM UTC 24 |
120820223167 ps |
T751 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_tx_rx.2410182178 |
|
|
Aug 29 11:24:40 AM UTC 24 |
Aug 29 11:27:24 AM UTC 24 |
50900972440 ps |
T752 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_stress_all.3327671362 |
|
|
Aug 29 11:23:47 AM UTC 24 |
Aug 29 11:27:26 AM UTC 24 |
54985158414 ps |
T753 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.3444987982 |
|
|
Aug 29 11:27:22 AM UTC 24 |
Aug 29 11:27:28 AM UTC 24 |
766272724 ps |
T754 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.4216707915 |
|
|
Aug 29 11:15:05 AM UTC 24 |
Aug 29 11:27:28 AM UTC 24 |
184917596461 ps |
T755 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_intr.3127135963 |
|
|
Aug 29 11:26:02 AM UTC 24 |
Aug 29 11:27:29 AM UTC 24 |
82312642071 ps |
T756 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1398144906 |
|
|
Aug 29 11:26:16 AM UTC 24 |
Aug 29 11:27:31 AM UTC 24 |
12142196682 ps |
T757 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_alert_test.3807596986 |
|
|
Aug 29 11:27:30 AM UTC 24 |
Aug 29 11:27:32 AM UTC 24 |
22647587 ps |
T157 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_fifo_full.2144694111 |
|
|
Aug 29 11:25:49 AM UTC 24 |
Aug 29 11:27:33 AM UTC 24 |
130345835473 ps |
T758 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.942866761 |
|
|
Aug 29 11:26:53 AM UTC 24 |
Aug 29 11:27:33 AM UTC 24 |
79803609962 ps |
T759 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_smoke.2191613075 |
|
|
Aug 29 11:27:32 AM UTC 24 |
Aug 29 11:27:37 AM UTC 24 |
659536416 ps |
T760 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_loopback.3274060899 |
|
|
Aug 29 11:27:22 AM UTC 24 |
Aug 29 11:27:37 AM UTC 24 |
9070638356 ps |
T761 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_noise_filter.110608543 |
|
|
Aug 29 11:26:07 AM UTC 24 |
Aug 29 11:27:38 AM UTC 24 |
53513286536 ps |
T762 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_noise_filter.2635360269 |
|
|
Aug 29 11:27:16 AM UTC 24 |
Aug 29 11:27:41 AM UTC 24 |
17219507801 ps |
T763 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.629890301 |
|
|
Aug 29 11:23:19 AM UTC 24 |
Aug 29 11:27:43 AM UTC 24 |
82743541748 ps |
T764 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_intr.2192125184 |
|
|
Aug 29 11:27:02 AM UTC 24 |
Aug 29 11:27:44 AM UTC 24 |
36738954159 ps |
T765 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_perf.1794305201 |
|
|
Aug 29 11:11:47 AM UTC 24 |
Aug 29 11:27:48 AM UTC 24 |
18003542078 ps |
T766 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1205587198 |
|
|
Aug 29 11:27:29 AM UTC 24 |
Aug 29 11:27:49 AM UTC 24 |
1174259039 ps |
T767 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.2145960467 |
|
|
Aug 29 11:27:49 AM UTC 24 |
Aug 29 11:27:53 AM UTC 24 |
1107879782 ps |
T183 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_stress_all.327781452 |
|
|
Aug 29 11:16:12 AM UTC 24 |
Aug 29 11:27:54 AM UTC 24 |
145050628905 ps |
T768 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.4065180911 |
|
|
Aug 29 11:27:43 AM UTC 24 |
Aug 29 11:27:55 AM UTC 24 |
2499480304 ps |
T769 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_tx_rx.2270284280 |
|
|
Aug 29 11:26:49 AM UTC 24 |
Aug 29 11:27:57 AM UTC 24 |
100668677529 ps |
T770 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.3783400328 |
|
|
Aug 29 11:26:30 AM UTC 24 |
Aug 29 11:28:05 AM UTC 24 |
3124334514 ps |
T771 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_alert_test.2857222226 |
|
|
Aug 29 11:28:06 AM UTC 24 |
Aug 29 11:28:08 AM UTC 24 |
37810343 ps |
T772 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_fifo_reset.2457957387 |
|
|
Aug 29 11:27:38 AM UTC 24 |
Aug 29 11:28:09 AM UTC 24 |
70617003114 ps |
T773 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_noise_filter.3085536783 |
|
|
Aug 29 11:27:41 AM UTC 24 |
Aug 29 11:28:10 AM UTC 24 |
32542515404 ps |
T774 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_stress_all.2679691513 |
|
|
Aug 29 11:23:26 AM UTC 24 |
Aug 29 11:28:10 AM UTC 24 |
196999805544 ps |
T775 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_smoke.3912727410 |
|
|
Aug 29 11:28:09 AM UTC 24 |
Aug 29 11:28:14 AM UTC 24 |
446268532 ps |
T776 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_rx_oversample.502967157 |
|
|
Aug 29 11:27:01 AM UTC 24 |
Aug 29 11:28:20 AM UTC 24 |
6618135723 ps |
T777 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_perf.3949003667 |
|
|
Aug 29 11:25:38 AM UTC 24 |
Aug 29 11:28:21 AM UTC 24 |
14462848592 ps |
T778 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_loopback.4046860916 |
|
|
Aug 29 11:27:50 AM UTC 24 |
Aug 29 11:28:22 AM UTC 24 |
3981675904 ps |
T779 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.2599786999 |
|
|
Aug 29 11:23:30 AM UTC 24 |
Aug 29 11:28:30 AM UTC 24 |
116523360268 ps |
T780 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_tx_rx.1153197701 |
|
|
Aug 29 11:25:48 AM UTC 24 |
Aug 29 11:28:33 AM UTC 24 |
148013127486 ps |
T781 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.2238807002 |
|
|
Aug 29 11:28:31 AM UTC 24 |
Aug 29 11:28:36 AM UTC 24 |
4556651442 ps |
T782 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_fifo_full.836561188 |
|
|
Aug 29 11:23:49 AM UTC 24 |
Aug 29 11:28:36 AM UTC 24 |
292048736966 ps |
T783 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.2180535732 |
|
|
Aug 29 11:27:56 AM UTC 24 |
Aug 29 11:28:41 AM UTC 24 |
2099378053 ps |
T784 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_loopback.1094103015 |
|
|
Aug 29 11:28:37 AM UTC 24 |
Aug 29 11:28:43 AM UTC 24 |
1202546654 ps |
T785 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_tx_rx.3740399422 |
|
|
Aug 29 11:28:10 AM UTC 24 |
Aug 29 11:28:45 AM UTC 24 |
37843694015 ps |
T786 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_rx_oversample.3719259273 |
|
|
Aug 29 11:28:21 AM UTC 24 |
Aug 29 11:28:47 AM UTC 24 |
2763690948 ps |
T787 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_rx_oversample.2988269531 |
|
|
Aug 29 11:27:38 AM UTC 24 |
Aug 29 11:28:48 AM UTC 24 |
5771459900 ps |
T788 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_alert_test.2011062628 |
|
|
Aug 29 11:28:49 AM UTC 24 |
Aug 29 11:28:51 AM UTC 24 |
10997603 ps |
T789 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.3566115524 |
|
|
Aug 29 11:26:14 AM UTC 24 |
Aug 29 11:28:55 AM UTC 24 |
132130145140 ps |
T790 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_perf.4255489398 |
|
|
Aug 29 11:22:12 AM UTC 24 |
Aug 29 11:28:56 AM UTC 24 |
25383620143 ps |
T791 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_smoke.838957647 |
|
|
Aug 29 11:28:51 AM UTC 24 |
Aug 29 11:28:57 AM UTC 24 |
844655491 ps |
T792 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_noise_filter.1218196806 |
|
|
Aug 29 11:28:23 AM UTC 24 |
Aug 29 11:28:59 AM UTC 24 |
43471761252 ps |
T167 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_fifo_full.44482188 |
|
|
Aug 29 11:27:33 AM UTC 24 |
Aug 29 11:29:01 AM UTC 24 |
226429288044 ps |
T793 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.526705201 |
|
|
Aug 29 11:27:19 AM UTC 24 |
Aug 29 11:29:05 AM UTC 24 |
61727473028 ps |
T794 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_rx_oversample.2214135157 |
|
|
Aug 29 11:29:02 AM UTC 24 |
Aug 29 11:29:06 AM UTC 24 |
2742742747 ps |
T795 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.3778618622 |
|
|
Aug 29 11:28:37 AM UTC 24 |
Aug 29 11:29:06 AM UTC 24 |
6554063635 ps |
T796 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_perf.4242750264 |
|
|
Aug 29 11:24:19 AM UTC 24 |
Aug 29 11:29:15 AM UTC 24 |
29238524006 ps |
T797 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_perf.38319913 |
|
|
Aug 29 11:26:22 AM UTC 24 |
Aug 29 11:29:15 AM UTC 24 |
4174419135 ps |
T798 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.2602502871 |
|
|
Aug 29 11:24:19 AM UTC 24 |
Aug 29 11:29:18 AM UTC 24 |
72858489177 ps |
T799 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.2485587541 |
|
|
Aug 29 11:29:16 AM UTC 24 |
Aug 29 11:29:20 AM UTC 24 |
1551228147 ps |
T800 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_fifo_full.2882693091 |
|
|
Aug 29 11:25:27 AM UTC 24 |
Aug 29 11:29:20 AM UTC 24 |
110281163860 ps |
T419 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_fifo_reset.3907898584 |
|
|
Aug 29 11:25:28 AM UTC 24 |
Aug 29 11:29:21 AM UTC 24 |
130281171073 ps |
T801 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_tx_rx.2898186482 |
|
|
Aug 29 11:27:33 AM UTC 24 |
Aug 29 11:29:22 AM UTC 24 |
111922029326 ps |
T802 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.3955161480 |
|
|
Aug 29 11:29:08 AM UTC 24 |
Aug 29 11:29:25 AM UTC 24 |
4696228939 ps |
T803 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_alert_test.3141183052 |
|
|
Aug 29 11:29:26 AM UTC 24 |
Aug 29 11:29:28 AM UTC 24 |
12697416 ps |
T804 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_loopback.3268818354 |
|
|
Aug 29 11:29:18 AM UTC 24 |
Aug 29 11:29:29 AM UTC 24 |
4542624286 ps |
T805 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_intr.1764952982 |
|
|
Aug 29 11:29:06 AM UTC 24 |
Aug 29 11:29:29 AM UTC 24 |
23092602815 ps |
T156 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_fifo_full.3877209403 |
|
|
Aug 29 11:28:58 AM UTC 24 |
Aug 29 11:29:29 AM UTC 24 |
26033527744 ps |
T806 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_noise_filter.3616980584 |
|
|
Aug 29 11:29:08 AM UTC 24 |
Aug 29 11:29:30 AM UTC 24 |
12125636524 ps |
T807 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_smoke.264831014 |
|
|
Aug 29 11:29:28 AM UTC 24 |
Aug 29 11:29:31 AM UTC 24 |
444591171 ps |
T808 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.1896858200 |
|
|
Aug 29 11:28:58 AM UTC 24 |
Aug 29 11:29:34 AM UTC 24 |
153861923446 ps |
T164 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.4036610714 |
|
|
Aug 29 11:27:35 AM UTC 24 |
Aug 29 11:29:44 AM UTC 24 |
141253879153 ps |
T809 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.1513109930 |
|
|
Aug 29 11:28:46 AM UTC 24 |
Aug 29 11:29:54 AM UTC 24 |
9154837961 ps |
T810 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_intr.3795087774 |
|
|
Aug 29 11:27:39 AM UTC 24 |
Aug 29 11:29:55 AM UTC 24 |
33206938142 ps |
T811 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.374535650 |
|
|
Aug 29 11:29:55 AM UTC 24 |
Aug 29 11:29:59 AM UTC 24 |
722151879 ps |
T812 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.289215273 |
|
|
Aug 29 11:30:00 AM UTC 24 |
Aug 29 11:30:04 AM UTC 24 |
1577303847 ps |
T813 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.1271434121 |
|
|
Aug 29 11:29:22 AM UTC 24 |
Aug 29 11:30:05 AM UTC 24 |
7036262084 ps |
T814 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_rx_oversample.1468639407 |
|
|
Aug 29 11:29:32 AM UTC 24 |
Aug 29 11:30:05 AM UTC 24 |
3595404531 ps |
T815 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_stress_all.1582636683 |
|
|
Aug 29 11:16:50 AM UTC 24 |
Aug 29 11:30:07 AM UTC 24 |
231907657323 ps |
T816 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.3902858124 |
|
|
Aug 29 11:21:41 AM UTC 24 |
Aug 29 11:30:09 AM UTC 24 |
125191152858 ps |
T817 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_loopback.2116608726 |
|
|
Aug 29 11:30:05 AM UTC 24 |
Aug 29 11:30:12 AM UTC 24 |
2228810648 ps |
T818 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_stress_all.684372517 |
|
|
Aug 29 11:28:48 AM UTC 24 |
Aug 29 11:30:13 AM UTC 24 |
110829711904 ps |
T819 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_alert_test.2307198197 |
|
|
Aug 29 11:30:13 AM UTC 24 |
Aug 29 11:30:15 AM UTC 24 |
13151346 ps |
T820 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_smoke.2368157439 |
|
|
Aug 29 11:30:14 AM UTC 24 |
Aug 29 11:30:18 AM UTC 24 |
287647265 ps |
T198 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_fifo_reset.3400756295 |
|
|
Aug 29 11:28:15 AM UTC 24 |
Aug 29 11:30:18 AM UTC 24 |
82566116020 ps |
T206 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_fifo_reset.627131607 |
|
|
Aug 29 11:26:53 AM UTC 24 |
Aug 29 11:30:24 AM UTC 24 |
197951734905 ps |
T821 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_stress_all.3426777441 |
|
|
Aug 29 11:22:20 AM UTC 24 |
Aug 29 11:30:38 AM UTC 24 |
441291779874 ps |
T230 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_fifo_reset.3998209951 |
|
|
Aug 29 11:25:51 AM UTC 24 |
Aug 29 11:30:49 AM UTC 24 |
113276590045 ps |
T822 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_tx_rx.2639749874 |
|
|
Aug 29 11:30:15 AM UTC 24 |
Aug 29 11:30:49 AM UTC 24 |
35970831347 ps |
T237 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_stress_all.481135385 |
|
|
Aug 29 11:25:14 AM UTC 24 |
Aug 29 11:30:51 AM UTC 24 |
630187495811 ps |
T823 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_perf.3130598347 |
|
|
Aug 29 11:15:33 AM UTC 24 |
Aug 29 11:30:54 AM UTC 24 |
18680811907 ps |
T169 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.4263023181 |
|
|
Aug 29 11:28:12 AM UTC 24 |
Aug 29 11:30:56 AM UTC 24 |
99523809849 ps |
T824 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.1294194928 |
|
|
Aug 29 11:30:52 AM UTC 24 |
Aug 29 11:30:59 AM UTC 24 |
6221238928 ps |
T825 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_intr.1272510615 |
|
|
Aug 29 11:28:22 AM UTC 24 |
Aug 29 11:31:00 AM UTC 24 |
40886991625 ps |
T826 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_noise_filter.3760889486 |
|
|
Aug 29 11:29:45 AM UTC 24 |
Aug 29 11:31:01 AM UTC 24 |
122355742369 ps |
T827 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.2690592177 |
|
|
Aug 29 11:29:30 AM UTC 24 |
Aug 29 11:31:07 AM UTC 24 |
144753449030 ps |
T828 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_tx_rx.1632731661 |
|
|
Aug 29 11:29:30 AM UTC 24 |
Aug 29 11:31:12 AM UTC 24 |
49663013046 ps |
T829 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_rx_oversample.1788418726 |
|
|
Aug 29 11:30:39 AM UTC 24 |
Aug 29 11:31:13 AM UTC 24 |
3596487947 ps |
T209 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/112.uart_fifo_reset.124117316 |
|
|
Aug 29 11:36:57 AM UTC 24 |
Aug 29 11:38:45 AM UTC 24 |
98240684112 ps |
T830 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_loopback.382483121 |
|
|
Aug 29 11:30:59 AM UTC 24 |
Aug 29 11:31:14 AM UTC 24 |
9275061903 ps |
T831 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_alert_test.820190162 |
|
|
Aug 29 11:31:13 AM UTC 24 |
Aug 29 11:31:15 AM UTC 24 |
68421806 ps |
T264 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_fifo_reset.621275083 |
|
|
Aug 29 11:29:00 AM UTC 24 |
Aug 29 11:31:16 AM UTC 24 |
37878825014 ps |
T832 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_tx_rx.1333057271 |
|
|
Aug 29 11:28:56 AM UTC 24 |
Aug 29 11:31:17 AM UTC 24 |
72721195387 ps |
T833 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_smoke.2710298153 |
|
|
Aug 29 11:31:14 AM UTC 24 |
Aug 29 11:31:18 AM UTC 24 |
291403079 ps |
T834 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.1486623808 |
|
|
Aug 29 11:30:08 AM UTC 24 |
Aug 29 11:31:20 AM UTC 24 |
34457206178 ps |
T835 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_perf.203451033 |
|
|
Aug 29 11:27:25 AM UTC 24 |
Aug 29 11:31:20 AM UTC 24 |
7829069406 ps |
T836 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.3896909321 |
|
|
Aug 29 11:30:57 AM UTC 24 |
Aug 29 11:31:22 AM UTC 24 |
6063932874 ps |
T837 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_fifo_full.3062852688 |
|
|
Aug 29 11:28:12 AM UTC 24 |
Aug 29 11:31:22 AM UTC 24 |
89217608164 ps |
T838 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_rx_oversample.851750438 |
|
|
Aug 29 11:31:20 AM UTC 24 |
Aug 29 11:31:28 AM UTC 24 |
2579400041 ps |
T839 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.518218999 |
|
|
Aug 29 11:21:11 AM UTC 24 |
Aug 29 11:31:35 AM UTC 24 |
101096689507 ps |
T840 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_stress_all.1762784569 |
|
|
Aug 29 11:30:10 AM UTC 24 |
Aug 29 11:31:39 AM UTC 24 |
62733929812 ps |
T841 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.3150202701 |
|
|
Aug 29 11:31:35 AM UTC 24 |
Aug 29 11:31:41 AM UTC 24 |
848447613 ps |
T842 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_fifo_full.1604844751 |
|
|
Aug 29 11:30:19 AM UTC 24 |
Aug 29 11:31:43 AM UTC 24 |
21617854187 ps |
T843 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_loopback.4076148474 |
|
|
Aug 29 11:31:37 AM UTC 24 |
Aug 29 11:31:48 AM UTC 24 |
2478960742 ps |
T844 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_perf.4037195937 |
|
|
Aug 29 11:28:42 AM UTC 24 |
Aug 29 11:31:50 AM UTC 24 |
13019203339 ps |
T845 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.3843520426 |
|
|
Aug 29 11:30:07 AM UTC 24 |
Aug 29 11:31:51 AM UTC 24 |
28356091708 ps |
T846 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.3574517307 |
|
|
Aug 29 11:31:18 AM UTC 24 |
Aug 29 11:31:52 AM UTC 24 |
31282088926 ps |
T847 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_fifo_full.2024536192 |
|
|
Aug 29 11:29:30 AM UTC 24 |
Aug 29 11:31:53 AM UTC 24 |
79937752415 ps |
T848 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_alert_test.4095956217 |
|
|
Aug 29 11:31:51 AM UTC 24 |
Aug 29 11:31:54 AM UTC 24 |
41456806 ps |
T849 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.724514056 |
|
|
Aug 29 11:27:46 AM UTC 24 |
Aug 29 11:31:54 AM UTC 24 |
167607606176 ps |
T850 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_smoke.986944206 |
|
|
Aug 29 11:31:51 AM UTC 24 |
Aug 29 11:31:55 AM UTC 24 |
270327772 ps |
T851 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.2248403842 |
|
|
Aug 29 11:25:08 AM UTC 24 |
Aug 29 11:31:56 AM UTC 24 |
30005827131 ps |
T852 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_stress_all.665793816 |
|
|
Aug 29 11:21:12 AM UTC 24 |
Aug 29 11:31:59 AM UTC 24 |
787786647345 ps |
T853 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.2225865467 |
|
|
Aug 29 11:31:08 AM UTC 24 |
Aug 29 11:32:00 AM UTC 24 |
4597604486 ps |
T854 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_perf.3951113267 |
|
|
Aug 29 11:17:57 AM UTC 24 |
Aug 29 11:32:01 AM UTC 24 |
11474097684 ps |
T855 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_stress_all.3950748791 |
|
|
Aug 29 11:21:44 AM UTC 24 |
Aug 29 11:32:01 AM UTC 24 |
269483653224 ps |
T856 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.3678884495 |
|
|
Aug 29 11:28:34 AM UTC 24 |
Aug 29 11:32:02 AM UTC 24 |
168976515751 ps |
T857 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_noise_filter.252722225 |
|
|
Aug 29 11:30:51 AM UTC 24 |
Aug 29 11:32:03 AM UTC 24 |
110147124663 ps |
T858 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_intr.653680792 |
|
|
Aug 29 11:29:34 AM UTC 24 |
Aug 29 11:32:07 AM UTC 24 |
44504263741 ps |
T859 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.1797716040 |
|
|
Aug 29 11:32:02 AM UTC 24 |
Aug 29 11:32:07 AM UTC 24 |
2813148279 ps |