| T186 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_fifo_reset.2238439699 |
|
|
Aug 29 11:32:43 AM UTC 24 |
Aug 29 11:40:03 AM UTC 24 |
175121214481 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/204.uart_fifo_reset.4270966222 |
|
|
Aug 29 11:39:45 AM UTC 24 |
Aug 29 11:40:03 AM UTC 24 |
18338914060 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_perf.1708752997 |
|
|
Aug 29 11:18:41 AM UTC 24 |
Aug 29 11:40:04 AM UTC 24 |
19271603104 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/203.uart_fifo_reset.4198053060 |
|
|
Aug 29 11:39:44 AM UTC 24 |
Aug 29 11:40:05 AM UTC 24 |
11755152898 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/195.uart_fifo_reset.2648327455 |
|
|
Aug 29 11:39:37 AM UTC 24 |
Aug 29 11:40:07 AM UTC 24 |
34075655667 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/189.uart_fifo_reset.3592361927 |
|
|
Aug 29 11:39:28 AM UTC 24 |
Aug 29 11:40:09 AM UTC 24 |
186208152570 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/175.uart_fifo_reset.2310454151 |
|
|
Aug 29 11:38:58 AM UTC 24 |
Aug 29 11:40:16 AM UTC 24 |
24147312345 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/167.uart_fifo_reset.906433982 |
|
|
Aug 29 11:38:45 AM UTC 24 |
Aug 29 11:40:18 AM UTC 24 |
49926771571 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2632453469 |
|
|
Aug 29 11:39:47 AM UTC 24 |
Aug 29 11:40:20 AM UTC 24 |
128098883168 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/169.uart_fifo_reset.638774667 |
|
|
Aug 29 11:38:47 AM UTC 24 |
Aug 29 11:40:21 AM UTC 24 |
58347035280 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/197.uart_fifo_reset.2010504350 |
|
|
Aug 29 11:39:40 AM UTC 24 |
Aug 29 11:40:22 AM UTC 24 |
70335469478 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.130792610 |
|
|
Aug 29 11:23:45 AM UTC 24 |
Aug 29 11:40:23 AM UTC 24 |
159694793433 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/187.uart_fifo_reset.3551216862 |
|
|
Aug 29 11:39:21 AM UTC 24 |
Aug 29 11:40:24 AM UTC 24 |
68632527458 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/190.uart_fifo_reset.2131831280 |
|
|
Aug 29 11:39:28 AM UTC 24 |
Aug 29 11:40:25 AM UTC 24 |
78701044437 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/198.uart_fifo_reset.4053664128 |
|
|
Aug 29 11:39:40 AM UTC 24 |
Aug 29 11:40:25 AM UTC 24 |
80288098816 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/209.uart_fifo_reset.3790634956 |
|
|
Aug 29 11:39:51 AM UTC 24 |
Aug 29 11:40:25 AM UTC 24 |
30646630130 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/191.uart_fifo_reset.2400819296 |
|
|
Aug 29 11:39:29 AM UTC 24 |
Aug 29 11:40:26 AM UTC 24 |
151791946341 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2323315970 |
|
|
Aug 29 11:39:49 AM UTC 24 |
Aug 29 11:40:27 AM UTC 24 |
22125813741 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1679797798 |
|
|
Aug 29 11:40:01 AM UTC 24 |
Aug 29 11:40:27 AM UTC 24 |
32321968350 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/188.uart_fifo_reset.1820714187 |
|
|
Aug 29 11:39:27 AM UTC 24 |
Aug 29 11:40:29 AM UTC 24 |
46155777716 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/163.uart_fifo_reset.4217943130 |
|
|
Aug 29 11:38:36 AM UTC 24 |
Aug 29 11:40:31 AM UTC 24 |
63734162579 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/214.uart_fifo_reset.287696530 |
|
|
Aug 29 11:39:57 AM UTC 24 |
Aug 29 11:40:32 AM UTC 24 |
48043843483 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.3589817304 |
|
|
Aug 29 11:16:50 AM UTC 24 |
Aug 29 11:40:33 AM UTC 24 |
128737980885 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/218.uart_fifo_reset.2728011824 |
|
|
Aug 29 11:40:03 AM UTC 24 |
Aug 29 11:40:37 AM UTC 24 |
22695293567 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/224.uart_fifo_reset.3131781775 |
|
|
Aug 29 11:40:10 AM UTC 24 |
Aug 29 11:40:37 AM UTC 24 |
174223129481 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/114.uart_fifo_reset.3706332575 |
|
|
Aug 29 11:36:58 AM UTC 24 |
Aug 29 11:40:39 AM UTC 24 |
81755027873 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/217.uart_fifo_reset.15226985 |
|
|
Aug 29 11:40:03 AM UTC 24 |
Aug 29 11:40:41 AM UTC 24 |
23805568925 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/223.uart_fifo_reset.855867589 |
|
|
Aug 29 11:40:08 AM UTC 24 |
Aug 29 11:40:41 AM UTC 24 |
51862496606 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/233.uart_fifo_reset.240863442 |
|
|
Aug 29 11:40:27 AM UTC 24 |
Aug 29 11:40:41 AM UTC 24 |
20840741116 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/220.uart_fifo_reset.458209974 |
|
|
Aug 29 11:40:05 AM UTC 24 |
Aug 29 11:40:42 AM UTC 24 |
204968463256 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_perf.2493347095 |
|
|
Aug 29 11:31:02 AM UTC 24 |
Aug 29 11:40:43 AM UTC 24 |
16110738368 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/171.uart_fifo_reset.1025479540 |
|
|
Aug 29 11:38:51 AM UTC 24 |
Aug 29 11:40:43 AM UTC 24 |
163028679645 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/225.uart_fifo_reset.3860662201 |
|
|
Aug 29 11:40:16 AM UTC 24 |
Aug 29 11:40:47 AM UTC 24 |
26195387710 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/232.uart_fifo_reset.1763879200 |
|
|
Aug 29 11:40:25 AM UTC 24 |
Aug 29 11:40:48 AM UTC 24 |
127696924958 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3289783027 |
|
|
Aug 29 11:39:53 AM UTC 24 |
Aug 29 11:40:56 AM UTC 24 |
126941736519 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/222.uart_fifo_reset.975016402 |
|
|
Aug 29 11:40:06 AM UTC 24 |
Aug 29 11:40:58 AM UTC 24 |
162642584870 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3404657241 |
|
|
Aug 29 11:39:34 AM UTC 24 |
Aug 29 11:40:59 AM UTC 24 |
47341833507 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/234.uart_fifo_reset.2114068109 |
|
|
Aug 29 11:40:27 AM UTC 24 |
Aug 29 11:40:59 AM UTC 24 |
38320074936 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1419994787 |
|
|
Aug 29 11:39:11 AM UTC 24 |
Aug 29 11:41:00 AM UTC 24 |
152580729998 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/194.uart_fifo_reset.2917321888 |
|
|
Aug 29 11:39:34 AM UTC 24 |
Aug 29 11:41:00 AM UTC 24 |
180944905587 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/199.uart_fifo_reset.4149340432 |
|
|
Aug 29 11:39:41 AM UTC 24 |
Aug 29 11:41:03 AM UTC 24 |
30821389117 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/229.uart_fifo_reset.1418434274 |
|
|
Aug 29 11:40:24 AM UTC 24 |
Aug 29 11:41:04 AM UTC 24 |
20082074033 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/202.uart_fifo_reset.1810915299 |
|
|
Aug 29 11:39:42 AM UTC 24 |
Aug 29 11:41:05 AM UTC 24 |
195357144167 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3379550512 |
|
|
Aug 29 11:40:42 AM UTC 24 |
Aug 29 11:41:07 AM UTC 24 |
12956011700 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/244.uart_fifo_reset.2457151491 |
|
|
Aug 29 11:40:41 AM UTC 24 |
Aug 29 11:41:07 AM UTC 24 |
15395039539 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/245.uart_fifo_reset.1488134494 |
|
|
Aug 29 11:40:42 AM UTC 24 |
Aug 29 11:41:10 AM UTC 24 |
58039003515 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1165762851 |
|
|
Aug 29 11:40:32 AM UTC 24 |
Aug 29 11:41:13 AM UTC 24 |
83136354581 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/161.uart_fifo_reset.1980994961 |
|
|
Aug 29 11:38:32 AM UTC 24 |
Aug 29 11:41:14 AM UTC 24 |
111608370545 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/238.uart_fifo_reset.151822561 |
|
|
Aug 29 11:40:29 AM UTC 24 |
Aug 29 11:41:15 AM UTC 24 |
85788666274 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/243.uart_fifo_reset.372728592 |
|
|
Aug 29 11:40:38 AM UTC 24 |
Aug 29 11:41:16 AM UTC 24 |
9172869742 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/240.uart_fifo_reset.3667272289 |
|
|
Aug 29 11:40:33 AM UTC 24 |
Aug 29 11:41:17 AM UTC 24 |
90720768150 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/219.uart_fifo_reset.1525797203 |
|
|
Aug 29 11:40:05 AM UTC 24 |
Aug 29 11:41:18 AM UTC 24 |
229861215452 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/230.uart_fifo_reset.1395994147 |
|
|
Aug 29 11:40:24 AM UTC 24 |
Aug 29 11:41:18 AM UTC 24 |
75931224926 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/253.uart_fifo_reset.718799748 |
|
|
Aug 29 11:40:57 AM UTC 24 |
Aug 29 11:41:19 AM UTC 24 |
27620555584 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1932992037 |
|
|
Aug 29 11:40:37 AM UTC 24 |
Aug 29 11:41:20 AM UTC 24 |
15881215001 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/261.uart_fifo_reset.2353546588 |
|
|
Aug 29 11:41:06 AM UTC 24 |
Aug 29 11:41:20 AM UTC 24 |
7853851741 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/93.uart_fifo_reset.2178612533 |
|
|
Aug 29 11:36:21 AM UTC 24 |
Aug 29 11:41:21 AM UTC 24 |
226269919456 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/235.uart_fifo_reset.1177597823 |
|
|
Aug 29 11:40:28 AM UTC 24 |
Aug 29 11:41:24 AM UTC 24 |
69269126225 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/246.uart_fifo_reset.2840172380 |
|
|
Aug 29 11:40:42 AM UTC 24 |
Aug 29 11:41:24 AM UTC 24 |
104833033852 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/257.uart_fifo_reset.1012444867 |
|
|
Aug 29 11:41:01 AM UTC 24 |
Aug 29 11:41:28 AM UTC 24 |
12180502153 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/260.uart_fifo_reset.2791670888 |
|
|
Aug 29 11:41:05 AM UTC 24 |
Aug 29 11:41:29 AM UTC 24 |
37445432771 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/256.uart_fifo_reset.743229474 |
|
|
Aug 29 11:41:00 AM UTC 24 |
Aug 29 11:41:30 AM UTC 24 |
48596884877 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2532888225 |
|
|
Aug 29 11:39:49 AM UTC 24 |
Aug 29 11:41:30 AM UTC 24 |
57112122475 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/249.uart_fifo_reset.1873756776 |
|
|
Aug 29 11:40:44 AM UTC 24 |
Aug 29 11:41:32 AM UTC 24 |
20156396014 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/172.uart_fifo_reset.1428150593 |
|
|
Aug 29 11:38:51 AM UTC 24 |
Aug 29 11:41:36 AM UTC 24 |
81577909471 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/162.uart_fifo_reset.3090850068 |
|
|
Aug 29 11:38:35 AM UTC 24 |
Aug 29 11:41:36 AM UTC 24 |
106677172315 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/173.uart_fifo_reset.272534075 |
|
|
Aug 29 11:38:56 AM UTC 24 |
Aug 29 11:41:36 AM UTC 24 |
97198211996 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1553062637 |
|
|
Aug 29 11:41:19 AM UTC 24 |
Aug 29 11:41:39 AM UTC 24 |
33600715106 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3417323131 |
|
|
Aug 29 11:40:43 AM UTC 24 |
Aug 29 11:41:39 AM UTC 24 |
96463121286 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/268.uart_fifo_reset.677914835 |
|
|
Aug 29 11:41:17 AM UTC 24 |
Aug 29 11:41:39 AM UTC 24 |
9334487280 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/174.uart_fifo_reset.2277995655 |
|
|
Aug 29 11:38:56 AM UTC 24 |
Aug 29 11:41:40 AM UTC 24 |
133095744810 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/272.uart_fifo_reset.631774160 |
|
|
Aug 29 11:41:19 AM UTC 24 |
Aug 29 11:41:41 AM UTC 24 |
8500530670 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/255.uart_fifo_reset.937484487 |
|
|
Aug 29 11:41:00 AM UTC 24 |
Aug 29 11:41:42 AM UTC 24 |
20504418813 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/228.uart_fifo_reset.1958676683 |
|
|
Aug 29 11:40:23 AM UTC 24 |
Aug 29 11:41:42 AM UTC 24 |
50449859307 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/236.uart_fifo_reset.2372513695 |
|
|
Aug 29 11:40:28 AM UTC 24 |
Aug 29 11:41:44 AM UTC 24 |
31084496734 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2330555138 |
|
|
Aug 29 11:39:59 AM UTC 24 |
Aug 29 11:41:48 AM UTC 24 |
176944991466 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/280.uart_fifo_reset.717953113 |
|
|
Aug 29 11:41:32 AM UTC 24 |
Aug 29 11:41:51 AM UTC 24 |
88594330134 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/192.uart_fifo_reset.2593283744 |
|
|
Aug 29 11:39:32 AM UTC 24 |
Aug 29 11:41:51 AM UTC 24 |
136685223770 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/263.uart_fifo_reset.3366280134 |
|
|
Aug 29 11:41:08 AM UTC 24 |
Aug 29 11:41:54 AM UTC 24 |
64837179459 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/252.uart_fifo_reset.3652224656 |
|
|
Aug 29 11:40:49 AM UTC 24 |
Aug 29 11:41:55 AM UTC 24 |
98387343625 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/265.uart_fifo_reset.3387320649 |
|
|
Aug 29 11:41:13 AM UTC 24 |
Aug 29 11:41:55 AM UTC 24 |
16887661045 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/212.uart_fifo_reset.3583218052 |
|
|
Aug 29 11:39:54 AM UTC 24 |
Aug 29 11:41:56 AM UTC 24 |
130469260709 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/275.uart_fifo_reset.116338819 |
|
|
Aug 29 11:41:22 AM UTC 24 |
Aug 29 11:41:56 AM UTC 24 |
57928912391 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/259.uart_fifo_reset.1124243476 |
|
|
Aug 29 11:41:04 AM UTC 24 |
Aug 29 11:41:57 AM UTC 24 |
205490121434 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/278.uart_fifo_reset.1189084562 |
|
|
Aug 29 11:41:29 AM UTC 24 |
Aug 29 11:41:59 AM UTC 24 |
63353462541 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/270.uart_fifo_reset.1175149150 |
|
|
Aug 29 11:41:19 AM UTC 24 |
Aug 29 11:42:00 AM UTC 24 |
21389024628 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/281.uart_fifo_reset.3672657434 |
|
|
Aug 29 11:41:32 AM UTC 24 |
Aug 29 11:42:02 AM UTC 24 |
121386914452 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2460293368 |
|
|
Aug 29 11:41:36 AM UTC 24 |
Aug 29 11:42:05 AM UTC 24 |
61231215807 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/196.uart_fifo_reset.3396351273 |
|
|
Aug 29 11:39:40 AM UTC 24 |
Aug 29 11:42:06 AM UTC 24 |
114397997561 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/295.uart_fifo_reset.2165538884 |
|
|
Aug 29 11:41:51 AM UTC 24 |
Aug 29 11:42:06 AM UTC 24 |
9459651429 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2247335852 |
|
|
Aug 29 11:41:43 AM UTC 24 |
Aug 29 11:42:08 AM UTC 24 |
36561302996 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/78.uart_fifo_reset.1089005044 |
|
|
Aug 29 11:35:26 AM UTC 24 |
Aug 29 11:42:16 AM UTC 24 |
185952468789 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/277.uart_fifo_reset.3160308854 |
|
|
Aug 29 11:41:25 AM UTC 24 |
Aug 29 11:42:18 AM UTC 24 |
33846453047 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/251.uart_fifo_reset.2448881565 |
|
|
Aug 29 11:40:49 AM UTC 24 |
Aug 29 11:42:19 AM UTC 24 |
26228745141 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/286.uart_fifo_reset.3352949760 |
|
|
Aug 29 11:41:40 AM UTC 24 |
Aug 29 11:42:19 AM UTC 24 |
86807164718 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/276.uart_fifo_reset.137487676 |
|
|
Aug 29 11:41:25 AM UTC 24 |
Aug 29 11:42:20 AM UTC 24 |
86615451700 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/273.uart_fifo_reset.4080035239 |
|
|
Aug 29 11:41:20 AM UTC 24 |
Aug 29 11:42:20 AM UTC 24 |
25096940507 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_perf.1748037285 |
|
|
Aug 29 11:27:54 AM UTC 24 |
Aug 29 11:42:33 AM UTC 24 |
27399006333 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/282.uart_fifo_reset.414570334 |
|
|
Aug 29 11:41:33 AM UTC 24 |
Aug 29 11:42:35 AM UTC 24 |
28417202189 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/269.uart_fifo_reset.2514027697 |
|
|
Aug 29 11:41:18 AM UTC 24 |
Aug 29 11:42:40 AM UTC 24 |
116579524091 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/258.uart_fifo_reset.2813452572 |
|
|
Aug 29 11:41:01 AM UTC 24 |
Aug 29 11:42:40 AM UTC 24 |
59684834955 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_stress_all.468346722 |
|
|
Aug 29 11:33:04 AM UTC 24 |
Aug 29 11:42:41 AM UTC 24 |
127395737797 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/185.uart_fifo_reset.1392117180 |
|
|
Aug 29 11:39:14 AM UTC 24 |
Aug 29 11:42:52 AM UTC 24 |
43944561640 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/288.uart_fifo_reset.4133783648 |
|
|
Aug 29 11:41:40 AM UTC 24 |
Aug 29 11:42:52 AM UTC 24 |
122040317510 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/291.uart_fifo_reset.42171293 |
|
|
Aug 29 11:41:43 AM UTC 24 |
Aug 29 11:42:54 AM UTC 24 |
138195154761 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/237.uart_fifo_reset.1169391294 |
|
|
Aug 29 11:40:28 AM UTC 24 |
Aug 29 11:42:58 AM UTC 24 |
152909166589 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/132.uart_fifo_reset.1415173982 |
|
|
Aug 29 11:37:38 AM UTC 24 |
Aug 29 11:43:02 AM UTC 24 |
145678919514 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/267.uart_fifo_reset.2749541533 |
|
|
Aug 29 11:41:15 AM UTC 24 |
Aug 29 11:43:03 AM UTC 24 |
73295881260 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/241.uart_fifo_reset.3610209732 |
|
|
Aug 29 11:40:34 AM UTC 24 |
Aug 29 11:43:04 AM UTC 24 |
71572249868 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/181.uart_fifo_reset.2019346126 |
|
|
Aug 29 11:39:08 AM UTC 24 |
Aug 29 11:43:05 AM UTC 24 |
143990827344 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/287.uart_fifo_reset.1199373115 |
|
|
Aug 29 11:41:40 AM UTC 24 |
Aug 29 11:43:06 AM UTC 24 |
45810048415 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/294.uart_fifo_reset.1529212175 |
|
|
Aug 29 11:41:49 AM UTC 24 |
Aug 29 11:43:08 AM UTC 24 |
69953723517 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/200.uart_fifo_reset.1913546991 |
|
|
Aug 29 11:39:41 AM UTC 24 |
Aug 29 11:43:11 AM UTC 24 |
155956582477 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/299.uart_fifo_reset.2106575750 |
|
|
Aug 29 11:41:56 AM UTC 24 |
Aug 29 11:43:13 AM UTC 24 |
52516895277 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/226.uart_fifo_reset.1637406614 |
|
|
Aug 29 11:40:19 AM UTC 24 |
Aug 29 11:43:14 AM UTC 24 |
128965712419 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/125.uart_fifo_reset.3012577092 |
|
|
Aug 29 11:37:16 AM UTC 24 |
Aug 29 11:43:15 AM UTC 24 |
130337208557 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/298.uart_fifo_reset.411576634 |
|
|
Aug 29 11:41:56 AM UTC 24 |
Aug 29 11:43:21 AM UTC 24 |
100200516772 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1926425657 |
|
|
Aug 29 11:40:58 AM UTC 24 |
Aug 29 11:43:23 AM UTC 24 |
88749766372 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/297.uart_fifo_reset.2186872531 |
|
|
Aug 29 11:41:55 AM UTC 24 |
Aug 29 11:43:27 AM UTC 24 |
27680014100 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/296.uart_fifo_reset.3453008652 |
|
|
Aug 29 11:41:53 AM UTC 24 |
Aug 29 11:43:34 AM UTC 24 |
127901711985 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.3779556377 |
|
|
Aug 29 11:33:00 AM UTC 24 |
Aug 29 11:43:47 AM UTC 24 |
155351804055 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/285.uart_fifo_reset.2360437335 |
|
|
Aug 29 11:41:38 AM UTC 24 |
Aug 29 11:43:53 AM UTC 24 |
201243600313 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/227.uart_fifo_reset.3686319647 |
|
|
Aug 29 11:40:23 AM UTC 24 |
Aug 29 11:43:59 AM UTC 24 |
160063051491 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/250.uart_fifo_reset.2762955502 |
|
|
Aug 29 11:40:44 AM UTC 24 |
Aug 29 11:44:13 AM UTC 24 |
97455782298 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/210.uart_fifo_reset.1939621252 |
|
|
Aug 29 11:39:51 AM UTC 24 |
Aug 29 11:44:20 AM UTC 24 |
119746449180 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_perf.2985689983 |
|
|
Aug 29 11:30:07 AM UTC 24 |
Aug 29 11:44:33 AM UTC 24 |
16967357315 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/279.uart_fifo_reset.861110488 |
|
|
Aug 29 11:41:31 AM UTC 24 |
Aug 29 11:44:48 AM UTC 24 |
103817515246 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/293.uart_fifo_reset.2033992852 |
|
|
Aug 29 11:41:45 AM UTC 24 |
Aug 29 11:45:05 AM UTC 24 |
66500396590 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/231.uart_fifo_reset.2693238987 |
|
|
Aug 29 11:40:25 AM UTC 24 |
Aug 29 11:45:19 AM UTC 24 |
207164314170 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/292.uart_fifo_reset.285156217 |
|
|
Aug 29 11:41:44 AM UTC 24 |
Aug 29 11:45:20 AM UTC 24 |
151220866360 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/221.uart_fifo_reset.1053402158 |
|
|
Aug 29 11:40:05 AM UTC 24 |
Aug 29 11:45:26 AM UTC 24 |
148216199877 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/143.uart_fifo_reset.563440147 |
|
|
Aug 29 11:37:48 AM UTC 24 |
Aug 29 11:45:26 AM UTC 24 |
204695457855 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/289.uart_fifo_reset.355740552 |
|
|
Aug 29 11:41:41 AM UTC 24 |
Aug 29 11:45:29 AM UTC 24 |
126504179829 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/283.uart_fifo_reset.2127293442 |
|
|
Aug 29 11:41:36 AM UTC 24 |
Aug 29 11:46:16 AM UTC 24 |
114658018626 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_stress_all.540651506 |
|
|
Aug 29 11:27:29 AM UTC 24 |
Aug 29 11:46:32 AM UTC 24 |
96133054997 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/117.uart_fifo_reset.193650382 |
|
|
Aug 29 11:37:01 AM UTC 24 |
Aug 29 11:46:37 AM UTC 24 |
183313217031 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/274.uart_fifo_reset.738490254 |
|
|
Aug 29 11:41:22 AM UTC 24 |
Aug 29 11:46:42 AM UTC 24 |
133401832852 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.3350775303 |
|
|
Aug 29 11:32:35 AM UTC 24 |
Aug 29 11:47:28 AM UTC 24 |
238854274834 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_stress_all.2761033458 |
|
|
Aug 29 11:29:23 AM UTC 24 |
Aug 29 11:47:30 AM UTC 24 |
214448520693 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/177.uart_fifo_reset.2015285962 |
|
|
Aug 29 11:39:00 AM UTC 24 |
Aug 29 11:47:47 AM UTC 24 |
115353017455 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/266.uart_fifo_reset.807385347 |
|
|
Aug 29 11:41:14 AM UTC 24 |
Aug 29 11:48:05 AM UTC 24 |
107280287016 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/262.uart_fifo_reset.1941658169 |
|
|
Aug 29 11:41:08 AM UTC 24 |
Aug 29 11:48:05 AM UTC 24 |
118569633527 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_perf.1245225754 |
|
|
Aug 29 11:14:21 AM UTC 24 |
Aug 29 11:49:11 AM UTC 24 |
31620163222 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/264.uart_fifo_reset.4272338226 |
|
|
Aug 29 11:41:11 AM UTC 24 |
Aug 29 11:51:08 AM UTC 24 |
93526947886 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.81665097 |
|
|
Aug 29 11:22:15 AM UTC 24 |
Aug 29 11:54:26 AM UTC 24 |
187822114567 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_perf.788896931 |
|
|
Aug 29 11:32:59 AM UTC 24 |
Aug 29 12:04:44 PM UTC 24 |
21056442615 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_stress_all.4276119993 |
|
|
Aug 29 11:08:45 AM UTC 24 |
Aug 29 12:14:02 PM UTC 24 |
312841771688 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_stress_all.1747073315 |
|
|
Aug 29 11:25:43 AM UTC 24 |
Aug 29 12:29:02 PM UTC 24 |
376693404959 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.1424802948 |
|
|
Aug 29 10:59:40 AM UTC 24 |
Aug 29 10:59:42 AM UTC 24 |
14261864 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1971903703 |
|
|
Aug 29 10:59:40 AM UTC 24 |
Aug 29 10:59:42 AM UTC 24 |
33268560 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2393531198 |
|
|
Aug 29 10:59:39 AM UTC 24 |
Aug 29 10:59:42 AM UTC 24 |
144337811 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.313735198 |
|
|
Aug 29 10:59:40 AM UTC 24 |
Aug 29 10:59:42 AM UTC 24 |
39018988 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2590618380 |
|
|
Aug 29 10:59:40 AM UTC 24 |
Aug 29 10:59:42 AM UTC 24 |
116289439 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.1047671524 |
|
|
Aug 29 10:59:40 AM UTC 24 |
Aug 29 10:59:42 AM UTC 24 |
54273132 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.186353665 |
|
|
Aug 29 10:59:40 AM UTC 24 |
Aug 29 10:59:43 AM UTC 24 |
77829456 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2138023424 |
|
|
Aug 29 10:59:40 AM UTC 24 |
Aug 29 10:59:43 AM UTC 24 |
211376882 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3030376493 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:46 AM UTC 24 |
54409622 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.1191200282 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:46 AM UTC 24 |
19153443 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.387674333 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:47 AM UTC 24 |
212283464 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1102895844 |
|
|
Aug 29 10:59:46 AM UTC 24 |
Aug 29 10:59:51 AM UTC 24 |
58958868 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3474520675 |
|
|
Aug 29 10:59:46 AM UTC 24 |
Aug 29 10:59:51 AM UTC 24 |
17183332 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.1239538012 |
|
|
Aug 29 10:59:40 AM UTC 24 |
Aug 29 10:59:51 AM UTC 24 |
13353960 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3134777394 |
|
|
Aug 29 10:59:48 AM UTC 24 |
Aug 29 10:59:52 AM UTC 24 |
256566956 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.676364391 |
|
|
Aug 29 10:59:43 AM UTC 24 |
Aug 29 10:59:52 AM UTC 24 |
14169642 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.3279075855 |
|
|
Aug 29 10:59:43 AM UTC 24 |
Aug 29 10:59:52 AM UTC 24 |
59928985 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2281536435 |
|
|
Aug 29 10:59:43 AM UTC 24 |
Aug 29 10:59:52 AM UTC 24 |
121931685 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3743929431 |
|
|
Aug 29 10:59:43 AM UTC 24 |
Aug 29 10:59:52 AM UTC 24 |
30297335 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.763153140 |
|
|
Aug 29 10:59:43 AM UTC 24 |
Aug 29 10:59:53 AM UTC 24 |
183373911 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.1119255811 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:55 AM UTC 24 |
16604752 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3875644633 |
|
|
Aug 29 10:59:38 AM UTC 24 |
Aug 29 10:59:55 AM UTC 24 |
33155431 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.4249290551 |
|
|
Aug 29 10:59:38 AM UTC 24 |
Aug 29 10:59:56 AM UTC 24 |
59534269 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.2040080717 |
|
|
Aug 29 10:59:51 AM UTC 24 |
Aug 29 10:59:56 AM UTC 24 |
33902432 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.2387776051 |
|
|
Aug 29 10:59:38 AM UTC 24 |
Aug 29 10:59:56 AM UTC 24 |
70124681 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.615308830 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:56 AM UTC 24 |
21446489 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.4275638783 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:56 AM UTC 24 |
54778991 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.4221314804 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:56 AM UTC 24 |
23280433 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.1350715497 |
|
|
Aug 29 10:59:53 AM UTC 24 |
Aug 29 10:59:56 AM UTC 24 |
39401201 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.3390191265 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:56 AM UTC 24 |
72845117 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3601129235 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:56 AM UTC 24 |
27820450 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.3753021855 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:56 AM UTC 24 |
21419175 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.3990791919 |
|
|
Aug 29 10:59:59 AM UTC 24 |
Aug 29 11:00:01 AM UTC 24 |
29651206 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2963652435 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
133120708 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.3975642914 |
|
|
Aug 29 10:59:59 AM UTC 24 |
Aug 29 11:00:01 AM UTC 24 |
30338412 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.3367757378 |
|
|
Aug 29 10:59:59 AM UTC 24 |
Aug 29 11:00:01 AM UTC 24 |
41097823 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2853308142 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
93148220 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.27736624 |
|
|
Aug 29 10:59:51 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
91013214 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3242639471 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
23739049 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3381132610 |
|
|
Aug 29 10:59:38 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
33768069 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.411168866 |
|
|
Aug 29 10:59:38 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
15051506 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.517085584 |
|
|
Aug 29 10:59:38 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
12900904 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.193989166 |
|
|
Aug 29 10:59:38 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
17884972 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.640559613 |
|
|
Aug 29 10:59:59 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
27943155 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.1840772792 |
|
|
Aug 29 10:59:38 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
80937003 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.1924837187 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
18028230 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.4243474571 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
89811058 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2847540808 |
|
|
Aug 29 10:59:44 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
37987767 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.496225260 |
|
|
Aug 29 10:59:35 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
16579705 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.2468220861 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
30583081 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.3535139203 |
|
|
Aug 29 10:59:35 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
24373440 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3492202884 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
98691484 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1840129859 |
|
|
Aug 29 10:59:52 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
23602101 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.2450641467 |
|
|
Aug 29 10:59:35 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
67569246 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.2886648266 |
|
|
Aug 29 10:59:52 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
80066290 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.2344120168 |
|
|
Aug 29 10:59:35 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
55347302 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.67497542 |
|
|
Aug 29 10:59:52 AM UTC 24 |
Aug 29 10:59:57 AM UTC 24 |
15114674 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.2453012623 |
|
|
Aug 29 10:59:38 AM UTC 24 |
Aug 29 10:59:58 AM UTC 24 |
317329992 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3788221580 |
|
|
Aug 29 10:59:52 AM UTC 24 |
Aug 29 10:59:58 AM UTC 24 |
26086240 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1790544411 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:58 AM UTC 24 |
776750493 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.2872357250 |
|
|
Aug 29 10:59:52 AM UTC 24 |
Aug 29 10:59:58 AM UTC 24 |
323951570 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.3519673442 |
|
|
Aug 29 10:59:37 AM UTC 24 |
Aug 29 10:59:58 AM UTC 24 |
1424903144 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.226655804 |
|
|
Aug 29 10:59:57 AM UTC 24 |
Aug 29 10:59:58 AM UTC 24 |
64038651 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.2669775495 |
|
|
Aug 29 10:59:52 AM UTC 24 |
Aug 29 10:59:58 AM UTC 24 |
72176448 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.846332945 |
|
|
Aug 29 10:59:57 AM UTC 24 |
Aug 29 10:59:58 AM UTC 24 |
168281568 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2167540937 |
|
|
Aug 29 10:59:35 AM UTC 24 |
Aug 29 10:59:58 AM UTC 24 |
406702925 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.3972345187 |
|
|
Aug 29 10:59:57 AM UTC 24 |
Aug 29 10:59:58 AM UTC 24 |
49093877 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3902031705 |
|
|
Aug 29 10:59:57 AM UTC 24 |
Aug 29 10:59:59 AM UTC 24 |
174908840 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3696994302 |
|
|
Aug 29 10:59:43 AM UTC 24 |
Aug 29 10:59:59 AM UTC 24 |
15541403 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3064493218 |
|
|
Aug 29 10:59:43 AM UTC 24 |
Aug 29 10:59:59 AM UTC 24 |
393752840 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.3035675935 |
|
|
Aug 29 10:59:57 AM UTC 24 |
Aug 29 10:59:59 AM UTC 24 |
195972174 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.1833165093 |
|
|
Aug 29 10:59:43 AM UTC 24 |
Aug 29 10:59:59 AM UTC 24 |
89252809 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3146037258 |
|
|
Aug 29 10:59:59 AM UTC 24 |
Aug 29 11:00:01 AM UTC 24 |
86815215 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.1048015019 |
|
|
Aug 29 10:59:59 AM UTC 24 |
Aug 29 11:00:02 AM UTC 24 |
38239244 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.497377566 |
|
|
Aug 29 10:59:59 AM UTC 24 |
Aug 29 11:00:02 AM UTC 24 |
30243801 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1732820445 |
|
|
Aug 29 10:59:59 AM UTC 24 |
Aug 29 11:00:02 AM UTC 24 |
57264952 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.950838078 |
|
|
Aug 29 10:59:59 AM UTC 24 |
Aug 29 11:00:02 AM UTC 24 |
142237914 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.949372642 |
|
|
Aug 29 10:59:59 AM UTC 24 |
Aug 29 11:00:02 AM UTC 24 |
123198105 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.4119279760 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:05 AM UTC 24 |
13467266 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.468250361 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:05 AM UTC 24 |
14943201 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.3578531907 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
40956165 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.4138003231 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
90361742 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.91267130 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
151507002 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.2650988210 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
84411069 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.3474827169 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
16661861 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2689123504 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
77514915 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1880629416 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
79473365 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.345284946 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
15990563 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1132433369 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
27351760 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3029354308 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
206529910 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2079231703 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
23363993 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.3949926552 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
31211098 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1990476118 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
172506115 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1557177753 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
114763912 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1854336257 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
12341780 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.602164430 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
34168114 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2008744532 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
202106745 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.1311130873 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
55203887 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.2822746706 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
27181690 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.3191063703 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
27372787 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.3568732864 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
118666438 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1020391625 |
|
|
Aug 29 11:00:00 AM UTC 24 |
Aug 29 11:00:06 AM UTC 24 |
40023575 ps |