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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.59


Total test records in report: 1313
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T1256 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1488249837 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:06 AM UTC 24 86368266 ps
T1257 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3627407018 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:06 AM UTC 24 99837763 ps
T1258 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2226128323 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:06 AM UTC 24 28229791 ps
T1259 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1321540065 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:06 AM UTC 24 90030830 ps
T1260 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.866113495 Aug 29 11:00:01 AM UTC 24 Aug 29 11:00:07 AM UTC 24 28470405 ps
T1261 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.269671834 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:07 AM UTC 24 73712445 ps
T1262 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3619910103 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:07 AM UTC 24 93599238 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.2744637874 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:07 AM UTC 24 173479016 ps
T1263 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1374019697 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:07 AM UTC 24 21267050 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.1481042193 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:07 AM UTC 24 75372079 ps
T1264 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.3695228617 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:07 AM UTC 24 38302309 ps
T1265 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.818071094 Aug 29 11:00:04 AM UTC 24 Aug 29 11:00:07 AM UTC 24 38075075 ps
T1266 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.3015734690 Aug 29 11:00:03 AM UTC 24 Aug 29 11:00:07 AM UTC 24 13363727 ps
T1267 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2796427033 Aug 29 11:00:04 AM UTC 24 Aug 29 11:00:07 AM UTC 24 27252587 ps
T1268 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.500794449 Aug 29 11:00:04 AM UTC 24 Aug 29 11:00:07 AM UTC 24 18508804 ps
T1269 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.1899798342 Aug 29 11:00:04 AM UTC 24 Aug 29 11:00:07 AM UTC 24 32462995 ps
T1270 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.549844632 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:07 AM UTC 24 273326674 ps
T1271 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.2622808791 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:07 AM UTC 24 195688097 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.1885901543 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:07 AM UTC 24 516418372 ps
T1272 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.367086643 Aug 29 11:00:04 AM UTC 24 Aug 29 11:00:07 AM UTC 24 34778564 ps
T1273 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.39978465 Aug 29 11:00:04 AM UTC 24 Aug 29 11:00:07 AM UTC 24 152735738 ps
T1274 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.3371198446 Aug 29 11:00:00 AM UTC 24 Aug 29 11:00:07 AM UTC 24 341587052 ps
T1275 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.1465575297 Aug 29 11:00:03 AM UTC 24 Aug 29 11:00:07 AM UTC 24 56278908 ps
T1276 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3408279056 Aug 29 11:00:02 AM UTC 24 Aug 29 11:00:08 AM UTC 24 604521313 ps
T1277 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1438763274 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 26068843 ps
T1278 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2495208225 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 27268008 ps
T1279 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3472175771 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 46787505 ps
T1280 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3563764392 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 37689155 ps
T1281 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.3737521565 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 53469795 ps
T1282 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.572113408 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 34620296 ps
T1283 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.2220924998 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 15062210 ps
T1284 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.366929823 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 226843704 ps
T1285 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1449117442 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 40000537 ps
T1286 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.1926224264 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 30014111 ps
T1287 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2227250656 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 25312671 ps
T1288 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.985737578 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 43731024 ps
T1289 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.720130975 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 55056482 ps
T1290 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.2491722920 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 26639144 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.1057767358 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:16 AM UTC 24 687013883 ps
T1291 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2623223110 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:17 AM UTC 24 714163886 ps
T1292 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.692885617 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:22 AM UTC 24 51396379 ps
T1293 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2021251410 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:22 AM UTC 24 26960505 ps
T1294 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.2990215930 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:22 AM UTC 24 22834587 ps
T1295 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.3511465515 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:22 AM UTC 24 129055785 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.2368211487 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:22 AM UTC 24 17801932 ps
T1296 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3555306661 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:22 AM UTC 24 59143196 ps
T1297 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.354565161 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:26 AM UTC 24 31377804 ps
T1298 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3822998720 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:26 AM UTC 24 15108274 ps
T1299 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.596470384 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:26 AM UTC 24 28140127 ps
T1300 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3668430234 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:26 AM UTC 24 25238806 ps
T1301 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1093689865 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:26 AM UTC 24 13840606 ps
T1302 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2993946038 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:26 AM UTC 24 39462108 ps
T1303 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.856468509 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:26 AM UTC 24 31994322 ps
T1304 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.978632137 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:27 AM UTC 24 13260444 ps
T1305 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3920324364 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:27 AM UTC 24 21237644 ps
T1306 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.4262056407 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:27 AM UTC 24 43585157 ps
T1307 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2919572475 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:27 AM UTC 24 13474457 ps
T1308 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.533744455 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:27 AM UTC 24 52073370 ps
T1309 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1255427789 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:27 AM UTC 24 36864835 ps
T1310 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3139401604 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:27 AM UTC 24 16777705 ps
T1311 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.3863118734 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:27 AM UTC 24 13683730 ps
T1312 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.283477936 Aug 29 11:00:08 AM UTC 24 Aug 29 11:00:27 AM UTC 24 28590318 ps
T1313 /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2057016027 Aug 29 11:00:07 AM UTC 24 Aug 29 11:00:29 AM UTC 24 21461915 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_tx_rx.1375055871
Short name T6
Test name
Test status
Simulation time 65716733407 ps
CPU time 67.19 seconds
Started Aug 29 11:06:39 AM UTC 24
Finished Aug 29 11:07:48 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375055871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1375055871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.2103673467
Short name T19
Test name
Test status
Simulation time 803932412 ps
CPU time 10.24 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:06:40 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2103673467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_
with_rand_reset.2103673467
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_intr.1474092827
Short name T21
Test name
Test status
Simulation time 28261672851 ps
CPU time 18.12 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:06:49 AM UTC 24
Peak memory 208584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474092827 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1474092827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_stress_all.1528662194
Short name T112
Test name
Test status
Simulation time 767246567530 ps
CPU time 91.88 seconds
Started Aug 29 11:07:48 AM UTC 24
Finished Aug 29 11:09:22 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528662194 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1528662194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_stress_all.846792007
Short name T144
Test name
Test status
Simulation time 104515392019 ps
CPU time 279.33 seconds
Started Aug 29 11:07:37 AM UTC 24
Finished Aug 29 11:12:20 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846792007 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.846792007
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_stress_all.3051396213
Short name T138
Test name
Test status
Simulation time 421763763298 ps
CPU time 137.27 seconds
Started Aug 29 11:11:52 AM UTC 24
Finished Aug 29 11:14:11 AM UTC 24
Peak memory 217872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051396213 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3051396213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1296720628
Short name T20
Test name
Test status
Simulation time 4973595779 ps
CPU time 32.7 seconds
Started Aug 29 11:06:35 AM UTC 24
Finished Aug 29 11:07:10 AM UTC 24
Peak memory 223952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1296720628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_
with_rand_reset.1296720628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.182407723
Short name T386
Test name
Test status
Simulation time 108300488282 ps
CPU time 539.34 seconds
Started Aug 29 11:09:39 AM UTC 24
Finished Aug 29 11:18:45 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182407723 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.182407723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_fifo_full.3431478777
Short name T143
Test name
Test status
Simulation time 64483802034 ps
CPU time 36.79 seconds
Started Aug 29 11:11:20 AM UTC 24
Finished Aug 29 11:11:59 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431478777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3431478777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_stress_all.945355451
Short name T118
Test name
Test status
Simulation time 192133235816 ps
CPU time 140.76 seconds
Started Aug 29 11:10:06 AM UTC 24
Finished Aug 29 11:12:30 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945355451 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.945355451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_sec_cm.3549293147
Short name T3
Test name
Test status
Simulation time 60855406 ps
CPU time 0.77 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:06:30 AM UTC 24
Peak memory 238032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549293147 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3549293147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_fifo_full.896376519
Short name T30
Test name
Test status
Simulation time 95861215199 ps
CPU time 17.33 seconds
Started Aug 29 11:06:40 AM UTC 24
Finished Aug 29 11:06:58 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896376519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.896376519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_fifo_full.3465358264
Short name T279
Test name
Test status
Simulation time 171570366714 ps
CPU time 260.38 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:10:54 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465358264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3465358264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.1529067934
Short name T142
Test name
Test status
Simulation time 88260911014 ps
CPU time 98.99 seconds
Started Aug 29 11:09:03 AM UTC 24
Finished Aug 29 11:10:44 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529067934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1529067934
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_perf.610018667
Short name T303
Test name
Test status
Simulation time 17067525560 ps
CPU time 187.32 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:09:38 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610018667 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.610018667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3601129235
Short name T61
Test name
Test status
Simulation time 27820450 ps
CPU time 0.55 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:56 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601129235 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3601129235
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_fifo_reset.3536223572
Short name T135
Test name
Test status
Simulation time 111377898431 ps
CPU time 135.59 seconds
Started Aug 29 11:09:47 AM UTC 24
Finished Aug 29 11:12:05 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536223572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3536223572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.1197286951
Short name T276
Test name
Test status
Simulation time 37875658819 ps
CPU time 100.52 seconds
Started Aug 29 11:11:08 AM UTC 24
Finished Aug 29 11:12:51 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197286951 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1197286951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2534654753
Short name T16
Test name
Test status
Simulation time 82011350244 ps
CPU time 24.03 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:06:53 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534654753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2534654753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_tx_rx.144374955
Short name T297
Test name
Test status
Simulation time 83087675891 ps
CPU time 93.53 seconds
Started Aug 29 11:10:11 AM UTC 24
Finished Aug 29 11:11:46 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144374955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.144374955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.2645675860
Short name T5
Test name
Test status
Simulation time 22789645844 ps
CPU time 74.88 seconds
Started Aug 29 11:06:30 AM UTC 24
Finished Aug 29 11:07:47 AM UTC 24
Peak memory 208428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645675860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2645675860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_fifo_reset.1011309825
Short name T280
Test name
Test status
Simulation time 138049719475 ps
CPU time 65.2 seconds
Started Aug 29 11:07:25 AM UTC 24
Finished Aug 29 11:08:32 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011309825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1011309825
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_stress_all.2081967447
Short name T101
Test name
Test status
Simulation time 462731769810 ps
CPU time 310.41 seconds
Started Aug 29 11:07:00 AM UTC 24
Finished Aug 29 11:12:14 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081967447 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2081967447
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.950838078
Short name T84
Test name
Test status
Simulation time 142237914 ps
CPU time 1.12 seconds
Started Aug 29 10:59:59 AM UTC 24
Finished Aug 29 11:00:02 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950838078 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.950838078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.783725690
Short name T104
Test name
Test status
Simulation time 26721518177 ps
CPU time 40.1 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:07:10 AM UTC 24
Peak memory 208196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783725690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.783725690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_stress_all.3636505434
Short name T152
Test name
Test status
Simulation time 428821577401 ps
CPU time 301.61 seconds
Started Aug 29 11:10:38 AM UTC 24
Finished Aug 29 11:15:43 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636505434 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3636505434
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_fifo_reset.1932651354
Short name T131
Test name
Test status
Simulation time 206452400211 ps
CPU time 182.2 seconds
Started Aug 29 11:06:31 AM UTC 24
Finished Aug 29 11:09:36 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932651354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1932651354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_stress_all.522600624
Short name T102
Test name
Test status
Simulation time 661549394381 ps
CPU time 441.24 seconds
Started Aug 29 11:08:13 AM UTC 24
Finished Aug 29 11:15:39 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522600624 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.522600624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_alert_test.1842830184
Short name T2
Test name
Test status
Simulation time 12385628 ps
CPU time 0.52 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:06:30 AM UTC 24
Peak memory 204372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842830184 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1842830184
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2720100464
Short name T296
Test name
Test status
Simulation time 73996124680 ps
CPU time 242.14 seconds
Started Aug 29 11:08:03 AM UTC 24
Finished Aug 29 11:12:09 AM UTC 24
Peak memory 208376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720100464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2720100464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_noise_filter.1715004316
Short name T52
Test name
Test status
Simulation time 72968606660 ps
CPU time 85.53 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:07:56 AM UTC 24
Peak memory 208036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715004316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1715004316
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_fifo_full.610812237
Short name T150
Test name
Test status
Simulation time 94491604440 ps
CPU time 51.14 seconds
Started Aug 29 11:07:52 AM UTC 24
Finished Aug 29 11:08:45 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610812237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.610812237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.759603893
Short name T33
Test name
Test status
Simulation time 14483988539 ps
CPU time 73.81 seconds
Started Aug 29 11:06:30 AM UTC 24
Finished Aug 29 11:07:46 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=759603893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_w
ith_rand_reset.759603893
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_fifo_reset.1982213404
Short name T136
Test name
Test status
Simulation time 16466171485 ps
CPU time 64.58 seconds
Started Aug 29 11:11:59 AM UTC 24
Finished Aug 29 11:13:05 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982213404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1982213404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_stress_all.680827663
Short name T180
Test name
Test status
Simulation time 226697783496 ps
CPU time 177.93 seconds
Started Aug 29 11:09:19 AM UTC 24
Finished Aug 29 11:12:20 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680827663 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.680827663
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.3414632100
Short name T17
Test name
Test status
Simulation time 175129901774 ps
CPU time 43.62 seconds
Started Aug 29 11:06:40 AM UTC 24
Finished Aug 29 11:07:25 AM UTC 24
Peak memory 208436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414632100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3414632100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_tx_rx.71606706
Short name T349
Test name
Test status
Simulation time 108788123739 ps
CPU time 117.38 seconds
Started Aug 29 11:13:30 AM UTC 24
Finished Aug 29 11:15:29 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71606706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.71606706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.1096484156
Short name T114
Test name
Test status
Simulation time 26001038484 ps
CPU time 133.33 seconds
Started Aug 29 11:10:37 AM UTC 24
Finished Aug 29 11:12:52 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1096484156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all
_with_rand_reset.1096484156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_fifo_reset.434093960
Short name T202
Test name
Test status
Simulation time 187078734763 ps
CPU time 73.96 seconds
Started Aug 29 11:16:32 AM UTC 24
Finished Aug 29 11:17:48 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434093960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.434093960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_tx_rx.1771054934
Short name T267
Test name
Test status
Simulation time 53710018595 ps
CPU time 119.21 seconds
Started Aug 29 11:07:51 AM UTC 24
Finished Aug 29 11:09:53 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771054934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1771054934
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.1057767358
Short name T121
Test name
Test status
Simulation time 687013883 ps
CPU time 1.21 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057767358 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1057767358
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_tx_rx.1705338710
Short name T373
Test name
Test status
Simulation time 115807955574 ps
CPU time 91.31 seconds
Started Aug 29 11:13:04 AM UTC 24
Finished Aug 29 11:14:37 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705338710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1705338710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/217.uart_fifo_reset.15226985
Short name T244
Test name
Test status
Simulation time 23805568925 ps
CPU time 36.49 seconds
Started Aug 29 11:40:03 AM UTC 24
Finished Aug 29 11:40:41 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15226985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.15226985
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/217.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_fifo_reset.3209002037
Short name T171
Test name
Test status
Simulation time 86245149631 ps
CPU time 37.33 seconds
Started Aug 29 11:15:25 AM UTC 24
Finished Aug 29 11:16:03 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209002037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3209002037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/231.uart_fifo_reset.2693238987
Short name T262
Test name
Test status
Simulation time 207164314170 ps
CPU time 289.27 seconds
Started Aug 29 11:40:25 AM UTC 24
Finished Aug 29 11:45:19 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693238987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2693238987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/231.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/242.uart_fifo_reset.1932992037
Short name T154
Test name
Test status
Simulation time 15881215001 ps
CPU time 41.4 seconds
Started Aug 29 11:40:37 AM UTC 24
Finished Aug 29 11:41:20 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932992037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1932992037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/242.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_fifo_reset.3727279196
Short name T192
Test name
Test status
Simulation time 26898749478 ps
CPU time 33.61 seconds
Started Aug 29 11:12:39 AM UTC 24
Finished Aug 29 11:13:13 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727279196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3727279196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.835306426
Short name T492
Test name
Test status
Simulation time 17408503619 ps
CPU time 12.75 seconds
Started Aug 29 11:14:51 AM UTC 24
Finished Aug 29 11:15:05 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835306426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.835306426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_stress_all.327781452
Short name T183
Test name
Test status
Simulation time 145050628905 ps
CPU time 694.51 seconds
Started Aug 29 11:16:12 AM UTC 24
Finished Aug 29 11:27:54 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327781452 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.327781452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_intr.4216401731
Short name T105
Test name
Test status
Simulation time 51418274667 ps
CPU time 40.59 seconds
Started Aug 29 11:07:29 AM UTC 24
Finished Aug 29 11:08:12 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216401731 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.4216401731
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_stress_all.3333084606
Short name T109
Test name
Test status
Simulation time 339160737089 ps
CPU time 257.81 seconds
Started Aug 29 11:12:13 AM UTC 24
Finished Aug 29 11:16:34 AM UTC 24
Peak memory 217520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333084606 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3333084606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.4263023181
Short name T169
Test name
Test status
Simulation time 99523809849 ps
CPU time 161.37 seconds
Started Aug 29 11:28:12 AM UTC 24
Finished Aug 29 11:30:56 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263023181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.4263023181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/94.uart_fifo_reset.2728190340
Short name T159
Test name
Test status
Simulation time 19101201347 ps
CPU time 43.93 seconds
Started Aug 29 11:36:25 AM UTC 24
Finished Aug 29 11:37:11 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728190340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2728190340
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/94.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_fifo_full.2224978337
Short name T187
Test name
Test status
Simulation time 55121394563 ps
CPU time 28.28 seconds
Started Aug 29 11:13:04 AM UTC 24
Finished Aug 29 11:13:33 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224978337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2224978337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/188.uart_fifo_reset.1820714187
Short name T253
Test name
Test status
Simulation time 46155777716 ps
CPU time 60.57 seconds
Started Aug 29 11:39:27 AM UTC 24
Finished Aug 29 11:40:29 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820714187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1820714187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/188.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/227.uart_fifo_reset.3686319647
Short name T220
Test name
Test status
Simulation time 160063051491 ps
CPU time 211.54 seconds
Started Aug 29 11:40:23 AM UTC 24
Finished Aug 29 11:43:59 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686319647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3686319647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/227.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_fifo_reset.627131607
Short name T206
Test name
Test status
Simulation time 197951734905 ps
CPU time 207.75 seconds
Started Aug 29 11:26:53 AM UTC 24
Finished Aug 29 11:30:24 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627131607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.627131607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_intr.3554658911
Short name T106
Test name
Test status
Simulation time 80393983000 ps
CPU time 47.56 seconds
Started Aug 29 11:08:33 AM UTC 24
Finished Aug 29 11:09:22 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554658911 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3554658911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.3446446437
Short name T88
Test name
Test status
Simulation time 51873580353 ps
CPU time 36.34 seconds
Started Aug 29 11:09:39 AM UTC 24
Finished Aug 29 11:10:17 AM UTC 24
Peak memory 222012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3446446437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all
_with_rand_reset.3446446437
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/118.uart_fifo_reset.3133868228
Short name T231
Test name
Test status
Simulation time 13469663941 ps
CPU time 22.13 seconds
Started Aug 29 11:37:02 AM UTC 24
Finished Aug 29 11:37:25 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133868228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3133868228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/118.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.858723428
Short name T291
Test name
Test status
Simulation time 3354133512 ps
CPU time 68.17 seconds
Started Aug 29 11:11:13 AM UTC 24
Finished Aug 29 11:12:23 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=858723428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all_
with_rand_reset.858723428
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_fifo_reset.1922007026
Short name T194
Test name
Test status
Simulation time 44601842985 ps
CPU time 35.28 seconds
Started Aug 29 11:12:20 AM UTC 24
Finished Aug 29 11:12:57 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922007026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1922007026
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_stress_all.513569479
Short name T367
Test name
Test status
Simulation time 25140276178 ps
CPU time 47.78 seconds
Started Aug 29 11:13:01 AM UTC 24
Finished Aug 29 11:13:51 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513569479 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.513569479
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_fifo_reset.3846369419
Short name T408
Test name
Test status
Simulation time 112922972100 ps
CPU time 116.69 seconds
Started Aug 29 11:13:34 AM UTC 24
Finished Aug 29 11:15:33 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846369419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3846369419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/230.uart_fifo_reset.1395994147
Short name T258
Test name
Test status
Simulation time 75931224926 ps
CPU time 51.18 seconds
Started Aug 29 11:40:24 AM UTC 24
Finished Aug 29 11:41:18 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395994147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1395994147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/230.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/252.uart_fifo_reset.3652224656
Short name T261
Test name
Test status
Simulation time 98387343625 ps
CPU time 64.14 seconds
Started Aug 29 11:40:49 AM UTC 24
Finished Aug 29 11:41:55 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652224656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3652224656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/252.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/99.uart_fifo_reset.1490641245
Short name T218
Test name
Test status
Simulation time 141787789919 ps
CPU time 110.03 seconds
Started Aug 29 11:36:35 AM UTC 24
Finished Aug 29 11:38:27 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490641245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1490641245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/99.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.4092156819
Short name T11
Test name
Test status
Simulation time 848512727 ps
CPU time 2.93 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:06:34 AM UTC 24
Peak memory 207404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092156819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.4092156819
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_fifo_reset.3545390038
Short name T314
Test name
Test status
Simulation time 65379559251 ps
CPU time 285.06 seconds
Started Aug 29 11:09:24 AM UTC 24
Finished Aug 29 11:14:13 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545390038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3545390038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/106.uart_fifo_reset.4160203010
Short name T1058
Test name
Test status
Simulation time 86109628929 ps
CPU time 186.69 seconds
Started Aug 29 11:36:44 AM UTC 24
Finished Aug 29 11:39:53 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160203010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.4160203010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/106.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/112.uart_fifo_reset.124117316
Short name T209
Test name
Test status
Simulation time 98240684112 ps
CPU time 106.25 seconds
Started Aug 29 11:36:57 AM UTC 24
Finished Aug 29 11:38:45 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124117316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.124117316
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/112.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/117.uart_fifo_reset.193650382
Short name T1172
Test name
Test status
Simulation time 183313217031 ps
CPU time 569.37 seconds
Started Aug 29 11:37:01 AM UTC 24
Finished Aug 29 11:46:37 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193650382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.193650382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/117.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/128.uart_fifo_reset.1405726287
Short name T254
Test name
Test status
Simulation time 71951813236 ps
CPU time 66.64 seconds
Started Aug 29 11:37:27 AM UTC 24
Finished Aug 29 11:38:36 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405726287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1405726287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/128.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/139.uart_fifo_reset.3674286001
Short name T229
Test name
Test status
Simulation time 15538825465 ps
CPU time 14.45 seconds
Started Aug 29 11:37:42 AM UTC 24
Finished Aug 29 11:37:57 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674286001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3674286001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/139.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/144.uart_fifo_reset.2092027694
Short name T242
Test name
Test status
Simulation time 23588013506 ps
CPU time 68.87 seconds
Started Aug 29 11:37:50 AM UTC 24
Finished Aug 29 11:39:00 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092027694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2092027694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/144.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_intr.2807800578
Short name T404
Test name
Test status
Simulation time 8066733554 ps
CPU time 8.16 seconds
Started Aug 29 11:12:02 AM UTC 24
Finished Aug 29 11:12:11 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807800578 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2807800578
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2632453469
Short name T235
Test name
Test status
Simulation time 128098883168 ps
CPU time 32.5 seconds
Started Aug 29 11:39:47 AM UTC 24
Finished Aug 29 11:40:20 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632453469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2632453469
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/206.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3289783027
Short name T247
Test name
Test status
Simulation time 126941736519 ps
CPU time 61.4 seconds
Started Aug 29 11:39:53 AM UTC 24
Finished Aug 29 11:40:56 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289783027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3289783027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/211.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/226.uart_fifo_reset.1637406614
Short name T256
Test name
Test status
Simulation time 128965712419 ps
CPU time 170.72 seconds
Started Aug 29 11:40:19 AM UTC 24
Finished Aug 29 11:43:14 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637406614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1637406614
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/226.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/269.uart_fifo_reset.2514027697
Short name T245
Test name
Test status
Simulation time 116579524091 ps
CPU time 80.61 seconds
Started Aug 29 11:41:18 AM UTC 24
Finished Aug 29 11:42:40 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514027697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2514027697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/269.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.3734431016
Short name T93
Test name
Test status
Simulation time 8936502926 ps
CPU time 35.99 seconds
Started Aug 29 11:18:46 AM UTC 24
Finished Aug 29 11:19:23 AM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3734431016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all
_with_rand_reset.3734431016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2460293368
Short name T252
Test name
Test status
Simulation time 61231215807 ps
CPU time 27.37 seconds
Started Aug 29 11:41:36 AM UTC 24
Finished Aug 29 11:42:05 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460293368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2460293368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/284.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/299.uart_fifo_reset.2106575750
Short name T174
Test name
Test status
Simulation time 52516895277 ps
CPU time 75.27 seconds
Started Aug 29 11:41:56 AM UTC 24
Finished Aug 29 11:43:13 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106575750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2106575750
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/299.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_stress_all.540651506
Short name T259
Test name
Test status
Simulation time 96133054997 ps
CPU time 1129.67 seconds
Started Aug 29 11:27:29 AM UTC 24
Finished Aug 29 11:46:32 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540651506 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.540651506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_fifo_reset.2238439699
Short name T186
Test name
Test status
Simulation time 175121214481 ps
CPU time 435.39 seconds
Started Aug 29 11:32:43 AM UTC 24
Finished Aug 29 11:40:03 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238439699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2238439699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/66.uart_fifo_reset.3030139546
Short name T234
Test name
Test status
Simulation time 167056779347 ps
CPU time 158.73 seconds
Started Aug 29 11:34:32 AM UTC 24
Finished Aug 29 11:37:13 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030139546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3030139546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/66.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/76.uart_fifo_reset.2061272810
Short name T214
Test name
Test status
Simulation time 50789418936 ps
CPU time 102.07 seconds
Started Aug 29 11:35:10 AM UTC 24
Finished Aug 29 11:36:55 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061272810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2061272810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/76.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.1191200282
Short name T57
Test name
Test status
Simulation time 19153443 ps
CPU time 0.67 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:46 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191200282 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1191200282
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.387674333
Short name T58
Test name
Test status
Simulation time 212283464 ps
CPU time 1.97 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:47 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387674333 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.387674333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.2450641467
Short name T1211
Test name
Test status
Simulation time 67569246 ps
CPU time 0.51 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450641467 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2450641467
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2963652435
Short name T1198
Test name
Test status
Simulation time 133120708 ps
CPU time 0.88 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 200136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2963652435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r
eset.2963652435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.496225260
Short name T1207
Test name
Test status
Simulation time 16579705 ps
CPU time 0.52 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496225260 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.496225260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.3535139203
Short name T1209
Test name
Test status
Simulation time 24373440 ps
CPU time 0.5 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535139203 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3535139203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3030376493
Short name T70
Test name
Test status
Simulation time 54409622 ps
CPU time 0.54 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:46 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030376493 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.3030376493
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2167540937
Short name T1220
Test name
Test status
Simulation time 406702925 ps
CPU time 1.81 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 203752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167540937 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2167540937
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.2344120168
Short name T83
Test name
Test status
Simulation time 55347302 ps
CPU time 0.93 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344120168 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2344120168
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.3753021855
Short name T62
Test name
Test status
Simulation time 21419175 ps
CPU time 0.61 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:56 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753021855 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3753021855
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3492202884
Short name T1210
Test name
Test status
Simulation time 98691484 ps
CPU time 1.45 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492202884 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3492202884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.4275638783
Short name T60
Test name
Test status
Simulation time 54778991 ps
CPU time 0.52 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:56 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275638783 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.4275638783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3242639471
Short name T1200
Test name
Test status
Simulation time 23739049 ps
CPU time 0.89 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3242639471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_r
eset.3242639471
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.615308830
Short name T1195
Test name
Test status
Simulation time 21446489 ps
CPU time 0.51 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:56 AM UTC 24
Peak memory 200196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615308830 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.615308830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.3390191265
Short name T75
Test name
Test status
Simulation time 72845117 ps
CPU time 0.59 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:56 AM UTC 24
Peak memory 201716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390191265 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.3390191265
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1790544411
Short name T1215
Test name
Test status
Simulation time 776750493 ps
CPU time 1.93 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 201580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790544411 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1790544411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2853308142
Short name T78
Test name
Test status
Simulation time 93148220 ps
CPU time 0.88 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853308142 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2853308142
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2689123504
Short name T1239
Test name
Test status
Simulation time 77514915 ps
CPU time 0.94 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 205672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2689123504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_
reset.2689123504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.468250361
Short name T1233
Test name
Test status
Simulation time 14943201 ps
CPU time 0.59 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:05 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468250361 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.468250361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.4119279760
Short name T1232
Test name
Test status
Simulation time 13467266 ps
CPU time 0.52 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:05 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119279760 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.4119279760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.4138003231
Short name T1235
Test name
Test status
Simulation time 90361742 ps
CPU time 0.66 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138003231 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.4138003231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.640559613
Short name T1203
Test name
Test status
Simulation time 27943155 ps
CPU time 1.19 seconds
Started Aug 29 10:59:59 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 203624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640559613 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.640559613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.2650988210
Short name T1237
Test name
Test status
Simulation time 84411069 ps
CPU time 0.89 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650988210 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2650988210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1990476118
Short name T1246
Test name
Test status
Simulation time 172506115 ps
CPU time 1.1 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 203624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1990476118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_
reset.1990476118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.91267130
Short name T1236
Test name
Test status
Simulation time 151507002 ps
CPU time 0.55 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91267130 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.91267130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.3578531907
Short name T1234
Test name
Test status
Simulation time 40956165 ps
CPU time 0.48 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 200732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578531907 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3578531907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1880629416
Short name T1240
Test name
Test status
Simulation time 79473365 ps
CPU time 0.64 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880629416 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.1880629416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2008744532
Short name T1250
Test name
Test status
Simulation time 202106745 ps
CPU time 1.17 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 200716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008744532 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2008744532
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.3568732864
Short name T1254
Test name
Test status
Simulation time 118666438 ps
CPU time 1.17 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568732864 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3568732864
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2079231703
Short name T1244
Test name
Test status
Simulation time 23363993 ps
CPU time 0.62 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2079231703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_
reset.2079231703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.2468220861
Short name T1208
Test name
Test status
Simulation time 30583081 ps
CPU time 0.57 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468220861 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2468220861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.3474827169
Short name T1238
Test name
Test status
Simulation time 16661861 ps
CPU time 0.51 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474827169 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3474827169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.345284946
Short name T1241
Test name
Test status
Simulation time 15990563 ps
CPU time 0.54 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345284946 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.345284946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.2622808791
Short name T1271
Test name
Test status
Simulation time 195688097 ps
CPU time 1.82 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622808791 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2622808791
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.2744637874
Short name T119
Test name
Test status
Simulation time 173479016 ps
CPU time 1.3 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744637874 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2744637874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1557177753
Short name T1247
Test name
Test status
Simulation time 114763912 ps
CPU time 0.59 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1557177753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_
reset.1557177753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.1924837187
Short name T1205
Test name
Test status
Simulation time 18028230 ps
CPU time 0.52 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924837187 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1924837187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1132433369
Short name T1242
Test name
Test status
Simulation time 27351760 ps
CPU time 0.52 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132433369 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1132433369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.3949926552
Short name T1245
Test name
Test status
Simulation time 31211098 ps
CPU time 0.57 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 200916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949926552 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.3949926552
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1020391625
Short name T1255
Test name
Test status
Simulation time 40023575 ps
CPU time 1.02 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020391625 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1020391625
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.1481042193
Short name T85
Test name
Test status
Simulation time 75372079 ps
CPU time 1.15 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481042193 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1481042193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1488249837
Short name T1256
Test name
Test status
Simulation time 86368266 ps
CPU time 0.63 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1488249837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_
reset.1488249837
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3029354308
Short name T1243
Test name
Test status
Simulation time 206529910 ps
CPU time 0.53 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029354308 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3029354308
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1854336257
Short name T1248
Test name
Test status
Simulation time 12341780 ps
CPU time 0.51 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854336257 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1854336257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1321540065
Short name T1259
Test name
Test status
Simulation time 90030830 ps
CPU time 0.67 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321540065 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.1321540065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.3371198446
Short name T1274
Test name
Test status
Simulation time 341587052 ps
CPU time 1.55 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371198446 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3371198446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3619910103
Short name T1262
Test name
Test status
Simulation time 93599238 ps
CPU time 0.83 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619910103 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3619910103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3627407018
Short name T1257
Test name
Test status
Simulation time 99837763 ps
CPU time 0.67 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3627407018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_
reset.3627407018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.1311130873
Short name T1251
Test name
Test status
Simulation time 55203887 ps
CPU time 0.53 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311130873 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1311130873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.602164430
Short name T1249
Test name
Test status
Simulation time 34168114 ps
CPU time 0.51 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602164430 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.602164430
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2226128323
Short name T1258
Test name
Test status
Simulation time 28229791 ps
CPU time 0.68 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226128323 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.2226128323
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.549844632
Short name T1270
Test name
Test status
Simulation time 273326674 ps
CPU time 1.29 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549844632 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.549844632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.1885901543
Short name T120
Test name
Test status
Simulation time 516418372 ps
CPU time 1.28 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885901543 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1885901543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.866113495
Short name T1260
Test name
Test status
Simulation time 28470405 ps
CPU time 0.77 seconds
Started Aug 29 11:00:01 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=866113495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_r
eset.866113495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.3191063703
Short name T1253
Test name
Test status
Simulation time 27372787 ps
CPU time 0.57 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191063703 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3191063703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.2822746706
Short name T1252
Test name
Test status
Simulation time 27181690 ps
CPU time 0.47 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:06 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822746706 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2822746706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1374019697
Short name T1263
Test name
Test status
Simulation time 21267050 ps
CPU time 0.57 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374019697 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.1374019697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.3695228617
Short name T1264
Test name
Test status
Simulation time 38302309 ps
CPU time 1.02 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695228617 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3695228617
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.269671834
Short name T1261
Test name
Test status
Simulation time 73712445 ps
CPU time 0.81 seconds
Started Aug 29 11:00:00 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269671834 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.269671834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.500794449
Short name T1268
Test name
Test status
Simulation time 18508804 ps
CPU time 0.57 seconds
Started Aug 29 11:00:04 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 199252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=500794449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_r
eset.500794449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2796427033
Short name T1267
Test name
Test status
Simulation time 27252587 ps
CPU time 0.52 seconds
Started Aug 29 11:00:04 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 200304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796427033 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2796427033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.3015734690
Short name T1266
Test name
Test status
Simulation time 13363727 ps
CPU time 0.52 seconds
Started Aug 29 11:00:03 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015734690 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3015734690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.1899798342
Short name T1269
Test name
Test status
Simulation time 32462995 ps
CPU time 0.7 seconds
Started Aug 29 11:00:04 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899798342 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.1899798342
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3408279056
Short name T1276
Test name
Test status
Simulation time 604521313 ps
CPU time 1.75 seconds
Started Aug 29 11:00:02 AM UTC 24
Finished Aug 29 11:00:08 AM UTC 24
Peak memory 201612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408279056 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3408279056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.1465575297
Short name T1275
Test name
Test status
Simulation time 56278908 ps
CPU time 0.85 seconds
Started Aug 29 11:00:03 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465575297 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1465575297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3472175771
Short name T1279
Test name
Test status
Simulation time 46787505 ps
CPU time 0.59 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3472175771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_
reset.3472175771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3563764392
Short name T1280
Test name
Test status
Simulation time 37689155 ps
CPU time 0.58 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563764392 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3563764392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.818071094
Short name T1265
Test name
Test status
Simulation time 38075075 ps
CPU time 0.49 seconds
Started Aug 29 11:00:04 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818071094 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.818071094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.3737521565
Short name T1281
Test name
Test status
Simulation time 53469795 ps
CPU time 0.69 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737521565 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.3737521565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.367086643
Short name T1272
Test name
Test status
Simulation time 34778564 ps
CPU time 0.81 seconds
Started Aug 29 11:00:04 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 199908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367086643 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.367086643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.39978465
Short name T1273
Test name
Test status
Simulation time 152735738 ps
CPU time 0.84 seconds
Started Aug 29 11:00:04 AM UTC 24
Finished Aug 29 11:00:07 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39978465 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.39978465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3555306661
Short name T1296
Test name
Test status
Simulation time 59143196 ps
CPU time 0.76 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 201384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3555306661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_
reset.3555306661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.2368211487
Short name T67
Test name
Test status
Simulation time 17801932 ps
CPU time 0.65 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368211487 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2368211487
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2495208225
Short name T1278
Test name
Test status
Simulation time 27268008 ps
CPU time 0.48 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495208225 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2495208225
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.692885617
Short name T1292
Test name
Test status
Simulation time 51396379 ps
CPU time 0.67 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 203676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692885617 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.692885617
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2623223110
Short name T1291
Test name
Test status
Simulation time 714163886 ps
CPU time 1.78 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:17 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623223110 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2623223110
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3875644633
Short name T59
Test name
Test status
Simulation time 33155431 ps
CPU time 0.66 seconds
Started Aug 29 10:59:38 AM UTC 24
Finished Aug 29 10:59:55 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875644633 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3875644633
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.2387776051
Short name T1194
Test name
Test status
Simulation time 70124681 ps
CPU time 1.2 seconds
Started Aug 29 10:59:38 AM UTC 24
Finished Aug 29 10:59:56 AM UTC 24
Peak memory 201832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387776051 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2387776051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.1119255811
Short name T1192
Test name
Test status
Simulation time 16604752 ps
CPU time 0.5 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:55 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119255811 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1119255811
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.193989166
Short name T1202
Test name
Test status
Simulation time 17884972 ps
CPU time 0.66 seconds
Started Aug 29 10:59:38 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=193989166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_re
set.193989166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3381132610
Short name T63
Test name
Test status
Simulation time 33768069 ps
CPU time 0.6 seconds
Started Aug 29 10:59:38 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381132610 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3381132610
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.4221314804
Short name T1196
Test name
Test status
Simulation time 23280433 ps
CPU time 0.48 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:56 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221314804 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.4221314804
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.4249290551
Short name T74
Test name
Test status
Simulation time 59534269 ps
CPU time 0.62 seconds
Started Aug 29 10:59:38 AM UTC 24
Finished Aug 29 10:59:56 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249290551 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.4249290551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.3519673442
Short name T1216
Test name
Test status
Simulation time 1424903144 ps
CPU time 2 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 201580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519673442 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3519673442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.4243474571
Short name T82
Test name
Test status
Simulation time 89811058 ps
CPU time 1.17 seconds
Started Aug 29 10:59:37 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243474571 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.4243474571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2021251410
Short name T1293
Test name
Test status
Simulation time 26960505 ps
CPU time 0.5 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021251410 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2021251410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.2990215930
Short name T1294
Test name
Test status
Simulation time 22834587 ps
CPU time 0.49 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990215930 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2990215930
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.3511465515
Short name T1295
Test name
Test status
Simulation time 129055785 ps
CPU time 0.56 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 201372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511465515 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3511465515
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1438763274
Short name T1277
Test name
Test status
Simulation time 26068843 ps
CPU time 0.47 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438763274 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1438763274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2057016027
Short name T1313
Test name
Test status
Simulation time 21461915 ps
CPU time 0.67 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:29 AM UTC 24
Peak memory 201500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057016027 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2057016027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.572113408
Short name T1282
Test name
Test status
Simulation time 34620296 ps
CPU time 0.51 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572113408 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.572113408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.1926224264
Short name T1286
Test name
Test status
Simulation time 30014111 ps
CPU time 0.51 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926224264 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1926224264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.366929823
Short name T1284
Test name
Test status
Simulation time 226843704 ps
CPU time 0.52 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366929823 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.366929823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.2220924998
Short name T1283
Test name
Test status
Simulation time 15062210 ps
CPU time 0.49 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220924998 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2220924998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.985737578
Short name T1288
Test name
Test status
Simulation time 43731024 ps
CPU time 0.5 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985737578 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.985737578
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.1424802948
Short name T1183
Test name
Test status
Simulation time 14261864 ps
CPU time 0.54 seconds
Started Aug 29 10:59:40 AM UTC 24
Finished Aug 29 10:59:42 AM UTC 24
Peak memory 201828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424802948 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1424802948
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2138023424
Short name T65
Test name
Test status
Simulation time 211376882 ps
CPU time 2.02 seconds
Started Aug 29 10:59:40 AM UTC 24
Finished Aug 29 10:59:43 AM UTC 24
Peak memory 202884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138023424 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2138023424
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.411168866
Short name T64
Test name
Test status
Simulation time 15051506 ps
CPU time 0.55 seconds
Started Aug 29 10:59:38 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411168866 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.411168866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2590618380
Short name T1184
Test name
Test status
Simulation time 116289439 ps
CPU time 0.67 seconds
Started Aug 29 10:59:40 AM UTC 24
Finished Aug 29 10:59:42 AM UTC 24
Peak memory 201636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2590618380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r
eset.2590618380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2393531198
Short name T55
Test name
Test status
Simulation time 144337811 ps
CPU time 0.56 seconds
Started Aug 29 10:59:39 AM UTC 24
Finished Aug 29 10:59:42 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393531198 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2393531198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.517085584
Short name T1201
Test name
Test status
Simulation time 12900904 ps
CPU time 0.51 seconds
Started Aug 29 10:59:38 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517085584 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.517085584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1971903703
Short name T69
Test name
Test status
Simulation time 33268560 ps
CPU time 0.53 seconds
Started Aug 29 10:59:40 AM UTC 24
Finished Aug 29 10:59:42 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971903703 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.1971903703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.1840772792
Short name T1204
Test name
Test status
Simulation time 80937003 ps
CPU time 2.11 seconds
Started Aug 29 10:59:38 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 204780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840772792 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1840772792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.2453012623
Short name T80
Test name
Test status
Simulation time 317329992 ps
CPU time 1.28 seconds
Started Aug 29 10:59:38 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 201652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453012623 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2453012623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1449117442
Short name T1285
Test name
Test status
Simulation time 40000537 ps
CPU time 0.48 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449117442 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1449117442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.720130975
Short name T1289
Test name
Test status
Simulation time 55056482 ps
CPU time 0.56 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720130975 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.720130975
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2227250656
Short name T1287
Test name
Test status
Simulation time 25312671 ps
CPU time 0.53 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227250656 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2227250656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.2491722920
Short name T1290
Test name
Test status
Simulation time 26639144 ps
CPU time 0.5 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:16 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491722920 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2491722920
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3668430234
Short name T1300
Test name
Test status
Simulation time 25238806 ps
CPU time 0.54 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668430234 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3668430234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.596470384
Short name T1299
Test name
Test status
Simulation time 28140127 ps
CPU time 0.52 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596470384 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.596470384
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.354565161
Short name T1297
Test name
Test status
Simulation time 31377804 ps
CPU time 0.49 seconds
Started Aug 29 11:00:07 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354565161 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.354565161
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2993946038
Short name T1302
Test name
Test status
Simulation time 39462108 ps
CPU time 0.65 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993946038 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2993946038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3822998720
Short name T1298
Test name
Test status
Simulation time 15108274 ps
CPU time 0.55 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 201464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822998720 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3822998720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3920324364
Short name T1305
Test name
Test status
Simulation time 21237644 ps
CPU time 0.69 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920324364 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3920324364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.3279075855
Short name T1189
Test name
Test status
Simulation time 59928985 ps
CPU time 0.67 seconds
Started Aug 29 10:59:43 AM UTC 24
Finished Aug 29 10:59:52 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279075855 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3279075855
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.763153140
Short name T1191
Test name
Test status
Simulation time 183373911 ps
CPU time 1.34 seconds
Started Aug 29 10:59:43 AM UTC 24
Finished Aug 29 10:59:53 AM UTC 24
Peak memory 200004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763153140 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.763153140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.313735198
Short name T56
Test name
Test status
Simulation time 39018988 ps
CPU time 0.47 seconds
Started Aug 29 10:59:40 AM UTC 24
Finished Aug 29 10:59:42 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313735198 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.313735198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3743929431
Short name T1190
Test name
Test status
Simulation time 30297335 ps
CPU time 0.73 seconds
Started Aug 29 10:59:43 AM UTC 24
Finished Aug 29 10:59:52 AM UTC 24
Peak memory 201636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3743929431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_r
eset.3743929431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.676364391
Short name T72
Test name
Test status
Simulation time 14169642 ps
CPU time 0.48 seconds
Started Aug 29 10:59:43 AM UTC 24
Finished Aug 29 10:59:52 AM UTC 24
Peak memory 199996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676364391 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.676364391
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.1239538012
Short name T1187
Test name
Test status
Simulation time 13353960 ps
CPU time 0.49 seconds
Started Aug 29 10:59:40 AM UTC 24
Finished Aug 29 10:59:51 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239538012 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1239538012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2281536435
Short name T73
Test name
Test status
Simulation time 121931685 ps
CPU time 0.64 seconds
Started Aug 29 10:59:43 AM UTC 24
Finished Aug 29 10:59:52 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281536435 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.2281536435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.186353665
Short name T1185
Test name
Test status
Simulation time 77829456 ps
CPU time 1.4 seconds
Started Aug 29 10:59:40 AM UTC 24
Finished Aug 29 10:59:43 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186353665 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.186353665
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.1047671524
Short name T77
Test name
Test status
Simulation time 54273132 ps
CPU time 0.81 seconds
Started Aug 29 10:59:40 AM UTC 24
Finished Aug 29 10:59:42 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047671524 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1047671524
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.978632137
Short name T1304
Test name
Test status
Simulation time 13260444 ps
CPU time 0.61 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978632137 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.978632137
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.4262056407
Short name T1306
Test name
Test status
Simulation time 43585157 ps
CPU time 0.59 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262056407 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.4262056407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1093689865
Short name T1301
Test name
Test status
Simulation time 13840606 ps
CPU time 0.52 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093689865 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1093689865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.856468509
Short name T1303
Test name
Test status
Simulation time 31994322 ps
CPU time 0.6 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856468509 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.856468509
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1255427789
Short name T1309
Test name
Test status
Simulation time 36864835 ps
CPU time 0.62 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 201652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255427789 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1255427789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.533744455
Short name T1308
Test name
Test status
Simulation time 52073370 ps
CPU time 0.64 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 201608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533744455 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.533744455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.283477936
Short name T1312
Test name
Test status
Simulation time 28590318 ps
CPU time 0.66 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283477936 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.283477936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2919572475
Short name T1307
Test name
Test status
Simulation time 13474457 ps
CPU time 0.57 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 201592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919572475 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2919572475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.3863118734
Short name T1311
Test name
Test status
Simulation time 13683730 ps
CPU time 0.51 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 201436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863118734 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3863118734
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3139401604
Short name T1310
Test name
Test status
Simulation time 16777705 ps
CPU time 0.56 seconds
Started Aug 29 11:00:08 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139401604 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3139401604
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3474520675
Short name T1186
Test name
Test status
Simulation time 17183332 ps
CPU time 0.52 seconds
Started Aug 29 10:59:46 AM UTC 24
Finished Aug 29 10:59:51 AM UTC 24
Peak memory 201636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3474520675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r
eset.3474520675
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2847540808
Short name T1206
Test name
Test status
Simulation time 37987767 ps
CPU time 0.5 seconds
Started Aug 29 10:59:44 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847540808 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2847540808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3696994302
Short name T1223
Test name
Test status
Simulation time 15541403 ps
CPU time 0.5 seconds
Started Aug 29 10:59:43 AM UTC 24
Finished Aug 29 10:59:59 AM UTC 24
Peak memory 199740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696994302 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3696994302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1102895844
Short name T71
Test name
Test status
Simulation time 58958868 ps
CPU time 0.55 seconds
Started Aug 29 10:59:46 AM UTC 24
Finished Aug 29 10:59:51 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102895844 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.1102895844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.1833165093
Short name T1226
Test name
Test status
Simulation time 89252809 ps
CPU time 0.94 seconds
Started Aug 29 10:59:43 AM UTC 24
Finished Aug 29 10:59:59 AM UTC 24
Peak memory 201748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833165093 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1833165093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3064493218
Short name T1224
Test name
Test status
Simulation time 393752840 ps
CPU time 0.85 seconds
Started Aug 29 10:59:43 AM UTC 24
Finished Aug 29 10:59:59 AM UTC 24
Peak memory 199472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064493218 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3064493218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3788221580
Short name T1214
Test name
Test status
Simulation time 26086240 ps
CPU time 0.7 seconds
Started Aug 29 10:59:52 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 201636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3788221580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_r
eset.3788221580
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1840129859
Short name T68
Test name
Test status
Simulation time 23602101 ps
CPU time 0.56 seconds
Started Aug 29 10:59:52 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840129859 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1840129859
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.2040080717
Short name T1193
Test name
Test status
Simulation time 33902432 ps
CPU time 0.48 seconds
Started Aug 29 10:59:51 AM UTC 24
Finished Aug 29 10:59:56 AM UTC 24
Peak memory 201508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040080717 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2040080717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.2886648266
Short name T1212
Test name
Test status
Simulation time 80066290 ps
CPU time 0.67 seconds
Started Aug 29 10:59:52 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886648266 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.2886648266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3134777394
Short name T1188
Test name
Test status
Simulation time 256566956 ps
CPU time 1.26 seconds
Started Aug 29 10:59:48 AM UTC 24
Finished Aug 29 10:59:52 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134777394 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3134777394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.27736624
Short name T79
Test name
Test status
Simulation time 91013214 ps
CPU time 1.18 seconds
Started Aug 29 10:59:51 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27736624 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.27736624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.226655804
Short name T1217
Test name
Test status
Simulation time 64038651 ps
CPU time 0.64 seconds
Started Aug 29 10:59:57 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 201640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=226655804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_re
set.226655804
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.1350715497
Short name T1197
Test name
Test status
Simulation time 39401201 ps
CPU time 0.49 seconds
Started Aug 29 10:59:53 AM UTC 24
Finished Aug 29 10:59:56 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350715497 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1350715497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.67497542
Short name T1213
Test name
Test status
Simulation time 15114674 ps
CPU time 0.56 seconds
Started Aug 29 10:59:52 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67497542 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.67497542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.3972345187
Short name T1221
Test name
Test status
Simulation time 49093877 ps
CPU time 0.79 seconds
Started Aug 29 10:59:57 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972345187 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.3972345187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.2669775495
Short name T1218
Test name
Test status
Simulation time 72176448 ps
CPU time 1.5 seconds
Started Aug 29 10:59:52 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 203796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669775495 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2669775495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.2872357250
Short name T81
Test name
Test status
Simulation time 323951570 ps
CPU time 1.11 seconds
Started Aug 29 10:59:52 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872357250 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2872357250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3146037258
Short name T1227
Test name
Test status
Simulation time 86815215 ps
CPU time 0.64 seconds
Started Aug 29 10:59:59 AM UTC 24
Finished Aug 29 11:00:01 AM UTC 24
Peak memory 200264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3146037258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r
eset.3146037258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.3975642914
Short name T1199
Test name
Test status
Simulation time 30338412 ps
CPU time 0.52 seconds
Started Aug 29 10:59:59 AM UTC 24
Finished Aug 29 11:00:01 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975642914 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3975642914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.846332945
Short name T1219
Test name
Test status
Simulation time 168281568 ps
CPU time 0.49 seconds
Started Aug 29 10:59:57 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846332945 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.846332945
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.3990791919
Short name T76
Test name
Test status
Simulation time 29651206 ps
CPU time 0.69 seconds
Started Aug 29 10:59:59 AM UTC 24
Finished Aug 29 11:00:01 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990791919 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.3990791919
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.3035675935
Short name T1225
Test name
Test status
Simulation time 195972174 ps
CPU time 1.57 seconds
Started Aug 29 10:59:57 AM UTC 24
Finished Aug 29 10:59:59 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035675935 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3035675935
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3902031705
Short name T1222
Test name
Test status
Simulation time 174908840 ps
CPU time 0.87 seconds
Started Aug 29 10:59:57 AM UTC 24
Finished Aug 29 10:59:59 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902031705 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3902031705
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1732820445
Short name T1230
Test name
Test status
Simulation time 57264952 ps
CPU time 0.68 seconds
Started Aug 29 10:59:59 AM UTC 24
Finished Aug 29 11:00:02 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1732820445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r
eset.1732820445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.3367757378
Short name T66
Test name
Test status
Simulation time 41097823 ps
CPU time 0.54 seconds
Started Aug 29 10:59:59 AM UTC 24
Finished Aug 29 11:00:01 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367757378 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3367757378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.497377566
Short name T1229
Test name
Test status
Simulation time 30243801 ps
CPU time 0.55 seconds
Started Aug 29 10:59:59 AM UTC 24
Finished Aug 29 11:00:02 AM UTC 24
Peak memory 201680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497377566 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.497377566
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.1048015019
Short name T1228
Test name
Test status
Simulation time 38239244 ps
CPU time 0.6 seconds
Started Aug 29 10:59:59 AM UTC 24
Finished Aug 29 11:00:02 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048015019 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.1048015019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.949372642
Short name T1231
Test name
Test status
Simulation time 123198105 ps
CPU time 1.33 seconds
Started Aug 29 10:59:59 AM UTC 24
Finished Aug 29 11:00:02 AM UTC 24
Peak memory 203788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949372642 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.949372642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_fifo_full.2199959648
Short name T285
Test name
Test status
Simulation time 153540846376 ps
CPU time 71.28 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:07:41 AM UTC 24
Peak memory 208148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199959648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2199959648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_intr.773880411
Short name T46
Test name
Test status
Simulation time 18729635160 ps
CPU time 30.91 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:07:00 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773880411 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.773880411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.1507381738
Short name T642
Test name
Test status
Simulation time 131045679857 ps
CPU time 960.89 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:22:40 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507381738 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1507381738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_loopback.981112637
Short name T4
Test name
Test status
Simulation time 1761468720 ps
CPU time 1.51 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:06:31 AM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981112637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.uart_loopback.981112637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_rx_oversample.3982699834
Short name T51
Test name
Test status
Simulation time 7401399138 ps
CPU time 68.48 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:07:38 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982699834 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3982699834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.1524828001
Short name T98
Test name
Test status
Simulation time 24772653061 ps
CPU time 43.94 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:07:13 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524828001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1524828001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.3218423904
Short name T42
Test name
Test status
Simulation time 43365103531 ps
CPU time 15.51 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:06:45 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218423904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3218423904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_smoke.192985753
Short name T1
Test name
Test status
Simulation time 295990897 ps
CPU time 1.07 seconds
Started Aug 29 11:06:26 AM UTC 24
Finished Aug 29 11:06:29 AM UTC 24
Peak memory 206644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192985753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.uart_smoke.192985753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_stress_all.1487474696
Short name T116
Test name
Test status
Simulation time 101387972126 ps
CPU time 118.86 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:08:30 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487474696 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1487474696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.2085613332
Short name T24
Test name
Test status
Simulation time 6773701069 ps
CPU time 30.29 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:07:00 AM UTC 24
Peak memory 206860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085613332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2085613332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/0.uart_tx_rx.2501196797
Short name T122
Test name
Test status
Simulation time 84533522321 ps
CPU time 65.55 seconds
Started Aug 29 11:06:26 AM UTC 24
Finished Aug 29 11:07:34 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501196797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2501196797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/0.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_alert_test.2098127771
Short name T10
Test name
Test status
Simulation time 14781198 ps
CPU time 0.8 seconds
Started Aug 29 11:06:30 AM UTC 24
Finished Aug 29 11:06:32 AM UTC 24
Peak memory 204372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098127771 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2098127771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.2232175083
Short name T95
Test name
Test status
Simulation time 45081381901 ps
CPU time 39.66 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:07:11 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232175083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2232175083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_fifo_reset.2699920083
Short name T129
Test name
Test status
Simulation time 118284719727 ps
CPU time 191.33 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:09:44 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699920083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2699920083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.2106180390
Short name T331
Test name
Test status
Simulation time 109894364675 ps
CPU time 486.23 seconds
Started Aug 29 11:06:30 AM UTC 24
Finished Aug 29 11:14:42 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106180390 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2106180390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_loopback.1953070226
Short name T15
Test name
Test status
Simulation time 10183566233 ps
CPU time 7.28 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:06:38 AM UTC 24
Peak memory 207972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953070226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1953070226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_noise_filter.567111190
Short name T7
Test name
Test status
Simulation time 132741990653 ps
CPU time 78.52 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:07:50 AM UTC 24
Peak memory 208148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567111190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.567111190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_perf.3988321298
Short name T534
Test name
Test status
Simulation time 23028672411 ps
CPU time 627.2 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:17:04 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988321298 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3988321298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_rx_oversample.2675083383
Short name T12
Test name
Test status
Simulation time 3524375829 ps
CPU time 3.62 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:06:34 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675083383 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2675083383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2574606722
Short name T22
Test name
Test status
Simulation time 13659687701 ps
CPU time 35.6 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:07:07 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574606722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2574606722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.1598993073
Short name T40
Test name
Test status
Simulation time 3786932249 ps
CPU time 8.96 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:06:40 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598993073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1598993073
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_sec_cm.1870354211
Short name T31
Test name
Test status
Simulation time 1228656517 ps
CPU time 1.05 seconds
Started Aug 29 11:06:30 AM UTC 24
Finished Aug 29 11:06:32 AM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870354211 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1870354211
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_smoke.1434377369
Short name T9
Test name
Test status
Simulation time 535715707 ps
CPU time 1.67 seconds
Started Aug 29 11:06:28 AM UTC 24
Finished Aug 29 11:06:31 AM UTC 24
Peak memory 206876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434377369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1434377369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_stress_all.480429973
Short name T740
Test name
Test status
Simulation time 270746779359 ps
CPU time 1189.37 seconds
Started Aug 29 11:06:30 AM UTC 24
Finished Aug 29 11:26:33 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480429973 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.480429973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/1.uart_tx_rx.3350981428
Short name T99
Test name
Test status
Simulation time 36382253729 ps
CPU time 43.22 seconds
Started Aug 29 11:06:29 AM UTC 24
Finished Aug 29 11:07:14 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350981428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3350981428
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/1.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_alert_test.1755298327
Short name T438
Test name
Test status
Simulation time 13672763 ps
CPU time 0.86 seconds
Started Aug 29 11:09:41 AM UTC 24
Finished Aug 29 11:09:43 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755298327 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1755298327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_fifo_full.2827177372
Short name T362
Test name
Test status
Simulation time 249179025799 ps
CPU time 179.08 seconds
Started Aug 29 11:09:22 AM UTC 24
Finished Aug 29 11:12:24 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827177372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2827177372
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.1520781939
Short name T274
Test name
Test status
Simulation time 225904434880 ps
CPU time 201.06 seconds
Started Aug 29 11:09:23 AM UTC 24
Finished Aug 29 11:12:48 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520781939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1520781939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_intr.375356912
Short name T111
Test name
Test status
Simulation time 10951577544 ps
CPU time 10.22 seconds
Started Aug 29 11:09:26 AM UTC 24
Finished Aug 29 11:09:37 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375356912 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.375356912
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_loopback.2709833390
Short name T440
Test name
Test status
Simulation time 4295836843 ps
CPU time 14.79 seconds
Started Aug 29 11:09:38 AM UTC 24
Finished Aug 29 11:09:54 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709833390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2709833390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_noise_filter.3358879446
Short name T292
Test name
Test status
Simulation time 120697442632 ps
CPU time 26.49 seconds
Started Aug 29 11:09:29 AM UTC 24
Finished Aug 29 11:09:57 AM UTC 24
Peak memory 209084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358879446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3358879446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_perf.2401611726
Short name T556
Test name
Test status
Simulation time 16004869154 ps
CPU time 519.05 seconds
Started Aug 29 11:09:38 AM UTC 24
Finished Aug 29 11:18:24 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401611726 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2401611726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_rx_oversample.1146145966
Short name T437
Test name
Test status
Simulation time 3000434772 ps
CPU time 6 seconds
Started Aug 29 11:09:26 AM UTC 24
Finished Aug 29 11:09:33 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146145966 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1146145966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.71732997
Short name T145
Test name
Test status
Simulation time 53664962708 ps
CPU time 28.22 seconds
Started Aug 29 11:09:34 AM UTC 24
Finished Aug 29 11:10:04 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71732997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.71732997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.513173034
Short name T382
Test name
Test status
Simulation time 1550896460 ps
CPU time 6.37 seconds
Started Aug 29 11:09:31 AM UTC 24
Finished Aug 29 11:09:40 AM UTC 24
Peak memory 204964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513173034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.513173034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_smoke.1335319406
Short name T324
Test name
Test status
Simulation time 109444223 ps
CPU time 1.62 seconds
Started Aug 29 11:09:21 AM UTC 24
Finished Aug 29 11:09:24 AM UTC 24
Peak memory 206860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335319406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1335319406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_stress_all.4055928444
Short name T117
Test name
Test status
Simulation time 61416371754 ps
CPU time 136.81 seconds
Started Aug 29 11:09:40 AM UTC 24
Finished Aug 29 11:11:59 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055928444 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4055928444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.2770391308
Short name T353
Test name
Test status
Simulation time 564803318 ps
CPU time 2.97 seconds
Started Aug 29 11:09:37 AM UTC 24
Finished Aug 29 11:09:41 AM UTC 24
Peak memory 208220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770391308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2770391308
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/10.uart_tx_rx.2254238297
Short name T397
Test name
Test status
Simulation time 31905794606 ps
CPU time 46.98 seconds
Started Aug 29 11:09:22 AM UTC 24
Finished Aug 29 11:10:11 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254238297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2254238297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/10.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/100.uart_fifo_reset.519970011
Short name T1017
Test name
Test status
Simulation time 230687071032 ps
CPU time 99.05 seconds
Started Aug 29 11:36:35 AM UTC 24
Finished Aug 29 11:38:16 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519970011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.519970011
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/100.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/101.uart_fifo_reset.2129504046
Short name T215
Test name
Test status
Simulation time 19297654078 ps
CPU time 47.02 seconds
Started Aug 29 11:36:36 AM UTC 24
Finished Aug 29 11:37:25 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129504046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2129504046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/101.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/102.uart_fifo_reset.1865938750
Short name T1024
Test name
Test status
Simulation time 159503728851 ps
CPU time 128.74 seconds
Started Aug 29 11:36:36 AM UTC 24
Finished Aug 29 11:38:47 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865938750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1865938750
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/102.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/103.uart_fifo_reset.2031303522
Short name T989
Test name
Test status
Simulation time 64858536186 ps
CPU time 22.09 seconds
Started Aug 29 11:36:36 AM UTC 24
Finished Aug 29 11:37:00 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031303522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2031303522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/103.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/104.uart_fifo_reset.2008666760
Short name T185
Test name
Test status
Simulation time 50294169236 ps
CPU time 30.98 seconds
Started Aug 29 11:36:37 AM UTC 24
Finished Aug 29 11:37:10 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008666760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2008666760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/104.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/105.uart_fifo_reset.4212501480
Short name T985
Test name
Test status
Simulation time 54721996023 ps
CPU time 17.11 seconds
Started Aug 29 11:36:39 AM UTC 24
Finished Aug 29 11:36:57 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212501480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.4212501480
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/105.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/107.uart_fifo_reset.1032232035
Short name T249
Test name
Test status
Simulation time 82789161129 ps
CPU time 46.99 seconds
Started Aug 29 11:36:48 AM UTC 24
Finished Aug 29 11:37:36 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032232035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1032232035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/107.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/108.uart_fifo_reset.624012472
Short name T1016
Test name
Test status
Simulation time 35722193796 ps
CPU time 83.32 seconds
Started Aug 29 11:36:50 AM UTC 24
Finished Aug 29 11:38:15 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624012472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.624012472
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/108.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/109.uart_fifo_reset.2466505802
Short name T216
Test name
Test status
Simulation time 16390440708 ps
CPU time 42.21 seconds
Started Aug 29 11:36:52 AM UTC 24
Finished Aug 29 11:37:36 AM UTC 24
Peak memory 208580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466505802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2466505802
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/109.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_alert_test.3949903608
Short name T443
Test name
Test status
Simulation time 11175176 ps
CPU time 0.82 seconds
Started Aug 29 11:10:09 AM UTC 24
Finished Aug 29 11:10:10 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949903608 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3949903608
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_fifo_full.2962167776
Short name T287
Test name
Test status
Simulation time 138346322799 ps
CPU time 63.72 seconds
Started Aug 29 11:09:45 AM UTC 24
Finished Aug 29 11:10:50 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962167776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2962167776
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.2048134724
Short name T352
Test name
Test status
Simulation time 123711651094 ps
CPU time 184.81 seconds
Started Aug 29 11:09:46 AM UTC 24
Finished Aug 29 11:12:54 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048134724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2048134724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_intr.2477829931
Short name T441
Test name
Test status
Simulation time 11775460113 ps
CPU time 11.05 seconds
Started Aug 29 11:09:49 AM UTC 24
Finished Aug 29 11:10:01 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477829931 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2477829931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.1454951290
Short name T707
Test name
Test status
Simulation time 117592427961 ps
CPU time 883.67 seconds
Started Aug 29 11:10:02 AM UTC 24
Finished Aug 29 11:24:56 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454951290 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1454951290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_loopback.2340579856
Short name T442
Test name
Test status
Simulation time 9355317795 ps
CPU time 10.25 seconds
Started Aug 29 11:09:58 AM UTC 24
Finished Aug 29 11:10:10 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340579856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2340579856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_noise_filter.1623229183
Short name T289
Test name
Test status
Simulation time 9088977855 ps
CPU time 28.62 seconds
Started Aug 29 11:09:51 AM UTC 24
Finished Aug 29 11:10:21 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623229183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1623229183
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_perf.2886186660
Short name T311
Test name
Test status
Simulation time 28582328585 ps
CPU time 79.46 seconds
Started Aug 29 11:10:00 AM UTC 24
Finished Aug 29 11:11:21 AM UTC 24
Peak memory 208988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886186660 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2886186660
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_rx_oversample.3746736644
Short name T439
Test name
Test status
Simulation time 1934694479 ps
CPU time 3.26 seconds
Started Aug 29 11:09:48 AM UTC 24
Finished Aug 29 11:09:52 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746736644 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3746736644
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.1094668650
Short name T309
Test name
Test status
Simulation time 140902785757 ps
CPU time 66.58 seconds
Started Aug 29 11:09:54 AM UTC 24
Finished Aug 29 11:11:02 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094668650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1094668650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.3104937736
Short name T312
Test name
Test status
Simulation time 3260316845 ps
CPU time 5.47 seconds
Started Aug 29 11:09:53 AM UTC 24
Finished Aug 29 11:10:00 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104937736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3104937736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_smoke.57242013
Short name T343
Test name
Test status
Simulation time 289442144 ps
CPU time 2.16 seconds
Started Aug 29 11:09:41 AM UTC 24
Finished Aug 29 11:09:45 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57242013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_smoke.57242013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.1563127244
Short name T293
Test name
Test status
Simulation time 12450061229 ps
CPU time 75.12 seconds
Started Aug 29 11:10:04 AM UTC 24
Finished Aug 29 11:11:21 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1563127244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all
_with_rand_reset.1563127244
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.3881247600
Short name T369
Test name
Test status
Simulation time 7239195410 ps
CPU time 26.74 seconds
Started Aug 29 11:09:55 AM UTC 24
Finished Aug 29 11:10:23 AM UTC 24
Peak memory 208564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881247600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3881247600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/11.uart_tx_rx.511086300
Short name T268
Test name
Test status
Simulation time 6627737547 ps
CPU time 28.65 seconds
Started Aug 29 11:09:44 AM UTC 24
Finished Aug 29 11:10:15 AM UTC 24
Peak memory 208600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511086300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.511086300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/11.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/110.uart_fifo_reset.1406411197
Short name T995
Test name
Test status
Simulation time 31568278487 ps
CPU time 27.42 seconds
Started Aug 29 11:36:56 AM UTC 24
Finished Aug 29 11:37:24 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406411197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1406411197
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/110.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/111.uart_fifo_reset.2019099316
Short name T213
Test name
Test status
Simulation time 15761175833 ps
CPU time 44.74 seconds
Started Aug 29 11:36:57 AM UTC 24
Finished Aug 29 11:37:43 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019099316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2019099316
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/111.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/113.uart_fifo_reset.1650849863
Short name T1021
Test name
Test status
Simulation time 150449047179 ps
CPU time 94.25 seconds
Started Aug 29 11:36:58 AM UTC 24
Finished Aug 29 11:38:34 AM UTC 24
Peak memory 208448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650849863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1650849863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/113.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/114.uart_fifo_reset.3706332575
Short name T1081
Test name
Test status
Simulation time 81755027873 ps
CPU time 217.83 seconds
Started Aug 29 11:36:58 AM UTC 24
Finished Aug 29 11:40:39 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706332575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3706332575
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/114.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/115.uart_fifo_reset.1332311534
Short name T1040
Test name
Test status
Simulation time 157269077732 ps
CPU time 144.69 seconds
Started Aug 29 11:37:00 AM UTC 24
Finished Aug 29 11:39:27 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332311534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1332311534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/115.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/116.uart_fifo_reset.1106562718
Short name T228
Test name
Test status
Simulation time 85344147493 ps
CPU time 51.02 seconds
Started Aug 29 11:37:00 AM UTC 24
Finished Aug 29 11:37:52 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106562718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1106562718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/116.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/119.uart_fifo_reset.3074534110
Short name T222
Test name
Test status
Simulation time 29489445099 ps
CPU time 28.46 seconds
Started Aug 29 11:37:05 AM UTC 24
Finished Aug 29 11:37:35 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074534110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3074534110
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/119.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_alert_test.3901234364
Short name T445
Test name
Test status
Simulation time 14840532 ps
CPU time 0.8 seconds
Started Aug 29 11:10:43 AM UTC 24
Finished Aug 29 11:10:45 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901234364 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3901234364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_fifo_full.128204600
Short name T307
Test name
Test status
Simulation time 120565377986 ps
CPU time 268.56 seconds
Started Aug 29 11:10:11 AM UTC 24
Finished Aug 29 11:14:43 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128204600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.128204600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.4094636009
Short name T325
Test name
Test status
Simulation time 73916875849 ps
CPU time 15.18 seconds
Started Aug 29 11:10:12 AM UTC 24
Finished Aug 29 11:10:28 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094636009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.4094636009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_fifo_reset.1583340978
Short name T336
Test name
Test status
Simulation time 202096231345 ps
CPU time 229.38 seconds
Started Aug 29 11:10:14 AM UTC 24
Finished Aug 29 11:14:06 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583340978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1583340978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.395727680
Short name T567
Test name
Test status
Simulation time 130948993723 ps
CPU time 491.28 seconds
Started Aug 29 11:10:34 AM UTC 24
Finished Aug 29 11:18:51 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395727680 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.395727680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_loopback.3218205118
Short name T444
Test name
Test status
Simulation time 2938294712 ps
CPU time 7.03 seconds
Started Aug 29 11:10:28 AM UTC 24
Finished Aug 29 11:10:37 AM UTC 24
Peak memory 208488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218205118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3218205118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_noise_filter.2867960345
Short name T361
Test name
Test status
Simulation time 33601203273 ps
CPU time 14.08 seconds
Started Aug 29 11:10:18 AM UTC 24
Finished Aug 29 11:10:33 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867960345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2867960345
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_perf.2687060899
Short name T498
Test name
Test status
Simulation time 16390973838 ps
CPU time 291.73 seconds
Started Aug 29 11:10:30 AM UTC 24
Finished Aug 29 11:15:25 AM UTC 24
Peak memory 208964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687060899 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2687060899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_rx_oversample.1510392822
Short name T446
Test name
Test status
Simulation time 6176400152 ps
CPU time 37.25 seconds
Started Aug 29 11:10:16 AM UTC 24
Finished Aug 29 11:10:55 AM UTC 24
Peak memory 208104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510392822 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1510392822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.779274751
Short name T282
Test name
Test status
Simulation time 26031002418 ps
CPU time 24.92 seconds
Started Aug 29 11:10:24 AM UTC 24
Finished Aug 29 11:10:51 AM UTC 24
Peak memory 208804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779274751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.779274751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.94136111
Short name T381
Test name
Test status
Simulation time 3305410395 ps
CPU time 2.98 seconds
Started Aug 29 11:10:22 AM UTC 24
Finished Aug 29 11:10:26 AM UTC 24
Peak memory 205236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94136111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.94136111
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_smoke.1805925892
Short name T351
Test name
Test status
Simulation time 697061703 ps
CPU time 5.01 seconds
Started Aug 29 11:10:10 AM UTC 24
Finished Aug 29 11:10:16 AM UTC 24
Peak memory 208004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805925892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1805925892
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.2113718114
Short name T357
Test name
Test status
Simulation time 6622909816 ps
CPU time 32.86 seconds
Started Aug 29 11:10:27 AM UTC 24
Finished Aug 29 11:11:02 AM UTC 24
Peak memory 207988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113718114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2113718114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/120.uart_fifo_reset.1902206692
Short name T1002
Test name
Test status
Simulation time 41152060978 ps
CPU time 32.58 seconds
Started Aug 29 11:37:06 AM UTC 24
Finished Aug 29 11:37:40 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902206692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1902206692
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/120.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/121.uart_fifo_reset.2235995505
Short name T1005
Test name
Test status
Simulation time 264146579412 ps
CPU time 34.63 seconds
Started Aug 29 11:37:10 AM UTC 24
Finished Aug 29 11:37:47 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235995505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2235995505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/121.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/122.uart_fifo_reset.432588846
Short name T1009
Test name
Test status
Simulation time 252593791455 ps
CPU time 42.04 seconds
Started Aug 29 11:37:12 AM UTC 24
Finished Aug 29 11:37:55 AM UTC 24
Peak memory 208576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432588846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.432588846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/122.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/123.uart_fifo_reset.1400124789
Short name T997
Test name
Test status
Simulation time 52659692797 ps
CPU time 20.68 seconds
Started Aug 29 11:37:14 AM UTC 24
Finished Aug 29 11:37:36 AM UTC 24
Peak memory 208336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400124789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1400124789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/123.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/124.uart_fifo_reset.4260046075
Short name T998
Test name
Test status
Simulation time 22864290305 ps
CPU time 19.23 seconds
Started Aug 29 11:37:15 AM UTC 24
Finished Aug 29 11:37:36 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260046075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.4260046075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/124.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/125.uart_fifo_reset.3012577092
Short name T1157
Test name
Test status
Simulation time 130337208557 ps
CPU time 354.31 seconds
Started Aug 29 11:37:16 AM UTC 24
Finished Aug 29 11:43:15 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012577092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3012577092
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/125.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/126.uart_fifo_reset.2754815233
Short name T239
Test name
Test status
Simulation time 18165044923 ps
CPU time 21.24 seconds
Started Aug 29 11:37:26 AM UTC 24
Finished Aug 29 11:37:48 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754815233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2754815233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/126.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/127.uart_fifo_reset.3993421149
Short name T1001
Test name
Test status
Simulation time 11337263859 ps
CPU time 12.64 seconds
Started Aug 29 11:37:26 AM UTC 24
Finished Aug 29 11:37:40 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993421149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3993421149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/127.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/129.uart_fifo_reset.2430027632
Short name T1012
Test name
Test status
Simulation time 61803251526 ps
CPU time 28.5 seconds
Started Aug 29 11:37:36 AM UTC 24
Finished Aug 29 11:38:06 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430027632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2430027632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/129.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_alert_test.1267656443
Short name T447
Test name
Test status
Simulation time 31668975 ps
CPU time 0.81 seconds
Started Aug 29 11:11:17 AM UTC 24
Finished Aug 29 11:11:19 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267656443 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1267656443
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_fifo_full.594815745
Short name T356
Test name
Test status
Simulation time 91808885601 ps
CPU time 29.84 seconds
Started Aug 29 11:10:45 AM UTC 24
Finished Aug 29 11:11:16 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594815745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.594815745
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.859286004
Short name T360
Test name
Test status
Simulation time 54711065124 ps
CPU time 65.46 seconds
Started Aug 29 11:10:49 AM UTC 24
Finished Aug 29 11:11:57 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859286004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.859286004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_fifo_reset.1312506851
Short name T359
Test name
Test status
Simulation time 75622863701 ps
CPU time 142.86 seconds
Started Aug 29 11:10:51 AM UTC 24
Finished Aug 29 11:13:16 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312506851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1312506851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_intr.884347012
Short name T457
Test name
Test status
Simulation time 63290081514 ps
CPU time 83.51 seconds
Started Aug 29 11:10:54 AM UTC 24
Finished Aug 29 11:12:20 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884347012 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.884347012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_loopback.971753337
Short name T448
Test name
Test status
Simulation time 10258558173 ps
CPU time 28.38 seconds
Started Aug 29 11:11:04 AM UTC 24
Finished Aug 29 11:11:33 AM UTC 24
Peak memory 208452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971753337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.uart_loopback.971753337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_noise_filter.3967736828
Short name T316
Test name
Test status
Simulation time 195739163549 ps
CPU time 122.89 seconds
Started Aug 29 11:10:56 AM UTC 24
Finished Aug 29 11:13:01 AM UTC 24
Peak memory 217452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967736828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3967736828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_perf.2090683027
Short name T390
Test name
Test status
Simulation time 5417195182 ps
CPU time 179.64 seconds
Started Aug 29 11:11:05 AM UTC 24
Finished Aug 29 11:14:07 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090683027 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2090683027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_rx_oversample.2956143136
Short name T454
Test name
Test status
Simulation time 6522283800 ps
CPU time 79.83 seconds
Started Aug 29 11:10:52 AM UTC 24
Finished Aug 29 11:12:14 AM UTC 24
Peak memory 207216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956143136 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2956143136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.2201266623
Short name T284
Test name
Test status
Simulation time 101136547051 ps
CPU time 51.91 seconds
Started Aug 29 11:11:03 AM UTC 24
Finished Aug 29 11:11:56 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201266623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2201266623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.3439071381
Short name T394
Test name
Test status
Simulation time 4607238688 ps
CPU time 18.87 seconds
Started Aug 29 11:11:02 AM UTC 24
Finished Aug 29 11:11:22 AM UTC 24
Peak memory 207080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439071381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3439071381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_smoke.4192897730
Short name T365
Test name
Test status
Simulation time 690098911 ps
CPU time 4.59 seconds
Started Aug 29 11:10:43 AM UTC 24
Finished Aug 29 11:10:49 AM UTC 24
Peak memory 208512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192897730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_smoke.4192897730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_stress_all.1837134331
Short name T662
Test name
Test status
Simulation time 108282032891 ps
CPU time 705.49 seconds
Started Aug 29 11:11:17 AM UTC 24
Finished Aug 29 11:23:11 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837134331 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1837134331
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.1622360137
Short name T372
Test name
Test status
Simulation time 617540999 ps
CPU time 3.3 seconds
Started Aug 29 11:11:03 AM UTC 24
Finished Aug 29 11:11:07 AM UTC 24
Peak memory 207080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622360137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1622360137
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/13.uart_tx_rx.2555980370
Short name T275
Test name
Test status
Simulation time 10340335735 ps
CPU time 32.68 seconds
Started Aug 29 11:10:44 AM UTC 24
Finished Aug 29 11:11:18 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555980370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2555980370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/13.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/130.uart_fifo_reset.1732804655
Short name T1056
Test name
Test status
Simulation time 88603200975 ps
CPU time 129.85 seconds
Started Aug 29 11:37:38 AM UTC 24
Finished Aug 29 11:39:50 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732804655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1732804655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/130.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/131.uart_fifo_reset.1559255574
Short name T1010
Test name
Test status
Simulation time 36376431896 ps
CPU time 21.89 seconds
Started Aug 29 11:37:38 AM UTC 24
Finished Aug 29 11:38:01 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559255574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1559255574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/131.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/132.uart_fifo_reset.1415173982
Short name T1151
Test name
Test status
Simulation time 145678919514 ps
CPU time 319.93 seconds
Started Aug 29 11:37:38 AM UTC 24
Finished Aug 29 11:43:02 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415173982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1415173982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/132.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/133.uart_fifo_reset.3538910395
Short name T1014
Test name
Test status
Simulation time 36880569823 ps
CPU time 29.82 seconds
Started Aug 29 11:37:38 AM UTC 24
Finished Aug 29 11:38:09 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538910395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3538910395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/133.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/134.uart_fifo_reset.991961663
Short name T1026
Test name
Test status
Simulation time 65753733274 ps
CPU time 70.11 seconds
Started Aug 29 11:37:38 AM UTC 24
Finished Aug 29 11:38:50 AM UTC 24
Peak memory 208648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991961663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.991961663
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/134.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/135.uart_fifo_reset.4281754909
Short name T225
Test name
Test status
Simulation time 98990663179 ps
CPU time 107.48 seconds
Started Aug 29 11:37:38 AM UTC 24
Finished Aug 29 11:39:28 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281754909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4281754909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/135.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/136.uart_fifo_reset.1346196602
Short name T1053
Test name
Test status
Simulation time 49160469155 ps
CPU time 123.78 seconds
Started Aug 29 11:37:39 AM UTC 24
Finished Aug 29 11:39:45 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346196602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1346196602
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/136.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/137.uart_fifo_reset.4013598578
Short name T1030
Test name
Test status
Simulation time 69527719455 ps
CPU time 76.38 seconds
Started Aug 29 11:37:40 AM UTC 24
Finished Aug 29 11:38:59 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013598578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4013598578
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/137.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/138.uart_fifo_reset.4105390290
Short name T410
Test name
Test status
Simulation time 7761978200 ps
CPU time 27.15 seconds
Started Aug 29 11:37:42 AM UTC 24
Finished Aug 29 11:38:10 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105390290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.4105390290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/138.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_alert_test.4104831408
Short name T452
Test name
Test status
Simulation time 26847094 ps
CPU time 0.8 seconds
Started Aug 29 11:11:57 AM UTC 24
Finished Aug 29 11:11:59 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104831408 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4104831408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.1521549366
Short name T132
Test name
Test status
Simulation time 71695238464 ps
CPU time 43.25 seconds
Started Aug 29 11:11:23 AM UTC 24
Finished Aug 29 11:12:07 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521549366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1521549366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_fifo_reset.3078379030
Short name T191
Test name
Test status
Simulation time 23894517562 ps
CPU time 21.97 seconds
Started Aug 29 11:11:23 AM UTC 24
Finished Aug 29 11:11:46 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078379030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3078379030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_intr.2077497144
Short name T451
Test name
Test status
Simulation time 12951956248 ps
CPU time 23.27 seconds
Started Aug 29 11:11:34 AM UTC 24
Finished Aug 29 11:11:58 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077497144 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2077497144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.1023864070
Short name T502
Test name
Test status
Simulation time 96073373980 ps
CPU time 221.17 seconds
Started Aug 29 11:11:51 AM UTC 24
Finished Aug 29 11:15:35 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023864070 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1023864070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_loopback.30286487
Short name T450
Test name
Test status
Simulation time 7812759860 ps
CPU time 9.98 seconds
Started Aug 29 11:11:46 AM UTC 24
Finished Aug 29 11:11:57 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30286487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.uart_loopback.30286487
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_noise_filter.4051726411
Short name T270
Test name
Test status
Simulation time 23976140205 ps
CPU time 28.98 seconds
Started Aug 29 11:11:36 AM UTC 24
Finished Aug 29 11:12:06 AM UTC 24
Peak memory 208496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051726411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.4051726411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_perf.1794305201
Short name T765
Test name
Test status
Simulation time 18003542078 ps
CPU time 949.78 seconds
Started Aug 29 11:11:47 AM UTC 24
Finished Aug 29 11:27:48 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794305201 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1794305201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_rx_oversample.4255728161
Short name T449
Test name
Test status
Simulation time 3145936750 ps
CPU time 26.17 seconds
Started Aug 29 11:11:23 AM UTC 24
Finished Aug 29 11:11:50 AM UTC 24
Peak memory 207420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255728161 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.4255728161
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.1550240992
Short name T387
Test name
Test status
Simulation time 35613504457 ps
CPU time 27.81 seconds
Started Aug 29 11:11:41 AM UTC 24
Finished Aug 29 11:12:10 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550240992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1550240992
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.2000476729
Short name T322
Test name
Test status
Simulation time 64736999534 ps
CPU time 30.41 seconds
Started Aug 29 11:11:40 AM UTC 24
Finished Aug 29 11:12:12 AM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000476729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2000476729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_smoke.1052455621
Short name T334
Test name
Test status
Simulation time 5720152052 ps
CPU time 54.83 seconds
Started Aug 29 11:11:18 AM UTC 24
Finished Aug 29 11:12:15 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052455621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1052455621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.1013549122
Short name T329
Test name
Test status
Simulation time 15921841564 ps
CPU time 39.53 seconds
Started Aug 29 11:11:51 AM UTC 24
Finished Aug 29 11:12:31 AM UTC 24
Peak memory 217736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1013549122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all
_with_rand_reset.1013549122
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.4223884742
Short name T375
Test name
Test status
Simulation time 1635449417 ps
CPU time 4.2 seconds
Started Aug 29 11:11:44 AM UTC 24
Finished Aug 29 11:11:49 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223884742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4223884742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/14.uart_tx_rx.2389410116
Short name T301
Test name
Test status
Simulation time 22494906657 ps
CPU time 23.18 seconds
Started Aug 29 11:11:19 AM UTC 24
Finished Aug 29 11:11:44 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389410116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2389410116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/14.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/140.uart_fifo_reset.4164924317
Short name T1031
Test name
Test status
Simulation time 98340817752 ps
CPU time 76.5 seconds
Started Aug 29 11:37:43 AM UTC 24
Finished Aug 29 11:39:01 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164924317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.4164924317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/140.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/141.uart_fifo_reset.3218921164
Short name T1042
Test name
Test status
Simulation time 54210323440 ps
CPU time 105 seconds
Started Aug 29 11:37:44 AM UTC 24
Finished Aug 29 11:39:31 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218921164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3218921164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/141.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/142.uart_fifo_reset.3365929532
Short name T166
Test name
Test status
Simulation time 22336727381 ps
CPU time 55.32 seconds
Started Aug 29 11:37:47 AM UTC 24
Finished Aug 29 11:38:44 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365929532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3365929532
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/142.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/143.uart_fifo_reset.563440147
Short name T1169
Test name
Test status
Simulation time 204695457855 ps
CPU time 452.45 seconds
Started Aug 29 11:37:48 AM UTC 24
Finished Aug 29 11:45:26 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563440147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.563440147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/143.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/145.uart_fifo_reset.523104511
Short name T1022
Test name
Test status
Simulation time 72768471317 ps
CPU time 47.11 seconds
Started Aug 29 11:37:50 AM UTC 24
Finished Aug 29 11:38:38 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523104511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.523104511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/145.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/146.uart_fifo_reset.1434281991
Short name T1018
Test name
Test status
Simulation time 30991265365 ps
CPU time 24.72 seconds
Started Aug 29 11:37:51 AM UTC 24
Finished Aug 29 11:38:17 AM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434281991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1434281991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/146.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/147.uart_fifo_reset.2591593896
Short name T1036
Test name
Test status
Simulation time 31059892515 ps
CPU time 78.47 seconds
Started Aug 29 11:37:53 AM UTC 24
Finished Aug 29 11:39:13 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591593896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2591593896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/147.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/148.uart_fifo_reset.3964573666
Short name T1025
Test name
Test status
Simulation time 77249504367 ps
CPU time 51.76 seconds
Started Aug 29 11:37:56 AM UTC 24
Finished Aug 29 11:38:49 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964573666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3964573666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/148.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/149.uart_fifo_reset.156243405
Short name T1038
Test name
Test status
Simulation time 27013562995 ps
CPU time 80.52 seconds
Started Aug 29 11:37:58 AM UTC 24
Finished Aug 29 11:39:21 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156243405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.156243405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/149.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_alert_test.3347614869
Short name T455
Test name
Test status
Simulation time 31884578 ps
CPU time 0.84 seconds
Started Aug 29 11:12:15 AM UTC 24
Finished Aug 29 11:12:17 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347614869 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3347614869
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_fifo_full.2024528820
Short name T305
Test name
Test status
Simulation time 14055441168 ps
CPU time 30.74 seconds
Started Aug 29 11:11:59 AM UTC 24
Finished Aug 29 11:12:31 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024528820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2024528820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.829690904
Short name T178
Test name
Test status
Simulation time 47265501743 ps
CPU time 115.74 seconds
Started Aug 29 11:11:59 AM UTC 24
Finished Aug 29 11:13:57 AM UTC 24
Peak memory 208552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829690904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.829690904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.3002834410
Short name T588
Test name
Test status
Simulation time 69950607045 ps
CPU time 445.73 seconds
Started Aug 29 11:12:12 AM UTC 24
Finished Aug 29 11:19:43 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002834410 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3002834410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_loopback.1524634140
Short name T458
Test name
Test status
Simulation time 4005260708 ps
CPU time 13.71 seconds
Started Aug 29 11:12:10 AM UTC 24
Finished Aug 29 11:12:24 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524634140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1524634140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_noise_filter.886610300
Short name T350
Test name
Test status
Simulation time 22487150725 ps
CPU time 29.26 seconds
Started Aug 29 11:12:02 AM UTC 24
Finished Aug 29 11:12:33 AM UTC 24
Peak memory 207616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886610300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.886610300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_perf.3326656267
Short name T709
Test name
Test status
Simulation time 11836333050 ps
CPU time 768.06 seconds
Started Aug 29 11:12:11 AM UTC 24
Finished Aug 29 11:25:08 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326656267 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3326656267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_rx_oversample.2457244726
Short name T453
Test name
Test status
Simulation time 3797019425 ps
CPU time 8.21 seconds
Started Aug 29 11:12:00 AM UTC 24
Finished Aug 29 11:12:11 AM UTC 24
Peak memory 207484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457244726 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2457244726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.3128770005
Short name T139
Test name
Test status
Simulation time 148555520585 ps
CPU time 195.27 seconds
Started Aug 29 11:12:07 AM UTC 24
Finished Aug 29 11:15:26 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128770005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3128770005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.3584785822
Short name T460
Test name
Test status
Simulation time 27792948760 ps
CPU time 50.42 seconds
Started Aug 29 11:12:05 AM UTC 24
Finished Aug 29 11:12:57 AM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584785822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3584785822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_smoke.4252837241
Short name T347
Test name
Test status
Simulation time 5368732528 ps
CPU time 34 seconds
Started Aug 29 11:11:58 AM UTC 24
Finished Aug 29 11:12:33 AM UTC 24
Peak memory 208412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252837241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_smoke.4252837241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.3786031808
Short name T400
Test name
Test status
Simulation time 2697719299 ps
CPU time 21.58 seconds
Started Aug 29 11:12:12 AM UTC 24
Finished Aug 29 11:12:35 AM UTC 24
Peak memory 223768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3786031808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all
_with_rand_reset.3786031808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.828691054
Short name T355
Test name
Test status
Simulation time 6869451718 ps
CPU time 15.93 seconds
Started Aug 29 11:12:09 AM UTC 24
Finished Aug 29 11:12:26 AM UTC 24
Peak memory 207988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828691054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.828691054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/15.uart_tx_rx.1678843544
Short name T337
Test name
Test status
Simulation time 47689761228 ps
CPU time 105.96 seconds
Started Aug 29 11:11:58 AM UTC 24
Finished Aug 29 11:13:46 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678843544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1678843544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/15.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/150.uart_fifo_reset.1729245266
Short name T1037
Test name
Test status
Simulation time 104407519075 ps
CPU time 74.82 seconds
Started Aug 29 11:38:02 AM UTC 24
Finished Aug 29 11:39:18 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729245266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1729245266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/150.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/151.uart_fifo_reset.246564658
Short name T232
Test name
Test status
Simulation time 130999082158 ps
CPU time 92.59 seconds
Started Aug 29 11:38:05 AM UTC 24
Finished Aug 29 11:39:39 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246564658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.246564658
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/151.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/152.uart_fifo_reset.3633582826
Short name T1020
Test name
Test status
Simulation time 9190625495 ps
CPU time 25.46 seconds
Started Aug 29 11:38:07 AM UTC 24
Finished Aug 29 11:38:34 AM UTC 24
Peak memory 207988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633582826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3633582826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/152.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/153.uart_fifo_reset.694418697
Short name T1029
Test name
Test status
Simulation time 35443566768 ps
CPU time 48.52 seconds
Started Aug 29 11:38:07 AM UTC 24
Finished Aug 29 11:38:57 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694418697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.694418697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/153.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/154.uart_fifo_reset.3745064860
Short name T1044
Test name
Test status
Simulation time 104016311461 ps
CPU time 80.75 seconds
Started Aug 29 11:38:10 AM UTC 24
Finished Aug 29 11:39:33 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745064860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3745064860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/154.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/155.uart_fifo_reset.1345498332
Short name T250
Test name
Test status
Simulation time 85946047643 ps
CPU time 86.5 seconds
Started Aug 29 11:38:10 AM UTC 24
Finished Aug 29 11:39:39 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345498332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1345498332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/155.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/156.uart_fifo_reset.4121544306
Short name T1027
Test name
Test status
Simulation time 164137481046 ps
CPU time 41.9 seconds
Started Aug 29 11:38:12 AM UTC 24
Finished Aug 29 11:38:55 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121544306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.4121544306
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/156.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/157.uart_fifo_reset.4035250147
Short name T1046
Test name
Test status
Simulation time 31376197768 ps
CPU time 81.45 seconds
Started Aug 29 11:38:16 AM UTC 24
Finished Aug 29 11:39:39 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035250147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.4035250147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/157.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/158.uart_fifo_reset.4285168243
Short name T1045
Test name
Test status
Simulation time 32686968497 ps
CPU time 77 seconds
Started Aug 29 11:38:17 AM UTC 24
Finished Aug 29 11:39:36 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285168243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.4285168243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/158.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/159.uart_fifo_reset.2656801897
Short name T1034
Test name
Test status
Simulation time 22727005327 ps
CPU time 50.6 seconds
Started Aug 29 11:38:17 AM UTC 24
Finished Aug 29 11:39:09 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656801897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2656801897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/159.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_alert_test.3122321113
Short name T459
Test name
Test status
Simulation time 70614895 ps
CPU time 0.8 seconds
Started Aug 29 11:12:34 AM UTC 24
Finished Aug 29 11:12:36 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122321113 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3122321113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_fifo_full.3773606746
Short name T332
Test name
Test status
Simulation time 56681613464 ps
CPU time 150.64 seconds
Started Aug 29 11:12:17 AM UTC 24
Finished Aug 29 11:14:50 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773606746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3773606746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.4215813223
Short name T148
Test name
Test status
Simulation time 15023911509 ps
CPU time 37.89 seconds
Started Aug 29 11:12:19 AM UTC 24
Finished Aug 29 11:12:59 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215813223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4215813223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_intr.1859318077
Short name T113
Test name
Test status
Simulation time 27443495791 ps
CPU time 41.73 seconds
Started Aug 29 11:12:21 AM UTC 24
Finished Aug 29 11:13:05 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859318077 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1859318077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.2408054187
Short name T664
Test name
Test status
Simulation time 121972283715 ps
CPU time 637.3 seconds
Started Aug 29 11:12:32 AM UTC 24
Finished Aug 29 11:23:17 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408054187 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2408054187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_loopback.1912760321
Short name T461
Test name
Test status
Simulation time 7998213356 ps
CPU time 29.42 seconds
Started Aug 29 11:12:31 AM UTC 24
Finished Aug 29 11:13:02 AM UTC 24
Peak memory 207404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912760321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1912760321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_noise_filter.3696896799
Short name T466
Test name
Test status
Simulation time 140618042112 ps
CPU time 44.49 seconds
Started Aug 29 11:12:25 AM UTC 24
Finished Aug 29 11:13:10 AM UTC 24
Peak memory 217708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696896799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3696896799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_perf.55890613
Short name T630
Test name
Test status
Simulation time 35922336161 ps
CPU time 561.35 seconds
Started Aug 29 11:12:32 AM UTC 24
Finished Aug 29 11:22:01 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55890613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.55890613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_rx_oversample.550004312
Short name T471
Test name
Test status
Simulation time 6107912339 ps
CPU time 66.57 seconds
Started Aug 29 11:12:20 AM UTC 24
Finished Aug 29 11:13:29 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550004312 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.550004312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.4198176284
Short name T313
Test name
Test status
Simulation time 41783958992 ps
CPU time 30.87 seconds
Started Aug 29 11:12:26 AM UTC 24
Finished Aug 29 11:12:58 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198176284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.4198176284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.3460942620
Short name T340
Test name
Test status
Simulation time 40650764240 ps
CPU time 12.31 seconds
Started Aug 29 11:12:25 AM UTC 24
Finished Aug 29 11:12:38 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460942620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3460942620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_smoke.488606544
Short name T456
Test name
Test status
Simulation time 500702858 ps
CPU time 3.02 seconds
Started Aug 29 11:12:15 AM UTC 24
Finished Aug 29 11:12:19 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488606544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 16.uart_smoke.488606544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_stress_all.3910019039
Short name T363
Test name
Test status
Simulation time 96751466636 ps
CPU time 125.79 seconds
Started Aug 29 11:12:34 AM UTC 24
Finished Aug 29 11:14:42 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910019039 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3910019039
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.4145006097
Short name T89
Test name
Test status
Simulation time 9970786874 ps
CPU time 42.59 seconds
Started Aug 29 11:12:32 AM UTC 24
Finished Aug 29 11:13:16 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4145006097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all
_with_rand_reset.4145006097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.2036365004
Short name T317
Test name
Test status
Simulation time 1575795221 ps
CPU time 2.87 seconds
Started Aug 29 11:12:27 AM UTC 24
Finished Aug 29 11:12:31 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036365004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2036365004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/16.uart_tx_rx.3085610155
Short name T338
Test name
Test status
Simulation time 85759279411 ps
CPU time 115.26 seconds
Started Aug 29 11:12:16 AM UTC 24
Finished Aug 29 11:14:13 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085610155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3085610155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/16.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/160.uart_fifo_reset.2549392517
Short name T240
Test name
Test status
Simulation time 14876242161 ps
CPU time 26.2 seconds
Started Aug 29 11:38:27 AM UTC 24
Finished Aug 29 11:38:55 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549392517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2549392517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/160.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/161.uart_fifo_reset.1980994961
Short name T1099
Test name
Test status
Simulation time 111608370545 ps
CPU time 159.01 seconds
Started Aug 29 11:38:32 AM UTC 24
Finished Aug 29 11:41:14 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980994961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1980994961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/161.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/162.uart_fifo_reset.3090850068
Short name T1115
Test name
Test status
Simulation time 106677172315 ps
CPU time 178.17 seconds
Started Aug 29 11:38:35 AM UTC 24
Finished Aug 29 11:41:36 AM UTC 24
Peak memory 208496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090850068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3090850068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/162.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/163.uart_fifo_reset.4217943130
Short name T243
Test name
Test status
Simulation time 63734162579 ps
CPU time 112.48 seconds
Started Aug 29 11:38:36 AM UTC 24
Finished Aug 29 11:40:31 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217943130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4217943130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/163.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/164.uart_fifo_reset.63283666
Short name T1028
Test name
Test status
Simulation time 11901419642 ps
CPU time 18.51 seconds
Started Aug 29 11:38:37 AM UTC 24
Finished Aug 29 11:38:57 AM UTC 24
Peak memory 208860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63283666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.63283666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/164.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/165.uart_fifo_reset.2516450574
Short name T1054
Test name
Test status
Simulation time 71645638516 ps
CPU time 64.47 seconds
Started Aug 29 11:38:39 AM UTC 24
Finished Aug 29 11:39:46 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516450574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2516450574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/165.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/166.uart_fifo_reset.2328986988
Short name T1043
Test name
Test status
Simulation time 13872038763 ps
CPU time 49.02 seconds
Started Aug 29 11:38:42 AM UTC 24
Finished Aug 29 11:39:32 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328986988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2328986988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/166.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/167.uart_fifo_reset.906433982
Short name T1068
Test name
Test status
Simulation time 49926771571 ps
CPU time 91.26 seconds
Started Aug 29 11:38:45 AM UTC 24
Finished Aug 29 11:40:18 AM UTC 24
Peak memory 208988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906433982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.906433982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/167.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/168.uart_fifo_reset.684482776
Short name T241
Test name
Test status
Simulation time 15519445060 ps
CPU time 21.94 seconds
Started Aug 29 11:38:46 AM UTC 24
Finished Aug 29 11:39:09 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684482776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.684482776
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/168.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/169.uart_fifo_reset.638774667
Short name T1069
Test name
Test status
Simulation time 58347035280 ps
CPU time 92.05 seconds
Started Aug 29 11:38:47 AM UTC 24
Finished Aug 29 11:40:21 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638774667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.638774667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/169.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_alert_test.3366642765
Short name T464
Test name
Test status
Simulation time 15782673 ps
CPU time 0.84 seconds
Started Aug 29 11:13:02 AM UTC 24
Finished Aug 29 11:13:04 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366642765 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3366642765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_fifo_full.3830018963
Short name T465
Test name
Test status
Simulation time 51932881587 ps
CPU time 29.87 seconds
Started Aug 29 11:12:36 AM UTC 24
Finished Aug 29 11:13:08 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830018963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3830018963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.492733833
Short name T141
Test name
Test status
Simulation time 6180673750 ps
CPU time 23.13 seconds
Started Aug 29 11:12:37 AM UTC 24
Finished Aug 29 11:13:02 AM UTC 24
Peak memory 207468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492733833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.492733833
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_intr.4203489802
Short name T385
Test name
Test status
Simulation time 31200165824 ps
CPU time 115.94 seconds
Started Aug 29 11:12:52 AM UTC 24
Finished Aug 29 11:14:50 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203489802 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.4203489802
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.2532559202
Short name T634
Test name
Test status
Simulation time 61909439893 ps
CPU time 543.98 seconds
Started Aug 29 11:12:59 AM UTC 24
Finished Aug 29 11:22:10 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532559202 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2532559202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_loopback.4212139609
Short name T463
Test name
Test status
Simulation time 2782527317 ps
CPU time 3.69 seconds
Started Aug 29 11:12:58 AM UTC 24
Finished Aug 29 11:13:03 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212139609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.4212139609
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_noise_filter.1782853883
Short name T531
Test name
Test status
Simulation time 157863654810 ps
CPU time 238.47 seconds
Started Aug 29 11:12:54 AM UTC 24
Finished Aug 29 11:16:56 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782853883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1782853883
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_perf.2368788452
Short name T536
Test name
Test status
Simulation time 20704458987 ps
CPU time 245.45 seconds
Started Aug 29 11:12:59 AM UTC 24
Finished Aug 29 11:17:09 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368788452 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2368788452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_rx_oversample.2066124094
Short name T469
Test name
Test status
Simulation time 3911208026 ps
CPU time 34.22 seconds
Started Aug 29 11:12:49 AM UTC 24
Finished Aug 29 11:13:24 AM UTC 24
Peak memory 207784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066124094 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2066124094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.699328371
Short name T151
Test name
Test status
Simulation time 15890078407 ps
CPU time 23 seconds
Started Aug 29 11:12:58 AM UTC 24
Finished Aug 29 11:13:22 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699328371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.699328371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.2174809922
Short name T370
Test name
Test status
Simulation time 36453693296 ps
CPU time 47.64 seconds
Started Aug 29 11:12:55 AM UTC 24
Finished Aug 29 11:13:44 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174809922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2174809922
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_smoke.811618354
Short name T333
Test name
Test status
Simulation time 99942984 ps
CPU time 1.36 seconds
Started Aug 29 11:12:34 AM UTC 24
Finished Aug 29 11:12:37 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811618354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.uart_smoke.811618354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.1193962033
Short name T399
Test name
Test status
Simulation time 5802828909 ps
CPU time 45.39 seconds
Started Aug 29 11:13:01 AM UTC 24
Finished Aug 29 11:13:48 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1193962033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all
_with_rand_reset.1193962033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.1985368782
Short name T462
Test name
Test status
Simulation time 1619928794 ps
CPU time 3.14 seconds
Started Aug 29 11:12:58 AM UTC 24
Finished Aug 29 11:13:02 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985368782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1985368782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/17.uart_tx_rx.921993885
Short name T420
Test name
Test status
Simulation time 8953329219 ps
CPU time 23.76 seconds
Started Aug 29 11:12:35 AM UTC 24
Finished Aug 29 11:13:00 AM UTC 24
Peak memory 208528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921993885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.921993885
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/17.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/170.uart_fifo_reset.17510561
Short name T1035
Test name
Test status
Simulation time 18239622031 ps
CPU time 22.12 seconds
Started Aug 29 11:38:48 AM UTC 24
Finished Aug 29 11:39:12 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17510561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.17510561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/170.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/171.uart_fifo_reset.1025479540
Short name T1086
Test name
Test status
Simulation time 163028679645 ps
CPU time 110.54 seconds
Started Aug 29 11:38:51 AM UTC 24
Finished Aug 29 11:40:43 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025479540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1025479540
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/171.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/172.uart_fifo_reset.1428150593
Short name T1114
Test name
Test status
Simulation time 81577909471 ps
CPU time 162.17 seconds
Started Aug 29 11:38:51 AM UTC 24
Finished Aug 29 11:41:36 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428150593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1428150593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/172.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/173.uart_fifo_reset.272534075
Short name T1116
Test name
Test status
Simulation time 97198211996 ps
CPU time 157.71 seconds
Started Aug 29 11:38:56 AM UTC 24
Finished Aug 29 11:41:36 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272534075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.272534075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/173.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/174.uart_fifo_reset.2277995655
Short name T1120
Test name
Test status
Simulation time 133095744810 ps
CPU time 161.14 seconds
Started Aug 29 11:38:56 AM UTC 24
Finished Aug 29 11:41:40 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277995655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2277995655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/174.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/175.uart_fifo_reset.2310454151
Short name T1067
Test name
Test status
Simulation time 24147312345 ps
CPU time 75.35 seconds
Started Aug 29 11:38:58 AM UTC 24
Finished Aug 29 11:40:16 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310454151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2310454151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/175.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/176.uart_fifo_reset.1476315739
Short name T226
Test name
Test status
Simulation time 19913738534 ps
CPU time 48.76 seconds
Started Aug 29 11:38:58 AM UTC 24
Finished Aug 29 11:39:49 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476315739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1476315739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/176.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/177.uart_fifo_reset.2015285962
Short name T1175
Test name
Test status
Simulation time 115353017455 ps
CPU time 520.8 seconds
Started Aug 29 11:39:00 AM UTC 24
Finished Aug 29 11:47:47 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015285962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2015285962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/177.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/178.uart_fifo_reset.1100041338
Short name T1048
Test name
Test status
Simulation time 40037536537 ps
CPU time 37.75 seconds
Started Aug 29 11:39:01 AM UTC 24
Finished Aug 29 11:39:40 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100041338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1100041338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/178.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/179.uart_fifo_reset.2571563417
Short name T1050
Test name
Test status
Simulation time 84892688755 ps
CPU time 37.89 seconds
Started Aug 29 11:39:02 AM UTC 24
Finished Aug 29 11:39:41 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571563417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2571563417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/179.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_alert_test.1829398425
Short name T470
Test name
Test status
Simulation time 39747753 ps
CPU time 0.83 seconds
Started Aug 29 11:13:25 AM UTC 24
Finished Aug 29 11:13:26 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829398425 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1829398425
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.884421080
Short name T175
Test name
Test status
Simulation time 165385247851 ps
CPU time 355.99 seconds
Started Aug 29 11:13:06 AM UTC 24
Finished Aug 29 11:19:06 AM UTC 24
Peak memory 208648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884421080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.884421080
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_fifo_reset.631557492
Short name T137
Test name
Test status
Simulation time 20807567271 ps
CPU time 33.88 seconds
Started Aug 29 11:13:06 AM UTC 24
Finished Aug 29 11:13:41 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631557492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.631557492
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_intr.2900735382
Short name T405
Test name
Test status
Simulation time 14127471908 ps
CPU time 32.31 seconds
Started Aug 29 11:13:07 AM UTC 24
Finished Aug 29 11:13:40 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900735382 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2900735382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.495095594
Short name T507
Test name
Test status
Simulation time 76747878276 ps
CPU time 150.18 seconds
Started Aug 29 11:13:19 AM UTC 24
Finished Aug 29 11:15:52 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495095594 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.495095594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_loopback.1705875190
Short name T473
Test name
Test status
Simulation time 2784663019 ps
CPU time 13.17 seconds
Started Aug 29 11:13:17 AM UTC 24
Finished Aug 29 11:13:32 AM UTC 24
Peak memory 207632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705875190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1705875190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_noise_filter.1703495202
Short name T348
Test name
Test status
Simulation time 383086417222 ps
CPU time 235.24 seconds
Started Aug 29 11:13:08 AM UTC 24
Finished Aug 29 11:17:07 AM UTC 24
Peak memory 209028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703495202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1703495202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_perf.1579520593
Short name T525
Test name
Test status
Simulation time 17018558545 ps
CPU time 207.89 seconds
Started Aug 29 11:13:17 AM UTC 24
Finished Aug 29 11:16:49 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579520593 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1579520593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1262359030
Short name T467
Test name
Test status
Simulation time 6690295729 ps
CPU time 11.36 seconds
Started Aug 29 11:13:06 AM UTC 24
Finished Aug 29 11:13:18 AM UTC 24
Peak memory 208224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262359030 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1262359030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.1774783512
Short name T366
Test name
Test status
Simulation time 19823341621 ps
CPU time 61.36 seconds
Started Aug 29 11:13:14 AM UTC 24
Finished Aug 29 11:14:17 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774783512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1774783512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.83304309
Short name T391
Test name
Test status
Simulation time 603827567 ps
CPU time 2.77 seconds
Started Aug 29 11:13:11 AM UTC 24
Finished Aug 29 11:13:15 AM UTC 24
Peak memory 205044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83304309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.83304309
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_smoke.2377250721
Short name T388
Test name
Test status
Simulation time 1049763790 ps
CPU time 1.58 seconds
Started Aug 29 11:13:02 AM UTC 24
Finished Aug 29 11:13:05 AM UTC 24
Peak memory 206400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377250721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2377250721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_stress_all.2739602470
Short name T580
Test name
Test status
Simulation time 150892422922 ps
CPU time 351.69 seconds
Started Aug 29 11:13:23 AM UTC 24
Finished Aug 29 11:19:20 AM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739602470 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2739602470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.1017569976
Short name T401
Test name
Test status
Simulation time 2399444386 ps
CPU time 31.29 seconds
Started Aug 29 11:13:20 AM UTC 24
Finished Aug 29 11:13:53 AM UTC 24
Peak memory 209024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1017569976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all
_with_rand_reset.1017569976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.2691883979
Short name T468
Test name
Test status
Simulation time 2336146990 ps
CPU time 2.73 seconds
Started Aug 29 11:13:16 AM UTC 24
Finished Aug 29 11:13:20 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691883979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2691883979
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/18.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/180.uart_fifo_reset.2081672962
Short name T1041
Test name
Test status
Simulation time 33023455186 ps
CPU time 24.05 seconds
Started Aug 29 11:39:02 AM UTC 24
Finished Aug 29 11:39:27 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081672962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2081672962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/180.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/181.uart_fifo_reset.2019346126
Short name T1154
Test name
Test status
Simulation time 143990827344 ps
CPU time 233.15 seconds
Started Aug 29 11:39:08 AM UTC 24
Finished Aug 29 11:43:05 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019346126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2019346126
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/181.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/182.uart_fifo_reset.4090976373
Short name T207
Test name
Test status
Simulation time 77555683438 ps
CPU time 47.25 seconds
Started Aug 29 11:39:11 AM UTC 24
Finished Aug 29 11:39:59 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090976373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.4090976373
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/182.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1419994787
Short name T1091
Test name
Test status
Simulation time 152580729998 ps
CPU time 107.05 seconds
Started Aug 29 11:39:11 AM UTC 24
Finished Aug 29 11:41:00 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419994787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1419994787
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/183.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/184.uart_fifo_reset.2457620404
Short name T1051
Test name
Test status
Simulation time 7004985853 ps
CPU time 29.13 seconds
Started Aug 29 11:39:13 AM UTC 24
Finished Aug 29 11:39:43 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457620404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2457620404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/184.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/185.uart_fifo_reset.1392117180
Short name T1147
Test name
Test status
Simulation time 43944561640 ps
CPU time 214.65 seconds
Started Aug 29 11:39:14 AM UTC 24
Finished Aug 29 11:42:52 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392117180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1392117180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/185.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/186.uart_fifo_reset.1120674213
Short name T1057
Test name
Test status
Simulation time 14084306191 ps
CPU time 31.18 seconds
Started Aug 29 11:39:19 AM UTC 24
Finished Aug 29 11:39:52 AM UTC 24
Peak memory 208360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120674213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1120674213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/186.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/187.uart_fifo_reset.3551216862
Short name T1072
Test name
Test status
Simulation time 68632527458 ps
CPU time 60.61 seconds
Started Aug 29 11:39:21 AM UTC 24
Finished Aug 29 11:40:24 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551216862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3551216862
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/187.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/189.uart_fifo_reset.3592361927
Short name T1066
Test name
Test status
Simulation time 186208152570 ps
CPU time 40 seconds
Started Aug 29 11:39:28 AM UTC 24
Finished Aug 29 11:40:09 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592361927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3592361927
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/189.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_alert_test.791238668
Short name T477
Test name
Test status
Simulation time 21993471 ps
CPU time 0.8 seconds
Started Aug 29 11:14:00 AM UTC 24
Finished Aug 29 11:14:02 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791238668 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.791238668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_fifo_full.1441792883
Short name T384
Test name
Test status
Simulation time 33109983729 ps
CPU time 75.31 seconds
Started Aug 29 11:13:33 AM UTC 24
Finished Aug 29 11:14:50 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441792883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1441792883
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.1245822036
Short name T389
Test name
Test status
Simulation time 45923022876 ps
CPU time 18.38 seconds
Started Aug 29 11:13:33 AM UTC 24
Finished Aug 29 11:13:52 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245822036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1245822036
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_intr.1066984453
Short name T564
Test name
Test status
Simulation time 88863426201 ps
CPU time 293.32 seconds
Started Aug 29 11:13:42 AM UTC 24
Finished Aug 29 11:18:40 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066984453 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1066984453
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.2091903782
Short name T880
Test name
Test status
Simulation time 150666037552 ps
CPU time 1112.2 seconds
Started Aug 29 11:13:53 AM UTC 24
Finished Aug 29 11:32:38 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091903782 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2091903782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_loopback.223387921
Short name T478
Test name
Test status
Simulation time 7677824574 ps
CPU time 13.71 seconds
Started Aug 29 11:13:51 AM UTC 24
Finished Aug 29 11:14:06 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223387921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.uart_loopback.223387921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_noise_filter.2705789544
Short name T497
Test name
Test status
Simulation time 23940822345 ps
CPU time 95.76 seconds
Started Aug 29 11:13:45 AM UTC 24
Finished Aug 29 11:15:23 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705789544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2705789544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_perf.3778727784
Short name T1033
Test name
Test status
Simulation time 25858856604 ps
CPU time 1499.37 seconds
Started Aug 29 11:13:51 AM UTC 24
Finished Aug 29 11:39:07 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778727784 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3778727784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_rx_oversample.2614736398
Short name T474
Test name
Test status
Simulation time 2892756613 ps
CPU time 8.31 seconds
Started Aug 29 11:13:41 AM UTC 24
Finished Aug 29 11:13:50 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614736398 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2614736398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.251247258
Short name T392
Test name
Test status
Simulation time 110166433593 ps
CPU time 92.38 seconds
Started Aug 29 11:13:49 AM UTC 24
Finished Aug 29 11:15:24 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251247258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.251247258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.320098772
Short name T475
Test name
Test status
Simulation time 3940462931 ps
CPU time 3.44 seconds
Started Aug 29 11:13:46 AM UTC 24
Finished Aug 29 11:13:51 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320098772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.320098772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_smoke.4114805539
Short name T472
Test name
Test status
Simulation time 504342280 ps
CPU time 2.83 seconds
Started Aug 29 11:13:28 AM UTC 24
Finished Aug 29 11:13:32 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114805539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.uart_smoke.4114805539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_stress_all.4029215721
Short name T603
Test name
Test status
Simulation time 315386305295 ps
CPU time 407.19 seconds
Started Aug 29 11:13:58 AM UTC 24
Finished Aug 29 11:20:50 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029215721 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.4029215721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.4045610007
Short name T480
Test name
Test status
Simulation time 1202740234 ps
CPU time 16.46 seconds
Started Aug 29 11:13:55 AM UTC 24
Finished Aug 29 11:14:12 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4045610007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all
_with_rand_reset.4045610007
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.273060978
Short name T476
Test name
Test status
Simulation time 1076015176 ps
CPU time 6.99 seconds
Started Aug 29 11:13:51 AM UTC 24
Finished Aug 29 11:13:59 AM UTC 24
Peak memory 208460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273060978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.273060978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/19.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/190.uart_fifo_reset.2131831280
Short name T1073
Test name
Test status
Simulation time 78701044437 ps
CPU time 55.25 seconds
Started Aug 29 11:39:28 AM UTC 24
Finished Aug 29 11:40:25 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131831280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2131831280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/190.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/191.uart_fifo_reset.2400819296
Short name T184
Test name
Test status
Simulation time 151791946341 ps
CPU time 55.44 seconds
Started Aug 29 11:39:29 AM UTC 24
Finished Aug 29 11:40:26 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400819296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2400819296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/191.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/192.uart_fifo_reset.2593283744
Short name T1127
Test name
Test status
Simulation time 136685223770 ps
CPU time 136.65 seconds
Started Aug 29 11:39:32 AM UTC 24
Finished Aug 29 11:41:51 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593283744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2593283744
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/192.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3404657241
Short name T1089
Test name
Test status
Simulation time 47341833507 ps
CPU time 83.09 seconds
Started Aug 29 11:39:34 AM UTC 24
Finished Aug 29 11:40:59 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404657241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3404657241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/193.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/194.uart_fifo_reset.2917321888
Short name T1092
Test name
Test status
Simulation time 180944905587 ps
CPU time 84.55 seconds
Started Aug 29 11:39:34 AM UTC 24
Finished Aug 29 11:41:00 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917321888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2917321888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/194.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/195.uart_fifo_reset.2648327455
Short name T1065
Test name
Test status
Simulation time 34075655667 ps
CPU time 28.78 seconds
Started Aug 29 11:39:37 AM UTC 24
Finished Aug 29 11:40:07 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648327455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2648327455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/195.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/196.uart_fifo_reset.3396351273
Short name T1134
Test name
Test status
Simulation time 114397997561 ps
CPU time 143.36 seconds
Started Aug 29 11:39:40 AM UTC 24
Finished Aug 29 11:42:06 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396351273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3396351273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/196.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/197.uart_fifo_reset.2010504350
Short name T1070
Test name
Test status
Simulation time 70335469478 ps
CPU time 40.57 seconds
Started Aug 29 11:39:40 AM UTC 24
Finished Aug 29 11:40:22 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010504350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2010504350
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/197.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/198.uart_fifo_reset.4053664128
Short name T260
Test name
Test status
Simulation time 80288098816 ps
CPU time 43.39 seconds
Started Aug 29 11:39:40 AM UTC 24
Finished Aug 29 11:40:25 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053664128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4053664128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/198.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/199.uart_fifo_reset.4149340432
Short name T1093
Test name
Test status
Simulation time 30821389117 ps
CPU time 80.45 seconds
Started Aug 29 11:39:41 AM UTC 24
Finished Aug 29 11:41:03 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149340432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4149340432
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/199.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_alert_test.3654718361
Short name T421
Test name
Test status
Simulation time 39753582 ps
CPU time 0.66 seconds
Started Aug 29 11:06:37 AM UTC 24
Finished Aug 29 11:06:38 AM UTC 24
Peak memory 204312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654718361 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3654718361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_fifo_full.2259988378
Short name T100
Test name
Test status
Simulation time 27159212784 ps
CPU time 51.12 seconds
Started Aug 29 11:06:30 AM UTC 24
Finished Aug 29 11:07:23 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259988378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2259988378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_intr.1394332493
Short name T374
Test name
Test status
Simulation time 207921178257 ps
CPU time 233.51 seconds
Started Aug 29 11:06:31 AM UTC 24
Finished Aug 29 11:10:28 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394332493 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1394332493
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.2043549130
Short name T273
Test name
Test status
Simulation time 115180626036 ps
CPU time 321.77 seconds
Started Aug 29 11:06:35 AM UTC 24
Finished Aug 29 11:12:02 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043549130 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2043549130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_loopback.2294139556
Short name T27
Test name
Test status
Simulation time 3031977787 ps
CPU time 9.82 seconds
Started Aug 29 11:06:33 AM UTC 24
Finished Aug 29 11:06:44 AM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294139556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2294139556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_noise_filter.1290646171
Short name T45
Test name
Test status
Simulation time 26992858216 ps
CPU time 27.52 seconds
Started Aug 29 11:06:31 AM UTC 24
Finished Aug 29 11:07:00 AM UTC 24
Peak memory 208968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290646171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1290646171
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_perf.715409527
Short name T306
Test name
Test status
Simulation time 6421753669 ps
CPU time 136.48 seconds
Started Aug 29 11:06:34 AM UTC 24
Finished Aug 29 11:08:53 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715409527 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.715409527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_rx_oversample.2248724886
Short name T26
Test name
Test status
Simulation time 4627592963 ps
CPU time 44.61 seconds
Started Aug 29 11:06:31 AM UTC 24
Finished Aug 29 11:07:17 AM UTC 24
Peak memory 207868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248724886 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2248724886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.3738942642
Short name T266
Test name
Test status
Simulation time 136899515466 ps
CPU time 213.62 seconds
Started Aug 29 11:06:32 AM UTC 24
Finished Aug 29 11:10:09 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738942642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3738942642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.546962715
Short name T13
Test name
Test status
Simulation time 846736544 ps
CPU time 1.2 seconds
Started Aug 29 11:06:32 AM UTC 24
Finished Aug 29 11:06:35 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546962715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.546962715
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_sec_cm.839042231
Short name T32
Test name
Test status
Simulation time 88810013 ps
CPU time 1.17 seconds
Started Aug 29 11:06:37 AM UTC 24
Finished Aug 29 11:06:39 AM UTC 24
Peak memory 240200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839042231 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.839042231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_smoke.3472024527
Short name T14
Test name
Test status
Simulation time 650661746 ps
CPU time 4.76 seconds
Started Aug 29 11:06:30 AM UTC 24
Finished Aug 29 11:06:36 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472024527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3472024527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_stress_all.2241701730
Short name T199
Test name
Test status
Simulation time 213129997153 ps
CPU time 864.28 seconds
Started Aug 29 11:06:35 AM UTC 24
Finished Aug 29 11:21:10 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241701730 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2241701730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.3230503255
Short name T23
Test name
Test status
Simulation time 778998103 ps
CPU time 4.85 seconds
Started Aug 29 11:06:32 AM UTC 24
Finished Aug 29 11:06:38 AM UTC 24
Peak memory 208564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230503255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3230503255
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/2.uart_tx_rx.2957633547
Short name T47
Test name
Test status
Simulation time 33738442069 ps
CPU time 29.14 seconds
Started Aug 29 11:06:30 AM UTC 24
Finished Aug 29 11:07:00 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957633547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2957633547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/2.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_alert_test.3284849876
Short name T486
Test name
Test status
Simulation time 33182637 ps
CPU time 0.81 seconds
Started Aug 29 11:14:38 AM UTC 24
Finished Aug 29 11:14:40 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284849876 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3284849876
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_fifo_full.1991452539
Short name T491
Test name
Test status
Simulation time 36362601961 ps
CPU time 56.09 seconds
Started Aug 29 11:14:07 AM UTC 24
Finished Aug 29 11:15:05 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991452539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1991452539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.3141511152
Short name T537
Test name
Test status
Simulation time 78130992929 ps
CPU time 179.86 seconds
Started Aug 29 11:14:07 AM UTC 24
Finished Aug 29 11:17:10 AM UTC 24
Peak memory 208524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141511152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3141511152
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_fifo_reset.3663284815
Short name T195
Test name
Test status
Simulation time 104108755981 ps
CPU time 70.85 seconds
Started Aug 29 11:14:08 AM UTC 24
Finished Aug 29 11:15:21 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663284815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3663284815
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_intr.885311502
Short name T483
Test name
Test status
Simulation time 9223507124 ps
CPU time 12.07 seconds
Started Aug 29 11:14:12 AM UTC 24
Finished Aug 29 11:14:25 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885311502 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.885311502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.3463973993
Short name T607
Test name
Test status
Simulation time 114916560166 ps
CPU time 390.48 seconds
Started Aug 29 11:14:26 AM UTC 24
Finished Aug 29 11:21:01 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463973993 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3463973993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_loopback.764427665
Short name T485
Test name
Test status
Simulation time 7665538566 ps
CPU time 16.46 seconds
Started Aug 29 11:14:18 AM UTC 24
Finished Aug 29 11:14:35 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764427665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.uart_loopback.764427665
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_noise_filter.772573151
Short name T346
Test name
Test status
Simulation time 54802182986 ps
CPU time 77.57 seconds
Started Aug 29 11:14:13 AM UTC 24
Finished Aug 29 11:15:33 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772573151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.772573151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_perf.1245225754
Short name T1178
Test name
Test status
Simulation time 31620163222 ps
CPU time 2067.26 seconds
Started Aug 29 11:14:21 AM UTC 24
Finished Aug 29 11:49:11 AM UTC 24
Peak memory 212212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245225754 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1245225754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_rx_oversample.3211462346
Short name T481
Test name
Test status
Simulation time 1393306289 ps
CPU time 2.9 seconds
Started Aug 29 11:14:10 AM UTC 24
Finished Aug 29 11:14:14 AM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211462346 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3211462346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.2335881237
Short name T487
Test name
Test status
Simulation time 23827434202 ps
CPU time 26.28 seconds
Started Aug 29 11:14:14 AM UTC 24
Finished Aug 29 11:14:42 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335881237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2335881237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.1395343185
Short name T484
Test name
Test status
Simulation time 4061227808 ps
CPU time 16.8 seconds
Started Aug 29 11:14:14 AM UTC 24
Finished Aug 29 11:14:32 AM UTC 24
Peak memory 205236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395343185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1395343185
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_smoke.3568826302
Short name T479
Test name
Test status
Simulation time 685904152 ps
CPU time 5.71 seconds
Started Aug 29 11:14:03 AM UTC 24
Finished Aug 29 11:14:10 AM UTC 24
Peak memory 208500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568826302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3568826302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_stress_all.586687441
Short name T155
Test name
Test status
Simulation time 448444708191 ps
CPU time 415.63 seconds
Started Aug 29 11:14:36 AM UTC 24
Finished Aug 29 11:21:37 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586687441 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.586687441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.356696812
Short name T495
Test name
Test status
Simulation time 494243992 ps
CPU time 45.67 seconds
Started Aug 29 11:14:33 AM UTC 24
Finished Aug 29 11:15:20 AM UTC 24
Peak memory 217592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=356696812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all_
with_rand_reset.356696812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.672712217
Short name T482
Test name
Test status
Simulation time 1935784487 ps
CPU time 3.57 seconds
Started Aug 29 11:14:16 AM UTC 24
Finished Aug 29 11:14:20 AM UTC 24
Peak memory 208588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672712217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.672712217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/20.uart_tx_rx.3672490262
Short name T503
Test name
Test status
Simulation time 71528835639 ps
CPU time 90.11 seconds
Started Aug 29 11:14:06 AM UTC 24
Finished Aug 29 11:15:38 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672490262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3672490262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/20.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/200.uart_fifo_reset.1913546991
Short name T1156
Test name
Test status
Simulation time 155956582477 ps
CPU time 207.53 seconds
Started Aug 29 11:39:41 AM UTC 24
Finished Aug 29 11:43:11 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913546991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1913546991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/200.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/201.uart_fifo_reset.883656200
Short name T1060
Test name
Test status
Simulation time 16374143035 ps
CPU time 13.46 seconds
Started Aug 29 11:39:42 AM UTC 24
Finished Aug 29 11:39:57 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883656200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.883656200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/201.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/202.uart_fifo_reset.1810915299
Short name T1095
Test name
Test status
Simulation time 195357144167 ps
CPU time 81.6 seconds
Started Aug 29 11:39:42 AM UTC 24
Finished Aug 29 11:41:05 AM UTC 24
Peak memory 208804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810915299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1810915299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/202.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/203.uart_fifo_reset.4198053060
Short name T1064
Test name
Test status
Simulation time 11755152898 ps
CPU time 19.75 seconds
Started Aug 29 11:39:44 AM UTC 24
Finished Aug 29 11:40:05 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198053060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.4198053060
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/203.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/204.uart_fifo_reset.4270966222
Short name T172
Test name
Test status
Simulation time 18338914060 ps
CPU time 17 seconds
Started Aug 29 11:39:45 AM UTC 24
Finished Aug 29 11:40:03 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270966222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.4270966222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/204.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/205.uart_fifo_reset.2909405932
Short name T1062
Test name
Test status
Simulation time 71754568167 ps
CPU time 14.61 seconds
Started Aug 29 11:39:47 AM UTC 24
Finished Aug 29 11:40:02 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909405932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2909405932
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/205.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2323315970
Short name T1075
Test name
Test status
Simulation time 22125813741 ps
CPU time 36.11 seconds
Started Aug 29 11:39:49 AM UTC 24
Finished Aug 29 11:40:27 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323315970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2323315970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/207.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2532888225
Short name T1112
Test name
Test status
Simulation time 57112122475 ps
CPU time 99.15 seconds
Started Aug 29 11:39:49 AM UTC 24
Finished Aug 29 11:41:30 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532888225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2532888225
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/208.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/209.uart_fifo_reset.3790634956
Short name T1074
Test name
Test status
Simulation time 30646630130 ps
CPU time 33.47 seconds
Started Aug 29 11:39:51 AM UTC 24
Finished Aug 29 11:40:25 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790634956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3790634956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/209.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_alert_test.3206133298
Short name T496
Test name
Test status
Simulation time 15245464 ps
CPU time 0.81 seconds
Started Aug 29 11:15:19 AM UTC 24
Finished Aug 29 11:15:21 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206133298 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3206133298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_fifo_full.100077157
Short name T515
Test name
Test status
Simulation time 38730464687 ps
CPU time 91 seconds
Started Aug 29 11:14:43 AM UTC 24
Finished Aug 29 11:16:16 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100077157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.100077157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.1457266291
Short name T633
Test name
Test status
Simulation time 261642671875 ps
CPU time 441.5 seconds
Started Aug 29 11:14:43 AM UTC 24
Finished Aug 29 11:22:10 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457266291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1457266291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_fifo_reset.963256808
Short name T193
Test name
Test status
Simulation time 19813124581 ps
CPU time 47.29 seconds
Started Aug 29 11:14:44 AM UTC 24
Finished Aug 29 11:15:33 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963256808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.963256808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_intr.1545748967
Short name T406
Test name
Test status
Simulation time 103006368458 ps
CPU time 41.79 seconds
Started Aug 29 11:14:47 AM UTC 24
Finished Aug 29 11:15:30 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545748967 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1545748967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.4216707915
Short name T754
Test name
Test status
Simulation time 184917596461 ps
CPU time 734.31 seconds
Started Aug 29 11:15:05 AM UTC 24
Finished Aug 29 11:27:28 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216707915 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.4216707915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_loopback.3656722512
Short name T494
Test name
Test status
Simulation time 10083305081 ps
CPU time 15.49 seconds
Started Aug 29 11:15:02 AM UTC 24
Finished Aug 29 11:15:19 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656722512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3656722512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_noise_filter.578254586
Short name T518
Test name
Test status
Simulation time 40135601318 ps
CPU time 91.83 seconds
Started Aug 29 11:14:51 AM UTC 24
Finished Aug 29 11:16:24 AM UTC 24
Peak memory 207824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578254586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.578254586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_perf.2283723292
Short name T679
Test name
Test status
Simulation time 12145040857 ps
CPU time 512.79 seconds
Started Aug 29 11:15:05 AM UTC 24
Finished Aug 29 11:23:45 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283723292 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2283723292
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_rx_oversample.1310818904
Short name T499
Test name
Test status
Simulation time 3359217419 ps
CPU time 39.21 seconds
Started Aug 29 11:14:45 AM UTC 24
Finished Aug 29 11:15:26 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310818904 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1310818904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.802551485
Short name T489
Test name
Test status
Simulation time 2558804170 ps
CPU time 4.56 seconds
Started Aug 29 11:14:51 AM UTC 24
Finished Aug 29 11:14:56 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802551485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.802551485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_smoke.3695782285
Short name T488
Test name
Test status
Simulation time 506638984 ps
CPU time 3.44 seconds
Started Aug 29 11:14:41 AM UTC 24
Finished Aug 29 11:14:46 AM UTC 24
Peak memory 207496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695782285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3695782285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_stress_all.795169242
Short name T146
Test name
Test status
Simulation time 416511234893 ps
CPU time 132.35 seconds
Started Aug 29 11:15:14 AM UTC 24
Finished Aug 29 11:17:29 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795169242 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.795169242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.3486210766
Short name T115
Test name
Test status
Simulation time 10472139286 ps
CPU time 29.04 seconds
Started Aug 29 11:15:10 AM UTC 24
Finished Aug 29 11:15:41 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3486210766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all
_with_rand_reset.3486210766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.4138986768
Short name T490
Test name
Test status
Simulation time 2875985521 ps
CPU time 2.92 seconds
Started Aug 29 11:14:57 AM UTC 24
Finished Aug 29 11:15:01 AM UTC 24
Peak memory 207616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138986768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4138986768
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/21.uart_tx_rx.2599697417
Short name T493
Test name
Test status
Simulation time 9808931478 ps
CPU time 28.54 seconds
Started Aug 29 11:14:43 AM UTC 24
Finished Aug 29 11:15:13 AM UTC 24
Peak memory 208592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599697417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2599697417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/21.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/210.uart_fifo_reset.1939621252
Short name T1165
Test name
Test status
Simulation time 119746449180 ps
CPU time 266.25 seconds
Started Aug 29 11:39:51 AM UTC 24
Finished Aug 29 11:44:20 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939621252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1939621252
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/210.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/212.uart_fifo_reset.3583218052
Short name T248
Test name
Test status
Simulation time 130469260709 ps
CPU time 119.58 seconds
Started Aug 29 11:39:54 AM UTC 24
Finished Aug 29 11:41:56 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583218052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3583218052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/212.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/213.uart_fifo_reset.1715033421
Short name T1061
Test name
Test status
Simulation time 6330147083 ps
CPU time 5.34 seconds
Started Aug 29 11:39:55 AM UTC 24
Finished Aug 29 11:40:02 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715033421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1715033421
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/213.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/214.uart_fifo_reset.287696530
Short name T1077
Test name
Test status
Simulation time 48043843483 ps
CPU time 33.41 seconds
Started Aug 29 11:39:57 AM UTC 24
Finished Aug 29 11:40:32 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287696530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.287696530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/214.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2330555138
Short name T1125
Test name
Test status
Simulation time 176944991466 ps
CPU time 107.24 seconds
Started Aug 29 11:39:59 AM UTC 24
Finished Aug 29 11:41:48 AM UTC 24
Peak memory 208736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330555138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2330555138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/215.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1679797798
Short name T1076
Test name
Test status
Simulation time 32321968350 ps
CPU time 25.36 seconds
Started Aug 29 11:40:01 AM UTC 24
Finished Aug 29 11:40:27 AM UTC 24
Peak memory 208232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679797798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1679797798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/216.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/218.uart_fifo_reset.2728011824
Short name T1079
Test name
Test status
Simulation time 22695293567 ps
CPU time 32.15 seconds
Started Aug 29 11:40:03 AM UTC 24
Finished Aug 29 11:40:37 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728011824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2728011824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/218.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/219.uart_fifo_reset.1525797203
Short name T1103
Test name
Test status
Simulation time 229861215452 ps
CPU time 71.43 seconds
Started Aug 29 11:40:05 AM UTC 24
Finished Aug 29 11:41:18 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525797203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1525797203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/219.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_alert_test.1412515765
Short name T504
Test name
Test status
Simulation time 12147174 ps
CPU time 0.84 seconds
Started Aug 29 11:15:39 AM UTC 24
Finished Aug 29 11:15:40 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412515765 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1412515765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_fifo_full.736063732
Short name T587
Test name
Test status
Simulation time 125549848699 ps
CPU time 254.77 seconds
Started Aug 29 11:15:22 AM UTC 24
Finished Aug 29 11:19:40 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736063732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.736063732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.3870522807
Short name T521
Test name
Test status
Simulation time 21338867469 ps
CPU time 71.52 seconds
Started Aug 29 11:15:24 AM UTC 24
Finished Aug 29 11:16:37 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870522807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3870522807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_intr.1919089067
Short name T526
Test name
Test status
Simulation time 111598302957 ps
CPU time 79.91 seconds
Started Aug 29 11:15:27 AM UTC 24
Finished Aug 29 11:16:49 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919089067 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1919089067
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.3826304267
Short name T571
Test name
Test status
Simulation time 63683540337 ps
CPU time 200.07 seconds
Started Aug 29 11:15:34 AM UTC 24
Finished Aug 29 11:18:58 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826304267 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3826304267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_loopback.1521159640
Short name T508
Test name
Test status
Simulation time 6822583452 ps
CPU time 18.83 seconds
Started Aug 29 11:15:33 AM UTC 24
Finished Aug 29 11:15:53 AM UTC 24
Peak memory 208520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521159640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1521159640
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_noise_filter.3170184124
Short name T371
Test name
Test status
Simulation time 207467020133 ps
CPU time 129.24 seconds
Started Aug 29 11:15:27 AM UTC 24
Finished Aug 29 11:17:38 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170184124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3170184124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_perf.3130598347
Short name T823
Test name
Test status
Simulation time 18680811907 ps
CPU time 910.07 seconds
Started Aug 29 11:15:33 AM UTC 24
Finished Aug 29 11:30:54 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130598347 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3130598347
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_rx_oversample.3439331366
Short name T506
Test name
Test status
Simulation time 2833201983 ps
CPU time 21.08 seconds
Started Aug 29 11:15:27 AM UTC 24
Finished Aug 29 11:15:49 AM UTC 24
Peak memory 207420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439331366 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3439331366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.3709989501
Short name T563
Test name
Test status
Simulation time 74883196602 ps
CPU time 186.51 seconds
Started Aug 29 11:15:30 AM UTC 24
Finished Aug 29 11:18:39 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709989501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3709989501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.2115488008
Short name T501
Test name
Test status
Simulation time 1739463562 ps
CPU time 2.44 seconds
Started Aug 29 11:15:29 AM UTC 24
Finished Aug 29 11:15:32 AM UTC 24
Peak memory 205044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115488008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2115488008
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_smoke.238211303
Short name T500
Test name
Test status
Simulation time 5825776070 ps
CPU time 6.54 seconds
Started Aug 29 11:15:20 AM UTC 24
Finished Aug 29 11:15:28 AM UTC 24
Peak memory 208396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238211303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.uart_smoke.238211303
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_stress_all.3373021731
Short name T561
Test name
Test status
Simulation time 34761708655 ps
CPU time 178.38 seconds
Started Aug 29 11:15:35 AM UTC 24
Finished Aug 29 11:18:37 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373021731 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3373021731
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.1808694070
Short name T90
Test name
Test status
Simulation time 5794199430 ps
CPU time 60.37 seconds
Started Aug 29 11:15:34 AM UTC 24
Finished Aug 29 11:16:36 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1808694070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all
_with_rand_reset.1808694070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.1185110963
Short name T510
Test name
Test status
Simulation time 6584318591 ps
CPU time 24.36 seconds
Started Aug 29 11:15:31 AM UTC 24
Finished Aug 29 11:15:57 AM UTC 24
Peak memory 208600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185110963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1185110963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/22.uart_tx_rx.121668993
Short name T519
Test name
Test status
Simulation time 54322492906 ps
CPU time 68.05 seconds
Started Aug 29 11:15:21 AM UTC 24
Finished Aug 29 11:16:31 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121668993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.121668993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/22.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/220.uart_fifo_reset.458209974
Short name T1084
Test name
Test status
Simulation time 204968463256 ps
CPU time 36.51 seconds
Started Aug 29 11:40:05 AM UTC 24
Finished Aug 29 11:40:42 AM UTC 24
Peak memory 208584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458209974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.458209974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/220.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/221.uart_fifo_reset.1053402158
Short name T1168
Test name
Test status
Simulation time 148216199877 ps
CPU time 316.92 seconds
Started Aug 29 11:40:05 AM UTC 24
Finished Aug 29 11:45:26 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053402158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1053402158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/221.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/222.uart_fifo_reset.975016402
Short name T170
Test name
Test status
Simulation time 162642584870 ps
CPU time 49.98 seconds
Started Aug 29 11:40:06 AM UTC 24
Finished Aug 29 11:40:58 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975016402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.975016402
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/222.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/223.uart_fifo_reset.855867589
Short name T1082
Test name
Test status
Simulation time 51862496606 ps
CPU time 30.82 seconds
Started Aug 29 11:40:08 AM UTC 24
Finished Aug 29 11:40:41 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855867589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.855867589
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/223.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/224.uart_fifo_reset.3131781775
Short name T1080
Test name
Test status
Simulation time 174223129481 ps
CPU time 25.35 seconds
Started Aug 29 11:40:10 AM UTC 24
Finished Aug 29 11:40:37 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131781775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3131781775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/224.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/225.uart_fifo_reset.3860662201
Short name T1087
Test name
Test status
Simulation time 26195387710 ps
CPU time 29.23 seconds
Started Aug 29 11:40:16 AM UTC 24
Finished Aug 29 11:40:47 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860662201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3860662201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/225.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/228.uart_fifo_reset.1958676683
Short name T1123
Test name
Test status
Simulation time 50449859307 ps
CPU time 76.9 seconds
Started Aug 29 11:40:23 AM UTC 24
Finished Aug 29 11:41:42 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958676683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1958676683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/228.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/229.uart_fifo_reset.1418434274
Short name T1094
Test name
Test status
Simulation time 20082074033 ps
CPU time 37.65 seconds
Started Aug 29 11:40:24 AM UTC 24
Finished Aug 29 11:41:04 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418434274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1418434274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/229.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_alert_test.2518442300
Short name T516
Test name
Test status
Simulation time 15634413 ps
CPU time 0.83 seconds
Started Aug 29 11:16:16 AM UTC 24
Finished Aug 29 11:16:18 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518442300 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2518442300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_fifo_full.1843843845
Short name T513
Test name
Test status
Simulation time 103888122422 ps
CPU time 28.12 seconds
Started Aug 29 11:15:42 AM UTC 24
Finished Aug 29 11:16:11 AM UTC 24
Peak memory 208984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843843845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1843843845
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.8820088
Short name T188
Test name
Test status
Simulation time 112478925657 ps
CPU time 85.98 seconds
Started Aug 29 11:15:43 AM UTC 24
Finished Aug 29 11:17:10 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8820088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.8820088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_fifo_reset.1108470034
Short name T520
Test name
Test status
Simulation time 152787856444 ps
CPU time 48.43 seconds
Started Aug 29 11:15:44 AM UTC 24
Finished Aug 29 11:16:34 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108470034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1108470034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_intr.544746845
Short name T512
Test name
Test status
Simulation time 24910656683 ps
CPU time 18.1 seconds
Started Aug 29 11:15:50 AM UTC 24
Finished Aug 29 11:16:09 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544746845 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.544746845
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.3990839868
Short name T610
Test name
Test status
Simulation time 110392409044 ps
CPU time 297.7 seconds
Started Aug 29 11:16:10 AM UTC 24
Finished Aug 29 11:21:11 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990839868 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3990839868
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_loopback.2949714356
Short name T514
Test name
Test status
Simulation time 3093878247 ps
CPU time 9.72 seconds
Started Aug 29 11:16:04 AM UTC 24
Finished Aug 29 11:16:15 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949714356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2949714356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_noise_filter.2568778927
Short name T620
Test name
Test status
Simulation time 120681645760 ps
CPU time 331.99 seconds
Started Aug 29 11:15:53 AM UTC 24
Finished Aug 29 11:21:29 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568778927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2568778927
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_perf.840499216
Short name T1007
Test name
Test status
Simulation time 23757631463 ps
CPU time 1284.62 seconds
Started Aug 29 11:16:08 AM UTC 24
Finished Aug 29 11:37:48 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840499216 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.840499216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_rx_oversample.2996922636
Short name T509
Test name
Test status
Simulation time 2000448741 ps
CPU time 8.49 seconds
Started Aug 29 11:15:44 AM UTC 24
Finished Aug 29 11:15:54 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996922636 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2996922636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.3534156643
Short name T160
Test name
Test status
Simulation time 85377415038 ps
CPU time 36.07 seconds
Started Aug 29 11:15:54 AM UTC 24
Finished Aug 29 11:16:31 AM UTC 24
Peak memory 208860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534156643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3534156643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.2830322950
Short name T511
Test name
Test status
Simulation time 3532773484 ps
CPU time 12.56 seconds
Started Aug 29 11:15:54 AM UTC 24
Finished Aug 29 11:16:08 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830322950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2830322950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_smoke.1841613258
Short name T376
Test name
Test status
Simulation time 244456435 ps
CPU time 1.87 seconds
Started Aug 29 11:15:40 AM UTC 24
Finished Aug 29 11:15:42 AM UTC 24
Peak memory 206248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841613258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1841613258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.1606379046
Short name T546
Test name
Test status
Simulation time 12112290897 ps
CPU time 86.75 seconds
Started Aug 29 11:16:10 AM UTC 24
Finished Aug 29 11:17:38 AM UTC 24
Peak memory 217940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1606379046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all
_with_rand_reset.1606379046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.3926219565
Short name T523
Test name
Test status
Simulation time 6374120888 ps
CPU time 49.08 seconds
Started Aug 29 11:15:57 AM UTC 24
Finished Aug 29 11:16:48 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926219565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3926219565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/23.uart_tx_rx.114588973
Short name T545
Test name
Test status
Simulation time 61156793502 ps
CPU time 112.2 seconds
Started Aug 29 11:15:41 AM UTC 24
Finished Aug 29 11:17:35 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114588973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.114588973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/23.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/232.uart_fifo_reset.1763879200
Short name T1088
Test name
Test status
Simulation time 127696924958 ps
CPU time 20.87 seconds
Started Aug 29 11:40:25 AM UTC 24
Finished Aug 29 11:40:48 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763879200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1763879200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/232.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/233.uart_fifo_reset.240863442
Short name T1083
Test name
Test status
Simulation time 20840741116 ps
CPU time 13.12 seconds
Started Aug 29 11:40:27 AM UTC 24
Finished Aug 29 11:40:41 AM UTC 24
Peak memory 208456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240863442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.240863442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/233.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/234.uart_fifo_reset.2114068109
Short name T1090
Test name
Test status
Simulation time 38320074936 ps
CPU time 30.34 seconds
Started Aug 29 11:40:27 AM UTC 24
Finished Aug 29 11:40:59 AM UTC 24
Peak memory 208548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114068109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2114068109
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/234.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/235.uart_fifo_reset.1177597823
Short name T1107
Test name
Test status
Simulation time 69269126225 ps
CPU time 53.63 seconds
Started Aug 29 11:40:28 AM UTC 24
Finished Aug 29 11:41:24 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177597823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1177597823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/235.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/236.uart_fifo_reset.2372513695
Short name T1124
Test name
Test status
Simulation time 31084496734 ps
CPU time 74.23 seconds
Started Aug 29 11:40:28 AM UTC 24
Finished Aug 29 11:41:44 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372513695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2372513695
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/236.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/237.uart_fifo_reset.1169391294
Short name T1150
Test name
Test status
Simulation time 152909166589 ps
CPU time 147.14 seconds
Started Aug 29 11:40:28 AM UTC 24
Finished Aug 29 11:42:58 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169391294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1169391294
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/237.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/238.uart_fifo_reset.151822561
Short name T1100
Test name
Test status
Simulation time 85788666274 ps
CPU time 43.39 seconds
Started Aug 29 11:40:29 AM UTC 24
Finished Aug 29 11:41:15 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151822561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.151822561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/238.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1165762851
Short name T211
Test name
Test status
Simulation time 83136354581 ps
CPU time 39.41 seconds
Started Aug 29 11:40:32 AM UTC 24
Finished Aug 29 11:41:13 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165762851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1165762851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/239.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_alert_test.2994655565
Short name T529
Test name
Test status
Simulation time 14647589 ps
CPU time 0.85 seconds
Started Aug 29 11:16:52 AM UTC 24
Finished Aug 29 11:16:54 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994655565 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2994655565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_fifo_full.159672911
Short name T189
Test name
Test status
Simulation time 160297619773 ps
CPU time 345.39 seconds
Started Aug 29 11:16:21 AM UTC 24
Finished Aug 29 11:22:11 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159672911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.159672911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.735630020
Short name T538
Test name
Test status
Simulation time 89214379171 ps
CPU time 45.91 seconds
Started Aug 29 11:16:25 AM UTC 24
Finished Aug 29 11:17:13 AM UTC 24
Peak memory 208252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735630020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.735630020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_intr.1236990565
Short name T522
Test name
Test status
Simulation time 2804921233 ps
CPU time 6.45 seconds
Started Aug 29 11:16:34 AM UTC 24
Finished Aug 29 11:16:42 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236990565 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1236990565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.3589817304
Short name T1078
Test name
Test status
Simulation time 128737980885 ps
CPU time 1407.89 seconds
Started Aug 29 11:16:50 AM UTC 24
Finished Aug 29 11:40:33 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589817304 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3589817304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_loopback.2576324674
Short name T530
Test name
Test status
Simulation time 3684256298 ps
CPU time 5.47 seconds
Started Aug 29 11:16:49 AM UTC 24
Finished Aug 29 11:16:55 AM UTC 24
Peak memory 208452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576324674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2576324674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_noise_filter.665879607
Short name T579
Test name
Test status
Simulation time 250372365434 ps
CPU time 158.28 seconds
Started Aug 29 11:16:35 AM UTC 24
Finished Aug 29 11:19:16 AM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665879607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.665879607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_perf.2367722966
Short name T730
Test name
Test status
Simulation time 7932485011 ps
CPU time 534.79 seconds
Started Aug 29 11:16:49 AM UTC 24
Finished Aug 29 11:25:50 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367722966 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2367722966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_rx_oversample.2080033706
Short name T533
Test name
Test status
Simulation time 6276874816 ps
CPU time 29.75 seconds
Started Aug 29 11:16:32 AM UTC 24
Finished Aug 29 11:17:03 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080033706 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2080033706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.1579039691
Short name T181
Test name
Test status
Simulation time 27678028847 ps
CPU time 68.53 seconds
Started Aug 29 11:16:38 AM UTC 24
Finished Aug 29 11:17:48 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579039691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1579039691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.1363299596
Short name T527
Test name
Test status
Simulation time 2869288228 ps
CPU time 10.01 seconds
Started Aug 29 11:16:38 AM UTC 24
Finished Aug 29 11:16:49 AM UTC 24
Peak memory 205236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363299596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1363299596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_smoke.3697349314
Short name T517
Test name
Test status
Simulation time 451876227 ps
CPU time 2.76 seconds
Started Aug 29 11:16:17 AM UTC 24
Finished Aug 29 11:16:21 AM UTC 24
Peak memory 208164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697349314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3697349314
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_stress_all.1582636683
Short name T815
Test name
Test status
Simulation time 231907657323 ps
CPU time 788.06 seconds
Started Aug 29 11:16:50 AM UTC 24
Finished Aug 29 11:30:07 AM UTC 24
Peak memory 217644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582636683 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1582636683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.1347736746
Short name T377
Test name
Test status
Simulation time 4132030506 ps
CPU time 69.68 seconds
Started Aug 29 11:16:50 AM UTC 24
Finished Aug 29 11:18:01 AM UTC 24
Peak memory 225004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1347736746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all
_with_rand_reset.1347736746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.1213026976
Short name T528
Test name
Test status
Simulation time 7964738565 ps
CPU time 7.96 seconds
Started Aug 29 11:16:43 AM UTC 24
Finished Aug 29 11:16:52 AM UTC 24
Peak memory 208580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213026976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1213026976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/24.uart_tx_rx.402430273
Short name T327
Test name
Test status
Simulation time 43195103627 ps
CPU time 51.83 seconds
Started Aug 29 11:16:18 AM UTC 24
Finished Aug 29 11:17:11 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402430273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.402430273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/24.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/240.uart_fifo_reset.3667272289
Short name T1102
Test name
Test status
Simulation time 90720768150 ps
CPU time 42.39 seconds
Started Aug 29 11:40:33 AM UTC 24
Finished Aug 29 11:41:17 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667272289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3667272289
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/240.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/241.uart_fifo_reset.3610209732
Short name T1153
Test name
Test status
Simulation time 71572249868 ps
CPU time 147.62 seconds
Started Aug 29 11:40:34 AM UTC 24
Finished Aug 29 11:43:04 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610209732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3610209732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/241.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/243.uart_fifo_reset.372728592
Short name T1101
Test name
Test status
Simulation time 9172869742 ps
CPU time 36.01 seconds
Started Aug 29 11:40:38 AM UTC 24
Finished Aug 29 11:41:16 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372728592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.372728592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/243.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/244.uart_fifo_reset.2457151491
Short name T1097
Test name
Test status
Simulation time 15395039539 ps
CPU time 24.54 seconds
Started Aug 29 11:40:41 AM UTC 24
Finished Aug 29 11:41:07 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457151491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2457151491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/244.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/245.uart_fifo_reset.1488134494
Short name T1098
Test name
Test status
Simulation time 58039003515 ps
CPU time 26.81 seconds
Started Aug 29 11:40:42 AM UTC 24
Finished Aug 29 11:41:10 AM UTC 24
Peak memory 208452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488134494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1488134494
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/245.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/246.uart_fifo_reset.2840172380
Short name T1108
Test name
Test status
Simulation time 104833033852 ps
CPU time 40.3 seconds
Started Aug 29 11:40:42 AM UTC 24
Finished Aug 29 11:41:24 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840172380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2840172380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/246.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/247.uart_fifo_reset.3379550512
Short name T1096
Test name
Test status
Simulation time 12956011700 ps
CPU time 23.2 seconds
Started Aug 29 11:40:42 AM UTC 24
Finished Aug 29 11:41:07 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379550512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3379550512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/247.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3417323131
Short name T1118
Test name
Test status
Simulation time 96463121286 ps
CPU time 53.73 seconds
Started Aug 29 11:40:43 AM UTC 24
Finished Aug 29 11:41:39 AM UTC 24
Peak memory 208460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417323131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3417323131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/248.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/249.uart_fifo_reset.1873756776
Short name T1113
Test name
Test status
Simulation time 20156396014 ps
CPU time 46.03 seconds
Started Aug 29 11:40:44 AM UTC 24
Finished Aug 29 11:41:32 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873756776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1873756776
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/249.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_alert_test.3526372655
Short name T543
Test name
Test status
Simulation time 11872303 ps
CPU time 0.83 seconds
Started Aug 29 11:17:28 AM UTC 24
Finished Aug 29 11:17:30 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526372655 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3526372655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_fifo_full.1137664582
Short name T140
Test name
Test status
Simulation time 55656174075 ps
CPU time 96.31 seconds
Started Aug 29 11:16:56 AM UTC 24
Finished Aug 29 11:18:34 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137664582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1137664582
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.3647497925
Short name T547
Test name
Test status
Simulation time 43144254031 ps
CPU time 41.91 seconds
Started Aug 29 11:16:57 AM UTC 24
Finished Aug 29 11:17:41 AM UTC 24
Peak memory 208460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647497925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3647497925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_fifo_reset.851168255
Short name T196
Test name
Test status
Simulation time 172145877490 ps
CPU time 506.14 seconds
Started Aug 29 11:17:04 AM UTC 24
Finished Aug 29 11:25:37 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851168255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.851168255
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_intr.3748639910
Short name T551
Test name
Test status
Simulation time 18648767286 ps
CPU time 50.13 seconds
Started Aug 29 11:17:08 AM UTC 24
Finished Aug 29 11:17:59 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748639910 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3748639910
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_loopback.2538420644
Short name T541
Test name
Test status
Simulation time 2066128080 ps
CPU time 7.94 seconds
Started Aug 29 11:17:12 AM UTC 24
Finished Aug 29 11:17:21 AM UTC 24
Peak memory 207680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538420644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2538420644
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_noise_filter.684905474
Short name T582
Test name
Test status
Simulation time 95313856470 ps
CPU time 133.78 seconds
Started Aug 29 11:17:10 AM UTC 24
Finished Aug 29 11:19:27 AM UTC 24
Peak memory 208600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684905474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.684905474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_perf.866812438
Short name T597
Test name
Test status
Simulation time 16835236109 ps
CPU time 192.78 seconds
Started Aug 29 11:17:13 AM UTC 24
Finished Aug 29 11:20:29 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866812438 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.866812438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_rx_oversample.2379568015
Short name T553
Test name
Test status
Simulation time 5316654066 ps
CPU time 57.93 seconds
Started Aug 29 11:17:05 AM UTC 24
Finished Aug 29 11:18:05 AM UTC 24
Peak memory 207420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379568015 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2379568015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.2618524632
Short name T565
Test name
Test status
Simulation time 388988482455 ps
CPU time 90.41 seconds
Started Aug 29 11:17:12 AM UTC 24
Finished Aug 29 11:18:44 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618524632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2618524632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.4024181008
Short name T540
Test name
Test status
Simulation time 2162574097 ps
CPU time 8.4 seconds
Started Aug 29 11:17:10 AM UTC 24
Finished Aug 29 11:17:20 AM UTC 24
Peak memory 205236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024181008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4024181008
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_smoke.550182351
Short name T532
Test name
Test status
Simulation time 111520355 ps
CPU time 0.95 seconds
Started Aug 29 11:16:55 AM UTC 24
Finished Aug 29 11:16:57 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550182351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.uart_smoke.550182351
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_stress_all.832369870
Short name T415
Test name
Test status
Simulation time 174678661326 ps
CPU time 224.99 seconds
Started Aug 29 11:17:22 AM UTC 24
Finished Aug 29 11:21:11 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832369870 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.832369870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.3601945274
Short name T91
Test name
Test status
Simulation time 767206588 ps
CPU time 10.53 seconds
Started Aug 29 11:17:21 AM UTC 24
Finished Aug 29 11:17:33 AM UTC 24
Peak memory 217696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3601945274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all
_with_rand_reset.3601945274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.2857207774
Short name T539
Test name
Test status
Simulation time 2265296246 ps
CPU time 3.5 seconds
Started Aug 29 11:17:12 AM UTC 24
Finished Aug 29 11:17:16 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857207774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2857207774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/25.uart_tx_rx.3740634852
Short name T542
Test name
Test status
Simulation time 41431304700 ps
CPU time 29.61 seconds
Started Aug 29 11:16:56 AM UTC 24
Finished Aug 29 11:17:27 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740634852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3740634852
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/250.uart_fifo_reset.2762955502
Short name T1164
Test name
Test status
Simulation time 97455782298 ps
CPU time 205.54 seconds
Started Aug 29 11:40:44 AM UTC 24
Finished Aug 29 11:44:13 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762955502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2762955502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/250.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/251.uart_fifo_reset.2448881565
Short name T1139
Test name
Test status
Simulation time 26228745141 ps
CPU time 88.17 seconds
Started Aug 29 11:40:49 AM UTC 24
Finished Aug 29 11:42:19 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448881565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2448881565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/251.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/253.uart_fifo_reset.718799748
Short name T1104
Test name
Test status
Simulation time 27620555584 ps
CPU time 20.36 seconds
Started Aug 29 11:40:57 AM UTC 24
Finished Aug 29 11:41:19 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718799748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.718799748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/253.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1926425657
Short name T1159
Test name
Test status
Simulation time 88749766372 ps
CPU time 142.37 seconds
Started Aug 29 11:40:58 AM UTC 24
Finished Aug 29 11:43:23 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926425657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1926425657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/254.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/255.uart_fifo_reset.937484487
Short name T1122
Test name
Test status
Simulation time 20504418813 ps
CPU time 40.83 seconds
Started Aug 29 11:41:00 AM UTC 24
Finished Aug 29 11:41:42 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937484487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.937484487
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/255.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/256.uart_fifo_reset.743229474
Short name T1111
Test name
Test status
Simulation time 48596884877 ps
CPU time 29.45 seconds
Started Aug 29 11:41:00 AM UTC 24
Finished Aug 29 11:41:30 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743229474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.743229474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/256.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/257.uart_fifo_reset.1012444867
Short name T1109
Test name
Test status
Simulation time 12180502153 ps
CPU time 26.33 seconds
Started Aug 29 11:41:01 AM UTC 24
Finished Aug 29 11:41:28 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012444867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1012444867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/257.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/258.uart_fifo_reset.2813452572
Short name T1145
Test name
Test status
Simulation time 59684834955 ps
CPU time 97.52 seconds
Started Aug 29 11:41:01 AM UTC 24
Finished Aug 29 11:42:40 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813452572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2813452572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/258.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/259.uart_fifo_reset.1124243476
Short name T1130
Test name
Test status
Simulation time 205490121434 ps
CPU time 51.51 seconds
Started Aug 29 11:41:04 AM UTC 24
Finished Aug 29 11:41:57 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124243476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1124243476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/259.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_alert_test.3987146965
Short name T554
Test name
Test status
Simulation time 12996068 ps
CPU time 0.84 seconds
Started Aug 29 11:18:06 AM UTC 24
Finished Aug 29 11:18:08 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987146965 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3987146965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_fifo_full.1805204121
Short name T562
Test name
Test status
Simulation time 83835570282 ps
CPU time 63.17 seconds
Started Aug 29 11:17:35 AM UTC 24
Finished Aug 29 11:18:39 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805204121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1805204121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.2118472677
Short name T168
Test name
Test status
Simulation time 35990026126 ps
CPU time 33.93 seconds
Started Aug 29 11:17:36 AM UTC 24
Finished Aug 29 11:18:11 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118472677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2118472677
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_fifo_reset.2005251807
Short name T110
Test name
Test status
Simulation time 50983867722 ps
CPU time 120.15 seconds
Started Aug 29 11:17:36 AM UTC 24
Finished Aug 29 11:19:38 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005251807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2005251807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_intr.3692094397
Short name T560
Test name
Test status
Simulation time 18860550798 ps
CPU time 51.66 seconds
Started Aug 29 11:17:39 AM UTC 24
Finished Aug 29 11:18:32 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692094397 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3692094397
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.1389588206
Short name T887
Test name
Test status
Simulation time 114000909925 ps
CPU time 882.01 seconds
Started Aug 29 11:18:00 AM UTC 24
Finished Aug 29 11:32:52 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389588206 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1389588206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_loopback.149660502
Short name T550
Test name
Test status
Simulation time 3779794078 ps
CPU time 3.37 seconds
Started Aug 29 11:17:52 AM UTC 24
Finished Aug 29 11:17:57 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149660502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.uart_loopback.149660502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_noise_filter.1411244246
Short name T379
Test name
Test status
Simulation time 106529493132 ps
CPU time 130.32 seconds
Started Aug 29 11:17:42 AM UTC 24
Finished Aug 29 11:19:55 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411244246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1411244246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_perf.3951113267
Short name T854
Test name
Test status
Simulation time 11474097684 ps
CPU time 833.62 seconds
Started Aug 29 11:17:57 AM UTC 24
Finished Aug 29 11:32:01 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951113267 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3951113267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_rx_oversample.3996518217
Short name T548
Test name
Test status
Simulation time 6234173339 ps
CPU time 9.91 seconds
Started Aug 29 11:17:39 AM UTC 24
Finished Aug 29 11:17:50 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996518217 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3996518217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.2877124004
Short name T558
Test name
Test status
Simulation time 17828091156 ps
CPU time 36.45 seconds
Started Aug 29 11:17:49 AM UTC 24
Finished Aug 29 11:18:27 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877124004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2877124004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.3777136574
Short name T549
Test name
Test status
Simulation time 3385300810 ps
CPU time 2.28 seconds
Started Aug 29 11:17:48 AM UTC 24
Finished Aug 29 11:17:51 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777136574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3777136574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_smoke.2750608734
Short name T544
Test name
Test status
Simulation time 293445022 ps
CPU time 3.1 seconds
Started Aug 29 11:17:30 AM UTC 24
Finished Aug 29 11:17:34 AM UTC 24
Peak memory 207924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750608734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2750608734
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_stress_all.106626393
Short name T393
Test name
Test status
Simulation time 468057005499 ps
CPU time 238.84 seconds
Started Aug 29 11:18:04 AM UTC 24
Finished Aug 29 11:22:06 AM UTC 24
Peak memory 217580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106626393 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.106626393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.774082745
Short name T92
Test name
Test status
Simulation time 20307976745 ps
CPU time 64.49 seconds
Started Aug 29 11:18:02 AM UTC 24
Finished Aug 29 11:19:09 AM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=774082745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all_
with_rand_reset.774082745
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.1213363045
Short name T552
Test name
Test status
Simulation time 7909034480 ps
CPU time 11.69 seconds
Started Aug 29 11:17:50 AM UTC 24
Finished Aug 29 11:18:03 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213363045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1213363045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/26.uart_tx_rx.1936176448
Short name T557
Test name
Test status
Simulation time 136258527163 ps
CPU time 53.13 seconds
Started Aug 29 11:17:30 AM UTC 24
Finished Aug 29 11:18:25 AM UTC 24
Peak memory 208868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936176448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1936176448
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/26.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/260.uart_fifo_reset.2791670888
Short name T1110
Test name
Test status
Simulation time 37445432771 ps
CPU time 22.92 seconds
Started Aug 29 11:41:05 AM UTC 24
Finished Aug 29 11:41:29 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791670888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2791670888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/260.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/261.uart_fifo_reset.2353546588
Short name T1105
Test name
Test status
Simulation time 7853851741 ps
CPU time 12.86 seconds
Started Aug 29 11:41:06 AM UTC 24
Finished Aug 29 11:41:20 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353546588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2353546588
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/261.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/262.uart_fifo_reset.1941658169
Short name T1177
Test name
Test status
Simulation time 118569633527 ps
CPU time 411.45 seconds
Started Aug 29 11:41:08 AM UTC 24
Finished Aug 29 11:48:05 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941658169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1941658169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/262.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/263.uart_fifo_reset.3366280134
Short name T1128
Test name
Test status
Simulation time 64837179459 ps
CPU time 44.21 seconds
Started Aug 29 11:41:08 AM UTC 24
Finished Aug 29 11:41:54 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366280134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3366280134
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/263.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/264.uart_fifo_reset.4272338226
Short name T257
Test name
Test status
Simulation time 93526947886 ps
CPU time 589.73 seconds
Started Aug 29 11:41:11 AM UTC 24
Finished Aug 29 11:51:08 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272338226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.4272338226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/264.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/265.uart_fifo_reset.3387320649
Short name T1129
Test name
Test status
Simulation time 16887661045 ps
CPU time 40.32 seconds
Started Aug 29 11:41:13 AM UTC 24
Finished Aug 29 11:41:55 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387320649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3387320649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/265.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/266.uart_fifo_reset.807385347
Short name T1176
Test name
Test status
Simulation time 107280287016 ps
CPU time 405.57 seconds
Started Aug 29 11:41:14 AM UTC 24
Finished Aug 29 11:48:05 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807385347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.807385347
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/266.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/267.uart_fifo_reset.2749541533
Short name T1152
Test name
Test status
Simulation time 73295881260 ps
CPU time 105.2 seconds
Started Aug 29 11:41:15 AM UTC 24
Finished Aug 29 11:43:03 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749541533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2749541533
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/267.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/268.uart_fifo_reset.677914835
Short name T1119
Test name
Test status
Simulation time 9334487280 ps
CPU time 21.03 seconds
Started Aug 29 11:41:17 AM UTC 24
Finished Aug 29 11:41:39 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677914835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.677914835
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/268.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_alert_test.4182083708
Short name T569
Test name
Test status
Simulation time 44375062 ps
CPU time 0.82 seconds
Started Aug 29 11:18:52 AM UTC 24
Finished Aug 29 11:18:54 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182083708 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4182083708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_fifo_full.1576586300
Short name T572
Test name
Test status
Simulation time 250436332098 ps
CPU time 41.58 seconds
Started Aug 29 11:18:15 AM UTC 24
Finished Aug 29 11:18:58 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576586300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1576586300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.2070293383
Short name T585
Test name
Test status
Simulation time 27216265606 ps
CPU time 65.13 seconds
Started Aug 29 11:18:24 AM UTC 24
Finished Aug 29 11:19:31 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070293383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2070293383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_fifo_reset.736098531
Short name T409
Test name
Test status
Simulation time 114341548031 ps
CPU time 290.81 seconds
Started Aug 29 11:18:26 AM UTC 24
Finished Aug 29 11:23:21 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736098531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.736098531
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_intr.1125066242
Short name T646
Test name
Test status
Simulation time 150276459444 ps
CPU time 251.35 seconds
Started Aug 29 11:18:32 AM UTC 24
Finished Aug 29 11:22:47 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125066242 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1125066242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.810934797
Short name T593
Test name
Test status
Simulation time 93596413436 ps
CPU time 92.55 seconds
Started Aug 29 11:18:45 AM UTC 24
Finished Aug 29 11:20:19 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810934797 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.810934797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_loopback.3467659337
Short name T568
Test name
Test status
Simulation time 4232374835 ps
CPU time 11.84 seconds
Started Aug 29 11:18:41 AM UTC 24
Finished Aug 29 11:18:53 AM UTC 24
Peak memory 208024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467659337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3467659337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_noise_filter.1629286619
Short name T595
Test name
Test status
Simulation time 56879893035 ps
CPU time 108.9 seconds
Started Aug 29 11:18:33 AM UTC 24
Finished Aug 29 11:20:24 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629286619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1629286619
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_perf.1708752997
Short name T1063
Test name
Test status
Simulation time 19271603104 ps
CPU time 1268.99 seconds
Started Aug 29 11:18:41 AM UTC 24
Finished Aug 29 11:40:04 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708752997 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1708752997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_rx_oversample.1899586881
Short name T576
Test name
Test status
Simulation time 3787287110 ps
CPU time 39.55 seconds
Started Aug 29 11:18:28 AM UTC 24
Finished Aug 29 11:19:09 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899586881 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1899586881
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.4188005326
Short name T575
Test name
Test status
Simulation time 15315875261 ps
CPU time 28.29 seconds
Started Aug 29 11:18:37 AM UTC 24
Finished Aug 29 11:19:07 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188005326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.4188005326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.3549364216
Short name T573
Test name
Test status
Simulation time 5686397020 ps
CPU time 22.34 seconds
Started Aug 29 11:18:35 AM UTC 24
Finished Aug 29 11:18:59 AM UTC 24
Peak memory 205236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549364216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3549364216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_smoke.2746126421
Short name T555
Test name
Test status
Simulation time 696184459 ps
CPU time 3.83 seconds
Started Aug 29 11:18:09 AM UTC 24
Finished Aug 29 11:18:14 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746126421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2746126421
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_stress_all.4083217214
Short name T688
Test name
Test status
Simulation time 103828349896 ps
CPU time 302.85 seconds
Started Aug 29 11:18:47 AM UTC 24
Finished Aug 29 11:23:54 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083217214 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.4083217214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.3457721424
Short name T566
Test name
Test status
Simulation time 2748531200 ps
CPU time 4.15 seconds
Started Aug 29 11:18:41 AM UTC 24
Finished Aug 29 11:18:46 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457721424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3457721424
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/27.uart_tx_rx.851205
Short name T559
Test name
Test status
Simulation time 6115758947 ps
CPU time 18.81 seconds
Started Aug 29 11:18:12 AM UTC 24
Finished Aug 29 11:18:32 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_t
x_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 27.uart_tx_rx.851205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/27.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/270.uart_fifo_reset.1175149150
Short name T1132
Test name
Test status
Simulation time 21389024628 ps
CPU time 39.63 seconds
Started Aug 29 11:41:19 AM UTC 24
Finished Aug 29 11:42:00 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175149150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1175149150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/270.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1553062637
Short name T1117
Test name
Test status
Simulation time 33600715106 ps
CPU time 18.15 seconds
Started Aug 29 11:41:19 AM UTC 24
Finished Aug 29 11:41:39 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553062637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1553062637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/271.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/272.uart_fifo_reset.631774160
Short name T1121
Test name
Test status
Simulation time 8500530670 ps
CPU time 20.66 seconds
Started Aug 29 11:41:19 AM UTC 24
Finished Aug 29 11:41:41 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631774160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.631774160
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/272.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/273.uart_fifo_reset.4080035239
Short name T1142
Test name
Test status
Simulation time 25096940507 ps
CPU time 58.14 seconds
Started Aug 29 11:41:20 AM UTC 24
Finished Aug 29 11:42:20 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080035239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.4080035239
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/273.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/274.uart_fifo_reset.738490254
Short name T1173
Test name
Test status
Simulation time 133401832852 ps
CPU time 316.12 seconds
Started Aug 29 11:41:22 AM UTC 24
Finished Aug 29 11:46:42 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738490254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.738490254
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/274.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/275.uart_fifo_reset.116338819
Short name T182
Test name
Test status
Simulation time 57928912391 ps
CPU time 32.99 seconds
Started Aug 29 11:41:22 AM UTC 24
Finished Aug 29 11:41:56 AM UTC 24
Peak memory 208648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116338819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.116338819
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/275.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/276.uart_fifo_reset.137487676
Short name T1141
Test name
Test status
Simulation time 86615451700 ps
CPU time 53.44 seconds
Started Aug 29 11:41:25 AM UTC 24
Finished Aug 29 11:42:20 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137487676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.137487676
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/276.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/277.uart_fifo_reset.3160308854
Short name T1138
Test name
Test status
Simulation time 33846453047 ps
CPU time 51.77 seconds
Started Aug 29 11:41:25 AM UTC 24
Finished Aug 29 11:42:18 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160308854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3160308854
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/277.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/278.uart_fifo_reset.1189084562
Short name T1131
Test name
Test status
Simulation time 63353462541 ps
CPU time 27.99 seconds
Started Aug 29 11:41:29 AM UTC 24
Finished Aug 29 11:41:59 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189084562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1189084562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/278.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/279.uart_fifo_reset.861110488
Short name T233
Test name
Test status
Simulation time 103817515246 ps
CPU time 194.55 seconds
Started Aug 29 11:41:31 AM UTC 24
Finished Aug 29 11:44:48 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861110488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.861110488
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/279.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_alert_test.855332764
Short name T583
Test name
Test status
Simulation time 13430864 ps
CPU time 0.81 seconds
Started Aug 29 11:19:25 AM UTC 24
Finished Aug 29 11:19:27 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855332764 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.855332764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_fifo_full.3850131504
Short name T599
Test name
Test status
Simulation time 54784093162 ps
CPU time 89.17 seconds
Started Aug 29 11:18:58 AM UTC 24
Finished Aug 29 11:20:29 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850131504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3850131504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.150163327
Short name T589
Test name
Test status
Simulation time 16252490982 ps
CPU time 45.91 seconds
Started Aug 29 11:18:58 AM UTC 24
Finished Aug 29 11:19:46 AM UTC 24
Peak memory 208964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150163327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.150163327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_fifo_reset.4287871386
Short name T212
Test name
Test status
Simulation time 124492980075 ps
CPU time 336 seconds
Started Aug 29 11:18:59 AM UTC 24
Finished Aug 29 11:24:40 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287871386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4287871386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_intr.481535487
Short name T643
Test name
Test status
Simulation time 73219578081 ps
CPU time 216.59 seconds
Started Aug 29 11:19:02 AM UTC 24
Finished Aug 29 11:22:42 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481535487 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.481535487
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.2805696944
Short name T745
Test name
Test status
Simulation time 75493522109 ps
CPU time 458.22 seconds
Started Aug 29 11:19:17 AM UTC 24
Finished Aug 29 11:27:01 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805696944 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2805696944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_loopback.989399573
Short name T581
Test name
Test status
Simulation time 2236180730 ps
CPU time 7.55 seconds
Started Aug 29 11:19:16 AM UTC 24
Finished Aug 29 11:19:24 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989399573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.uart_loopback.989399573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_noise_filter.1977858326
Short name T598
Test name
Test status
Simulation time 79543744047 ps
CPU time 79.6 seconds
Started Aug 29 11:19:08 AM UTC 24
Finished Aug 29 11:20:29 AM UTC 24
Peak memory 217660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977858326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1977858326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_perf.706139635
Short name T657
Test name
Test status
Simulation time 7335726939 ps
CPU time 221.9 seconds
Started Aug 29 11:19:16 AM UTC 24
Finished Aug 29 11:23:01 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706139635 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.706139635
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_rx_oversample.2974469633
Short name T577
Test name
Test status
Simulation time 6966588660 ps
CPU time 14.54 seconds
Started Aug 29 11:18:59 AM UTC 24
Finished Aug 29 11:19:15 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974469633 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2974469633
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.2531536788
Short name T626
Test name
Test status
Simulation time 86541703429 ps
CPU time 156.34 seconds
Started Aug 29 11:19:10 AM UTC 24
Finished Aug 29 11:21:48 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531536788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2531536788
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.1830021767
Short name T647
Test name
Test status
Simulation time 89995358278 ps
CPU time 217.95 seconds
Started Aug 29 11:19:08 AM UTC 24
Finished Aug 29 11:22:49 AM UTC 24
Peak memory 205232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830021767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1830021767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_smoke.2595669586
Short name T570
Test name
Test status
Simulation time 732403708 ps
CPU time 2.52 seconds
Started Aug 29 11:18:54 AM UTC 24
Finished Aug 29 11:18:57 AM UTC 24
Peak memory 207488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595669586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2595669586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_stress_all.4208132463
Short name T737
Test name
Test status
Simulation time 596603979422 ps
CPU time 410.16 seconds
Started Aug 29 11:19:24 AM UTC 24
Finished Aug 29 11:26:19 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208132463 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4208132463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.2720174097
Short name T590
Test name
Test status
Simulation time 3208374416 ps
CPU time 36.96 seconds
Started Aug 29 11:19:20 AM UTC 24
Finished Aug 29 11:19:58 AM UTC 24
Peak memory 217824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2720174097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all
_with_rand_reset.2720174097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.4238314655
Short name T586
Test name
Test status
Simulation time 6985400896 ps
CPU time 27.27 seconds
Started Aug 29 11:19:10 AM UTC 24
Finished Aug 29 11:19:38 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238314655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4238314655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/28.uart_tx_rx.1556109295
Short name T578
Test name
Test status
Simulation time 35959499488 ps
CPU time 18.88 seconds
Started Aug 29 11:18:55 AM UTC 24
Finished Aug 29 11:19:15 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556109295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1556109295
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/28.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/280.uart_fifo_reset.717953113
Short name T1126
Test name
Test status
Simulation time 88594330134 ps
CPU time 17.92 seconds
Started Aug 29 11:41:32 AM UTC 24
Finished Aug 29 11:41:51 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717953113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.717953113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/280.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/281.uart_fifo_reset.3672657434
Short name T1133
Test name
Test status
Simulation time 121386914452 ps
CPU time 28.66 seconds
Started Aug 29 11:41:32 AM UTC 24
Finished Aug 29 11:42:02 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672657434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3672657434
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/281.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/282.uart_fifo_reset.414570334
Short name T1144
Test name
Test status
Simulation time 28417202189 ps
CPU time 59.9 seconds
Started Aug 29 11:41:33 AM UTC 24
Finished Aug 29 11:42:35 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414570334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.414570334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/282.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/283.uart_fifo_reset.2127293442
Short name T1171
Test name
Test status
Simulation time 114658018626 ps
CPU time 275.69 seconds
Started Aug 29 11:41:36 AM UTC 24
Finished Aug 29 11:46:16 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127293442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2127293442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/283.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/285.uart_fifo_reset.2360437335
Short name T1163
Test name
Test status
Simulation time 201243600313 ps
CPU time 133.18 seconds
Started Aug 29 11:41:38 AM UTC 24
Finished Aug 29 11:43:53 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360437335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2360437335
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/285.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/286.uart_fifo_reset.3352949760
Short name T1140
Test name
Test status
Simulation time 86807164718 ps
CPU time 37.96 seconds
Started Aug 29 11:41:40 AM UTC 24
Finished Aug 29 11:42:19 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352949760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3352949760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/286.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/287.uart_fifo_reset.1199373115
Short name T173
Test name
Test status
Simulation time 45810048415 ps
CPU time 84.3 seconds
Started Aug 29 11:41:40 AM UTC 24
Finished Aug 29 11:43:06 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199373115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1199373115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/287.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/288.uart_fifo_reset.4133783648
Short name T1148
Test name
Test status
Simulation time 122040317510 ps
CPU time 70.61 seconds
Started Aug 29 11:41:40 AM UTC 24
Finished Aug 29 11:42:52 AM UTC 24
Peak memory 208592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133783648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.4133783648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/288.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/289.uart_fifo_reset.355740552
Short name T1170
Test name
Test status
Simulation time 126504179829 ps
CPU time 224.4 seconds
Started Aug 29 11:41:41 AM UTC 24
Finished Aug 29 11:45:29 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355740552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.355740552
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/289.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_alert_test.3445171262
Short name T600
Test name
Test status
Simulation time 42891577 ps
CPU time 0.84 seconds
Started Aug 29 11:20:28 AM UTC 24
Finished Aug 29 11:20:29 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445171262 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3445171262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_fifo_full.1522430809
Short name T670
Test name
Test status
Simulation time 125222057768 ps
CPU time 234.28 seconds
Started Aug 29 11:19:30 AM UTC 24
Finished Aug 29 11:23:28 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522430809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1522430809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.978428336
Short name T147
Test name
Test status
Simulation time 100299593605 ps
CPU time 86.64 seconds
Started Aug 29 11:19:31 AM UTC 24
Finished Aug 29 11:21:00 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978428336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.978428336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_fifo_reset.97507251
Short name T161
Test name
Test status
Simulation time 134231371700 ps
CPU time 140.33 seconds
Started Aug 29 11:19:40 AM UTC 24
Finished Aug 29 11:22:03 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97507251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.97507251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_intr.1769322936
Short name T596
Test name
Test status
Simulation time 36039370583 ps
CPU time 44.08 seconds
Started Aug 29 11:19:41 AM UTC 24
Finished Aug 29 11:20:27 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769322936 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1769322936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.3342494530
Short name T659
Test name
Test status
Simulation time 182732868693 ps
CPU time 160.16 seconds
Started Aug 29 11:20:20 AM UTC 24
Finished Aug 29 11:23:03 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342494530 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3342494530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_loopback.1660506207
Short name T594
Test name
Test status
Simulation time 5939652118 ps
CPU time 15.06 seconds
Started Aug 29 11:20:03 AM UTC 24
Finished Aug 29 11:20:19 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660506207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1660506207
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_noise_filter.3806589519
Short name T616
Test name
Test status
Simulation time 116546723715 ps
CPU time 93.13 seconds
Started Aug 29 11:19:44 AM UTC 24
Finished Aug 29 11:21:19 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806589519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3806589519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_perf.2608346166
Short name T612
Test name
Test status
Simulation time 3137238414 ps
CPU time 56.7 seconds
Started Aug 29 11:20:15 AM UTC 24
Finished Aug 29 11:21:13 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608346166 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2608346166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_rx_oversample.3833825952
Short name T602
Test name
Test status
Simulation time 5970517915 ps
CPU time 54.52 seconds
Started Aug 29 11:19:40 AM UTC 24
Finished Aug 29 11:20:36 AM UTC 24
Peak memory 207820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833825952 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3833825952
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.1263597602
Short name T412
Test name
Test status
Simulation time 107641614279 ps
CPU time 130.33 seconds
Started Aug 29 11:19:55 AM UTC 24
Finished Aug 29 11:22:08 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263597602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1263597602
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.3325596710
Short name T591
Test name
Test status
Simulation time 4295457325 ps
CPU time 14.34 seconds
Started Aug 29 11:19:47 AM UTC 24
Finished Aug 29 11:20:02 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325596710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3325596710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_smoke.315702096
Short name T584
Test name
Test status
Simulation time 312241294 ps
CPU time 1.58 seconds
Started Aug 29 11:19:27 AM UTC 24
Finished Aug 29 11:19:30 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315702096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.uart_smoke.315702096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_stress_all.1591404066
Short name T906
Test name
Test status
Simulation time 185328819879 ps
CPU time 774.25 seconds
Started Aug 29 11:20:25 AM UTC 24
Finished Aug 29 11:33:29 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591404066 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1591404066
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.2086576547
Short name T605
Test name
Test status
Simulation time 6845089293 ps
CPU time 35.35 seconds
Started Aug 29 11:20:20 AM UTC 24
Finished Aug 29 11:20:57 AM UTC 24
Peak memory 217580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2086576547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all
_with_rand_reset.2086576547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.1214251013
Short name T592
Test name
Test status
Simulation time 6483023694 ps
CPU time 14.48 seconds
Started Aug 29 11:19:59 AM UTC 24
Finished Aug 29 11:20:15 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214251013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1214251013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/29.uart_tx_rx.3409785865
Short name T604
Test name
Test status
Simulation time 73427054804 ps
CPU time 81.83 seconds
Started Aug 29 11:19:28 AM UTC 24
Finished Aug 29 11:20:52 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409785865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3409785865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/29.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2247335852
Short name T1136
Test name
Test status
Simulation time 36561302996 ps
CPU time 23.73 seconds
Started Aug 29 11:41:43 AM UTC 24
Finished Aug 29 11:42:08 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247335852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2247335852
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/290.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/291.uart_fifo_reset.42171293
Short name T1149
Test name
Test status
Simulation time 138195154761 ps
CPU time 69.66 seconds
Started Aug 29 11:41:43 AM UTC 24
Finished Aug 29 11:42:54 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42171293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.42171293
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/291.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/292.uart_fifo_reset.285156217
Short name T1167
Test name
Test status
Simulation time 151220866360 ps
CPU time 213.08 seconds
Started Aug 29 11:41:44 AM UTC 24
Finished Aug 29 11:45:20 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285156217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.285156217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/292.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/293.uart_fifo_reset.2033992852
Short name T208
Test name
Test status
Simulation time 66500396590 ps
CPU time 196.87 seconds
Started Aug 29 11:41:45 AM UTC 24
Finished Aug 29 11:45:05 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033992852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2033992852
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/293.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/294.uart_fifo_reset.1529212175
Short name T1155
Test name
Test status
Simulation time 69953723517 ps
CPU time 76.94 seconds
Started Aug 29 11:41:49 AM UTC 24
Finished Aug 29 11:43:08 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529212175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1529212175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/294.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/295.uart_fifo_reset.2165538884
Short name T1135
Test name
Test status
Simulation time 9459651429 ps
CPU time 13.94 seconds
Started Aug 29 11:41:51 AM UTC 24
Finished Aug 29 11:42:06 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165538884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2165538884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/295.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/296.uart_fifo_reset.3453008652
Short name T1161
Test name
Test status
Simulation time 127901711985 ps
CPU time 99.39 seconds
Started Aug 29 11:41:53 AM UTC 24
Finished Aug 29 11:43:34 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453008652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3453008652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/296.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/297.uart_fifo_reset.2186872531
Short name T1160
Test name
Test status
Simulation time 27680014100 ps
CPU time 90.79 seconds
Started Aug 29 11:41:55 AM UTC 24
Finished Aug 29 11:43:27 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186872531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2186872531
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/297.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/298.uart_fifo_reset.411576634
Short name T1158
Test name
Test status
Simulation time 100200516772 ps
CPU time 82.38 seconds
Started Aug 29 11:41:56 AM UTC 24
Finished Aug 29 11:43:21 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411576634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.411576634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/298.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_alert_test.1613379392
Short name T422
Test name
Test status
Simulation time 12045198 ps
CPU time 0.74 seconds
Started Aug 29 11:07:01 AM UTC 24
Finished Aug 29 11:07:03 AM UTC 24
Peak memory 204372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613379392 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1613379392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_fifo_reset.2718201736
Short name T96
Test name
Test status
Simulation time 23843673053 ps
CPU time 28.5 seconds
Started Aug 29 11:06:41 AM UTC 24
Finished Aug 29 11:07:11 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718201736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2718201736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_intr.1424296803
Short name T18
Test name
Test status
Simulation time 45155050403 ps
CPU time 46.81 seconds
Started Aug 29 11:06:43 AM UTC 24
Finished Aug 29 11:07:32 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424296803 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1424296803
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.663031626
Short name T505
Test name
Test status
Simulation time 91490971308 ps
CPU time 521.15 seconds
Started Aug 29 11:06:56 AM UTC 24
Finished Aug 29 11:15:43 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663031626 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.663031626
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_loopback.1556830239
Short name T97
Test name
Test status
Simulation time 11643238506 ps
CPU time 21.73 seconds
Started Aug 29 11:06:50 AM UTC 24
Finished Aug 29 11:07:13 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556830239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1556830239
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_noise_filter.257079578
Short name T283
Test name
Test status
Simulation time 167045352591 ps
CPU time 121.82 seconds
Started Aug 29 11:06:45 AM UTC 24
Finished Aug 29 11:08:49 AM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257079578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.257079578
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_perf.1652781958
Short name T645
Test name
Test status
Simulation time 16574397732 ps
CPU time 940.03 seconds
Started Aug 29 11:06:54 AM UTC 24
Finished Aug 29 11:22:45 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652781958 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1652781958
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_rx_oversample.74822362
Short name T43
Test name
Test status
Simulation time 5166046793 ps
CPU time 5.92 seconds
Started Aug 29 11:06:41 AM UTC 24
Finished Aug 29 11:06:48 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74822362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.74822362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.2584054916
Short name T103
Test name
Test status
Simulation time 69955843386 ps
CPU time 40.88 seconds
Started Aug 29 11:06:46 AM UTC 24
Finished Aug 29 11:07:29 AM UTC 24
Peak memory 208516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584054916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2584054916
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.1932092644
Short name T44
Test name
Test status
Simulation time 7129612607 ps
CPU time 12.44 seconds
Started Aug 29 11:06:45 AM UTC 24
Finished Aug 29 11:06:59 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932092644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1932092644
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_sec_cm.2802940250
Short name T86
Test name
Test status
Simulation time 367670780 ps
CPU time 1.36 seconds
Started Aug 29 11:07:01 AM UTC 24
Finished Aug 29 11:07:03 AM UTC 24
Peak memory 240072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802940250 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2802940250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_smoke.3711231882
Short name T41
Test name
Test status
Simulation time 534574962 ps
CPU time 4.64 seconds
Started Aug 29 11:06:39 AM UTC 24
Finished Aug 29 11:06:44 AM UTC 24
Peak memory 207544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711231882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3711231882
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.3345505214
Short name T29
Test name
Test status
Simulation time 772543273 ps
CPU time 5.9 seconds
Started Aug 29 11:06:59 AM UTC 24
Finished Aug 29 11:07:05 AM UTC 24
Peak memory 222032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3345505214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_
with_rand_reset.3345505214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.3001805439
Short name T50
Test name
Test status
Simulation time 7251108414 ps
CPU time 29.34 seconds
Started Aug 29 11:06:49 AM UTC 24
Finished Aug 29 11:07:20 AM UTC 24
Peak memory 208536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001805439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3001805439
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/3.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_alert_test.1528099300
Short name T613
Test name
Test status
Simulation time 14832600 ps
CPU time 0.8 seconds
Started Aug 29 11:21:13 AM UTC 24
Finished Aug 29 11:21:15 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528099300 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1528099300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_fifo_full.2208488133
Short name T608
Test name
Test status
Simulation time 18595863691 ps
CPU time 36.45 seconds
Started Aug 29 11:20:30 AM UTC 24
Finished Aug 29 11:21:08 AM UTC 24
Peak memory 208736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208488133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2208488133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.358492974
Short name T618
Test name
Test status
Simulation time 178779072158 ps
CPU time 51.42 seconds
Started Aug 29 11:20:31 AM UTC 24
Finished Aug 29 11:21:24 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358492974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.358492974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_fifo_reset.3573895334
Short name T622
Test name
Test status
Simulation time 71711170804 ps
CPU time 62.9 seconds
Started Aug 29 11:20:34 AM UTC 24
Finished Aug 29 11:21:38 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573895334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3573895334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_intr.3094767615
Short name T609
Test name
Test status
Simulation time 6115847949 ps
CPU time 18.31 seconds
Started Aug 29 11:20:51 AM UTC 24
Finished Aug 29 11:21:11 AM UTC 24
Peak memory 205024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094767615 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3094767615
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.518218999
Short name T839
Test name
Test status
Simulation time 101096689507 ps
CPU time 616.34 seconds
Started Aug 29 11:21:11 AM UTC 24
Finished Aug 29 11:31:35 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518218999 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.518218999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_loopback.1534648515
Short name T611
Test name
Test status
Simulation time 5169675377 ps
CPU time 9.73 seconds
Started Aug 29 11:21:02 AM UTC 24
Finished Aug 29 11:21:13 AM UTC 24
Peak memory 207644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534648515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1534648515
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_noise_filter.1084632153
Short name T617
Test name
Test status
Simulation time 16701677899 ps
CPU time 27.99 seconds
Started Aug 29 11:20:53 AM UTC 24
Finished Aug 29 11:21:22 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084632153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1084632153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_perf.2871832082
Short name T658
Test name
Test status
Simulation time 6690105592 ps
CPU time 112.02 seconds
Started Aug 29 11:21:09 AM UTC 24
Finished Aug 29 11:23:03 AM UTC 24
Peak memory 208924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871832082 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2871832082
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_rx_oversample.270365032
Short name T615
Test name
Test status
Simulation time 6790232618 ps
CPU time 39.78 seconds
Started Aug 29 11:20:37 AM UTC 24
Finished Aug 29 11:21:18 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270365032 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.270365032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.288895150
Short name T621
Test name
Test status
Simulation time 54521132412 ps
CPU time 36.68 seconds
Started Aug 29 11:21:00 AM UTC 24
Finished Aug 29 11:21:38 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288895150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.288895150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.321438832
Short name T606
Test name
Test status
Simulation time 3332806771 ps
CPU time 1.67 seconds
Started Aug 29 11:20:58 AM UTC 24
Finished Aug 29 11:21:01 AM UTC 24
Peak memory 204504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321438832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.321438832
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_smoke.3284090973
Short name T601
Test name
Test status
Simulation time 934660640 ps
CPU time 2.35 seconds
Started Aug 29 11:20:30 AM UTC 24
Finished Aug 29 11:20:33 AM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284090973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3284090973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_stress_all.665793816
Short name T852
Test name
Test status
Simulation time 787786647345 ps
CPU time 639.68 seconds
Started Aug 29 11:21:12 AM UTC 24
Finished Aug 29 11:31:59 AM UTC 24
Peak memory 217620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665793816 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.665793816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.4048429413
Short name T625
Test name
Test status
Simulation time 3107460558 ps
CPU time 32.17 seconds
Started Aug 29 11:21:12 AM UTC 24
Finished Aug 29 11:21:45 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4048429413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all
_with_rand_reset.4048429413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.2153456353
Short name T619
Test name
Test status
Simulation time 6853664784 ps
CPU time 24.12 seconds
Started Aug 29 11:21:01 AM UTC 24
Finished Aug 29 11:21:27 AM UTC 24
Peak memory 208580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153456353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2153456353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/30.uart_tx_rx.4118344628
Short name T639
Test name
Test status
Simulation time 73672853081 ps
CPU time 113.36 seconds
Started Aug 29 11:20:30 AM UTC 24
Finished Aug 29 11:22:25 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118344628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.4118344628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/30.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_alert_test.4223675748
Short name T627
Test name
Test status
Simulation time 49563753 ps
CPU time 0.83 seconds
Started Aug 29 11:21:46 AM UTC 24
Finished Aug 29 11:21:49 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223675748 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.4223675748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_fifo_full.1145925214
Short name T149
Test name
Test status
Simulation time 102355776399 ps
CPU time 25.31 seconds
Started Aug 29 11:21:15 AM UTC 24
Finished Aug 29 11:21:41 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145925214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1145925214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.138008226
Short name T660
Test name
Test status
Simulation time 63577762658 ps
CPU time 104.56 seconds
Started Aug 29 11:21:18 AM UTC 24
Finished Aug 29 11:23:05 AM UTC 24
Peak memory 208520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138008226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.138008226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_fifo_reset.2755085372
Short name T197
Test name
Test status
Simulation time 25771176492 ps
CPU time 112.81 seconds
Started Aug 29 11:21:19 AM UTC 24
Finished Aug 29 11:23:14 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755085372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2755085372
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_intr.599781739
Short name T637
Test name
Test status
Simulation time 17519413117 ps
CPU time 55.45 seconds
Started Aug 29 11:21:23 AM UTC 24
Finished Aug 29 11:22:21 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599781739 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.599781739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.3902858124
Short name T816
Test name
Test status
Simulation time 125191152858 ps
CPU time 501.01 seconds
Started Aug 29 11:21:41 AM UTC 24
Finished Aug 29 11:30:09 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902858124 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3902858124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_loopback.406723256
Short name T624
Test name
Test status
Simulation time 862852565 ps
CPU time 1.93 seconds
Started Aug 29 11:21:40 AM UTC 24
Finished Aug 29 11:21:43 AM UTC 24
Peak memory 204436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406723256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.uart_loopback.406723256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_noise_filter.2251311294
Short name T411
Test name
Test status
Simulation time 44604394479 ps
CPU time 53.57 seconds
Started Aug 29 11:21:24 AM UTC 24
Finished Aug 29 11:22:20 AM UTC 24
Peak memory 207772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251311294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2251311294
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_perf.1352413130
Short name T695
Test name
Test status
Simulation time 28489174955 ps
CPU time 155.31 seconds
Started Aug 29 11:21:40 AM UTC 24
Finished Aug 29 11:24:18 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352413130 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1352413130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_rx_oversample.4164092994
Short name T640
Test name
Test status
Simulation time 5511765196 ps
CPU time 64.35 seconds
Started Aug 29 11:21:20 AM UTC 24
Finished Aug 29 11:22:26 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164092994 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4164092994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.1310885514
Short name T628
Test name
Test status
Simulation time 33866255325 ps
CPU time 22.71 seconds
Started Aug 29 11:21:30 AM UTC 24
Finished Aug 29 11:21:54 AM UTC 24
Peak memory 208604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310885514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1310885514
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.4002500935
Short name T623
Test name
Test status
Simulation time 2739156457 ps
CPU time 11 seconds
Started Aug 29 11:21:27 AM UTC 24
Finished Aug 29 11:21:40 AM UTC 24
Peak memory 205236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002500935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4002500935
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_smoke.4158204907
Short name T614
Test name
Test status
Simulation time 1075337914 ps
CPU time 2.29 seconds
Started Aug 29 11:21:14 AM UTC 24
Finished Aug 29 11:21:17 AM UTC 24
Peak memory 208192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158204907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4158204907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_stress_all.3950748791
Short name T855
Test name
Test status
Simulation time 269483653224 ps
CPU time 610.12 seconds
Started Aug 29 11:21:44 AM UTC 24
Finished Aug 29 11:32:01 AM UTC 24
Peak memory 217604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950748791 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3950748791
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.3777427173
Short name T678
Test name
Test status
Simulation time 4305290293 ps
CPU time 117.57 seconds
Started Aug 29 11:21:42 AM UTC 24
Finished Aug 29 11:23:43 AM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3777427173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all
_with_rand_reset.3777427173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.1731847234
Short name T629
Test name
Test status
Simulation time 6556088685 ps
CPU time 14.75 seconds
Started Aug 29 11:21:38 AM UTC 24
Finished Aug 29 11:21:54 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731847234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1731847234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/31.uart_tx_rx.1850149286
Short name T668
Test name
Test status
Simulation time 40941220851 ps
CPU time 131.78 seconds
Started Aug 29 11:21:14 AM UTC 24
Finished Aug 29 11:23:28 AM UTC 24
Peak memory 208352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850149286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1850149286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/31.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_alert_test.369051550
Short name T638
Test name
Test status
Simulation time 28072141 ps
CPU time 0.84 seconds
Started Aug 29 11:22:21 AM UTC 24
Finished Aug 29 11:22:23 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369051550 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.369051550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_fifo_full.2884108554
Short name T641
Test name
Test status
Simulation time 107798160735 ps
CPU time 33.25 seconds
Started Aug 29 11:21:54 AM UTC 24
Finished Aug 29 11:22:29 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884108554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2884108554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.1385637251
Short name T680
Test name
Test status
Simulation time 112832008418 ps
CPU time 108.06 seconds
Started Aug 29 11:21:54 AM UTC 24
Finished Aug 29 11:23:45 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385637251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1385637251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_fifo_reset.2182748359
Short name T201
Test name
Test status
Simulation time 106752726585 ps
CPU time 164.68 seconds
Started Aug 29 11:22:01 AM UTC 24
Finished Aug 29 11:24:49 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182748359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2182748359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_intr.3506451119
Short name T652
Test name
Test status
Simulation time 45076591616 ps
CPU time 45.59 seconds
Started Aug 29 11:22:07 AM UTC 24
Finished Aug 29 11:22:54 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506451119 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3506451119
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.81665097
Short name T1179
Test name
Test status
Simulation time 187822114567 ps
CPU time 1909.21 seconds
Started Aug 29 11:22:15 AM UTC 24
Finished Aug 29 11:54:26 AM UTC 24
Peak memory 212264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81665097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.81665097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_loopback.1099578901
Short name T635
Test name
Test status
Simulation time 3076830725 ps
CPU time 1.77 seconds
Started Aug 29 11:22:11 AM UTC 24
Finished Aug 29 11:22:14 AM UTC 24
Peak memory 206492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099578901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1099578901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_noise_filter.1455481693
Short name T417
Test name
Test status
Simulation time 42751032601 ps
CPU time 90.31 seconds
Started Aug 29 11:22:09 AM UTC 24
Finished Aug 29 11:23:41 AM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455481693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1455481693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_perf.4255489398
Short name T790
Test name
Test status
Simulation time 25383620143 ps
CPU time 398.65 seconds
Started Aug 29 11:22:12 AM UTC 24
Finished Aug 29 11:28:56 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255489398 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4255489398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_rx_oversample.2129319444
Short name T631
Test name
Test status
Simulation time 1933163515 ps
CPU time 3.23 seconds
Started Aug 29 11:22:04 AM UTC 24
Finished Aug 29 11:22:08 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129319444 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2129319444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.4033059179
Short name T653
Test name
Test status
Simulation time 24131198152 ps
CPU time 46.02 seconds
Started Aug 29 11:22:09 AM UTC 24
Finished Aug 29 11:22:56 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033059179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.4033059179
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.1811215376
Short name T636
Test name
Test status
Simulation time 2693106037 ps
CPU time 8.33 seconds
Started Aug 29 11:22:09 AM UTC 24
Finished Aug 29 11:22:18 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811215376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1811215376
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_smoke.1728403305
Short name T649
Test name
Test status
Simulation time 11618503227 ps
CPU time 59.95 seconds
Started Aug 29 11:21:49 AM UTC 24
Finished Aug 29 11:22:51 AM UTC 24
Peak memory 208192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728403305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1728403305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_stress_all.3426777441
Short name T821
Test name
Test status
Simulation time 441291779874 ps
CPU time 491.87 seconds
Started Aug 29 11:22:20 AM UTC 24
Finished Aug 29 11:30:38 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426777441 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3426777441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.4072280856
Short name T398
Test name
Test status
Simulation time 3162404525 ps
CPU time 78.46 seconds
Started Aug 29 11:22:19 AM UTC 24
Finished Aug 29 11:23:39 AM UTC 24
Peak memory 219648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4072280856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all
_with_rand_reset.4072280856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.1312854502
Short name T654
Test name
Test status
Simulation time 11950643278 ps
CPU time 44.62 seconds
Started Aug 29 11:22:11 AM UTC 24
Finished Aug 29 11:22:57 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312854502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1312854502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/32.uart_tx_rx.1778830271
Short name T632
Test name
Test status
Simulation time 20484040967 ps
CPU time 17.18 seconds
Started Aug 29 11:21:49 AM UTC 24
Finished Aug 29 11:22:08 AM UTC 24
Peak memory 207828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778830271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1778830271
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/32.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_alert_test.1317764841
Short name T656
Test name
Test status
Simulation time 34274132 ps
CPU time 0.83 seconds
Started Aug 29 11:22:57 AM UTC 24
Finished Aug 29 11:22:59 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317764841 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1317764841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_fifo_full.61714481
Short name T648
Test name
Test status
Simulation time 38260902715 ps
CPU time 22.1 seconds
Started Aug 29 11:22:28 AM UTC 24
Finished Aug 29 11:22:51 AM UTC 24
Peak memory 208604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61714481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.61714481
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.1003639579
Short name T704
Test name
Test status
Simulation time 156175284482 ps
CPU time 133.66 seconds
Started Aug 29 11:22:29 AM UTC 24
Finished Aug 29 11:24:45 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003639579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1003639579
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_fifo_reset.158621119
Short name T655
Test name
Test status
Simulation time 8126111848 ps
CPU time 27.09 seconds
Started Aug 29 11:22:30 AM UTC 24
Finished Aug 29 11:22:58 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158621119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.158621119
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_intr.3344272202
Short name T667
Test name
Test status
Simulation time 59464418680 ps
CPU time 40.83 seconds
Started Aug 29 11:22:43 AM UTC 24
Finished Aug 29 11:23:25 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344272202 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3344272202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.875602459
Short name T931
Test name
Test status
Simulation time 120734436852 ps
CPU time 724.89 seconds
Started Aug 29 11:22:53 AM UTC 24
Finished Aug 29 11:35:06 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875602459 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.875602459
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_loopback.1568114292
Short name T663
Test name
Test status
Simulation time 9127705132 ps
CPU time 21.33 seconds
Started Aug 29 11:22:51 AM UTC 24
Finished Aug 29 11:23:14 AM UTC 24
Peak memory 208168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568114292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1568114292
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_noise_filter.3783173575
Short name T674
Test name
Test status
Simulation time 34587751289 ps
CPU time 50.13 seconds
Started Aug 29 11:22:45 AM UTC 24
Finished Aug 29 11:23:37 AM UTC 24
Peak memory 209092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783173575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3783173575
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_perf.1116549055
Short name T413
Test name
Test status
Simulation time 24031569298 ps
CPU time 131.69 seconds
Started Aug 29 11:22:53 AM UTC 24
Finished Aug 29 11:25:07 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116549055 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1116549055
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_rx_oversample.1091473048
Short name T661
Test name
Test status
Simulation time 6533611344 ps
CPU time 23.58 seconds
Started Aug 29 11:22:41 AM UTC 24
Finished Aug 29 11:23:06 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091473048 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1091473048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.42382494
Short name T407
Test name
Test status
Simulation time 12295496887 ps
CPU time 21.17 seconds
Started Aug 29 11:22:48 AM UTC 24
Finished Aug 29 11:23:11 AM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42382494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.42382494
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.1026267900
Short name T650
Test name
Test status
Simulation time 3992019668 ps
CPU time 4.2 seconds
Started Aug 29 11:22:46 AM UTC 24
Finished Aug 29 11:22:51 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026267900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1026267900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_smoke.2252230253
Short name T644
Test name
Test status
Simulation time 6008319755 ps
CPU time 19.25 seconds
Started Aug 29 11:22:23 AM UTC 24
Finished Aug 29 11:22:44 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252230253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2252230253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.18314074
Short name T94
Test name
Test status
Simulation time 10256372227 ps
CPU time 60.02 seconds
Started Aug 29 11:22:55 AM UTC 24
Finished Aug 29 11:23:56 AM UTC 24
Peak memory 217660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=18314074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all_w
ith_rand_reset.18314074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.2790961279
Short name T651
Test name
Test status
Simulation time 560822456 ps
CPU time 3.26 seconds
Started Aug 29 11:22:49 AM UTC 24
Finished Aug 29 11:22:54 AM UTC 24
Peak memory 207164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790961279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2790961279
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/33.uart_tx_rx.2188946083
Short name T682
Test name
Test status
Simulation time 30505411601 ps
CPU time 78.66 seconds
Started Aug 29 11:22:25 AM UTC 24
Finished Aug 29 11:23:46 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188946083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2188946083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_alert_test.1729781779
Short name T669
Test name
Test status
Simulation time 33586002 ps
CPU time 0.83 seconds
Started Aug 29 11:23:26 AM UTC 24
Finished Aug 29 11:23:28 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729781779 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1729781779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_fifo_full.3436556277
Short name T744
Test name
Test status
Simulation time 98801279182 ps
CPU time 236.28 seconds
Started Aug 29 11:23:00 AM UTC 24
Finished Aug 29 11:27:00 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436556277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3436556277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.292128574
Short name T689
Test name
Test status
Simulation time 68148214448 ps
CPU time 50.27 seconds
Started Aug 29 11:23:02 AM UTC 24
Finished Aug 29 11:23:54 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292128574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.292128574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_fifo_reset.539229623
Short name T672
Test name
Test status
Simulation time 63034101316 ps
CPU time 24.78 seconds
Started Aug 29 11:23:03 AM UTC 24
Finished Aug 29 11:23:30 AM UTC 24
Peak memory 207876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539229623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.539229623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_intr.3385920638
Short name T683
Test name
Test status
Simulation time 53542253524 ps
CPU time 39.71 seconds
Started Aug 29 11:23:05 AM UTC 24
Finished Aug 29 11:23:47 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385920638 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3385920638
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.629890301
Short name T763
Test name
Test status
Simulation time 82743541748 ps
CPU time 259.89 seconds
Started Aug 29 11:23:19 AM UTC 24
Finished Aug 29 11:27:43 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629890301 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.629890301
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_loopback.1701837269
Short name T675
Test name
Test status
Simulation time 4960110285 ps
CPU time 24.67 seconds
Started Aug 29 11:23:15 AM UTC 24
Finished Aug 29 11:23:41 AM UTC 24
Peak memory 208252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701837269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1701837269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_noise_filter.848381315
Short name T696
Test name
Test status
Simulation time 28174194033 ps
CPU time 69.27 seconds
Started Aug 29 11:23:07 AM UTC 24
Finished Aug 29 11:24:18 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848381315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.848381315
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_perf.3989994313
Short name T883
Test name
Test status
Simulation time 12254535135 ps
CPU time 557.14 seconds
Started Aug 29 11:23:18 AM UTC 24
Finished Aug 29 11:32:42 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989994313 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3989994313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_rx_oversample.1260234861
Short name T681
Test name
Test status
Simulation time 4075330352 ps
CPU time 39.88 seconds
Started Aug 29 11:23:04 AM UTC 24
Finished Aug 29 11:23:46 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260234861 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1260234861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.3445137758
Short name T699
Test name
Test status
Simulation time 85491589537 ps
CPU time 72.49 seconds
Started Aug 29 11:23:12 AM UTC 24
Finished Aug 29 11:24:26 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445137758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3445137758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.2582925020
Short name T665
Test name
Test status
Simulation time 4230167803 ps
CPU time 5.15 seconds
Started Aug 29 11:23:12 AM UTC 24
Finished Aug 29 11:23:18 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582925020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2582925020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_smoke.855495027
Short name T666
Test name
Test status
Simulation time 11064023820 ps
CPU time 24.99 seconds
Started Aug 29 11:22:58 AM UTC 24
Finished Aug 29 11:23:25 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855495027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 34.uart_smoke.855495027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_stress_all.2679691513
Short name T774
Test name
Test status
Simulation time 196999805544 ps
CPU time 280.41 seconds
Started Aug 29 11:23:26 AM UTC 24
Finished Aug 29 11:28:10 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679691513 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2679691513
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.4238590019
Short name T676
Test name
Test status
Simulation time 1316798869 ps
CPU time 18.69 seconds
Started Aug 29 11:23:21 AM UTC 24
Finished Aug 29 11:23:41 AM UTC 24
Peak memory 217940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4238590019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all
_with_rand_reset.4238590019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.3570185452
Short name T671
Test name
Test status
Simulation time 6914196304 ps
CPU time 12.66 seconds
Started Aug 29 11:23:15 AM UTC 24
Finished Aug 29 11:23:29 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570185452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3570185452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/34.uart_tx_rx.1909890564
Short name T690
Test name
Test status
Simulation time 75793009526 ps
CPU time 56 seconds
Started Aug 29 11:22:59 AM UTC 24
Finished Aug 29 11:23:57 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909890564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1909890564
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/34.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_alert_test.547545821
Short name T685
Test name
Test status
Simulation time 38769875 ps
CPU time 0.81 seconds
Started Aug 29 11:23:47 AM UTC 24
Finished Aug 29 11:23:48 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547545821 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.547545821
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_fifo_full.52643650
Short name T719
Test name
Test status
Simulation time 45534754044 ps
CPU time 119.14 seconds
Started Aug 29 11:23:30 AM UTC 24
Finished Aug 29 11:25:31 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52643650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.52643650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.2599786999
Short name T779
Test name
Test status
Simulation time 116523360268 ps
CPU time 296.04 seconds
Started Aug 29 11:23:30 AM UTC 24
Finished Aug 29 11:28:30 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599786999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2599786999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_intr.2700337465
Short name T694
Test name
Test status
Simulation time 19018677498 ps
CPU time 31.24 seconds
Started Aug 29 11:23:38 AM UTC 24
Finished Aug 29 11:24:10 AM UTC 24
Peak memory 208236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700337465 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2700337465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.130792610
Short name T1071
Test name
Test status
Simulation time 159694793433 ps
CPU time 986.93 seconds
Started Aug 29 11:23:45 AM UTC 24
Finished Aug 29 11:40:23 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130792610 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.130792610
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_loopback.3313602553
Short name T692
Test name
Test status
Simulation time 8159575267 ps
CPU time 15.65 seconds
Started Aug 29 11:23:42 AM UTC 24
Finished Aug 29 11:23:59 AM UTC 24
Peak memory 207812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313602553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3313602553
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_noise_filter.2535228768
Short name T750
Test name
Test status
Simulation time 120820223167 ps
CPU time 218.31 seconds
Started Aug 29 11:23:40 AM UTC 24
Finished Aug 29 11:27:21 AM UTC 24
Peak memory 217612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535228768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2535228768
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_perf.1123662588
Short name T922
Test name
Test status
Simulation time 10928957501 ps
CPU time 643.97 seconds
Started Aug 29 11:23:43 AM UTC 24
Finished Aug 29 11:34:35 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123662588 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1123662588
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_rx_oversample.2422610329
Short name T706
Test name
Test status
Simulation time 6726179382 ps
CPU time 74.29 seconds
Started Aug 29 11:23:33 AM UTC 24
Finished Aug 29 11:24:49 AM UTC 24
Peak memory 207420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422610329 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2422610329
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.2821595549
Short name T176
Test name
Test status
Simulation time 120144324184 ps
CPU time 84.79 seconds
Started Aug 29 11:23:42 AM UTC 24
Finished Aug 29 11:25:09 AM UTC 24
Peak memory 208864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821595549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2821595549
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.2276766752
Short name T733
Test name
Test status
Simulation time 35530969797 ps
CPU time 141.24 seconds
Started Aug 29 11:23:42 AM UTC 24
Finished Aug 29 11:26:06 AM UTC 24
Peak memory 205236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276766752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2276766752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_smoke.722899777
Short name T677
Test name
Test status
Simulation time 6075711842 ps
CPU time 11.94 seconds
Started Aug 29 11:23:28 AM UTC 24
Finished Aug 29 11:23:41 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722899777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.uart_smoke.722899777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_stress_all.3327671362
Short name T752
Test name
Test status
Simulation time 54985158414 ps
CPU time 216.66 seconds
Started Aug 29 11:23:47 AM UTC 24
Finished Aug 29 11:27:26 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327671362 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3327671362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.3600022382
Short name T701
Test name
Test status
Simulation time 11150697362 ps
CPU time 55.58 seconds
Started Aug 29 11:23:45 AM UTC 24
Finished Aug 29 11:24:43 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3600022382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all
_with_rand_reset.3600022382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.1100250013
Short name T684
Test name
Test status
Simulation time 804998303 ps
CPU time 4.45 seconds
Started Aug 29 11:23:42 AM UTC 24
Finished Aug 29 11:23:48 AM UTC 24
Peak memory 208576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100250013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1100250013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/35.uart_tx_rx.229446068
Short name T686
Test name
Test status
Simulation time 14750573275 ps
CPU time 19.25 seconds
Started Aug 29 11:23:30 AM UTC 24
Finished Aug 29 11:23:50 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229446068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.229446068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_alert_test.3805375874
Short name T700
Test name
Test status
Simulation time 42112788 ps
CPU time 0.82 seconds
Started Aug 29 11:24:26 AM UTC 24
Finished Aug 29 11:24:28 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805375874 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3805375874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_fifo_full.836561188
Short name T782
Test name
Test status
Simulation time 292048736966 ps
CPU time 283.36 seconds
Started Aug 29 11:23:49 AM UTC 24
Finished Aug 29 11:28:36 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836561188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.836561188
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.497025889
Short name T713
Test name
Test status
Simulation time 52700305212 ps
CPU time 88.14 seconds
Started Aug 29 11:23:51 AM UTC 24
Finished Aug 29 11:25:21 AM UTC 24
Peak memory 208648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497025889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.497025889
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_fifo_reset.873693627
Short name T723
Test name
Test status
Simulation time 85687294387 ps
CPU time 103.65 seconds
Started Aug 29 11:23:54 AM UTC 24
Finished Aug 29 11:25:40 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873693627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.873693627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_intr.2216219100
Short name T1052
Test name
Test status
Simulation time 356476006795 ps
CPU time 937.69 seconds
Started Aug 29 11:23:55 AM UTC 24
Finished Aug 29 11:39:45 AM UTC 24
Peak memory 208292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216219100 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2216219100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.2602502871
Short name T798
Test name
Test status
Simulation time 72858489177 ps
CPU time 294.82 seconds
Started Aug 29 11:24:19 AM UTC 24
Finished Aug 29 11:29:18 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602502871 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2602502871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_loopback.3419375737
Short name T708
Test name
Test status
Simulation time 7908694191 ps
CPU time 51.15 seconds
Started Aug 29 11:24:11 AM UTC 24
Finished Aug 29 11:25:04 AM UTC 24
Peak memory 208012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419375737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3419375737
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_noise_filter.2362051649
Short name T726
Test name
Test status
Simulation time 33656338346 ps
CPU time 107.62 seconds
Started Aug 29 11:23:57 AM UTC 24
Finished Aug 29 11:25:47 AM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362051649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2362051649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_perf.4242750264
Short name T796
Test name
Test status
Simulation time 29238524006 ps
CPU time 291.75 seconds
Started Aug 29 11:24:19 AM UTC 24
Finished Aug 29 11:29:15 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242750264 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4242750264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_rx_oversample.1052146064
Short name T702
Test name
Test status
Simulation time 4091933914 ps
CPU time 47.2 seconds
Started Aug 29 11:23:54 AM UTC 24
Finished Aug 29 11:24:43 AM UTC 24
Peak memory 208232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052146064 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1052146064
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.3643316396
Short name T731
Test name
Test status
Simulation time 32242166090 ps
CPU time 109.44 seconds
Started Aug 29 11:24:00 AM UTC 24
Finished Aug 29 11:25:51 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643316396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3643316396
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.1552145197
Short name T693
Test name
Test status
Simulation time 2887087632 ps
CPU time 4.09 seconds
Started Aug 29 11:23:57 AM UTC 24
Finished Aug 29 11:24:03 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552145197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1552145197
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_smoke.3653732304
Short name T687
Test name
Test status
Simulation time 605545532 ps
CPU time 4.44 seconds
Started Aug 29 11:23:48 AM UTC 24
Finished Aug 29 11:23:53 AM UTC 24
Peak memory 208520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653732304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3653732304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_stress_all.3374057696
Short name T162
Test name
Test status
Simulation time 174064386109 ps
CPU time 59.14 seconds
Started Aug 29 11:24:25 AM UTC 24
Finished Aug 29 11:25:26 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374057696 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3374057696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.1719084829
Short name T720
Test name
Test status
Simulation time 14896003760 ps
CPU time 69.53 seconds
Started Aug 29 11:24:20 AM UTC 24
Finished Aug 29 11:25:31 AM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1719084829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all
_with_rand_reset.1719084829
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.638432403
Short name T697
Test name
Test status
Simulation time 8116655984 ps
CPU time 14.86 seconds
Started Aug 29 11:24:04 AM UTC 24
Finished Aug 29 11:24:20 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638432403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.638432403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/36.uart_tx_rx.2089716497
Short name T698
Test name
Test status
Simulation time 24713588953 ps
CPU time 34.15 seconds
Started Aug 29 11:23:49 AM UTC 24
Finished Aug 29 11:24:24 AM UTC 24
Peak memory 208452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089716497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2089716497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/36.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_alert_test.3945688597
Short name T714
Test name
Test status
Simulation time 20181197 ps
CPU time 0.81 seconds
Started Aug 29 11:25:20 AM UTC 24
Finished Aug 29 11:25:22 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945688597 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3945688597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_fifo_full.2235762348
Short name T747
Test name
Test status
Simulation time 88483659644 ps
CPU time 150.97 seconds
Started Aug 29 11:24:44 AM UTC 24
Finished Aug 29 11:27:17 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235762348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2235762348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.1250562195
Short name T743
Test name
Test status
Simulation time 131271073448 ps
CPU time 125.32 seconds
Started Aug 29 11:24:44 AM UTC 24
Finished Aug 29 11:26:52 AM UTC 24
Peak memory 208908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250562195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1250562195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_fifo_reset.3826979387
Short name T711
Test name
Test status
Simulation time 17369009227 ps
CPU time 27.11 seconds
Started Aug 29 11:24:44 AM UTC 24
Finished Aug 29 11:25:12 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826979387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3826979387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_intr.2509748330
Short name T725
Test name
Test status
Simulation time 31704297136 ps
CPU time 53.72 seconds
Started Aug 29 11:24:50 AM UTC 24
Finished Aug 29 11:25:45 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509748330 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2509748330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.2248403842
Short name T851
Test name
Test status
Simulation time 30005827131 ps
CPU time 402.14 seconds
Started Aug 29 11:25:08 AM UTC 24
Finished Aug 29 11:31:56 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248403842 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2248403842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_loopback.4240148596
Short name T716
Test name
Test status
Simulation time 5207546375 ps
CPU time 19.28 seconds
Started Aug 29 11:25:07 AM UTC 24
Finished Aug 29 11:25:28 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240148596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4240148596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_noise_filter.411287642
Short name T742
Test name
Test status
Simulation time 304651533852 ps
CPU time 117.89 seconds
Started Aug 29 11:24:50 AM UTC 24
Finished Aug 29 11:26:50 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411287642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.411287642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_perf.2204824756
Short name T889
Test name
Test status
Simulation time 9787879985 ps
CPU time 460.61 seconds
Started Aug 29 11:25:08 AM UTC 24
Finished Aug 29 11:32:55 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204824756 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2204824756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_rx_oversample.2550569381
Short name T705
Test name
Test status
Simulation time 1420179849 ps
CPU time 1.89 seconds
Started Aug 29 11:24:46 AM UTC 24
Finished Aug 29 11:24:49 AM UTC 24
Peak memory 206396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550569381 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2550569381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.803740009
Short name T712
Test name
Test status
Simulation time 11363801512 ps
CPU time 20.18 seconds
Started Aug 29 11:24:57 AM UTC 24
Finished Aug 29 11:25:19 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803740009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.803740009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.1078248094
Short name T717
Test name
Test status
Simulation time 45068236817 ps
CPU time 37.71 seconds
Started Aug 29 11:24:50 AM UTC 24
Finished Aug 29 11:25:29 AM UTC 24
Peak memory 205236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078248094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1078248094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_smoke.2544587206
Short name T703
Test name
Test status
Simulation time 5490194570 ps
CPU time 12.52 seconds
Started Aug 29 11:24:29 AM UTC 24
Finished Aug 29 11:24:43 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544587206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2544587206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_stress_all.481135385
Short name T237
Test name
Test status
Simulation time 630187495811 ps
CPU time 333.04 seconds
Started Aug 29 11:25:14 AM UTC 24
Finished Aug 29 11:30:51 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481135385 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.481135385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.3272165978
Short name T732
Test name
Test status
Simulation time 6800519723 ps
CPU time 49.76 seconds
Started Aug 29 11:25:10 AM UTC 24
Finished Aug 29 11:26:01 AM UTC 24
Peak memory 217516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3272165978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all
_with_rand_reset.3272165978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.1816528539
Short name T710
Test name
Test status
Simulation time 1840363451 ps
CPU time 2.84 seconds
Started Aug 29 11:25:04 AM UTC 24
Finished Aug 29 11:25:08 AM UTC 24
Peak memory 207572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816528539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1816528539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/37.uart_tx_rx.2410182178
Short name T751
Test name
Test status
Simulation time 50900972440 ps
CPU time 161.15 seconds
Started Aug 29 11:24:40 AM UTC 24
Finished Aug 29 11:27:24 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410182178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2410182178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/37.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_alert_test.1613816313
Short name T729
Test name
Test status
Simulation time 158767488 ps
CPU time 0.83 seconds
Started Aug 29 11:25:46 AM UTC 24
Finished Aug 29 11:25:48 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613816313 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1613816313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_fifo_full.2882693091
Short name T800
Test name
Test status
Simulation time 110281163860 ps
CPU time 229.91 seconds
Started Aug 29 11:25:27 AM UTC 24
Finished Aug 29 11:29:20 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882693091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2882693091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.915674541
Short name T734
Test name
Test status
Simulation time 187243188055 ps
CPU time 38.29 seconds
Started Aug 29 11:25:28 AM UTC 24
Finished Aug 29 11:26:08 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915674541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.915674541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_fifo_reset.3907898584
Short name T419
Test name
Test status
Simulation time 130281171073 ps
CPU time 229.37 seconds
Started Aug 29 11:25:28 AM UTC 24
Finished Aug 29 11:29:21 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907898584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3907898584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_intr.764865302
Short name T728
Test name
Test status
Simulation time 9095792085 ps
CPU time 15.97 seconds
Started Aug 29 11:25:30 AM UTC 24
Finished Aug 29 11:25:48 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764865302 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.764865302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.1677197930
Short name T917
Test name
Test status
Simulation time 66974254430 ps
CPU time 497.49 seconds
Started Aug 29 11:25:39 AM UTC 24
Finished Aug 29 11:34:03 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677197930 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1677197930
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_loopback.3268067511
Short name T727
Test name
Test status
Simulation time 2408508479 ps
CPU time 9.36 seconds
Started Aug 29 11:25:37 AM UTC 24
Finished Aug 29 11:25:47 AM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268067511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3268067511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_noise_filter.2408333988
Short name T418
Test name
Test status
Simulation time 56851008617 ps
CPU time 48.71 seconds
Started Aug 29 11:25:31 AM UTC 24
Finished Aug 29 11:26:22 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408333988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2408333988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_perf.3949003667
Short name T777
Test name
Test status
Simulation time 14462848592 ps
CPU time 160.7 seconds
Started Aug 29 11:25:38 AM UTC 24
Finished Aug 29 11:28:21 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949003667 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3949003667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_rx_oversample.1848464054
Short name T724
Test name
Test status
Simulation time 4157865407 ps
CPU time 10.91 seconds
Started Aug 29 11:25:30 AM UTC 24
Finished Aug 29 11:25:42 AM UTC 24
Peak memory 207356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848464054 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1848464054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.3402524601
Short name T163
Test name
Test status
Simulation time 99727272657 ps
CPU time 54.59 seconds
Started Aug 29 11:25:33 AM UTC 24
Finished Aug 29 11:26:29 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402524601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3402524601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.3842831154
Short name T721
Test name
Test status
Simulation time 2797530423 ps
CPU time 2.64 seconds
Started Aug 29 11:25:33 AM UTC 24
Finished Aug 29 11:25:36 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842831154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3842831154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_smoke.4024187044
Short name T718
Test name
Test status
Simulation time 6409851779 ps
CPU time 7 seconds
Started Aug 29 11:25:22 AM UTC 24
Finished Aug 29 11:25:30 AM UTC 24
Peak memory 207836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024187044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4024187044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_stress_all.1747073315
Short name T1182
Test name
Test status
Simulation time 376693404959 ps
CPU time 3756.08 seconds
Started Aug 29 11:25:43 AM UTC 24
Finished Aug 29 12:29:02 PM UTC 24
Peak memory 212148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747073315 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1747073315
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.1922668577
Short name T722
Test name
Test status
Simulation time 318190261 ps
CPU time 2.11 seconds
Started Aug 29 11:25:35 AM UTC 24
Finished Aug 29 11:25:38 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922668577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1922668577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/38.uart_tx_rx.2724724885
Short name T748
Test name
Test status
Simulation time 55658169283 ps
CPU time 113.72 seconds
Started Aug 29 11:25:22 AM UTC 24
Finished Aug 29 11:27:18 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724724885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2724724885
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_alert_test.2318372222
Short name T741
Test name
Test status
Simulation time 24693459 ps
CPU time 0.82 seconds
Started Aug 29 11:26:34 AM UTC 24
Finished Aug 29 11:26:36 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318372222 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2318372222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_fifo_full.2144694111
Short name T157
Test name
Test status
Simulation time 130345835473 ps
CPU time 102.33 seconds
Started Aug 29 11:25:49 AM UTC 24
Finished Aug 29 11:27:33 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144694111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2144694111
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.3162548671
Short name T746
Test name
Test status
Simulation time 110355200244 ps
CPU time 84.49 seconds
Started Aug 29 11:25:50 AM UTC 24
Finished Aug 29 11:27:16 AM UTC 24
Peak memory 208864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162548671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3162548671
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_fifo_reset.3998209951
Short name T230
Test name
Test status
Simulation time 113276590045 ps
CPU time 294.56 seconds
Started Aug 29 11:25:51 AM UTC 24
Finished Aug 29 11:30:49 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998209951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3998209951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_intr.3127135963
Short name T755
Test name
Test status
Simulation time 82312642071 ps
CPU time 85.78 seconds
Started Aug 29 11:26:02 AM UTC 24
Finished Aug 29 11:27:29 AM UTC 24
Peak memory 208800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127135963 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3127135963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.2717546657
Short name T930
Test name
Test status
Simulation time 98106476409 ps
CPU time 511.44 seconds
Started Aug 29 11:26:25 AM UTC 24
Finished Aug 29 11:35:02 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717546657 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2717546657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_loopback.1483539857
Short name T739
Test name
Test status
Simulation time 12161953106 ps
CPU time 7.52 seconds
Started Aug 29 11:26:20 AM UTC 24
Finished Aug 29 11:26:29 AM UTC 24
Peak memory 207620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483539857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1483539857
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_noise_filter.110608543
Short name T761
Test name
Test status
Simulation time 53513286536 ps
CPU time 88.55 seconds
Started Aug 29 11:26:07 AM UTC 24
Finished Aug 29 11:27:38 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110608543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.110608543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_perf.38319913
Short name T797
Test name
Test status
Simulation time 4174419135 ps
CPU time 169.27 seconds
Started Aug 29 11:26:22 AM UTC 24
Finished Aug 29 11:29:15 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38319913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.38319913
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_rx_oversample.2312289005
Short name T736
Test name
Test status
Simulation time 6981845531 ps
CPU time 22.69 seconds
Started Aug 29 11:25:52 AM UTC 24
Finished Aug 29 11:26:16 AM UTC 24
Peak memory 208104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312289005 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2312289005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.3566115524
Short name T789
Test name
Test status
Simulation time 132130145140 ps
CPU time 157.95 seconds
Started Aug 29 11:26:14 AM UTC 24
Finished Aug 29 11:28:55 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566115524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3566115524
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.2067299829
Short name T735
Test name
Test status
Simulation time 729602020 ps
CPU time 3.52 seconds
Started Aug 29 11:26:09 AM UTC 24
Finished Aug 29 11:26:14 AM UTC 24
Peak memory 205172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067299829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2067299829
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_smoke.1803528462
Short name T738
Test name
Test status
Simulation time 5489012344 ps
CPU time 33.91 seconds
Started Aug 29 11:25:48 AM UTC 24
Finished Aug 29 11:26:24 AM UTC 24
Peak memory 208476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803528462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1803528462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_stress_all.3782313623
Short name T158
Test name
Test status
Simulation time 302708609267 ps
CPU time 531.74 seconds
Started Aug 29 11:26:30 AM UTC 24
Finished Aug 29 11:35:28 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782313623 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3782313623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.3783400328
Short name T770
Test name
Test status
Simulation time 3124334514 ps
CPU time 93.39 seconds
Started Aug 29 11:26:30 AM UTC 24
Finished Aug 29 11:28:05 AM UTC 24
Peak memory 217616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3783400328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all
_with_rand_reset.3783400328
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1398144906
Short name T756
Test name
Test status
Simulation time 12142196682 ps
CPU time 72.9 seconds
Started Aug 29 11:26:16 AM UTC 24
Finished Aug 29 11:27:31 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398144906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1398144906
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/39.uart_tx_rx.1153197701
Short name T780
Test name
Test status
Simulation time 148013127486 ps
CPU time 161.31 seconds
Started Aug 29 11:25:48 AM UTC 24
Finished Aug 29 11:28:33 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153197701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1153197701
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/39.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_alert_test.4025980310
Short name T423
Test name
Test status
Simulation time 14753440 ps
CPU time 0.86 seconds
Started Aug 29 11:07:24 AM UTC 24
Finished Aug 29 11:07:26 AM UTC 24
Peak memory 204436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025980310 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4025980310
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_fifo_full.107100512
Short name T130
Test name
Test status
Simulation time 67808256261 ps
CPU time 31.45 seconds
Started Aug 29 11:07:01 AM UTC 24
Finished Aug 29 11:07:34 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107100512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.107100512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.1757323787
Short name T125
Test name
Test status
Simulation time 33379582380 ps
CPU time 19.18 seconds
Started Aug 29 11:07:03 AM UTC 24
Finished Aug 29 11:07:23 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757323787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1757323787
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_fifo_reset.1065631950
Short name T133
Test name
Test status
Simulation time 77800071221 ps
CPU time 29.87 seconds
Started Aug 29 11:07:04 AM UTC 24
Finished Aug 29 11:07:35 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065631950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1065631950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_intr.1295491126
Short name T108
Test name
Test status
Simulation time 31144968840 ps
CPU time 25.97 seconds
Started Aug 29 11:07:07 AM UTC 24
Finished Aug 29 11:07:34 AM UTC 24
Peak memory 208576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295491126 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1295491126
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.3099519268
Short name T574
Test name
Test status
Simulation time 109730853028 ps
CPU time 698.52 seconds
Started Aug 29 11:07:15 AM UTC 24
Finished Aug 29 11:19:01 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099519268 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3099519268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_loopback.4130836113
Short name T424
Test name
Test status
Simulation time 8529930485 ps
CPU time 18.41 seconds
Started Aug 29 11:07:12 AM UTC 24
Finished Aug 29 11:07:31 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130836113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4130836113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_noise_filter.78775059
Short name T308
Test name
Test status
Simulation time 43064440016 ps
CPU time 30.97 seconds
Started Aug 29 11:07:10 AM UTC 24
Finished Aug 29 11:07:43 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78775059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.78775059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_perf.740355155
Short name T330
Test name
Test status
Simulation time 9093395180 ps
CPU time 263.03 seconds
Started Aug 29 11:07:14 AM UTC 24
Finished Aug 29 11:11:40 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740355155 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.740355155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_rx_oversample.1360505739
Short name T28
Test name
Test status
Simulation time 2011599117 ps
CPU time 17.6 seconds
Started Aug 29 11:07:06 AM UTC 24
Finished Aug 29 11:07:25 AM UTC 24
Peak memory 208232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360505739 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1360505739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.2371136656
Short name T123
Test name
Test status
Simulation time 73710129712 ps
CPU time 27.99 seconds
Started Aug 29 11:07:10 AM UTC 24
Finished Aug 29 11:07:40 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371136656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2371136656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.2125835390
Short name T339
Test name
Test status
Simulation time 33044010369 ps
CPU time 26.84 seconds
Started Aug 29 11:07:10 AM UTC 24
Finished Aug 29 11:07:39 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125835390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2125835390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_sec_cm.4000128968
Short name T87
Test name
Test status
Simulation time 160517788 ps
CPU time 1.02 seconds
Started Aug 29 11:07:21 AM UTC 24
Finished Aug 29 11:07:23 AM UTC 24
Peak memory 240136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000128968 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.4000128968
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_smoke.2692551911
Short name T49
Test name
Test status
Simulation time 5567804954 ps
CPU time 7.54 seconds
Started Aug 29 11:07:01 AM UTC 24
Finished Aug 29 11:07:09 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692551911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2692551911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_stress_all.1306709251
Short name T53
Test name
Test status
Simulation time 33645346621 ps
CPU time 54.62 seconds
Started Aug 29 11:07:18 AM UTC 24
Finished Aug 29 11:08:14 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306709251 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1306709251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.850449088
Short name T36
Test name
Test status
Simulation time 26703016331 ps
CPU time 63.46 seconds
Started Aug 29 11:07:15 AM UTC 24
Finished Aug 29 11:08:20 AM UTC 24
Peak memory 221892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=850449088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_w
ith_rand_reset.850449088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.1630864946
Short name T318
Test name
Test status
Simulation time 6558890005 ps
CPU time 23.03 seconds
Started Aug 29 11:07:11 AM UTC 24
Finished Aug 29 11:07:36 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630864946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1630864946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/4.uart_tx_rx.2879210491
Short name T294
Test name
Test status
Simulation time 84263090828 ps
CPU time 218.07 seconds
Started Aug 29 11:07:01 AM UTC 24
Finished Aug 29 11:10:42 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879210491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2879210491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/4.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_alert_test.3807596986
Short name T757
Test name
Test status
Simulation time 22647587 ps
CPU time 0.81 seconds
Started Aug 29 11:27:30 AM UTC 24
Finished Aug 29 11:27:32 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807596986 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3807596986
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_fifo_full.4055252299
Short name T945
Test name
Test status
Simulation time 146613649674 ps
CPU time 520.61 seconds
Started Aug 29 11:26:52 AM UTC 24
Finished Aug 29 11:35:38 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055252299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.4055252299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.942866761
Short name T758
Test name
Test status
Simulation time 79803609962 ps
CPU time 38.97 seconds
Started Aug 29 11:26:53 AM UTC 24
Finished Aug 29 11:27:33 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942866761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.942866761
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_intr.2192125184
Short name T764
Test name
Test status
Simulation time 36738954159 ps
CPU time 40.69 seconds
Started Aug 29 11:27:02 AM UTC 24
Finished Aug 29 11:27:44 AM UTC 24
Peak memory 208592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192125184 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2192125184
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.2632185529
Short name T941
Test name
Test status
Simulation time 86682330566 ps
CPU time 480.79 seconds
Started Aug 29 11:27:27 AM UTC 24
Finished Aug 29 11:35:35 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632185529 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2632185529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_loopback.3274060899
Short name T760
Test name
Test status
Simulation time 9070638356 ps
CPU time 13.47 seconds
Started Aug 29 11:27:22 AM UTC 24
Finished Aug 29 11:27:37 AM UTC 24
Peak memory 208500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274060899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3274060899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_noise_filter.2635360269
Short name T762
Test name
Test status
Simulation time 17219507801 ps
CPU time 23.04 seconds
Started Aug 29 11:27:16 AM UTC 24
Finished Aug 29 11:27:41 AM UTC 24
Peak memory 205432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635360269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2635360269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_perf.203451033
Short name T835
Test name
Test status
Simulation time 7829069406 ps
CPU time 231.32 seconds
Started Aug 29 11:27:25 AM UTC 24
Finished Aug 29 11:31:20 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203451033 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.203451033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_rx_oversample.502967157
Short name T776
Test name
Test status
Simulation time 6618135723 ps
CPU time 77.15 seconds
Started Aug 29 11:27:01 AM UTC 24
Finished Aug 29 11:28:20 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502967157 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.502967157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.526705201
Short name T793
Test name
Test status
Simulation time 61727473028 ps
CPU time 104.65 seconds
Started Aug 29 11:27:19 AM UTC 24
Finished Aug 29 11:29:05 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526705201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.526705201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.1994246556
Short name T749
Test name
Test status
Simulation time 700593342 ps
CPU time 1.37 seconds
Started Aug 29 11:27:19 AM UTC 24
Finished Aug 29 11:27:21 AM UTC 24
Peak memory 204444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994246556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1994246556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_smoke.741603631
Short name T691
Test name
Test status
Simulation time 6332666126 ps
CPU time 13.26 seconds
Started Aug 29 11:26:37 AM UTC 24
Finished Aug 29 11:26:52 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741603631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 40.uart_smoke.741603631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1205587198
Short name T766
Test name
Test status
Simulation time 1174259039 ps
CPU time 18.91 seconds
Started Aug 29 11:27:29 AM UTC 24
Finished Aug 29 11:27:49 AM UTC 24
Peak memory 209044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1205587198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all
_with_rand_reset.1205587198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.3444987982
Short name T753
Test name
Test status
Simulation time 766272724 ps
CPU time 4.41 seconds
Started Aug 29 11:27:22 AM UTC 24
Finished Aug 29 11:27:28 AM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444987982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3444987982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/40.uart_tx_rx.2270284280
Short name T769
Test name
Test status
Simulation time 100668677529 ps
CPU time 65.91 seconds
Started Aug 29 11:26:49 AM UTC 24
Finished Aug 29 11:27:57 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270284280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2270284280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/40.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_alert_test.2857222226
Short name T771
Test name
Test status
Simulation time 37810343 ps
CPU time 0.83 seconds
Started Aug 29 11:28:06 AM UTC 24
Finished Aug 29 11:28:08 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857222226 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2857222226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_fifo_full.44482188
Short name T167
Test name
Test status
Simulation time 226429288044 ps
CPU time 85.72 seconds
Started Aug 29 11:27:33 AM UTC 24
Finished Aug 29 11:29:01 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44482188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.44482188
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.4036610714
Short name T164
Test name
Test status
Simulation time 141253879153 ps
CPU time 127.64 seconds
Started Aug 29 11:27:35 AM UTC 24
Finished Aug 29 11:29:44 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036610714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.4036610714
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_fifo_reset.2457957387
Short name T772
Test name
Test status
Simulation time 70617003114 ps
CPU time 29.71 seconds
Started Aug 29 11:27:38 AM UTC 24
Finished Aug 29 11:28:09 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457957387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2457957387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_intr.3795087774
Short name T810
Test name
Test status
Simulation time 33206938142 ps
CPU time 133.64 seconds
Started Aug 29 11:27:39 AM UTC 24
Finished Aug 29 11:29:55 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795087774 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3795087774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.828336796
Short name T893
Test name
Test status
Simulation time 99089696183 ps
CPU time 301.46 seconds
Started Aug 29 11:27:56 AM UTC 24
Finished Aug 29 11:33:01 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828336796 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.828336796
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_loopback.4046860916
Short name T778
Test name
Test status
Simulation time 3981675904 ps
CPU time 30.46 seconds
Started Aug 29 11:27:50 AM UTC 24
Finished Aug 29 11:28:22 AM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046860916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.uart_loopback.4046860916
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_noise_filter.3085536783
Short name T773
Test name
Test status
Simulation time 32542515404 ps
CPU time 27.41 seconds
Started Aug 29 11:27:41 AM UTC 24
Finished Aug 29 11:28:10 AM UTC 24
Peak memory 207596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085536783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3085536783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_perf.1748037285
Short name T1143
Test name
Test status
Simulation time 27399006333 ps
CPU time 869.29 seconds
Started Aug 29 11:27:54 AM UTC 24
Finished Aug 29 11:42:33 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748037285 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1748037285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_rx_oversample.2988269531
Short name T787
Test name
Test status
Simulation time 5771459900 ps
CPU time 68.18 seconds
Started Aug 29 11:27:38 AM UTC 24
Finished Aug 29 11:28:48 AM UTC 24
Peak memory 207420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988269531 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2988269531
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.724514056
Short name T849
Test name
Test status
Simulation time 167607606176 ps
CPU time 245.31 seconds
Started Aug 29 11:27:46 AM UTC 24
Finished Aug 29 11:31:54 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724514056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.724514056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.4065180911
Short name T768
Test name
Test status
Simulation time 2499480304 ps
CPU time 9.75 seconds
Started Aug 29 11:27:43 AM UTC 24
Finished Aug 29 11:27:55 AM UTC 24
Peak memory 205300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065180911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.4065180911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_smoke.2191613075
Short name T759
Test name
Test status
Simulation time 659536416 ps
CPU time 3.34 seconds
Started Aug 29 11:27:32 AM UTC 24
Finished Aug 29 11:27:37 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191613075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2191613075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_stress_all.4001949681
Short name T863
Test name
Test status
Simulation time 274319999989 ps
CPU time 251.66 seconds
Started Aug 29 11:27:58 AM UTC 24
Finished Aug 29 11:32:13 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001949681 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4001949681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.2180535732
Short name T783
Test name
Test status
Simulation time 2099378053 ps
CPU time 44.07 seconds
Started Aug 29 11:27:56 AM UTC 24
Finished Aug 29 11:28:41 AM UTC 24
Peak memory 223940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2180535732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all
_with_rand_reset.2180535732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.2145960467
Short name T767
Test name
Test status
Simulation time 1107879782 ps
CPU time 2.9 seconds
Started Aug 29 11:27:49 AM UTC 24
Finished Aug 29 11:27:53 AM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145960467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2145960467
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/41.uart_tx_rx.2898186482
Short name T801
Test name
Test status
Simulation time 111922029326 ps
CPU time 106.63 seconds
Started Aug 29 11:27:33 AM UTC 24
Finished Aug 29 11:29:22 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898186482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2898186482
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/41.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_alert_test.2011062628
Short name T788
Test name
Test status
Simulation time 10997603 ps
CPU time 0.81 seconds
Started Aug 29 11:28:49 AM UTC 24
Finished Aug 29 11:28:51 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011062628 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2011062628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_fifo_full.3062852688
Short name T837
Test name
Test status
Simulation time 89217608164 ps
CPU time 187.52 seconds
Started Aug 29 11:28:12 AM UTC 24
Finished Aug 29 11:31:22 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062852688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3062852688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_fifo_reset.3400756295
Short name T198
Test name
Test status
Simulation time 82566116020 ps
CPU time 121.55 seconds
Started Aug 29 11:28:15 AM UTC 24
Finished Aug 29 11:30:18 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400756295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3400756295
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_intr.1272510615
Short name T825
Test name
Test status
Simulation time 40886991625 ps
CPU time 155.39 seconds
Started Aug 29 11:28:22 AM UTC 24
Finished Aug 29 11:31:00 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272510615 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1272510615
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.811650784
Short name T1004
Test name
Test status
Simulation time 175938696669 ps
CPU time 531.39 seconds
Started Aug 29 11:28:43 AM UTC 24
Finished Aug 29 11:37:41 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811650784 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.811650784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_loopback.1094103015
Short name T784
Test name
Test status
Simulation time 1202546654 ps
CPU time 4.88 seconds
Started Aug 29 11:28:37 AM UTC 24
Finished Aug 29 11:28:43 AM UTC 24
Peak memory 207552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094103015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1094103015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_noise_filter.1218196806
Short name T792
Test name
Test status
Simulation time 43471761252 ps
CPU time 33.94 seconds
Started Aug 29 11:28:23 AM UTC 24
Finished Aug 29 11:28:59 AM UTC 24
Peak memory 209092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218196806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1218196806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_perf.4037195937
Short name T844
Test name
Test status
Simulation time 13019203339 ps
CPU time 185.23 seconds
Started Aug 29 11:28:42 AM UTC 24
Finished Aug 29 11:31:50 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037195937 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.4037195937
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_rx_oversample.3719259273
Short name T786
Test name
Test status
Simulation time 2763690948 ps
CPU time 24.88 seconds
Started Aug 29 11:28:21 AM UTC 24
Finished Aug 29 11:28:47 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719259273 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3719259273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.3678884495
Short name T856
Test name
Test status
Simulation time 168976515751 ps
CPU time 205.65 seconds
Started Aug 29 11:28:34 AM UTC 24
Finished Aug 29 11:32:02 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678884495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3678884495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.2238807002
Short name T781
Test name
Test status
Simulation time 4556651442 ps
CPU time 4.2 seconds
Started Aug 29 11:28:31 AM UTC 24
Finished Aug 29 11:28:36 AM UTC 24
Peak memory 205036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238807002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2238807002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_smoke.3912727410
Short name T775
Test name
Test status
Simulation time 446268532 ps
CPU time 3.61 seconds
Started Aug 29 11:28:09 AM UTC 24
Finished Aug 29 11:28:14 AM UTC 24
Peak memory 207604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912727410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3912727410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_stress_all.684372517
Short name T818
Test name
Test status
Simulation time 110829711904 ps
CPU time 83.19 seconds
Started Aug 29 11:28:48 AM UTC 24
Finished Aug 29 11:30:13 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684372517 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.684372517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.1513109930
Short name T809
Test name
Test status
Simulation time 9154837961 ps
CPU time 66.74 seconds
Started Aug 29 11:28:46 AM UTC 24
Finished Aug 29 11:29:54 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1513109930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all
_with_rand_reset.1513109930
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.3778618622
Short name T795
Test name
Test status
Simulation time 6554063635 ps
CPU time 27.67 seconds
Started Aug 29 11:28:37 AM UTC 24
Finished Aug 29 11:29:06 AM UTC 24
Peak memory 208580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778618622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3778618622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/42.uart_tx_rx.3740399422
Short name T785
Test name
Test status
Simulation time 37843694015 ps
CPU time 33.02 seconds
Started Aug 29 11:28:10 AM UTC 24
Finished Aug 29 11:28:45 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740399422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3740399422
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/42.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_alert_test.3141183052
Short name T803
Test name
Test status
Simulation time 12697416 ps
CPU time 0.82 seconds
Started Aug 29 11:29:26 AM UTC 24
Finished Aug 29 11:29:28 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141183052 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3141183052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_fifo_full.3877209403
Short name T156
Test name
Test status
Simulation time 26033527744 ps
CPU time 30.03 seconds
Started Aug 29 11:28:58 AM UTC 24
Finished Aug 29 11:29:29 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877209403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3877209403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.1896858200
Short name T808
Test name
Test status
Simulation time 153861923446 ps
CPU time 34.78 seconds
Started Aug 29 11:28:58 AM UTC 24
Finished Aug 29 11:29:34 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896858200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1896858200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_fifo_reset.621275083
Short name T264
Test name
Test status
Simulation time 37878825014 ps
CPU time 133.31 seconds
Started Aug 29 11:29:00 AM UTC 24
Finished Aug 29 11:31:16 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621275083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.621275083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_intr.1764952982
Short name T805
Test name
Test status
Simulation time 23092602815 ps
CPU time 21.38 seconds
Started Aug 29 11:29:06 AM UTC 24
Finished Aug 29 11:29:29 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764952982 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1764952982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.1431164381
Short name T886
Test name
Test status
Simulation time 106643024329 ps
CPU time 206.87 seconds
Started Aug 29 11:29:22 AM UTC 24
Finished Aug 29 11:32:52 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431164381 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1431164381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_loopback.3268818354
Short name T804
Test name
Test status
Simulation time 4542624286 ps
CPU time 9.32 seconds
Started Aug 29 11:29:18 AM UTC 24
Finished Aug 29 11:29:29 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268818354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3268818354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_noise_filter.3616980584
Short name T806
Test name
Test status
Simulation time 12125636524 ps
CPU time 21.25 seconds
Started Aug 29 11:29:08 AM UTC 24
Finished Aug 29 11:29:30 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616980584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3616980584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_perf.205821270
Short name T868
Test name
Test status
Simulation time 17756094491 ps
CPU time 173.45 seconds
Started Aug 29 11:29:22 AM UTC 24
Finished Aug 29 11:32:18 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205821270 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.205821270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_rx_oversample.2214135157
Short name T794
Test name
Test status
Simulation time 2742742747 ps
CPU time 2.96 seconds
Started Aug 29 11:29:02 AM UTC 24
Finished Aug 29 11:29:06 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214135157 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2214135157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.3634220793
Short name T870
Test name
Test status
Simulation time 112956714640 ps
CPU time 185.73 seconds
Started Aug 29 11:29:16 AM UTC 24
Finished Aug 29 11:32:25 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634220793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3634220793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.3955161480
Short name T802
Test name
Test status
Simulation time 4696228939 ps
CPU time 16.54 seconds
Started Aug 29 11:29:08 AM UTC 24
Finished Aug 29 11:29:25 AM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955161480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3955161480
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_smoke.838957647
Short name T791
Test name
Test status
Simulation time 844655491 ps
CPU time 4.93 seconds
Started Aug 29 11:28:51 AM UTC 24
Finished Aug 29 11:28:57 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838957647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.uart_smoke.838957647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_stress_all.2761033458
Short name T263
Test name
Test status
Simulation time 214448520693 ps
CPU time 1075.12 seconds
Started Aug 29 11:29:23 AM UTC 24
Finished Aug 29 11:47:30 AM UTC 24
Peak memory 208976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761033458 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2761033458
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.1271434121
Short name T813
Test name
Test status
Simulation time 7036262084 ps
CPU time 41.9 seconds
Started Aug 29 11:29:22 AM UTC 24
Finished Aug 29 11:30:05 AM UTC 24
Peak memory 217696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1271434121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all
_with_rand_reset.1271434121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.2485587541
Short name T799
Test name
Test status
Simulation time 1551228147 ps
CPU time 3.34 seconds
Started Aug 29 11:29:16 AM UTC 24
Finished Aug 29 11:29:20 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485587541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2485587541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/43.uart_tx_rx.1333057271
Short name T832
Test name
Test status
Simulation time 72721195387 ps
CPU time 137.67 seconds
Started Aug 29 11:28:56 AM UTC 24
Finished Aug 29 11:31:17 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333057271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1333057271
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/43.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_alert_test.2307198197
Short name T819
Test name
Test status
Simulation time 13151346 ps
CPU time 0.8 seconds
Started Aug 29 11:30:13 AM UTC 24
Finished Aug 29 11:30:15 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307198197 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2307198197
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_fifo_full.2024536192
Short name T847
Test name
Test status
Simulation time 79937752415 ps
CPU time 141.33 seconds
Started Aug 29 11:29:30 AM UTC 24
Finished Aug 29 11:31:53 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024536192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2024536192
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.2690592177
Short name T827
Test name
Test status
Simulation time 144753449030 ps
CPU time 95.45 seconds
Started Aug 29 11:29:30 AM UTC 24
Finished Aug 29 11:31:07 AM UTC 24
Peak memory 208584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690592177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2690592177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_fifo_reset.4204145672
Short name T907
Test name
Test status
Simulation time 130643574038 ps
CPU time 240.77 seconds
Started Aug 29 11:29:31 AM UTC 24
Finished Aug 29 11:33:35 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204145672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.4204145672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_intr.653680792
Short name T858
Test name
Test status
Simulation time 44504263741 ps
CPU time 150.3 seconds
Started Aug 29 11:29:34 AM UTC 24
Finished Aug 29 11:32:07 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653680792 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.653680792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.3843520426
Short name T845
Test name
Test status
Simulation time 28356091708 ps
CPU time 101.71 seconds
Started Aug 29 11:30:07 AM UTC 24
Finished Aug 29 11:31:51 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843520426 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3843520426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_loopback.2116608726
Short name T817
Test name
Test status
Simulation time 2228810648 ps
CPU time 5.01 seconds
Started Aug 29 11:30:05 AM UTC 24
Finished Aug 29 11:30:12 AM UTC 24
Peak memory 205300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116608726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2116608726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_noise_filter.3760889486
Short name T826
Test name
Test status
Simulation time 122355742369 ps
CPU time 73.49 seconds
Started Aug 29 11:29:45 AM UTC 24
Finished Aug 29 11:31:01 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760889486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3760889486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_perf.2985689983
Short name T1166
Test name
Test status
Simulation time 16967357315 ps
CPU time 855.53 seconds
Started Aug 29 11:30:07 AM UTC 24
Finished Aug 29 11:44:33 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985689983 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2985689983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_rx_oversample.1468639407
Short name T814
Test name
Test status
Simulation time 3595404531 ps
CPU time 32.11 seconds
Started Aug 29 11:29:32 AM UTC 24
Finished Aug 29 11:30:05 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468639407 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1468639407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.1425143632
Short name T873
Test name
Test status
Simulation time 45146316672 ps
CPU time 151.93 seconds
Started Aug 29 11:29:56 AM UTC 24
Finished Aug 29 11:32:30 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425143632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1425143632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.374535650
Short name T811
Test name
Test status
Simulation time 722151879 ps
CPU time 3.47 seconds
Started Aug 29 11:29:55 AM UTC 24
Finished Aug 29 11:29:59 AM UTC 24
Peak memory 205036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374535650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.374535650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_smoke.264831014
Short name T807
Test name
Test status
Simulation time 444591171 ps
CPU time 1.92 seconds
Started Aug 29 11:29:28 AM UTC 24
Finished Aug 29 11:29:31 AM UTC 24
Peak memory 207932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264831014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 44.uart_smoke.264831014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_stress_all.1762784569
Short name T840
Test name
Test status
Simulation time 62733929812 ps
CPU time 86.98 seconds
Started Aug 29 11:30:10 AM UTC 24
Finished Aug 29 11:31:39 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762784569 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1762784569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.1486623808
Short name T834
Test name
Test status
Simulation time 34457206178 ps
CPU time 69.92 seconds
Started Aug 29 11:30:08 AM UTC 24
Finished Aug 29 11:31:20 AM UTC 24
Peak memory 217736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1486623808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all
_with_rand_reset.1486623808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.289215273
Short name T812
Test name
Test status
Simulation time 1577303847 ps
CPU time 2.89 seconds
Started Aug 29 11:30:00 AM UTC 24
Finished Aug 29 11:30:04 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289215273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.289215273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/44.uart_tx_rx.1632731661
Short name T828
Test name
Test status
Simulation time 49663013046 ps
CPU time 100.03 seconds
Started Aug 29 11:29:30 AM UTC 24
Finished Aug 29 11:31:12 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632731661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1632731661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/44.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_alert_test.820190162
Short name T831
Test name
Test status
Simulation time 68421806 ps
CPU time 0.83 seconds
Started Aug 29 11:31:13 AM UTC 24
Finished Aug 29 11:31:15 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820190162 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.820190162
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_fifo_full.1604844751
Short name T842
Test name
Test status
Simulation time 21617854187 ps
CPU time 82.01 seconds
Started Aug 29 11:30:19 AM UTC 24
Finished Aug 29 11:31:43 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604844751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1604844751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.150614923
Short name T860
Test name
Test status
Simulation time 34466535915 ps
CPU time 105.34 seconds
Started Aug 29 11:30:20 AM UTC 24
Finished Aug 29 11:32:08 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150614923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.150614923
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_fifo_reset.791628577
Short name T940
Test name
Test status
Simulation time 121048101752 ps
CPU time 303.31 seconds
Started Aug 29 11:30:25 AM UTC 24
Finished Aug 29 11:35:32 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791628577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.791628577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_intr.2307543384
Short name T876
Test name
Test status
Simulation time 170952170628 ps
CPU time 101.74 seconds
Started Aug 29 11:30:51 AM UTC 24
Finished Aug 29 11:32:34 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307543384 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2307543384
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.3599801468
Short name T1055
Test name
Test status
Simulation time 258348223523 ps
CPU time 519.9 seconds
Started Aug 29 11:31:02 AM UTC 24
Finished Aug 29 11:39:48 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599801468 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3599801468
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_loopback.382483121
Short name T830
Test name
Test status
Simulation time 9275061903 ps
CPU time 13.09 seconds
Started Aug 29 11:30:59 AM UTC 24
Finished Aug 29 11:31:14 AM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382483121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.uart_loopback.382483121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_noise_filter.252722225
Short name T857
Test name
Test status
Simulation time 110147124663 ps
CPU time 70.57 seconds
Started Aug 29 11:30:51 AM UTC 24
Finished Aug 29 11:32:03 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252722225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.252722225
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_perf.2493347095
Short name T1085
Test name
Test status
Simulation time 16110738368 ps
CPU time 574.96 seconds
Started Aug 29 11:31:02 AM UTC 24
Finished Aug 29 11:40:43 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493347095 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2493347095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_rx_oversample.1788418726
Short name T829
Test name
Test status
Simulation time 3596487947 ps
CPU time 31.96 seconds
Started Aug 29 11:30:39 AM UTC 24
Finished Aug 29 11:31:13 AM UTC 24
Peak memory 208460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788418726 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1788418726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.263148770
Short name T937
Test name
Test status
Simulation time 108295964528 ps
CPU time 266.64 seconds
Started Aug 29 11:30:55 AM UTC 24
Finished Aug 29 11:35:25 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263148770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.263148770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.1294194928
Short name T824
Test name
Test status
Simulation time 6221238928 ps
CPU time 5.93 seconds
Started Aug 29 11:30:52 AM UTC 24
Finished Aug 29 11:30:59 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294194928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1294194928
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_smoke.2368157439
Short name T820
Test name
Test status
Simulation time 287647265 ps
CPU time 2.46 seconds
Started Aug 29 11:30:14 AM UTC 24
Finished Aug 29 11:30:18 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368157439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2368157439
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_stress_all.4026782108
Short name T911
Test name
Test status
Simulation time 95795847120 ps
CPU time 146.63 seconds
Started Aug 29 11:31:12 AM UTC 24
Finished Aug 29 11:33:41 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026782108 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4026782108
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.2225865467
Short name T853
Test name
Test status
Simulation time 4597604486 ps
CPU time 50.69 seconds
Started Aug 29 11:31:08 AM UTC 24
Finished Aug 29 11:32:00 AM UTC 24
Peak memory 217576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2225865467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all
_with_rand_reset.2225865467
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.3896909321
Short name T836
Test name
Test status
Simulation time 6063932874 ps
CPU time 23.42 seconds
Started Aug 29 11:30:57 AM UTC 24
Finished Aug 29 11:31:22 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896909321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3896909321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/45.uart_tx_rx.2639749874
Short name T822
Test name
Test status
Simulation time 35970831347 ps
CPU time 32.23 seconds
Started Aug 29 11:30:15 AM UTC 24
Finished Aug 29 11:30:49 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639749874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2639749874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/45.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_alert_test.4095956217
Short name T848
Test name
Test status
Simulation time 41456806 ps
CPU time 0.85 seconds
Started Aug 29 11:31:51 AM UTC 24
Finished Aug 29 11:31:54 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095956217 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4095956217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_fifo_full.1626151514
Short name T932
Test name
Test status
Simulation time 231891167237 ps
CPU time 225.87 seconds
Started Aug 29 11:31:17 AM UTC 24
Finished Aug 29 11:35:06 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626151514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1626151514
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.3574517307
Short name T846
Test name
Test status
Simulation time 31282088926 ps
CPU time 32.71 seconds
Started Aug 29 11:31:18 AM UTC 24
Finished Aug 29 11:31:52 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574517307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3574517307
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_fifo_reset.2257735246
Short name T884
Test name
Test status
Simulation time 61053580325 ps
CPU time 82.06 seconds
Started Aug 29 11:31:19 AM UTC 24
Finished Aug 29 11:32:43 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257735246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2257735246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_intr.2564545438
Short name T908
Test name
Test status
Simulation time 64778314570 ps
CPU time 133.28 seconds
Started Aug 29 11:31:20 AM UTC 24
Finished Aug 29 11:33:36 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564545438 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2564545438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.2909960455
Short name T1011
Test name
Test status
Simulation time 91421043077 ps
CPU time 376.96 seconds
Started Aug 29 11:31:42 AM UTC 24
Finished Aug 29 11:38:04 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909960455 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2909960455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_loopback.4076148474
Short name T843
Test name
Test status
Simulation time 2478960742 ps
CPU time 9.27 seconds
Started Aug 29 11:31:37 AM UTC 24
Finished Aug 29 11:31:48 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076148474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.uart_loopback.4076148474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_noise_filter.20981513
Short name T885
Test name
Test status
Simulation time 83632889998 ps
CPU time 83.75 seconds
Started Aug 29 11:31:23 AM UTC 24
Finished Aug 29 11:32:48 AM UTC 24
Peak memory 208288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20981513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.20981513
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_perf.1899504283
Short name T928
Test name
Test status
Simulation time 9410066498 ps
CPU time 196.16 seconds
Started Aug 29 11:31:40 AM UTC 24
Finished Aug 29 11:34:59 AM UTC 24
Peak memory 208928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899504283 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1899504283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_rx_oversample.851750438
Short name T838
Test name
Test status
Simulation time 2579400041 ps
CPU time 6.71 seconds
Started Aug 29 11:31:20 AM UTC 24
Finished Aug 29 11:31:28 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851750438 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.851750438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.2121547156
Short name T901
Test name
Test status
Simulation time 280505370921 ps
CPU time 104.58 seconds
Started Aug 29 11:31:29 AM UTC 24
Finished Aug 29 11:33:16 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121547156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2121547156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.2268496076
Short name T902
Test name
Test status
Simulation time 65877672366 ps
CPU time 111.34 seconds
Started Aug 29 11:31:23 AM UTC 24
Finished Aug 29 11:33:16 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268496076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2268496076
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_smoke.2710298153
Short name T833
Test name
Test status
Simulation time 291403079 ps
CPU time 2.35 seconds
Started Aug 29 11:31:14 AM UTC 24
Finished Aug 29 11:31:18 AM UTC 24
Peak memory 208316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710298153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2710298153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_stress_all.1279533457
Short name T994
Test name
Test status
Simulation time 151556983473 ps
CPU time 321.89 seconds
Started Aug 29 11:31:49 AM UTC 24
Finished Aug 29 11:37:15 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279533457 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1279533457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.2603747805
Short name T878
Test name
Test status
Simulation time 3409271178 ps
CPU time 49.63 seconds
Started Aug 29 11:31:44 AM UTC 24
Finished Aug 29 11:32:35 AM UTC 24
Peak memory 217612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2603747805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all
_with_rand_reset.2603747805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.3150202701
Short name T841
Test name
Test status
Simulation time 848447613 ps
CPU time 5.01 seconds
Started Aug 29 11:31:35 AM UTC 24
Finished Aug 29 11:31:41 AM UTC 24
Peak memory 207596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150202701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3150202701
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/46.uart_tx_rx.2778771136
Short name T869
Test name
Test status
Simulation time 86263684188 ps
CPU time 62.7 seconds
Started Aug 29 11:31:16 AM UTC 24
Finished Aug 29 11:32:20 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778771136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2778771136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/46.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_alert_test.1774129845
Short name T862
Test name
Test status
Simulation time 37401644 ps
CPU time 0.78 seconds
Started Aug 29 11:32:09 AM UTC 24
Finished Aug 29 11:32:11 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774129845 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1774129845
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_fifo_full.2538688297
Short name T875
Test name
Test status
Simulation time 22439734685 ps
CPU time 36.95 seconds
Started Aug 29 11:31:55 AM UTC 24
Finished Aug 29 11:32:34 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538688297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2538688297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.1718492145
Short name T949
Test name
Test status
Simulation time 146238022967 ps
CPU time 234.76 seconds
Started Aug 29 11:31:55 AM UTC 24
Finished Aug 29 11:35:53 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718492145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1718492145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_fifo_reset.1401229263
Short name T867
Test name
Test status
Simulation time 9449493140 ps
CPU time 19.39 seconds
Started Aug 29 11:31:56 AM UTC 24
Finished Aug 29 11:32:17 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401229263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1401229263
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_intr.56436332
Short name T865
Test name
Test status
Simulation time 15189825081 ps
CPU time 16.68 seconds
Started Aug 29 11:31:57 AM UTC 24
Finished Aug 29 11:32:16 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56436332 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.56436332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.1013584371
Short name T947
Test name
Test status
Simulation time 327047543433 ps
CPU time 209.14 seconds
Started Aug 29 11:32:08 AM UTC 24
Finished Aug 29 11:35:40 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013584371 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1013584371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_loopback.1639312374
Short name T866
Test name
Test status
Simulation time 4849291001 ps
CPU time 11.87 seconds
Started Aug 29 11:32:03 AM UTC 24
Finished Aug 29 11:32:16 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639312374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1639312374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_noise_filter.2713185758
Short name T890
Test name
Test status
Simulation time 50764419784 ps
CPU time 55.8 seconds
Started Aug 29 11:32:00 AM UTC 24
Finished Aug 29 11:32:57 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713185758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2713185758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_perf.2709794708
Short name T913
Test name
Test status
Simulation time 4654969818 ps
CPU time 104.08 seconds
Started Aug 29 11:32:03 AM UTC 24
Finished Aug 29 11:33:50 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709794708 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2709794708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_rx_oversample.3894348274
Short name T903
Test name
Test status
Simulation time 6400583755 ps
CPU time 81.74 seconds
Started Aug 29 11:31:56 AM UTC 24
Finished Aug 29 11:33:21 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894348274 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3894348274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.1355974618
Short name T153
Test name
Test status
Simulation time 149307980005 ps
CPU time 97.62 seconds
Started Aug 29 11:32:02 AM UTC 24
Finished Aug 29 11:33:42 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355974618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1355974618
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.3676254110
Short name T861
Test name
Test status
Simulation time 3985899137 ps
CPU time 5.9 seconds
Started Aug 29 11:32:01 AM UTC 24
Finished Aug 29 11:32:08 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676254110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3676254110
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_smoke.986944206
Short name T850
Test name
Test status
Simulation time 270327772 ps
CPU time 2.28 seconds
Started Aug 29 11:31:51 AM UTC 24
Finished Aug 29 11:31:55 AM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986944206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.uart_smoke.986944206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_stress_all.3974232803
Short name T1059
Test name
Test status
Simulation time 451462023461 ps
CPU time 460.04 seconds
Started Aug 29 11:32:09 AM UTC 24
Finished Aug 29 11:39:55 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974232803 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3974232803
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.1779508463
Short name T881
Test name
Test status
Simulation time 6978870056 ps
CPU time 27.92 seconds
Started Aug 29 11:32:09 AM UTC 24
Finished Aug 29 11:32:38 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1779508463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all
_with_rand_reset.1779508463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.1797716040
Short name T859
Test name
Test status
Simulation time 2813148279 ps
CPU time 4.03 seconds
Started Aug 29 11:32:02 AM UTC 24
Finished Aug 29 11:32:07 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797716040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1797716040
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/47.uart_tx_rx.107161105
Short name T872
Test name
Test status
Simulation time 54507721258 ps
CPU time 34.42 seconds
Started Aug 29 11:31:54 AM UTC 24
Finished Aug 29 11:32:29 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107161105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.107161105
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/47.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_alert_test.970308176
Short name T879
Test name
Test status
Simulation time 19509769 ps
CPU time 0.86 seconds
Started Aug 29 11:32:36 AM UTC 24
Finished Aug 29 11:32:38 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970308176 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.970308176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_fifo_full.2283311710
Short name T895
Test name
Test status
Simulation time 50156640321 ps
CPU time 46.92 seconds
Started Aug 29 11:32:15 AM UTC 24
Finished Aug 29 11:33:03 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283311710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2283311710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.1673229954
Short name T897
Test name
Test status
Simulation time 111604705718 ps
CPU time 45.99 seconds
Started Aug 29 11:32:17 AM UTC 24
Finished Aug 29 11:33:04 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673229954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1673229954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_fifo_reset.552990991
Short name T203
Test name
Test status
Simulation time 147258787595 ps
CPU time 44.78 seconds
Started Aug 29 11:32:17 AM UTC 24
Finished Aug 29 11:33:03 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552990991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.552990991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_intr.4002926412
Short name T904
Test name
Test status
Simulation time 56231706429 ps
CPU time 64 seconds
Started Aug 29 11:32:19 AM UTC 24
Finished Aug 29 11:33:25 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002926412 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.4002926412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.3350775303
Short name T1174
Test name
Test status
Simulation time 238854274834 ps
CPU time 883.44 seconds
Started Aug 29 11:32:35 AM UTC 24
Finished Aug 29 11:47:28 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350775303 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3350775303
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_loopback.2839440173
Short name T877
Test name
Test status
Simulation time 2602809104 ps
CPU time 3 seconds
Started Aug 29 11:32:31 AM UTC 24
Finished Aug 29 11:32:35 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839440173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2839440173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_noise_filter.2675754217
Short name T888
Test name
Test status
Simulation time 9839853455 ps
CPU time 32.92 seconds
Started Aug 29 11:32:20 AM UTC 24
Finished Aug 29 11:32:55 AM UTC 24
Peak memory 207480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675754217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2675754217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_perf.2771532222
Short name T1047
Test name
Test status
Simulation time 27501985457 ps
CPU time 419.08 seconds
Started Aug 29 11:32:34 AM UTC 24
Finished Aug 29 11:39:39 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771532222 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2771532222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_rx_oversample.237602964
Short name T871
Test name
Test status
Simulation time 2008363175 ps
CPU time 9.74 seconds
Started Aug 29 11:32:18 AM UTC 24
Finished Aug 29 11:32:29 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237602964 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.237602964
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.3011539947
Short name T967
Test name
Test status
Simulation time 93230087326 ps
CPU time 238.05 seconds
Started Aug 29 11:32:30 AM UTC 24
Finished Aug 29 11:36:31 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011539947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3011539947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.2254908241
Short name T874
Test name
Test status
Simulation time 3796263811 ps
CPU time 6.6 seconds
Started Aug 29 11:32:26 AM UTC 24
Finished Aug 29 11:32:33 AM UTC 24
Peak memory 205300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254908241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2254908241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_smoke.2319635368
Short name T864
Test name
Test status
Simulation time 109570033 ps
CPU time 1.34 seconds
Started Aug 29 11:32:11 AM UTC 24
Finished Aug 29 11:32:14 AM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319635368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2319635368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_stress_all.1927225556
Short name T1032
Test name
Test status
Simulation time 189212612873 ps
CPU time 380.75 seconds
Started Aug 29 11:32:36 AM UTC 24
Finished Aug 29 11:39:01 AM UTC 24
Peak memory 217708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927225556 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1927225556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.845002999
Short name T892
Test name
Test status
Simulation time 6948257281 ps
CPU time 28.5 seconds
Started Aug 29 11:32:30 AM UTC 24
Finished Aug 29 11:33:00 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845002999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.845002999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/48.uart_tx_rx.201838635
Short name T946
Test name
Test status
Simulation time 117094880686 ps
CPU time 202.2 seconds
Started Aug 29 11:32:15 AM UTC 24
Finished Aug 29 11:35:40 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201838635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.201838635
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_alert_test.1558421068
Short name T899
Test name
Test status
Simulation time 26966522 ps
CPU time 0.86 seconds
Started Aug 29 11:33:04 AM UTC 24
Finished Aug 29 11:33:06 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558421068 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1558421068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_fifo_full.2976026088
Short name T999
Test name
Test status
Simulation time 192223686490 ps
CPU time 293.05 seconds
Started Aug 29 11:32:40 AM UTC 24
Finished Aug 29 11:37:37 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976026088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2976026088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.1087247143
Short name T910
Test name
Test status
Simulation time 15353769161 ps
CPU time 56.46 seconds
Started Aug 29 11:32:43 AM UTC 24
Finished Aug 29 11:33:41 AM UTC 24
Peak memory 208420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087247143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1087247143
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_intr.1297061893
Short name T896
Test name
Test status
Simulation time 6902276092 ps
CPU time 12.67 seconds
Started Aug 29 11:32:49 AM UTC 24
Finished Aug 29 11:33:03 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297061893 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1297061893
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.3779556377
Short name T1162
Test name
Test status
Simulation time 155351804055 ps
CPU time 639.39 seconds
Started Aug 29 11:33:00 AM UTC 24
Finished Aug 29 11:43:47 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779556377 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3779556377
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_loopback.2204593084
Short name T894
Test name
Test status
Simulation time 14547506363 ps
CPU time 3.6 seconds
Started Aug 29 11:32:58 AM UTC 24
Finished Aug 29 11:33:03 AM UTC 24
Peak memory 207428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204593084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2204593084
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_noise_filter.1314971862
Short name T920
Test name
Test status
Simulation time 69463769001 ps
CPU time 94.42 seconds
Started Aug 29 11:32:52 AM UTC 24
Finished Aug 29 11:34:29 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314971862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1314971862
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_perf.788896931
Short name T1180
Test name
Test status
Simulation time 21056442615 ps
CPU time 1881.96 seconds
Started Aug 29 11:32:59 AM UTC 24
Finished Aug 29 12:04:44 PM UTC 24
Peak memory 212428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788896931 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.788896931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_rx_oversample.1439231789
Short name T891
Test name
Test status
Simulation time 1700925360 ps
CPU time 12.84 seconds
Started Aug 29 11:32:44 AM UTC 24
Finished Aug 29 11:32:58 AM UTC 24
Peak memory 208084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439231789 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1439231789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.3762853128
Short name T1023
Test name
Test status
Simulation time 143823354968 ps
CPU time 345.76 seconds
Started Aug 29 11:32:56 AM UTC 24
Finished Aug 29 11:38:46 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762853128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3762853128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.351310793
Short name T900
Test name
Test status
Simulation time 5909801579 ps
CPU time 14.97 seconds
Started Aug 29 11:32:54 AM UTC 24
Finished Aug 29 11:33:10 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351310793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.351310793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_smoke.3765116247
Short name T882
Test name
Test status
Simulation time 127700294 ps
CPU time 1.54 seconds
Started Aug 29 11:32:39 AM UTC 24
Finished Aug 29 11:32:42 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765116247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3765116247
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_stress_all.468346722
Short name T1146
Test name
Test status
Simulation time 127395737797 ps
CPU time 569.87 seconds
Started Aug 29 11:33:04 AM UTC 24
Finished Aug 29 11:42:41 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468346722 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.468346722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.2695734969
Short name T929
Test name
Test status
Simulation time 6366264973 ps
CPU time 113.79 seconds
Started Aug 29 11:33:02 AM UTC 24
Finished Aug 29 11:34:59 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2695734969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all
_with_rand_reset.2695734969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.350620007
Short name T898
Test name
Test status
Simulation time 8648389461 ps
CPU time 8.64 seconds
Started Aug 29 11:32:56 AM UTC 24
Finished Aug 29 11:33:06 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350620007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.350620007
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/49.uart_tx_rx.714019770
Short name T912
Test name
Test status
Simulation time 16404577463 ps
CPU time 63 seconds
Started Aug 29 11:32:39 AM UTC 24
Finished Aug 29 11:33:44 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714019770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.714019770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/49.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_alert_test.2834856072
Short name T425
Test name
Test status
Simulation time 10881692 ps
CPU time 0.81 seconds
Started Aug 29 11:07:37 AM UTC 24
Finished Aug 29 11:07:39 AM UTC 24
Peak memory 204372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834856072 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2834856072
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_fifo_full.2169948516
Short name T107
Test name
Test status
Simulation time 33902205469 ps
CPU time 29.69 seconds
Started Aug 29 11:07:24 AM UTC 24
Finished Aug 29 11:07:55 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169948516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2169948516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.954556952
Short name T323
Test name
Test status
Simulation time 94634035304 ps
CPU time 215.01 seconds
Started Aug 29 11:07:25 AM UTC 24
Finished Aug 29 11:11:04 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954556952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.954556952
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.4267953800
Short name T281
Test name
Test status
Simulation time 41643881645 ps
CPU time 81.8 seconds
Started Aug 29 11:07:35 AM UTC 24
Finished Aug 29 11:08:59 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267953800 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.4267953800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_loopback.604941874
Short name T426
Test name
Test status
Simulation time 9727115868 ps
CPU time 8.41 seconds
Started Aug 29 11:07:35 AM UTC 24
Finished Aug 29 11:07:44 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604941874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.uart_loopback.604941874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_noise_filter.524262623
Short name T321
Test name
Test status
Simulation time 132144903641 ps
CPU time 92.5 seconds
Started Aug 29 11:07:31 AM UTC 24
Finished Aug 29 11:09:06 AM UTC 24
Peak memory 208156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524262623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.524262623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_perf.2721980671
Short name T358
Test name
Test status
Simulation time 12426582490 ps
CPU time 318.26 seconds
Started Aug 29 11:07:35 AM UTC 24
Finished Aug 29 11:12:58 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721980671 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2721980671
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_rx_oversample.1674129026
Short name T402
Test name
Test status
Simulation time 6585081242 ps
CPU time 69.34 seconds
Started Aug 29 11:07:26 AM UTC 24
Finished Aug 29 11:08:38 AM UTC 24
Peak memory 208572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674129026 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1674129026
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.251171024
Short name T320
Test name
Test status
Simulation time 67679940920 ps
CPU time 152.89 seconds
Started Aug 29 11:07:33 AM UTC 24
Finished Aug 29 11:10:08 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251171024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.251171024
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.3325981983
Short name T310
Test name
Test status
Simulation time 1404496977 ps
CPU time 2.06 seconds
Started Aug 29 11:07:33 AM UTC 24
Finished Aug 29 11:07:36 AM UTC 24
Peak memory 205164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325981983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3325981983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_smoke.17689333
Short name T269
Test name
Test status
Simulation time 5724505557 ps
CPU time 12.61 seconds
Started Aug 29 11:07:24 AM UTC 24
Finished Aug 29 11:07:38 AM UTC 24
Peak memory 207984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17689333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_smoke.17689333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.3447119810
Short name T34
Test name
Test status
Simulation time 4109196670 ps
CPU time 16.87 seconds
Started Aug 29 11:07:36 AM UTC 24
Finished Aug 29 11:07:54 AM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3447119810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_
with_rand_reset.3447119810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.3939706346
Short name T341
Test name
Test status
Simulation time 357844242 ps
CPU time 2.27 seconds
Started Aug 29 11:07:33 AM UTC 24
Finished Aug 29 11:07:36 AM UTC 24
Peak memory 207080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939706346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3939706346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/5.uart_tx_rx.3733353086
Short name T286
Test name
Test status
Simulation time 70165564104 ps
CPU time 133.86 seconds
Started Aug 29 11:07:24 AM UTC 24
Finished Aug 29 11:09:40 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733353086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3733353086
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/5.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/50.uart_fifo_reset.4168624704
Short name T204
Test name
Test status
Simulation time 20011041190 ps
CPU time 58.82 seconds
Started Aug 29 11:33:04 AM UTC 24
Finished Aug 29 11:34:05 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168624704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.4168624704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/50.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.3414142497
Short name T905
Test name
Test status
Simulation time 1301605820 ps
CPU time 21.29 seconds
Started Aug 29 11:33:04 AM UTC 24
Finished Aug 29 11:33:27 AM UTC 24
Peak memory 222036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3414142497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all
_with_rand_reset.3414142497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/51.uart_fifo_reset.707929628
Short name T914
Test name
Test status
Simulation time 23928736338 ps
CPU time 47.42 seconds
Started Aug 29 11:33:05 AM UTC 24
Finished Aug 29 11:33:54 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707929628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.707929628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/51.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.2362235769
Short name T915
Test name
Test status
Simulation time 3337296707 ps
CPU time 50.24 seconds
Started Aug 29 11:33:07 AM UTC 24
Finished Aug 29 11:33:59 AM UTC 24
Peak memory 219724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2362235769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all
_with_rand_reset.2362235769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/52.uart_fifo_reset.2150598398
Short name T251
Test name
Test status
Simulation time 20336581380 ps
CPU time 65.79 seconds
Started Aug 29 11:33:07 AM UTC 24
Finished Aug 29 11:34:14 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150598398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2150598398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/52.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.3923203860
Short name T909
Test name
Test status
Simulation time 3055719719 ps
CPU time 27.96 seconds
Started Aug 29 11:33:11 AM UTC 24
Finished Aug 29 11:33:40 AM UTC 24
Peak memory 224008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3923203860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all
_with_rand_reset.3923203860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/53.uart_fifo_reset.2914674725
Short name T255
Test name
Test status
Simulation time 36215996757 ps
CPU time 34.36 seconds
Started Aug 29 11:33:16 AM UTC 24
Finished Aug 29 11:33:52 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914674725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2914674725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/53.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.1408803489
Short name T950
Test name
Test status
Simulation time 5781678795 ps
CPU time 156.94 seconds
Started Aug 29 11:33:17 AM UTC 24
Finished Aug 29 11:35:57 AM UTC 24
Peak memory 224900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1408803489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all
_with_rand_reset.1408803489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/54.uart_fifo_reset.845736851
Short name T960
Test name
Test status
Simulation time 121299445545 ps
CPU time 170.96 seconds
Started Aug 29 11:33:22 AM UTC 24
Finished Aug 29 11:36:15 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845736851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.845736851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/54.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.2552301243
Short name T952
Test name
Test status
Simulation time 5464968783 ps
CPU time 149.19 seconds
Started Aug 29 11:33:26 AM UTC 24
Finished Aug 29 11:35:57 AM UTC 24
Peak memory 219760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2552301243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all
_with_rand_reset.2552301243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/55.uart_fifo_reset.3862823089
Short name T179
Test name
Test status
Simulation time 107993115048 ps
CPU time 83.59 seconds
Started Aug 29 11:33:28 AM UTC 24
Finished Aug 29 11:34:53 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862823089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3862823089
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/55.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/56.uart_fifo_reset.76689777
Short name T205
Test name
Test status
Simulation time 65072601121 ps
CPU time 52.88 seconds
Started Aug 29 11:33:36 AM UTC 24
Finished Aug 29 11:34:31 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76689777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.76689777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/56.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.3420797057
Short name T919
Test name
Test status
Simulation time 8168657304 ps
CPU time 44.03 seconds
Started Aug 29 11:33:36 AM UTC 24
Finished Aug 29 11:34:22 AM UTC 24
Peak memory 219700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3420797057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all
_with_rand_reset.3420797057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/57.uart_fifo_reset.1493316068
Short name T966
Test name
Test status
Simulation time 110443457700 ps
CPU time 165.9 seconds
Started Aug 29 11:33:42 AM UTC 24
Finished Aug 29 11:36:30 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493316068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1493316068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/57.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.1661263243
Short name T916
Test name
Test status
Simulation time 1165266183 ps
CPU time 18.59 seconds
Started Aug 29 11:33:42 AM UTC 24
Finished Aug 29 11:34:02 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1661263243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all
_with_rand_reset.1661263243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/58.uart_fifo_reset.3272438364
Short name T236
Test name
Test status
Simulation time 52886918871 ps
CPU time 24.66 seconds
Started Aug 29 11:33:43 AM UTC 24
Finished Aug 29 11:34:09 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272438364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3272438364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/58.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.3233525033
Short name T921
Test name
Test status
Simulation time 3155758078 ps
CPU time 48.08 seconds
Started Aug 29 11:33:43 AM UTC 24
Finished Aug 29 11:34:33 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3233525033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all
_with_rand_reset.3233525033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/59.uart_fifo_reset.4049702408
Short name T221
Test name
Test status
Simulation time 40005419736 ps
CPU time 70.32 seconds
Started Aug 29 11:33:45 AM UTC 24
Finished Aug 29 11:34:58 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049702408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.4049702408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/59.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.2641713302
Short name T918
Test name
Test status
Simulation time 6349086036 ps
CPU time 23.18 seconds
Started Aug 29 11:33:51 AM UTC 24
Finished Aug 29 11:34:15 AM UTC 24
Peak memory 217808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2641713302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all
_with_rand_reset.2641713302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_alert_test.2053940297
Short name T8
Test name
Test status
Simulation time 24256470 ps
CPU time 0.72 seconds
Started Aug 29 11:07:50 AM UTC 24
Finished Aug 29 11:07:52 AM UTC 24
Peak memory 204312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053940297 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2053940297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_fifo_full.3238425074
Short name T177
Test name
Test status
Simulation time 90257457974 ps
CPU time 231.55 seconds
Started Aug 29 11:07:39 AM UTC 24
Finished Aug 29 11:11:34 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238425074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3238425074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.2035280775
Short name T124
Test name
Test status
Simulation time 29068078341 ps
CPU time 46.33 seconds
Started Aug 29 11:07:39 AM UTC 24
Finished Aug 29 11:08:27 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035280775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2035280775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_fifo_reset.861507218
Short name T128
Test name
Test status
Simulation time 31370413633 ps
CPU time 57.51 seconds
Started Aug 29 11:07:39 AM UTC 24
Finished Aug 29 11:08:38 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861507218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.861507218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_intr.1447024994
Short name T25
Test name
Test status
Simulation time 22613784032 ps
CPU time 12.4 seconds
Started Aug 29 11:07:41 AM UTC 24
Finished Aug 29 11:07:54 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447024994 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1447024994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.2636230955
Short name T524
Test name
Test status
Simulation time 109959645341 ps
CPU time 534.88 seconds
Started Aug 29 11:07:47 AM UTC 24
Finished Aug 29 11:16:48 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636230955 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2636230955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_loopback.3151480765
Short name T427
Test name
Test status
Simulation time 9151082603 ps
CPU time 7.89 seconds
Started Aug 29 11:07:46 AM UTC 24
Finished Aug 29 11:07:55 AM UTC 24
Peak memory 208580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151480765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3151480765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_noise_filter.190835012
Short name T288
Test name
Test status
Simulation time 11427075032 ps
CPU time 26.93 seconds
Started Aug 29 11:07:41 AM UTC 24
Finished Aug 29 11:08:09 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190835012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.190835012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_perf.1022445994
Short name T272
Test name
Test status
Simulation time 7898736187 ps
CPU time 240.71 seconds
Started Aug 29 11:07:46 AM UTC 24
Finished Aug 29 11:11:50 AM UTC 24
Peak memory 208964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022445994 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1022445994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_rx_oversample.1861348278
Short name T432
Test name
Test status
Simulation time 5778424998 ps
CPU time 57.03 seconds
Started Aug 29 11:07:40 AM UTC 24
Finished Aug 29 11:08:39 AM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861348278 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1861348278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.1039479093
Short name T295
Test name
Test status
Simulation time 13588666544 ps
CPU time 52.03 seconds
Started Aug 29 11:07:44 AM UTC 24
Finished Aug 29 11:08:37 AM UTC 24
Peak memory 208224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039479093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1039479093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.2695464554
Short name T300
Test name
Test status
Simulation time 2448958367 ps
CPU time 3.06 seconds
Started Aug 29 11:07:42 AM UTC 24
Finished Aug 29 11:07:46 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695464554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2695464554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_smoke.638910618
Short name T342
Test name
Test status
Simulation time 465605759 ps
CPU time 1.81 seconds
Started Aug 29 11:07:37 AM UTC 24
Finished Aug 29 11:07:40 AM UTC 24
Peak memory 207812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638910618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.uart_smoke.638910618
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.4203750999
Short name T35
Test name
Test status
Simulation time 3018021389 ps
CPU time 30.15 seconds
Started Aug 29 11:07:48 AM UTC 24
Finished Aug 29 11:08:20 AM UTC 24
Peak memory 217648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4203750999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_
with_rand_reset.4203750999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.3476861562
Short name T380
Test name
Test status
Simulation time 1035131048 ps
CPU time 3.57 seconds
Started Aug 29 11:07:45 AM UTC 24
Finished Aug 29 11:07:49 AM UTC 24
Peak memory 208220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476861562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3476861562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/6.uart_tx_rx.1182186933
Short name T298
Test name
Test status
Simulation time 58212765491 ps
CPU time 27.94 seconds
Started Aug 29 11:07:38 AM UTC 24
Finished Aug 29 11:08:07 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182186933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1182186933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/6.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/60.uart_fifo_reset.793416544
Short name T414
Test name
Test status
Simulation time 20928743360 ps
CPU time 37.9 seconds
Started Aug 29 11:33:53 AM UTC 24
Finished Aug 29 11:34:32 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793416544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.793416544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/60.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.358713139
Short name T926
Test name
Test status
Simulation time 55579849270 ps
CPU time 57.22 seconds
Started Aug 29 11:33:55 AM UTC 24
Finished Aug 29 11:34:54 AM UTC 24
Peak memory 225532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=358713139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all_
with_rand_reset.358713139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/61.uart_fifo_reset.2182788779
Short name T238
Test name
Test status
Simulation time 183751825486 ps
CPU time 95.83 seconds
Started Aug 29 11:33:56 AM UTC 24
Finished Aug 29 11:35:34 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182788779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2182788779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/61.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.3148001402
Short name T924
Test name
Test status
Simulation time 5681650339 ps
CPU time 37.46 seconds
Started Aug 29 11:33:59 AM UTC 24
Finished Aug 29 11:34:38 AM UTC 24
Peak memory 217804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3148001402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all
_with_rand_reset.3148001402
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/62.uart_fifo_reset.1315579924
Short name T416
Test name
Test status
Simulation time 66226816386 ps
CPU time 39.77 seconds
Started Aug 29 11:34:02 AM UTC 24
Finished Aug 29 11:34:44 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315579924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1315579924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/62.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.2556904464
Short name T925
Test name
Test status
Simulation time 7046399164 ps
CPU time 41.06 seconds
Started Aug 29 11:34:04 AM UTC 24
Finished Aug 29 11:34:46 AM UTC 24
Peak memory 225412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2556904464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all
_with_rand_reset.2556904464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/63.uart_fifo_reset.653644431
Short name T223
Test name
Test status
Simulation time 35400222877 ps
CPU time 86.78 seconds
Started Aug 29 11:34:06 AM UTC 24
Finished Aug 29 11:35:34 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653644431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.653644431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/63.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.485913924
Short name T923
Test name
Test status
Simulation time 6849622152 ps
CPU time 24.88 seconds
Started Aug 29 11:34:10 AM UTC 24
Finished Aug 29 11:34:36 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=485913924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all_
with_rand_reset.485913924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/64.uart_fifo_reset.3246692407
Short name T246
Test name
Test status
Simulation time 20670338876 ps
CPU time 30.7 seconds
Started Aug 29 11:34:15 AM UTC 24
Finished Aug 29 11:34:47 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246692407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3246692407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/64.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.2821306349
Short name T933
Test name
Test status
Simulation time 2749060712 ps
CPU time 49.49 seconds
Started Aug 29 11:34:16 AM UTC 24
Finished Aug 29 11:35:07 AM UTC 24
Peak memory 217580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2821306349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all
_with_rand_reset.2821306349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/65.uart_fifo_reset.953968785
Short name T224
Test name
Test status
Simulation time 39527343497 ps
CPU time 88.16 seconds
Started Aug 29 11:34:23 AM UTC 24
Finished Aug 29 11:35:53 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953968785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.953968785
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/65.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.3397435723
Short name T927
Test name
Test status
Simulation time 4136951503 ps
CPU time 26.57 seconds
Started Aug 29 11:34:30 AM UTC 24
Finished Aug 29 11:34:58 AM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3397435723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all
_with_rand_reset.3397435723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.3155703249
Short name T935
Test name
Test status
Simulation time 3335567054 ps
CPU time 36.49 seconds
Started Aug 29 11:34:33 AM UTC 24
Finished Aug 29 11:35:11 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3155703249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all
_with_rand_reset.3155703249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/67.uart_fifo_reset.2814495820
Short name T217
Test name
Test status
Simulation time 231955065630 ps
CPU time 45.82 seconds
Started Aug 29 11:34:34 AM UTC 24
Finished Aug 29 11:35:21 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814495820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2814495820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/67.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.267578676
Short name T939
Test name
Test status
Simulation time 696858669 ps
CPU time 54.55 seconds
Started Aug 29 11:34:35 AM UTC 24
Finished Aug 29 11:35:32 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=267578676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all_
with_rand_reset.267578676
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/68.uart_fifo_reset.1532695396
Short name T200
Test name
Test status
Simulation time 77761719823 ps
CPU time 105.52 seconds
Started Aug 29 11:34:37 AM UTC 24
Finished Aug 29 11:36:24 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532695396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1532695396
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/68.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.3555701304
Short name T934
Test name
Test status
Simulation time 2870048090 ps
CPU time 28.65 seconds
Started Aug 29 11:34:40 AM UTC 24
Finished Aug 29 11:35:10 AM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3555701304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all
_with_rand_reset.3555701304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/69.uart_fifo_reset.3667993692
Short name T955
Test name
Test status
Simulation time 102149591432 ps
CPU time 75.87 seconds
Started Aug 29 11:34:45 AM UTC 24
Finished Aug 29 11:36:03 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667993692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3667993692
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/69.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.2575800512
Short name T953
Test name
Test status
Simulation time 4562785540 ps
CPU time 72.76 seconds
Started Aug 29 11:34:47 AM UTC 24
Finished Aug 29 11:36:02 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2575800512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all
_with_rand_reset.2575800512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_alert_test.2767280804
Short name T430
Test name
Test status
Simulation time 54712536 ps
CPU time 0.81 seconds
Started Aug 29 11:08:15 AM UTC 24
Finished Aug 29 11:08:17 AM UTC 24
Peak memory 204372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767280804 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2767280804
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.2121789608
Short name T54
Test name
Test status
Simulation time 8555119610 ps
CPU time 31.78 seconds
Started Aug 29 11:08:02 AM UTC 24
Finished Aug 29 11:08:35 AM UTC 24
Peak memory 207816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121789608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2121789608
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_intr.426982763
Short name T395
Test name
Test status
Simulation time 90410666077 ps
CPU time 47.19 seconds
Started Aug 29 11:08:03 AM UTC 24
Finished Aug 29 11:08:52 AM UTC 24
Peak memory 207060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426982763 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.426982763
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.3301904387
Short name T535
Test name
Test status
Simulation time 74768839852 ps
CPU time 532.86 seconds
Started Aug 29 11:08:09 AM UTC 24
Finished Aug 29 11:17:09 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301904387 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3301904387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_loopback.3356412859
Short name T429
Test name
Test status
Simulation time 4515701629 ps
CPU time 4.71 seconds
Started Aug 29 11:08:08 AM UTC 24
Finished Aug 29 11:08:14 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356412859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3356412859
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_noise_filter.2844419287
Short name T299
Test name
Test status
Simulation time 75860050371 ps
CPU time 234 seconds
Started Aug 29 11:08:03 AM UTC 24
Finished Aug 29 11:12:01 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844419287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2844419287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_perf.3456682219
Short name T383
Test name
Test status
Simulation time 15297279533 ps
CPU time 260.81 seconds
Started Aug 29 11:08:08 AM UTC 24
Finished Aug 29 11:12:33 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456682219 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3456682219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_rx_oversample.2615951221
Short name T428
Test name
Test status
Simulation time 3578443711 ps
CPU time 7.04 seconds
Started Aug 29 11:08:03 AM UTC 24
Finished Aug 29 11:08:12 AM UTC 24
Peak memory 206860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615951221 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2615951221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.1390089018
Short name T265
Test name
Test status
Simulation time 119892699235 ps
CPU time 74.23 seconds
Started Aug 29 11:08:03 AM UTC 24
Finished Aug 29 11:09:20 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390089018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1390089018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.2231872775
Short name T354
Test name
Test status
Simulation time 38772186465 ps
CPU time 92.12 seconds
Started Aug 29 11:08:03 AM UTC 24
Finished Aug 29 11:09:38 AM UTC 24
Peak memory 207340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231872775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2231872775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_smoke.732205338
Short name T48
Test name
Test status
Simulation time 632492270 ps
CPU time 1.19 seconds
Started Aug 29 11:07:51 AM UTC 24
Finished Aug 29 11:07:53 AM UTC 24
Peak memory 206492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732205338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 7.uart_smoke.732205338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.1428912863
Short name T38
Test name
Test status
Simulation time 4941558464 ps
CPU time 76.11 seconds
Started Aug 29 11:08:12 AM UTC 24
Finished Aug 29 11:09:30 AM UTC 24
Peak memory 217912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1428912863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_
with_rand_reset.1428912863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.1776935936
Short name T364
Test name
Test status
Simulation time 738228790 ps
CPU time 2.85 seconds
Started Aug 29 11:08:03 AM UTC 24
Finished Aug 29 11:08:08 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776935936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1776935936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/7.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/70.uart_fifo_reset.2694063665
Short name T959
Test name
Test status
Simulation time 20884923374 ps
CPU time 84.8 seconds
Started Aug 29 11:34:48 AM UTC 24
Finished Aug 29 11:36:15 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694063665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2694063665
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/70.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.2143015713
Short name T956
Test name
Test status
Simulation time 21414575154 ps
CPU time 67.91 seconds
Started Aug 29 11:34:55 AM UTC 24
Finished Aug 29 11:36:04 AM UTC 24
Peak memory 219776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2143015713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all
_with_rand_reset.2143015713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/71.uart_fifo_reset.444795019
Short name T944
Test name
Test status
Simulation time 37920140653 ps
CPU time 41.92 seconds
Started Aug 29 11:34:55 AM UTC 24
Finished Aug 29 11:35:38 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444795019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.444795019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/71.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.1658098708
Short name T936
Test name
Test status
Simulation time 5226957949 ps
CPU time 18.39 seconds
Started Aug 29 11:34:59 AM UTC 24
Finished Aug 29 11:35:19 AM UTC 24
Peak memory 217868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1658098708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all
_with_rand_reset.1658098708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/72.uart_fifo_reset.1824740872
Short name T1039
Test name
Test status
Simulation time 282589820373 ps
CPU time 263.16 seconds
Started Aug 29 11:34:59 AM UTC 24
Finished Aug 29 11:39:26 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824740872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1824740872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/72.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.3673324313
Short name T938
Test name
Test status
Simulation time 5164200338 ps
CPU time 24.91 seconds
Started Aug 29 11:35:00 AM UTC 24
Finished Aug 29 11:35:27 AM UTC 24
Peak memory 219904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3673324313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all
_with_rand_reset.3673324313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/73.uart_fifo_reset.365928458
Short name T210
Test name
Test status
Simulation time 18092305043 ps
CPU time 27 seconds
Started Aug 29 11:35:00 AM UTC 24
Finished Aug 29 11:35:29 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365928458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.365928458
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/73.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.3922761420
Short name T948
Test name
Test status
Simulation time 1942244295 ps
CPU time 44.38 seconds
Started Aug 29 11:35:02 AM UTC 24
Finished Aug 29 11:35:47 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3922761420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all
_with_rand_reset.3922761420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/74.uart_fifo_reset.3840235769
Short name T954
Test name
Test status
Simulation time 67423362404 ps
CPU time 56.68 seconds
Started Aug 29 11:35:04 AM UTC 24
Finished Aug 29 11:36:02 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840235769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3840235769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/74.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.2181041660
Short name T943
Test name
Test status
Simulation time 10767912993 ps
CPU time 28.79 seconds
Started Aug 29 11:35:07 AM UTC 24
Finished Aug 29 11:35:37 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2181041660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all
_with_rand_reset.2181041660
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/75.uart_fifo_reset.1919620895
Short name T970
Test name
Test status
Simulation time 116313919011 ps
CPU time 84.01 seconds
Started Aug 29 11:35:07 AM UTC 24
Finished Aug 29 11:36:33 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919620895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1919620895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/75.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.396241656
Short name T942
Test name
Test status
Simulation time 1332062188 ps
CPU time 25.4 seconds
Started Aug 29 11:35:08 AM UTC 24
Finished Aug 29 11:35:35 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=396241656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all_
with_rand_reset.396241656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.1769212525
Short name T961
Test name
Test status
Simulation time 3561188672 ps
CPU time 66.08 seconds
Started Aug 29 11:35:12 AM UTC 24
Finished Aug 29 11:36:19 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1769212525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all
_with_rand_reset.1769212525
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/77.uart_fifo_reset.456345209
Short name T975
Test name
Test status
Simulation time 56020154835 ps
CPU time 72.93 seconds
Started Aug 29 11:35:20 AM UTC 24
Finished Aug 29 11:36:35 AM UTC 24
Peak memory 208860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456345209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.456345209
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/77.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.2745453937
Short name T964
Test name
Test status
Simulation time 5881758527 ps
CPU time 60.29 seconds
Started Aug 29 11:35:22 AM UTC 24
Finished Aug 29 11:36:24 AM UTC 24
Peak memory 217600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2745453937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all
_with_rand_reset.2745453937
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/78.uart_fifo_reset.1089005044
Short name T1137
Test name
Test status
Simulation time 185952468789 ps
CPU time 404.86 seconds
Started Aug 29 11:35:26 AM UTC 24
Finished Aug 29 11:42:16 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089005044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1089005044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/78.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.4032717905
Short name T951
Test name
Test status
Simulation time 20237777725 ps
CPU time 28.73 seconds
Started Aug 29 11:35:27 AM UTC 24
Finished Aug 29 11:35:57 AM UTC 24
Peak memory 223956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4032717905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all
_with_rand_reset.4032717905
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/79.uart_fifo_reset.2891009219
Short name T972
Test name
Test status
Simulation time 90700119217 ps
CPU time 63.23 seconds
Started Aug 29 11:35:29 AM UTC 24
Finished Aug 29 11:36:33 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891009219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2891009219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/79.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.4146430898
Short name T958
Test name
Test status
Simulation time 10937190616 ps
CPU time 38.99 seconds
Started Aug 29 11:35:30 AM UTC 24
Finished Aug 29 11:36:10 AM UTC 24
Peak memory 217604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4146430898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all
_with_rand_reset.4146430898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_alert_test.2514512925
Short name T434
Test name
Test status
Simulation time 53372130 ps
CPU time 0.82 seconds
Started Aug 29 11:08:46 AM UTC 24
Finished Aug 29 11:08:48 AM UTC 24
Peak memory 204372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514512925 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2514512925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_fifo_full.2719120401
Short name T304
Test name
Test status
Simulation time 136678641317 ps
CPU time 39.05 seconds
Started Aug 29 11:08:21 AM UTC 24
Finished Aug 29 11:09:01 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719120401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2719120401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.4231086178
Short name T134
Test name
Test status
Simulation time 12011675162 ps
CPU time 34.65 seconds
Started Aug 29 11:08:21 AM UTC 24
Finished Aug 29 11:08:57 AM UTC 24
Peak memory 208228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231086178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.4231086178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_fifo_reset.1835406563
Short name T126
Test name
Test status
Simulation time 18096992659 ps
CPU time 38.49 seconds
Started Aug 29 11:08:28 AM UTC 24
Finished Aug 29 11:09:08 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835406563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1835406563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.4202712664
Short name T715
Test name
Test status
Simulation time 129432042107 ps
CPU time 997.03 seconds
Started Aug 29 11:08:40 AM UTC 24
Finished Aug 29 11:25:28 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202712664 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.4202712664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_loopback.3368813318
Short name T433
Test name
Test status
Simulation time 4797392701 ps
CPU time 6.54 seconds
Started Aug 29 11:08:40 AM UTC 24
Finished Aug 29 11:08:47 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368813318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3368813318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_noise_filter.1467607196
Short name T302
Test name
Test status
Simulation time 67464516582 ps
CPU time 62.14 seconds
Started Aug 29 11:08:34 AM UTC 24
Finished Aug 29 11:09:38 AM UTC 24
Peak memory 208284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467607196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1467607196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_perf.2020369596
Short name T335
Test name
Test status
Simulation time 17415716878 ps
CPU time 140.3 seconds
Started Aug 29 11:08:40 AM UTC 24
Finished Aug 29 11:11:02 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020369596 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2020369596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_rx_oversample.1838842954
Short name T431
Test name
Test status
Simulation time 2562915090 ps
CPU time 7.15 seconds
Started Aug 29 11:08:30 AM UTC 24
Finished Aug 29 11:08:38 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838842954 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1838842954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.3404533905
Short name T378
Test name
Test status
Simulation time 124268798603 ps
CPU time 444.37 seconds
Started Aug 29 11:08:38 AM UTC 24
Finished Aug 29 11:16:09 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404533905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3404533905
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.2527556328
Short name T326
Test name
Test status
Simulation time 2202952470 ps
CPU time 3.26 seconds
Started Aug 29 11:08:36 AM UTC 24
Finished Aug 29 11:08:41 AM UTC 24
Peak memory 205228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527556328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2527556328
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_smoke.609747338
Short name T315
Test name
Test status
Simulation time 5807564659 ps
CPU time 56.36 seconds
Started Aug 29 11:08:15 AM UTC 24
Finished Aug 29 11:09:13 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609747338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.uart_smoke.609747338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_stress_all.4276119993
Short name T1181
Test name
Test status
Simulation time 312841771688 ps
CPU time 3873.9 seconds
Started Aug 29 11:08:45 AM UTC 24
Finished Aug 29 12:14:02 PM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276119993 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4276119993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.1426655922
Short name T37
Test name
Test status
Simulation time 8867762706 ps
CPU time 18.58 seconds
Started Aug 29 11:08:42 AM UTC 24
Finished Aug 29 11:09:01 AM UTC 24
Peak memory 225280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1426655922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_
with_rand_reset.1426655922
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.3240926190
Short name T319
Test name
Test status
Simulation time 3280703277 ps
CPU time 4.82 seconds
Started Aug 29 11:08:38 AM UTC 24
Finished Aug 29 11:08:44 AM UTC 24
Peak memory 208016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240926190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3240926190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/8.uart_tx_rx.2914505330
Short name T277
Test name
Test status
Simulation time 107751905434 ps
CPU time 61.11 seconds
Started Aug 29 11:08:18 AM UTC 24
Finished Aug 29 11:09:21 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914505330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2914505330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/8.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/80.uart_fifo_reset.2498305596
Short name T962
Test name
Test status
Simulation time 37894446438 ps
CPU time 48.11 seconds
Started Aug 29 11:35:33 AM UTC 24
Finished Aug 29 11:36:23 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498305596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2498305596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/80.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2609731074
Short name T982
Test name
Test status
Simulation time 31370296177 ps
CPU time 73.67 seconds
Started Aug 29 11:35:33 AM UTC 24
Finished Aug 29 11:36:49 AM UTC 24
Peak memory 221884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2609731074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all
_with_rand_reset.2609731074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/81.uart_fifo_reset.4021495392
Short name T981
Test name
Test status
Simulation time 119751786842 ps
CPU time 69.39 seconds
Started Aug 29 11:35:36 AM UTC 24
Finished Aug 29 11:36:47 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021495392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.4021495392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/81.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.2676484512
Short name T971
Test name
Test status
Simulation time 2875797273 ps
CPU time 55.61 seconds
Started Aug 29 11:35:36 AM UTC 24
Finished Aug 29 11:36:33 AM UTC 24
Peak memory 219784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2676484512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all
_with_rand_reset.2676484512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/82.uart_fifo_reset.3330191150
Short name T976
Test name
Test status
Simulation time 89464438945 ps
CPU time 57.24 seconds
Started Aug 29 11:35:36 AM UTC 24
Finished Aug 29 11:36:35 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330191150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3330191150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/82.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.1897480609
Short name T990
Test name
Test status
Simulation time 24391870198 ps
CPU time 82.86 seconds
Started Aug 29 11:35:36 AM UTC 24
Finished Aug 29 11:37:01 AM UTC 24
Peak memory 221888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1897480609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all
_with_rand_reset.1897480609
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/83.uart_fifo_reset.1790319058
Short name T957
Test name
Test status
Simulation time 14827374437 ps
CPU time 24.98 seconds
Started Aug 29 11:35:38 AM UTC 24
Finished Aug 29 11:36:05 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790319058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1790319058
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/83.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.2617386537
Short name T973
Test name
Test status
Simulation time 13179784342 ps
CPU time 52.01 seconds
Started Aug 29 11:35:39 AM UTC 24
Finished Aug 29 11:36:33 AM UTC 24
Peak memory 219836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2617386537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all
_with_rand_reset.2617386537
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/84.uart_fifo_reset.2451848662
Short name T983
Test name
Test status
Simulation time 21853868819 ps
CPU time 70.27 seconds
Started Aug 29 11:35:39 AM UTC 24
Finished Aug 29 11:36:52 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451848662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2451848662
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/84.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.3520559946
Short name T979
Test name
Test status
Simulation time 7299075861 ps
CPU time 55.22 seconds
Started Aug 29 11:35:41 AM UTC 24
Finished Aug 29 11:36:38 AM UTC 24
Peak memory 221884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3520559946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all
_with_rand_reset.3520559946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/85.uart_fifo_reset.3196842871
Short name T1049
Test name
Test status
Simulation time 92399179085 ps
CPU time 236.58 seconds
Started Aug 29 11:35:41 AM UTC 24
Finished Aug 29 11:39:41 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196842871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3196842871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/85.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.2545205290
Short name T978
Test name
Test status
Simulation time 10565205175 ps
CPU time 45.68 seconds
Started Aug 29 11:35:49 AM UTC 24
Finished Aug 29 11:36:36 AM UTC 24
Peak memory 225432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2545205290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all
_with_rand_reset.2545205290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3987024380
Short name T1019
Test name
Test status
Simulation time 57195040457 ps
CPU time 154.59 seconds
Started Aug 29 11:35:54 AM UTC 24
Finished Aug 29 11:38:32 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987024380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3987024380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/86.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.2345817434
Short name T963
Test name
Test status
Simulation time 3816521622 ps
CPU time 27.93 seconds
Started Aug 29 11:35:54 AM UTC 24
Finished Aug 29 11:36:24 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2345817434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all
_with_rand_reset.2345817434
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/87.uart_fifo_reset.402801242
Short name T165
Test name
Test status
Simulation time 26907836762 ps
CPU time 13.53 seconds
Started Aug 29 11:35:59 AM UTC 24
Finished Aug 29 11:36:13 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402801242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.402801242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/87.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.3701737293
Short name T984
Test name
Test status
Simulation time 22045690146 ps
CPU time 55.78 seconds
Started Aug 29 11:35:59 AM UTC 24
Finished Aug 29 11:36:56 AM UTC 24
Peak memory 224804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3701737293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all
_with_rand_reset.3701737293
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/88.uart_fifo_reset.951656741
Short name T969
Test name
Test status
Simulation time 13045261079 ps
CPU time 32.21 seconds
Started Aug 29 11:35:59 AM UTC 24
Finished Aug 29 11:36:32 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951656741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.951656741
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/88.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.689924054
Short name T1015
Test name
Test status
Simulation time 23792444059 ps
CPU time 125.59 seconds
Started Aug 29 11:36:03 AM UTC 24
Finished Aug 29 11:38:11 AM UTC 24
Peak memory 222004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=689924054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all_
with_rand_reset.689924054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2833453750
Short name T1000
Test name
Test status
Simulation time 21516650077 ps
CPU time 91.92 seconds
Started Aug 29 11:36:03 AM UTC 24
Finished Aug 29 11:37:37 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833453750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2833453750
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/89.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.2456178468
Short name T996
Test name
Test status
Simulation time 5461614389 ps
CPU time 89.47 seconds
Started Aug 29 11:36:04 AM UTC 24
Finished Aug 29 11:37:36 AM UTC 24
Peak memory 217812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2456178468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all
_with_rand_reset.2456178468
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_alert_test.2262269254
Short name T436
Test name
Test status
Simulation time 16437412 ps
CPU time 0.79 seconds
Started Aug 29 11:09:20 AM UTC 24
Finished Aug 29 11:09:22 AM UTC 24
Peak memory 204372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262269254 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2262269254
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_fifo_full.2346942148
Short name T127
Test name
Test status
Simulation time 23847451467 ps
CPU time 58.22 seconds
Started Aug 29 11:08:50 AM UTC 24
Finished Aug 29 11:09:50 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346942148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2346942148
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.1881078742
Short name T396
Test name
Test status
Simulation time 45349920095 ps
CPU time 72.14 seconds
Started Aug 29 11:08:52 AM UTC 24
Finished Aug 29 11:10:06 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881078742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1881078742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_fifo_reset.2759587359
Short name T190
Test name
Test status
Simulation time 34923852193 ps
CPU time 33.33 seconds
Started Aug 29 11:08:53 AM UTC 24
Finished Aug 29 11:09:28 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759587359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2759587359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_intr.1079316027
Short name T344
Test name
Test status
Simulation time 18164357050 ps
CPU time 48.39 seconds
Started Aug 29 11:08:57 AM UTC 24
Finished Aug 29 11:09:47 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079316027 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1079316027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.3289115810
Short name T345
Test name
Test status
Simulation time 118401708131 ps
CPU time 351.28 seconds
Started Aug 29 11:09:14 AM UTC 24
Finished Aug 29 11:15:10 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289115810 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3289115810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_loopback.2468989730
Short name T403
Test name
Test status
Simulation time 1738512199 ps
CPU time 8.3 seconds
Started Aug 29 11:09:07 AM UTC 24
Finished Aug 29 11:09:16 AM UTC 24
Peak memory 207356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468989730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2468989730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_noise_filter.2869346432
Short name T271
Test name
Test status
Simulation time 107360828905 ps
CPU time 119.11 seconds
Started Aug 29 11:08:59 AM UTC 24
Finished Aug 29 11:11:01 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869346432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2869346432
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_perf.2310163376
Short name T673
Test name
Test status
Simulation time 20552017759 ps
CPU time 853.41 seconds
Started Aug 29 11:09:09 AM UTC 24
Finished Aug 29 11:23:32 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310163376 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2310163376
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_rx_oversample.791877285
Short name T435
Test name
Test status
Simulation time 7190088260 ps
CPU time 22.88 seconds
Started Aug 29 11:08:54 AM UTC 24
Finished Aug 29 11:09:18 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791877285 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.791877285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.4202891641
Short name T278
Test name
Test status
Simulation time 29732490570 ps
CPU time 91.34 seconds
Started Aug 29 11:09:03 AM UTC 24
Finished Aug 29 11:10:36 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202891641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.4202891641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_smoke.439718591
Short name T328
Test name
Test status
Simulation time 657508426 ps
CPU time 2.88 seconds
Started Aug 29 11:08:48 AM UTC 24
Finished Aug 29 11:08:52 AM UTC 24
Peak memory 207868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439718591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.uart_smoke.439718591
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.1001727768
Short name T39
Test name
Test status
Simulation time 2624307761 ps
CPU time 29.33 seconds
Started Aug 29 11:09:17 AM UTC 24
Finished Aug 29 11:09:48 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1001727768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_
with_rand_reset.1001727768
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.693623590
Short name T368
Test name
Test status
Simulation time 6413318869 ps
CPU time 19.71 seconds
Started Aug 29 11:09:04 AM UTC 24
Finished Aug 29 11:09:25 AM UTC 24
Peak memory 207924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693623590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.693623590
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/9.uart_tx_rx.1758331233
Short name T290
Test name
Test status
Simulation time 10513040098 ps
CPU time 35.59 seconds
Started Aug 29 11:08:48 AM UTC 24
Finished Aug 29 11:09:25 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758331233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1758331233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/9.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/90.uart_fifo_reset.3790032593
Short name T965
Test name
Test status
Simulation time 46928183732 ps
CPU time 17.67 seconds
Started Aug 29 11:36:06 AM UTC 24
Finished Aug 29 11:36:24 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790032593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3790032593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/90.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.1321718773
Short name T988
Test name
Test status
Simulation time 3641665422 ps
CPU time 51.54 seconds
Started Aug 29 11:36:06 AM UTC 24
Finished Aug 29 11:36:59 AM UTC 24
Peak memory 219756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1321718773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all
_with_rand_reset.1321718773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/91.uart_fifo_reset.351594854
Short name T992
Test name
Test status
Simulation time 128763351058 ps
CPU time 53.04 seconds
Started Aug 29 11:36:11 AM UTC 24
Finished Aug 29 11:37:05 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351594854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.351594854
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/91.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.4211421518
Short name T977
Test name
Test status
Simulation time 1074661025 ps
CPU time 19.78 seconds
Started Aug 29 11:36:14 AM UTC 24
Finished Aug 29 11:36:35 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4211421518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all
_with_rand_reset.4211421518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/92.uart_fifo_reset.1875203285
Short name T219
Test name
Test status
Simulation time 58763948374 ps
CPU time 37.48 seconds
Started Aug 29 11:36:16 AM UTC 24
Finished Aug 29 11:36:55 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875203285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1875203285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/92.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.2024509024
Short name T980
Test name
Test status
Simulation time 1554053460 ps
CPU time 25.41 seconds
Started Aug 29 11:36:16 AM UTC 24
Finished Aug 29 11:36:43 AM UTC 24
Peak memory 217668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2024509024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all
_with_rand_reset.2024509024
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/93.uart_fifo_reset.2178612533
Short name T1106
Test name
Test status
Simulation time 226269919456 ps
CPU time 296.43 seconds
Started Aug 29 11:36:21 AM UTC 24
Finished Aug 29 11:41:21 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178612533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2178612533
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/93.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.2234687419
Short name T974
Test name
Test status
Simulation time 806032053 ps
CPU time 9.27 seconds
Started Aug 29 11:36:24 AM UTC 24
Finished Aug 29 11:36:34 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2234687419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all
_with_rand_reset.2234687419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.3336909066
Short name T991
Test name
Test status
Simulation time 2739107296 ps
CPU time 37.16 seconds
Started Aug 29 11:36:25 AM UTC 24
Finished Aug 29 11:37:04 AM UTC 24
Peak memory 217804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3336909066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all
_with_rand_reset.3336909066
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/95.uart_fifo_reset.3882973274
Short name T1006
Test name
Test status
Simulation time 154936111317 ps
CPU time 80.02 seconds
Started Aug 29 11:36:25 AM UTC 24
Finished Aug 29 11:37:47 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882973274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3882973274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/95.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.4002168735
Short name T968
Test name
Test status
Simulation time 243759064 ps
CPU time 5.21 seconds
Started Aug 29 11:36:25 AM UTC 24
Finished Aug 29 11:36:32 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4002168735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all
_with_rand_reset.4002168735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/96.uart_fifo_reset.3617986163
Short name T227
Test name
Test status
Simulation time 168567754715 ps
CPU time 203.43 seconds
Started Aug 29 11:36:31 AM UTC 24
Finished Aug 29 11:39:58 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617986163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3617986163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/96.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.3829148414
Short name T987
Test name
Test status
Simulation time 1738359583 ps
CPU time 23.92 seconds
Started Aug 29 11:36:33 AM UTC 24
Finished Aug 29 11:36:58 AM UTC 24
Peak memory 222036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3829148414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all
_with_rand_reset.3829148414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/97.uart_fifo_reset.3380919456
Short name T1003
Test name
Test status
Simulation time 41372450162 ps
CPU time 65.7 seconds
Started Aug 29 11:36:33 AM UTC 24
Finished Aug 29 11:37:40 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380919456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3380919456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/97.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.3415759502
Short name T1013
Test name
Test status
Simulation time 18498759746 ps
CPU time 90.98 seconds
Started Aug 29 11:36:33 AM UTC 24
Finished Aug 29 11:38:06 AM UTC 24
Peak memory 223820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3415759502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all
_with_rand_reset.3415759502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/98.uart_fifo_reset.3109254452
Short name T1008
Test name
Test status
Simulation time 45644414287 ps
CPU time 72.92 seconds
Started Aug 29 11:36:35 AM UTC 24
Finished Aug 29 11:37:49 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109254452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3109254452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/98.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.143877033
Short name T993
Test name
Test status
Simulation time 7020913849 ps
CPU time 38.06 seconds
Started Aug 29 11:36:35 AM UTC 24
Finished Aug 29 11:37:14 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=143877033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all_
with_rand_reset.143877033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.565978817
Short name T986
Test name
Test status
Simulation time 4672988833 ps
CPU time 21.55 seconds
Started Aug 29 11:36:35 AM UTC 24
Finished Aug 29 11:36:58 AM UTC 24
Peak memory 221828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=565978817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all_
with_rand_reset.565978817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest
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