| T194 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_fifo_reset.2653802563 |
|
|
Sep 01 06:43:55 AM UTC 24 |
Sep 01 06:54:58 AM UTC 24 |
238446427579 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2406777363 |
|
|
Sep 01 06:54:47 AM UTC 24 |
Sep 01 06:55:00 AM UTC 24 |
8317485098 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/197.uart_fifo_reset.3445835370 |
|
|
Sep 01 06:54:31 AM UTC 24 |
Sep 01 06:55:01 AM UTC 24 |
33129132365 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/196.uart_fifo_reset.4111651000 |
|
|
Sep 01 06:54:31 AM UTC 24 |
Sep 01 06:55:02 AM UTC 24 |
18380216030 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/94.uart_fifo_reset.2807979164 |
|
|
Sep 01 06:51:22 AM UTC 24 |
Sep 01 06:55:02 AM UTC 24 |
217774242661 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/213.uart_fifo_reset.289001267 |
|
|
Sep 01 06:54:52 AM UTC 24 |
Sep 01 06:56:11 AM UTC 24 |
301907986774 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/179.uart_fifo_reset.3953232841 |
|
|
Sep 01 06:53:47 AM UTC 24 |
Sep 01 06:55:03 AM UTC 24 |
23807486836 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/193.uart_fifo_reset.1632444945 |
|
|
Sep 01 06:54:21 AM UTC 24 |
Sep 01 06:55:05 AM UTC 24 |
13172394550 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/154.uart_fifo_reset.1238777889 |
|
|
Sep 01 06:53:03 AM UTC 24 |
Sep 01 06:55:08 AM UTC 24 |
94095887423 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2632951038 |
|
|
Sep 01 06:54:43 AM UTC 24 |
Sep 01 06:55:08 AM UTC 24 |
20485317480 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2600309964 |
|
|
Sep 01 06:54:46 AM UTC 24 |
Sep 01 06:55:08 AM UTC 24 |
53546123605 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/177.uart_fifo_reset.3820926415 |
|
|
Sep 01 06:53:42 AM UTC 24 |
Sep 01 06:55:10 AM UTC 24 |
210650513895 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.2176663662 |
|
|
Sep 01 06:39:32 AM UTC 24 |
Sep 01 06:55:11 AM UTC 24 |
95509472216 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/72.uart_fifo_reset.2910140337 |
|
|
Sep 01 06:49:59 AM UTC 24 |
Sep 01 06:55:12 AM UTC 24 |
189394447997 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/195.uart_fifo_reset.2186947784 |
|
|
Sep 01 06:54:24 AM UTC 24 |
Sep 01 06:55:13 AM UTC 24 |
56727096632 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/210.uart_fifo_reset.115449019 |
|
|
Sep 01 06:54:50 AM UTC 24 |
Sep 01 06:55:16 AM UTC 24 |
24711900798 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/149.uart_fifo_reset.3749660290 |
|
|
Sep 01 06:52:56 AM UTC 24 |
Sep 01 06:55:18 AM UTC 24 |
128797651822 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/212.uart_fifo_reset.1066241210 |
|
|
Sep 01 06:54:51 AM UTC 24 |
Sep 01 06:55:20 AM UTC 24 |
9005266764 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/172.uart_fifo_reset.305102938 |
|
|
Sep 01 06:53:33 AM UTC 24 |
Sep 01 06:55:27 AM UTC 24 |
106891441045 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/198.uart_fifo_reset.4141709627 |
|
|
Sep 01 06:54:32 AM UTC 24 |
Sep 01 06:55:31 AM UTC 24 |
35883513771 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/228.uart_fifo_reset.3965493494 |
|
|
Sep 01 06:55:17 AM UTC 24 |
Sep 01 06:55:34 AM UTC 24 |
14565831156 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/185.uart_fifo_reset.637565126 |
|
|
Sep 01 06:53:58 AM UTC 24 |
Sep 01 06:55:36 AM UTC 24 |
42007159469 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_stress_all.2986086439 |
|
|
Sep 01 06:40:41 AM UTC 24 |
Sep 01 06:55:36 AM UTC 24 |
292463089491 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/226.uart_fifo_reset.723226711 |
|
|
Sep 01 06:55:13 AM UTC 24 |
Sep 01 06:55:37 AM UTC 24 |
6592617025 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/204.uart_fifo_reset.3706653360 |
|
|
Sep 01 06:54:44 AM UTC 24 |
Sep 01 06:55:40 AM UTC 24 |
84188130423 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/175.uart_fifo_reset.601364922 |
|
|
Sep 01 06:53:39 AM UTC 24 |
Sep 01 06:55:42 AM UTC 24 |
52083590439 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/220.uart_fifo_reset.2992979916 |
|
|
Sep 01 06:55:06 AM UTC 24 |
Sep 01 06:55:43 AM UTC 24 |
9558615249 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/97.uart_fifo_reset.3855799987 |
|
|
Sep 01 06:51:31 AM UTC 24 |
Sep 01 06:55:43 AM UTC 24 |
147798513524 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2929809919 |
|
|
Sep 01 06:55:11 AM UTC 24 |
Sep 01 06:55:44 AM UTC 24 |
282085369611 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/124.uart_fifo_reset.1380827099 |
|
|
Sep 01 06:52:20 AM UTC 24 |
Sep 01 06:55:49 AM UTC 24 |
103498014247 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/205.uart_fifo_reset.2950685579 |
|
|
Sep 01 06:54:45 AM UTC 24 |
Sep 01 06:55:50 AM UTC 24 |
53796790007 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/201.uart_fifo_reset.1883263240 |
|
|
Sep 01 06:54:34 AM UTC 24 |
Sep 01 06:55:51 AM UTC 24 |
72442928486 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/167.uart_fifo_reset.1722592297 |
|
|
Sep 01 06:53:23 AM UTC 24 |
Sep 01 06:55:54 AM UTC 24 |
74103246758 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/227.uart_fifo_reset.888528949 |
|
|
Sep 01 06:55:14 AM UTC 24 |
Sep 01 06:55:57 AM UTC 24 |
17860279369 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2118975454 |
|
|
Sep 01 06:55:04 AM UTC 24 |
Sep 01 06:56:01 AM UTC 24 |
202086337352 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/202.uart_fifo_reset.2347432607 |
|
|
Sep 01 06:54:40 AM UTC 24 |
Sep 01 06:56:03 AM UTC 24 |
27400371984 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/240.uart_fifo_reset.1900989412 |
|
|
Sep 01 06:55:44 AM UTC 24 |
Sep 01 06:56:08 AM UTC 24 |
28950200064 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/187.uart_fifo_reset.2234845905 |
|
|
Sep 01 06:54:03 AM UTC 24 |
Sep 01 06:56:09 AM UTC 24 |
286513150768 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/229.uart_fifo_reset.929264473 |
|
|
Sep 01 06:55:19 AM UTC 24 |
Sep 01 06:56:10 AM UTC 24 |
25089531175 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/192.uart_fifo_reset.2094171047 |
|
|
Sep 01 06:54:18 AM UTC 24 |
Sep 01 06:56:11 AM UTC 24 |
162826439820 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/239.uart_fifo_reset.488522887 |
|
|
Sep 01 06:55:43 AM UTC 24 |
Sep 01 06:56:13 AM UTC 24 |
32581461163 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/176.uart_fifo_reset.2860689589 |
|
|
Sep 01 06:53:41 AM UTC 24 |
Sep 01 06:56:13 AM UTC 24 |
76557478993 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/242.uart_fifo_reset.4198873928 |
|
|
Sep 01 06:55:49 AM UTC 24 |
Sep 01 06:56:15 AM UTC 24 |
39887563227 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/181.uart_fifo_reset.1911131391 |
|
|
Sep 01 06:53:48 AM UTC 24 |
Sep 01 06:56:23 AM UTC 24 |
87669310541 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/87.uart_fifo_reset.914996661 |
|
|
Sep 01 06:50:58 AM UTC 24 |
Sep 01 06:56:25 AM UTC 24 |
152373099974 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/246.uart_fifo_reset.856698786 |
|
|
Sep 01 06:55:58 AM UTC 24 |
Sep 01 06:56:26 AM UTC 24 |
30098522469 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/182.uart_fifo_reset.3814286355 |
|
|
Sep 01 06:53:50 AM UTC 24 |
Sep 01 06:56:26 AM UTC 24 |
155893338582 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/238.uart_fifo_reset.460766009 |
|
|
Sep 01 06:55:42 AM UTC 24 |
Sep 01 06:56:27 AM UTC 24 |
15185403303 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/235.uart_fifo_reset.3706843222 |
|
|
Sep 01 06:55:37 AM UTC 24 |
Sep 01 06:56:27 AM UTC 24 |
29930080237 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2096097134 |
|
|
Sep 01 06:55:35 AM UTC 24 |
Sep 01 06:56:28 AM UTC 24 |
39163107101 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/50.uart_fifo_reset.1486499529 |
|
|
Sep 01 06:48:27 AM UTC 24 |
Sep 01 06:56:32 AM UTC 24 |
190550565749 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2533121964 |
|
|
Sep 01 06:54:49 AM UTC 24 |
Sep 01 06:56:33 AM UTC 24 |
99706254191 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/234.uart_fifo_reset.3642853554 |
|
|
Sep 01 06:55:37 AM UTC 24 |
Sep 01 06:56:36 AM UTC 24 |
146644726033 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/248.uart_fifo_reset.638435174 |
|
|
Sep 01 06:56:04 AM UTC 24 |
Sep 01 06:56:37 AM UTC 24 |
47890650831 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/247.uart_fifo_reset.32631238 |
|
|
Sep 01 06:56:02 AM UTC 24 |
Sep 01 06:56:37 AM UTC 24 |
248730881286 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/138.uart_fifo_reset.1576904211 |
|
|
Sep 01 06:52:43 AM UTC 24 |
Sep 01 06:56:42 AM UTC 24 |
214698822650 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/215.uart_fifo_reset.1730642615 |
|
|
Sep 01 06:55:01 AM UTC 24 |
Sep 01 06:56:42 AM UTC 24 |
131871363481 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/171.uart_fifo_reset.3570986073 |
|
|
Sep 01 06:53:31 AM UTC 24 |
Sep 01 06:56:44 AM UTC 24 |
180513844087 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/236.uart_fifo_reset.3393052789 |
|
|
Sep 01 06:55:38 AM UTC 24 |
Sep 01 06:56:45 AM UTC 24 |
28550484609 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/188.uart_fifo_reset.2367580207 |
|
|
Sep 01 06:54:07 AM UTC 24 |
Sep 01 06:56:49 AM UTC 24 |
137473989392 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/225.uart_fifo_reset.968977749 |
|
|
Sep 01 06:55:12 AM UTC 24 |
Sep 01 06:56:51 AM UTC 24 |
95284579807 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1349547746 |
|
|
Sep 01 06:55:03 AM UTC 24 |
Sep 01 06:56:51 AM UTC 24 |
34927453861 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/231.uart_fifo_reset.3458979096 |
|
|
Sep 01 06:55:27 AM UTC 24 |
Sep 01 06:56:51 AM UTC 24 |
26480765315 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/117.uart_fifo_reset.463957273 |
|
|
Sep 01 06:52:09 AM UTC 24 |
Sep 01 06:56:53 AM UTC 24 |
246801564496 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/260.uart_fifo_reset.345374675 |
|
|
Sep 01 06:56:27 AM UTC 24 |
Sep 01 06:56:54 AM UTC 24 |
16458494609 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/250.uart_fifo_reset.371150903 |
|
|
Sep 01 06:56:10 AM UTC 24 |
Sep 01 06:56:55 AM UTC 24 |
50192305827 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/237.uart_fifo_reset.4195580908 |
|
|
Sep 01 06:55:41 AM UTC 24 |
Sep 01 06:56:55 AM UTC 24 |
106589727989 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/221.uart_fifo_reset.1539506306 |
|
|
Sep 01 06:55:09 AM UTC 24 |
Sep 01 06:56:59 AM UTC 24 |
97547888077 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/254.uart_fifo_reset.2827173625 |
|
|
Sep 01 06:56:14 AM UTC 24 |
Sep 01 06:57:01 AM UTC 24 |
41948992070 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/222.uart_fifo_reset.4287781217 |
|
|
Sep 01 06:55:09 AM UTC 24 |
Sep 01 06:57:01 AM UTC 24 |
162020099911 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/275.uart_fifo_reset.2752552874 |
|
|
Sep 01 06:56:52 AM UTC 24 |
Sep 01 06:57:14 AM UTC 24 |
19289321918 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/270.uart_fifo_reset.604296797 |
|
|
Sep 01 06:56:43 AM UTC 24 |
Sep 01 06:57:15 AM UTC 24 |
31319157366 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/217.uart_fifo_reset.59886296 |
|
|
Sep 01 06:55:02 AM UTC 24 |
Sep 01 06:57:16 AM UTC 24 |
112164193952 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/266.uart_fifo_reset.2776760892 |
|
|
Sep 01 06:56:38 AM UTC 24 |
Sep 01 06:57:19 AM UTC 24 |
69879492787 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/255.uart_fifo_reset.2630313197 |
|
|
Sep 01 06:56:14 AM UTC 24 |
Sep 01 06:57:20 AM UTC 24 |
45354887057 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/268.uart_fifo_reset.855497456 |
|
|
Sep 01 06:56:39 AM UTC 24 |
Sep 01 06:57:20 AM UTC 24 |
105916738296 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/269.uart_fifo_reset.3295841634 |
|
|
Sep 01 06:56:43 AM UTC 24 |
Sep 01 06:57:22 AM UTC 24 |
35115722421 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/259.uart_fifo_reset.3886906447 |
|
|
Sep 01 06:56:27 AM UTC 24 |
Sep 01 06:57:22 AM UTC 24 |
63504152523 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/253.uart_fifo_reset.4059294689 |
|
|
Sep 01 06:56:12 AM UTC 24 |
Sep 01 06:57:27 AM UTC 24 |
21528888604 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/258.uart_fifo_reset.366225690 |
|
|
Sep 01 06:56:26 AM UTC 24 |
Sep 01 06:57:28 AM UTC 24 |
124330086717 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/241.uart_fifo_reset.4125329486 |
|
|
Sep 01 06:55:44 AM UTC 24 |
Sep 01 06:57:29 AM UTC 24 |
56083996162 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/278.uart_fifo_reset.3956638742 |
|
|
Sep 01 06:56:55 AM UTC 24 |
Sep 01 06:57:31 AM UTC 24 |
29958778078 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2392998469 |
|
|
Sep 01 06:56:56 AM UTC 24 |
Sep 01 06:57:31 AM UTC 24 |
14479182906 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/285.uart_fifo_reset.2066190569 |
|
|
Sep 01 06:57:16 AM UTC 24 |
Sep 01 06:57:33 AM UTC 24 |
8905529187 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/277.uart_fifo_reset.2485805891 |
|
|
Sep 01 06:56:54 AM UTC 24 |
Sep 01 06:57:33 AM UTC 24 |
72541097833 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/264.uart_fifo_reset.3889213255 |
|
|
Sep 01 06:56:32 AM UTC 24 |
Sep 01 06:57:34 AM UTC 24 |
17039688847 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/289.uart_fifo_reset.3659345245 |
|
|
Sep 01 06:57:22 AM UTC 24 |
Sep 01 06:57:35 AM UTC 24 |
11844972120 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/276.uart_fifo_reset.3008022915 |
|
|
Sep 01 06:56:52 AM UTC 24 |
Sep 01 06:57:38 AM UTC 24 |
27347882624 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/280.uart_fifo_reset.442334360 |
|
|
Sep 01 06:56:56 AM UTC 24 |
Sep 01 06:57:38 AM UTC 24 |
190604766826 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/252.uart_fifo_reset.1455649274 |
|
|
Sep 01 06:56:11 AM UTC 24 |
Sep 01 06:57:39 AM UTC 24 |
129895182896 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/169.uart_fifo_reset.34609469 |
|
|
Sep 01 06:53:27 AM UTC 24 |
Sep 01 06:57:42 AM UTC 24 |
84359555037 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/291.uart_fifo_reset.2156040592 |
|
|
Sep 01 06:57:23 AM UTC 24 |
Sep 01 06:57:46 AM UTC 24 |
36538267398 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/200.uart_fifo_reset.4248888298 |
|
|
Sep 01 06:54:33 AM UTC 24 |
Sep 01 06:57:47 AM UTC 24 |
97876464417 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/294.uart_fifo_reset.3140709219 |
|
|
Sep 01 06:57:30 AM UTC 24 |
Sep 01 06:57:50 AM UTC 24 |
76442516047 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/180.uart_fifo_reset.2689766895 |
|
|
Sep 01 06:53:48 AM UTC 24 |
Sep 01 06:57:52 AM UTC 24 |
93689073907 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/286.uart_fifo_reset.3038562329 |
|
|
Sep 01 06:57:17 AM UTC 24 |
Sep 01 06:57:52 AM UTC 24 |
13191596744 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/243.uart_fifo_reset.2756389590 |
|
|
Sep 01 06:55:51 AM UTC 24 |
Sep 01 06:57:52 AM UTC 24 |
123099297650 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1382258405 |
|
|
Sep 01 06:56:38 AM UTC 24 |
Sep 01 06:57:53 AM UTC 24 |
21920028530 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.2939364421 |
|
|
Sep 01 06:35:17 AM UTC 24 |
Sep 01 06:57:55 AM UTC 24 |
138011981506 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/297.uart_fifo_reset.750425717 |
|
|
Sep 01 06:57:33 AM UTC 24 |
Sep 01 06:58:06 AM UTC 24 |
24802049342 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/162.uart_fifo_reset.2520852757 |
|
|
Sep 01 06:53:13 AM UTC 24 |
Sep 01 06:58:09 AM UTC 24 |
170648864127 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/283.uart_fifo_reset.1295807289 |
|
|
Sep 01 06:57:02 AM UTC 24 |
Sep 01 06:58:11 AM UTC 24 |
31608254657 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/261.uart_fifo_reset.486127903 |
|
|
Sep 01 06:56:28 AM UTC 24 |
Sep 01 06:58:11 AM UTC 24 |
162457598075 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/295.uart_fifo_reset.3887187349 |
|
|
Sep 01 06:57:31 AM UTC 24 |
Sep 01 06:58:13 AM UTC 24 |
75956354915 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/290.uart_fifo_reset.3311232965 |
|
|
Sep 01 06:57:23 AM UTC 24 |
Sep 01 06:58:17 AM UTC 24 |
59010166439 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/107.uart_fifo_reset.268209364 |
|
|
Sep 01 06:51:48 AM UTC 24 |
Sep 01 06:58:19 AM UTC 24 |
195340728941 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/292.uart_fifo_reset.1516347541 |
|
|
Sep 01 06:57:28 AM UTC 24 |
Sep 01 06:58:23 AM UTC 24 |
130521013534 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/271.uart_fifo_reset.2392838097 |
|
|
Sep 01 06:56:44 AM UTC 24 |
Sep 01 06:58:26 AM UTC 24 |
86316527406 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/251.uart_fifo_reset.3632917568 |
|
|
Sep 01 06:56:10 AM UTC 24 |
Sep 01 06:58:28 AM UTC 24 |
41448754053 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/153.uart_fifo_reset.3145553468 |
|
|
Sep 01 06:53:02 AM UTC 24 |
Sep 01 06:58:32 AM UTC 24 |
147221664813 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3725841450 |
|
|
Sep 01 06:54:24 AM UTC 24 |
Sep 01 06:58:35 AM UTC 24 |
104522643254 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/298.uart_fifo_reset.1785663005 |
|
|
Sep 01 06:57:34 AM UTC 24 |
Sep 01 06:58:39 AM UTC 24 |
61517751534 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/281.uart_fifo_reset.1412746300 |
|
|
Sep 01 06:57:00 AM UTC 24 |
Sep 01 06:58:40 AM UTC 24 |
159831211064 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/249.uart_fifo_reset.2866705538 |
|
|
Sep 01 06:56:08 AM UTC 24 |
Sep 01 06:58:42 AM UTC 24 |
180753510817 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3699114128 |
|
|
Sep 01 06:57:19 AM UTC 24 |
Sep 01 06:58:43 AM UTC 24 |
117522436311 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/288.uart_fifo_reset.4119826987 |
|
|
Sep 01 06:57:21 AM UTC 24 |
Sep 01 06:58:46 AM UTC 24 |
87736550696 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/232.uart_fifo_reset.936705202 |
|
|
Sep 01 06:55:33 AM UTC 24 |
Sep 01 06:58:47 AM UTC 24 |
96000749625 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/262.uart_fifo_reset.3241343900 |
|
|
Sep 01 06:56:28 AM UTC 24 |
Sep 01 06:58:49 AM UTC 24 |
158580215409 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_perf.3679022937 |
|
|
Sep 01 06:43:44 AM UTC 24 |
Sep 01 06:58:52 AM UTC 24 |
14306529578 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/282.uart_fifo_reset.4116028346 |
|
|
Sep 01 06:57:02 AM UTC 24 |
Sep 01 06:58:56 AM UTC 24 |
49269717594 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_stress_all.2003302392 |
|
|
Sep 01 06:48:20 AM UTC 24 |
Sep 01 06:59:03 AM UTC 24 |
332006652746 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2491291738 |
|
|
Sep 01 06:57:14 AM UTC 24 |
Sep 01 06:59:04 AM UTC 24 |
44577001789 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/257.uart_fifo_reset.1230533866 |
|
|
Sep 01 06:56:25 AM UTC 24 |
Sep 01 06:59:07 AM UTC 24 |
59785932664 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/273.uart_fifo_reset.2476444665 |
|
|
Sep 01 06:56:50 AM UTC 24 |
Sep 01 06:59:16 AM UTC 24 |
73810835095 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/230.uart_fifo_reset.1677528322 |
|
|
Sep 01 06:55:20 AM UTC 24 |
Sep 01 06:59:20 AM UTC 24 |
143497926445 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/293.uart_fifo_reset.4272633408 |
|
|
Sep 01 06:57:28 AM UTC 24 |
Sep 01 06:59:21 AM UTC 24 |
54924973719 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/223.uart_fifo_reset.3626544254 |
|
|
Sep 01 06:55:10 AM UTC 24 |
Sep 01 06:59:33 AM UTC 24 |
117110256068 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/216.uart_fifo_reset.2833291252 |
|
|
Sep 01 06:55:01 AM UTC 24 |
Sep 01 06:59:33 AM UTC 24 |
111142368520 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/214.uart_fifo_reset.2082456068 |
|
|
Sep 01 06:54:59 AM UTC 24 |
Sep 01 06:59:46 AM UTC 24 |
124844530008 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/263.uart_fifo_reset.572829809 |
|
|
Sep 01 06:56:29 AM UTC 24 |
Sep 01 06:59:48 AM UTC 24 |
175683939061 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/272.uart_fifo_reset.2124146448 |
|
|
Sep 01 06:56:46 AM UTC 24 |
Sep 01 06:59:48 AM UTC 24 |
96755033766 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.985475551 |
|
|
Sep 01 06:46:35 AM UTC 24 |
Sep 01 06:59:50 AM UTC 24 |
111488256880 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/244.uart_fifo_reset.1092150189 |
|
|
Sep 01 06:55:52 AM UTC 24 |
Sep 01 06:59:53 AM UTC 24 |
94691528292 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/256.uart_fifo_reset.1074904508 |
|
|
Sep 01 06:56:17 AM UTC 24 |
Sep 01 06:59:56 AM UTC 24 |
177132722601 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/274.uart_fifo_reset.729967166 |
|
|
Sep 01 06:56:51 AM UTC 24 |
Sep 01 06:59:56 AM UTC 24 |
76687371874 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.2316251378 |
|
|
Sep 01 06:47:28 AM UTC 24 |
Sep 01 06:59:58 AM UTC 24 |
90430221084 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/265.uart_fifo_reset.1229170527 |
|
|
Sep 01 06:56:33 AM UTC 24 |
Sep 01 07:00:01 AM UTC 24 |
123441026006 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/145.uart_fifo_reset.61279519 |
|
|
Sep 01 06:52:53 AM UTC 24 |
Sep 01 07:00:05 AM UTC 24 |
226240590146 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_perf.1803628122 |
|
|
Sep 01 06:46:32 AM UTC 24 |
Sep 01 07:00:10 AM UTC 24 |
23982767530 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_stress_all.804550063 |
|
|
Sep 01 06:31:53 AM UTC 24 |
Sep 01 07:00:43 AM UTC 24 |
122813139882 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/209.uart_fifo_reset.1736471627 |
|
|
Sep 01 06:54:50 AM UTC 24 |
Sep 01 07:00:47 AM UTC 24 |
99099000918 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/296.uart_fifo_reset.1803695723 |
|
|
Sep 01 06:57:32 AM UTC 24 |
Sep 01 07:00:58 AM UTC 24 |
217985389123 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3481103870 |
|
|
Sep 01 06:54:51 AM UTC 24 |
Sep 01 07:01:05 AM UTC 24 |
99786066429 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.2406684635 |
|
|
Sep 01 06:42:55 AM UTC 24 |
Sep 01 07:01:15 AM UTC 24 |
114147399166 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_perf.3494269485 |
|
|
Sep 01 06:45:14 AM UTC 24 |
Sep 01 07:01:29 AM UTC 24 |
15273874935 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3025272124 |
|
|
Sep 01 06:55:55 AM UTC 24 |
Sep 01 07:01:52 AM UTC 24 |
106628344979 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/161.uart_fifo_reset.2846500678 |
|
|
Sep 01 06:53:12 AM UTC 24 |
Sep 01 07:02:52 AM UTC 24 |
321728834550 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/299.uart_fifo_reset.781030195 |
|
|
Sep 01 06:57:34 AM UTC 24 |
Sep 01 07:05:14 AM UTC 24 |
112637892824 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_stress_all.2762669860 |
|
|
Sep 01 06:34:29 AM UTC 24 |
Sep 01 07:05:36 AM UTC 24 |
481995045237 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_perf.3043185291 |
|
|
Sep 01 06:45:48 AM UTC 24 |
Sep 01 07:05:38 AM UTC 24 |
22115342179 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/146.uart_fifo_reset.144287770 |
|
|
Sep 01 06:52:53 AM UTC 24 |
Sep 01 07:06:14 AM UTC 24 |
221273053479 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_stress_all.702576868 |
|
|
Sep 01 06:45:53 AM UTC 24 |
Sep 01 07:08:27 AM UTC 24 |
27795784562 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_stress_all.2050171847 |
|
|
Sep 01 06:45:20 AM UTC 24 |
Sep 01 07:09:09 AM UTC 24 |
174571022602 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/101.uart_fifo_reset.3450373038 |
|
|
Sep 01 06:51:43 AM UTC 24 |
Sep 01 07:10:10 AM UTC 24 |
144009295039 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_stress_all.403163988 |
|
|
Sep 01 06:35:18 AM UTC 24 |
Sep 01 07:11:58 AM UTC 24 |
147346779633 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2225954935 |
|
|
Sep 01 06:57:36 AM UTC 24 |
Sep 01 06:57:40 AM UTC 24 |
53285576 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.2114527373 |
|
|
Sep 01 06:57:39 AM UTC 24 |
Sep 01 06:57:41 AM UTC 24 |
12024118 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3036893322 |
|
|
Sep 01 06:57:39 AM UTC 24 |
Sep 01 06:57:41 AM UTC 24 |
140526496 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.208878001 |
|
|
Sep 01 06:57:40 AM UTC 24 |
Sep 01 06:57:42 AM UTC 24 |
21602809 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.92896893 |
|
|
Sep 01 06:57:41 AM UTC 24 |
Sep 01 06:57:43 AM UTC 24 |
17985150 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.3714778759 |
|
|
Sep 01 06:57:41 AM UTC 24 |
Sep 01 06:57:44 AM UTC 24 |
93882034 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.991278050 |
|
|
Sep 01 06:57:42 AM UTC 24 |
Sep 01 06:57:44 AM UTC 24 |
24306626 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2741067049 |
|
|
Sep 01 06:57:42 AM UTC 24 |
Sep 01 06:57:44 AM UTC 24 |
36471997 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.3479188937 |
|
|
Sep 01 06:57:42 AM UTC 24 |
Sep 01 06:57:44 AM UTC 24 |
18406240 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2215500858 |
|
|
Sep 01 06:57:43 AM UTC 24 |
Sep 01 06:57:46 AM UTC 24 |
49833394 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.230704274 |
|
|
Sep 01 06:57:46 AM UTC 24 |
Sep 01 06:57:48 AM UTC 24 |
42920475 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.923234219 |
|
|
Sep 01 06:57:45 AM UTC 24 |
Sep 01 06:57:48 AM UTC 24 |
44961743 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.2601299744 |
|
|
Sep 01 06:57:46 AM UTC 24 |
Sep 01 06:57:48 AM UTC 24 |
13790366 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2097960836 |
|
|
Sep 01 06:57:45 AM UTC 24 |
Sep 01 06:57:48 AM UTC 24 |
45837423 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.183337785 |
|
|
Sep 01 06:57:47 AM UTC 24 |
Sep 01 06:57:49 AM UTC 24 |
19511100 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.937119628 |
|
|
Sep 01 06:57:48 AM UTC 24 |
Sep 01 06:57:50 AM UTC 24 |
50756899 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.2407583904 |
|
|
Sep 01 06:57:47 AM UTC 24 |
Sep 01 06:57:51 AM UTC 24 |
793984259 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.834968192 |
|
|
Sep 01 06:57:49 AM UTC 24 |
Sep 01 06:57:52 AM UTC 24 |
36578603 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.256717186 |
|
|
Sep 01 06:57:49 AM UTC 24 |
Sep 01 06:57:52 AM UTC 24 |
16006724 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.463189280 |
|
|
Sep 01 06:57:49 AM UTC 24 |
Sep 01 06:57:52 AM UTC 24 |
16330157 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.2318781826 |
|
|
Sep 01 06:57:49 AM UTC 24 |
Sep 01 06:57:52 AM UTC 24 |
65252585 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3173957467 |
|
|
Sep 01 06:57:50 AM UTC 24 |
Sep 01 06:57:53 AM UTC 24 |
13679706 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.2934031020 |
|
|
Sep 01 06:57:49 AM UTC 24 |
Sep 01 06:57:54 AM UTC 24 |
428872959 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.1302274151 |
|
|
Sep 01 06:57:52 AM UTC 24 |
Sep 01 06:57:54 AM UTC 24 |
210620111 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.124000327 |
|
|
Sep 01 06:57:51 AM UTC 24 |
Sep 01 06:57:55 AM UTC 24 |
109232866 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.2148519429 |
|
|
Sep 01 06:57:53 AM UTC 24 |
Sep 01 06:57:55 AM UTC 24 |
14466513 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.612653167 |
|
|
Sep 01 06:57:53 AM UTC 24 |
Sep 01 06:57:55 AM UTC 24 |
13417120 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.4224094631 |
|
|
Sep 01 06:57:53 AM UTC 24 |
Sep 01 06:57:55 AM UTC 24 |
11634450 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3918052852 |
|
|
Sep 01 06:57:53 AM UTC 24 |
Sep 01 06:57:56 AM UTC 24 |
118188029 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3972979098 |
|
|
Sep 01 06:57:53 AM UTC 24 |
Sep 01 06:57:56 AM UTC 24 |
36919020 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.1006624708 |
|
|
Sep 01 06:57:53 AM UTC 24 |
Sep 01 06:57:56 AM UTC 24 |
380664789 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2030079883 |
|
|
Sep 01 06:57:55 AM UTC 24 |
Sep 01 06:57:57 AM UTC 24 |
13123081 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.2421183790 |
|
|
Sep 01 06:57:53 AM UTC 24 |
Sep 01 06:57:57 AM UTC 24 |
164163381 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1861554996 |
|
|
Sep 01 06:57:55 AM UTC 24 |
Sep 01 06:57:57 AM UTC 24 |
44421859 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2190562547 |
|
|
Sep 01 06:57:55 AM UTC 24 |
Sep 01 06:57:58 AM UTC 24 |
54201807 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.1514918964 |
|
|
Sep 01 06:57:56 AM UTC 24 |
Sep 01 06:57:58 AM UTC 24 |
14664594 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.2283812238 |
|
|
Sep 01 06:58:07 AM UTC 24 |
Sep 01 06:58:10 AM UTC 24 |
39949919 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.814555021 |
|
|
Sep 01 06:57:56 AM UTC 24 |
Sep 01 06:57:58 AM UTC 24 |
42193584 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.3612337195 |
|
|
Sep 01 06:57:57 AM UTC 24 |
Sep 01 06:57:58 AM UTC 24 |
102825481 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2718140536 |
|
|
Sep 01 06:57:57 AM UTC 24 |
Sep 01 06:57:59 AM UTC 24 |
15613036 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.696375180 |
|
|
Sep 01 06:57:56 AM UTC 24 |
Sep 01 06:57:59 AM UTC 24 |
302337201 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2114390187 |
|
|
Sep 01 06:57:55 AM UTC 24 |
Sep 01 06:57:59 AM UTC 24 |
230991454 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.3816106626 |
|
|
Sep 01 06:58:07 AM UTC 24 |
Sep 01 06:58:09 AM UTC 24 |
35590516 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.381364005 |
|
|
Sep 01 06:57:57 AM UTC 24 |
Sep 01 06:58:00 AM UTC 24 |
357659358 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.311683508 |
|
|
Sep 01 06:57:58 AM UTC 24 |
Sep 01 06:58:00 AM UTC 24 |
48991849 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.2246037009 |
|
|
Sep 01 06:57:56 AM UTC 24 |
Sep 01 06:58:00 AM UTC 24 |
364328845 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2645045038 |
|
|
Sep 01 06:57:58 AM UTC 24 |
Sep 01 06:58:00 AM UTC 24 |
51126612 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.3235217570 |
|
|
Sep 01 06:57:58 AM UTC 24 |
Sep 01 06:58:01 AM UTC 24 |
125738626 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.620742986 |
|
|
Sep 01 06:57:58 AM UTC 24 |
Sep 01 06:58:01 AM UTC 24 |
92961228 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3880437877 |
|
|
Sep 01 06:58:00 AM UTC 24 |
Sep 01 06:58:01 AM UTC 24 |
14198465 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.583610709 |
|
|
Sep 01 06:58:00 AM UTC 24 |
Sep 01 06:58:02 AM UTC 24 |
49155292 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1848774417 |
|
|
Sep 01 06:58:00 AM UTC 24 |
Sep 01 06:58:02 AM UTC 24 |
56657268 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3208848440 |
|
|
Sep 01 06:58:00 AM UTC 24 |
Sep 01 06:58:02 AM UTC 24 |
25231124 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.639188263 |
|
|
Sep 01 06:58:00 AM UTC 24 |
Sep 01 06:58:03 AM UTC 24 |
148733157 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.1369606847 |
|
|
Sep 01 06:58:01 AM UTC 24 |
Sep 01 06:58:03 AM UTC 24 |
39148620 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1592767275 |
|
|
Sep 01 06:58:01 AM UTC 24 |
Sep 01 06:58:03 AM UTC 24 |
44496518 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.3028917617 |
|
|
Sep 01 06:58:01 AM UTC 24 |
Sep 01 06:58:03 AM UTC 24 |
42362688 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.743028616 |
|
|
Sep 01 06:58:00 AM UTC 24 |
Sep 01 06:58:03 AM UTC 24 |
465184687 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.683168441 |
|
|
Sep 01 06:58:01 AM UTC 24 |
Sep 01 06:58:03 AM UTC 24 |
35227062 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.4281282578 |
|
|
Sep 01 06:58:02 AM UTC 24 |
Sep 01 06:58:05 AM UTC 24 |
77712372 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.4208074756 |
|
|
Sep 01 06:58:03 AM UTC 24 |
Sep 01 06:58:05 AM UTC 24 |
42839980 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.1043044466 |
|
|
Sep 01 06:58:03 AM UTC 24 |
Sep 01 06:58:05 AM UTC 24 |
51293650 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2248473211 |
|
|
Sep 01 06:58:03 AM UTC 24 |
Sep 01 06:58:06 AM UTC 24 |
33599871 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.1075870001 |
|
|
Sep 01 06:58:03 AM UTC 24 |
Sep 01 06:58:06 AM UTC 24 |
19121528 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.2912270527 |
|
|
Sep 01 06:58:04 AM UTC 24 |
Sep 01 06:58:06 AM UTC 24 |
93311423 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.2470616579 |
|
|
Sep 01 06:58:03 AM UTC 24 |
Sep 01 06:58:07 AM UTC 24 |
323838398 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.198801107 |
|
|
Sep 01 06:58:04 AM UTC 24 |
Sep 01 06:58:07 AM UTC 24 |
276845009 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.4280157908 |
|
|
Sep 01 06:58:05 AM UTC 24 |
Sep 01 06:58:07 AM UTC 24 |
29081515 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.2496497254 |
|
|
Sep 01 06:58:05 AM UTC 24 |
Sep 01 06:58:07 AM UTC 24 |
96541403 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.1589868019 |
|
|
Sep 01 06:58:05 AM UTC 24 |
Sep 01 06:58:08 AM UTC 24 |
16318393 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3336395643 |
|
|
Sep 01 06:58:05 AM UTC 24 |
Sep 01 06:58:08 AM UTC 24 |
75859268 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.1896714851 |
|
|
Sep 01 06:58:05 AM UTC 24 |
Sep 01 06:58:09 AM UTC 24 |
244045379 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2808786407 |
|
|
Sep 01 06:58:08 AM UTC 24 |
Sep 01 06:58:10 AM UTC 24 |
14426724 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.2585631722 |
|
|
Sep 01 06:58:08 AM UTC 24 |
Sep 01 06:58:10 AM UTC 24 |
27636589 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3259299692 |
|
|
Sep 01 06:58:07 AM UTC 24 |
Sep 01 06:58:10 AM UTC 24 |
41382891 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1366873435 |
|
|
Sep 01 06:58:08 AM UTC 24 |
Sep 01 06:58:10 AM UTC 24 |
68135120 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1985334166 |
|
|
Sep 01 06:58:08 AM UTC 24 |
Sep 01 06:58:10 AM UTC 24 |
181099337 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1217207012 |
|
|
Sep 01 06:58:08 AM UTC 24 |
Sep 01 06:58:10 AM UTC 24 |
77845585 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.3000447003 |
|
|
Sep 01 06:58:10 AM UTC 24 |
Sep 01 06:58:12 AM UTC 24 |
62615116 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.1115615908 |
|
|
Sep 01 06:58:10 AM UTC 24 |
Sep 01 06:58:12 AM UTC 24 |
18287118 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.4007141409 |
|
|
Sep 01 06:58:10 AM UTC 24 |
Sep 01 06:58:12 AM UTC 24 |
52725666 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1200773894 |
|
|
Sep 01 06:58:10 AM UTC 24 |
Sep 01 06:58:12 AM UTC 24 |
139007731 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2971521039 |
|
|
Sep 01 06:58:10 AM UTC 24 |
Sep 01 06:58:12 AM UTC 24 |
61035268 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4272883848 |
|
|
Sep 01 06:58:10 AM UTC 24 |
Sep 01 06:58:12 AM UTC 24 |
24717771 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.184030435 |
|
|
Sep 01 06:58:13 AM UTC 24 |
Sep 01 06:58:15 AM UTC 24 |
15881532 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.242559025 |
|
|
Sep 01 06:58:14 AM UTC 24 |
Sep 01 06:58:15 AM UTC 24 |
14420173 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.4209695400 |
|
|
Sep 01 06:58:13 AM UTC 24 |
Sep 01 06:58:15 AM UTC 24 |
25684687 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1154638062 |
|
|
Sep 01 06:58:13 AM UTC 24 |
Sep 01 06:58:15 AM UTC 24 |
171487524 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.290043733 |
|
|
Sep 01 06:58:14 AM UTC 24 |
Sep 01 06:58:16 AM UTC 24 |
49685222 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.1826696778 |
|
|
Sep 01 06:58:14 AM UTC 24 |
Sep 01 06:58:16 AM UTC 24 |
24029976 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.3822989465 |
|
|
Sep 01 06:58:14 AM UTC 24 |
Sep 01 06:58:16 AM UTC 24 |
18741816 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3850374656 |
|
|
Sep 01 06:58:14 AM UTC 24 |
Sep 01 06:58:16 AM UTC 24 |
72097478 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1523905692 |
|
|
Sep 01 06:58:14 AM UTC 24 |
Sep 01 06:58:16 AM UTC 24 |
16619459 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.3074236178 |
|
|
Sep 01 06:58:14 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.2773796481 |
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